1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* Copyright (c) 2017 Microsemi Corporation 3 */ 4 5 #ifndef _SOC_MSCC_OCELOT_H 6 #define _SOC_MSCC_OCELOT_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/net_tstamp.h> 10 #include <linux/if_vlan.h> 11 #include <linux/regmap.h> 12 #include <net/dsa.h> 13 14 /* Port Group IDs (PGID) are masks of destination ports. 15 * 16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each 17 * frame, and forwards the frame to the ports that are present in the logical 18 * AND of all 3 PGIDs. 19 * 20 * These PGID lookups are: 21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by 22 * which the switch selects a destination PGID: 23 * - The {DMAC, VID} is present in the MAC table. In that case, the 24 * destination PGID is given by the DEST_IDX field of the MAC table entry 25 * that matched. 26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The 27 * frame is disseminated as being either unicast, multicast or broadcast, 28 * and according to that, the destination PGID is chosen as being the 29 * value contained by ANA_FLOODING_FLD_UNICAST, 30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST. 31 * The destination PGID can be an unicast set: the first PGIDs, 0 to 32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from 33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to 34 * a physical port and has a single bit set in the destination ports mask: 35 * that corresponding to the port number itself. In contrast, a multicast 36 * PGID will have potentially more than one single bit set in the destination 37 * ports mask. 38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier 39 * dissects each frame and generates a 4-bit Link Aggregation Code which is 40 * used for this second PGID table lookup. The goal of link aggregation is to 41 * hash multiple flows within the same LAG on to different destination ports. 42 * The first lookup will result in a PGID with all the LAG members present in 43 * the destination ports mask, and the second lookup, by Link Aggregation 44 * Code, will ensure that each flow gets forwarded only to a single port out 45 * of that mask (there are no duplicates). 46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table 47 * is indexed with the ingress port (plus 80). These PGIDs answer the 48 * question "is port i allowed to forward traffic to port j?" If yes, then 49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used 50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge. 51 */ 52 53 /* Reserve some destination PGIDs at the end of the range: 54 * PGID_BLACKHOLE: used for not forwarding the frames 55 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses 56 * of the switch port net devices, towards the CPU port module. 57 * PGID_UC: the flooding destinations for unknown unicast traffic. 58 * PGID_MC: the flooding destinations for non-IP multicast traffic. 59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic. 60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic. 61 * PGID_BC: the flooding destinations for broadcast traffic. 62 */ 63 #define PGID_BLACKHOLE 57 64 #define PGID_CPU 58 65 #define PGID_UC 59 66 #define PGID_MC 60 67 #define PGID_MCIPV4 61 68 #define PGID_MCIPV6 62 69 #define PGID_BC 63 70 71 #define for_each_unicast_dest_pgid(ocelot, pgid) \ 72 for ((pgid) = 0; \ 73 (pgid) < (ocelot)->num_phys_ports; \ 74 (pgid)++) 75 76 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \ 77 for ((pgid) = (ocelot)->num_phys_ports + 1; \ 78 (pgid) < PGID_BLACKHOLE; \ 79 (pgid)++) 80 81 #define for_each_aggr_pgid(ocelot, pgid) \ 82 for ((pgid) = PGID_AGGR; \ 83 (pgid) < PGID_SRC; \ 84 (pgid)++) 85 86 /* Aggregation PGIDs, one per Link Aggregation Code */ 87 #define PGID_AGGR 64 88 89 /* Source PGIDs, one per physical port */ 90 #define PGID_SRC 80 91 92 #define OCELOT_NUM_TC 8 93 94 #define OCELOT_SPEED_2500 0 95 #define OCELOT_SPEED_1000 1 96 #define OCELOT_SPEED_100 2 97 #define OCELOT_SPEED_10 3 98 99 #define OCELOT_PTP_PINS_NUM 4 100 101 #define TARGET_OFFSET 24 102 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0) 103 #define REG(reg, offset) [reg & REG_MASK] = offset 104 105 #define REG_RESERVED_ADDR 0xffffffff 106 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR) 107 108 enum ocelot_target { 109 ANA = 1, 110 QS, 111 QSYS, 112 REW, 113 SYS, 114 S0, 115 S1, 116 S2, 117 HSIO, 118 PTP, 119 FDMA, 120 GCB, 121 DEV_GMII, 122 TARGET_MAX, 123 }; 124 125 enum ocelot_reg { 126 ANA_ADVLEARN = ANA << TARGET_OFFSET, 127 ANA_VLANMASK, 128 ANA_PORT_B_DOMAIN, 129 ANA_ANAGEFIL, 130 ANA_ANEVENTS, 131 ANA_STORMLIMIT_BURST, 132 ANA_STORMLIMIT_CFG, 133 ANA_ISOLATED_PORTS, 134 ANA_COMMUNITY_PORTS, 135 ANA_AUTOAGE, 136 ANA_MACTOPTIONS, 137 ANA_LEARNDISC, 138 ANA_AGENCTRL, 139 ANA_MIRRORPORTS, 140 ANA_EMIRRORPORTS, 141 ANA_FLOODING, 142 ANA_FLOODING_IPMC, 143 ANA_SFLOW_CFG, 144 ANA_PORT_MODE, 145 ANA_CUT_THRU_CFG, 146 ANA_PGID_PGID, 147 ANA_TABLES_ANMOVED, 148 ANA_TABLES_MACHDATA, 149 ANA_TABLES_MACLDATA, 150 ANA_TABLES_STREAMDATA, 151 ANA_TABLES_MACACCESS, 152 ANA_TABLES_MACTINDX, 153 ANA_TABLES_VLANACCESS, 154 ANA_TABLES_VLANTIDX, 155 ANA_TABLES_ISDXACCESS, 156 ANA_TABLES_ISDXTIDX, 157 ANA_TABLES_ENTRYLIM, 158 ANA_TABLES_PTP_ID_HIGH, 159 ANA_TABLES_PTP_ID_LOW, 160 ANA_TABLES_STREAMACCESS, 161 ANA_TABLES_STREAMTIDX, 162 ANA_TABLES_SEQ_HISTORY, 163 ANA_TABLES_SEQ_MASK, 164 ANA_TABLES_SFID_MASK, 165 ANA_TABLES_SFIDACCESS, 166 ANA_TABLES_SFIDTIDX, 167 ANA_MSTI_STATE, 168 ANA_OAM_UPM_LM_CNT, 169 ANA_SG_ACCESS_CTRL, 170 ANA_SG_CONFIG_REG_1, 171 ANA_SG_CONFIG_REG_2, 172 ANA_SG_CONFIG_REG_3, 173 ANA_SG_CONFIG_REG_4, 174 ANA_SG_CONFIG_REG_5, 175 ANA_SG_GCL_GS_CONFIG, 176 ANA_SG_GCL_TI_CONFIG, 177 ANA_SG_STATUS_REG_1, 178 ANA_SG_STATUS_REG_2, 179 ANA_SG_STATUS_REG_3, 180 ANA_PORT_VLAN_CFG, 181 ANA_PORT_DROP_CFG, 182 ANA_PORT_QOS_CFG, 183 ANA_PORT_VCAP_CFG, 184 ANA_PORT_VCAP_S1_KEY_CFG, 185 ANA_PORT_VCAP_S2_CFG, 186 ANA_PORT_PCP_DEI_MAP, 187 ANA_PORT_CPU_FWD_CFG, 188 ANA_PORT_CPU_FWD_BPDU_CFG, 189 ANA_PORT_CPU_FWD_GARP_CFG, 190 ANA_PORT_CPU_FWD_CCM_CFG, 191 ANA_PORT_PORT_CFG, 192 ANA_PORT_POL_CFG, 193 ANA_PORT_PTP_CFG, 194 ANA_PORT_PTP_DLY1_CFG, 195 ANA_PORT_PTP_DLY2_CFG, 196 ANA_PORT_SFID_CFG, 197 ANA_PFC_PFC_CFG, 198 ANA_PFC_PFC_TIMER, 199 ANA_IPT_OAM_MEP_CFG, 200 ANA_IPT_IPT, 201 ANA_PPT_PPT, 202 ANA_FID_MAP_FID_MAP, 203 ANA_AGGR_CFG, 204 ANA_CPUQ_CFG, 205 ANA_CPUQ_CFG2, 206 ANA_CPUQ_8021_CFG, 207 ANA_DSCP_CFG, 208 ANA_DSCP_REWR_CFG, 209 ANA_VCAP_RNG_TYPE_CFG, 210 ANA_VCAP_RNG_VAL_CFG, 211 ANA_VRAP_CFG, 212 ANA_VRAP_HDR_DATA, 213 ANA_VRAP_HDR_MASK, 214 ANA_DISCARD_CFG, 215 ANA_FID_CFG, 216 ANA_POL_PIR_CFG, 217 ANA_POL_CIR_CFG, 218 ANA_POL_MODE_CFG, 219 ANA_POL_PIR_STATE, 220 ANA_POL_CIR_STATE, 221 ANA_POL_STATE, 222 ANA_POL_FLOWC, 223 ANA_POL_HYST, 224 ANA_POL_MISC_CFG, 225 QS_XTR_GRP_CFG = QS << TARGET_OFFSET, 226 QS_XTR_RD, 227 QS_XTR_FRM_PRUNING, 228 QS_XTR_FLUSH, 229 QS_XTR_DATA_PRESENT, 230 QS_XTR_CFG, 231 QS_INJ_GRP_CFG, 232 QS_INJ_WR, 233 QS_INJ_CTRL, 234 QS_INJ_STATUS, 235 QS_INJ_ERR, 236 QS_INH_DBG, 237 QSYS_PORT_MODE = QSYS << TARGET_OFFSET, 238 QSYS_SWITCH_PORT_MODE, 239 QSYS_STAT_CNT_CFG, 240 QSYS_EEE_CFG, 241 QSYS_EEE_THRES, 242 QSYS_IGR_NO_SHARING, 243 QSYS_EGR_NO_SHARING, 244 QSYS_SW_STATUS, 245 QSYS_EXT_CPU_CFG, 246 QSYS_PAD_CFG, 247 QSYS_CPU_GROUP_MAP, 248 QSYS_QMAP, 249 QSYS_ISDX_SGRP, 250 QSYS_TIMED_FRAME_ENTRY, 251 QSYS_TFRM_MISC, 252 QSYS_TFRM_PORT_DLY, 253 QSYS_TFRM_TIMER_CFG_1, 254 QSYS_TFRM_TIMER_CFG_2, 255 QSYS_TFRM_TIMER_CFG_3, 256 QSYS_TFRM_TIMER_CFG_4, 257 QSYS_TFRM_TIMER_CFG_5, 258 QSYS_TFRM_TIMER_CFG_6, 259 QSYS_TFRM_TIMER_CFG_7, 260 QSYS_TFRM_TIMER_CFG_8, 261 QSYS_RED_PROFILE, 262 QSYS_RES_QOS_MODE, 263 QSYS_RES_CFG, 264 QSYS_RES_STAT, 265 QSYS_EGR_DROP_MODE, 266 QSYS_EQ_CTRL, 267 QSYS_EVENTS_CORE, 268 QSYS_QMAXSDU_CFG_0, 269 QSYS_QMAXSDU_CFG_1, 270 QSYS_QMAXSDU_CFG_2, 271 QSYS_QMAXSDU_CFG_3, 272 QSYS_QMAXSDU_CFG_4, 273 QSYS_QMAXSDU_CFG_5, 274 QSYS_QMAXSDU_CFG_6, 275 QSYS_QMAXSDU_CFG_7, 276 QSYS_PREEMPTION_CFG, 277 QSYS_CIR_CFG, 278 QSYS_EIR_CFG, 279 QSYS_SE_CFG, 280 QSYS_SE_DWRR_CFG, 281 QSYS_SE_CONNECT, 282 QSYS_SE_DLB_SENSE, 283 QSYS_CIR_STATE, 284 QSYS_EIR_STATE, 285 QSYS_SE_STATE, 286 QSYS_HSCH_MISC_CFG, 287 QSYS_TAG_CONFIG, 288 QSYS_TAS_PARAM_CFG_CTRL, 289 QSYS_PORT_MAX_SDU, 290 QSYS_PARAM_CFG_REG_1, 291 QSYS_PARAM_CFG_REG_2, 292 QSYS_PARAM_CFG_REG_3, 293 QSYS_PARAM_CFG_REG_4, 294 QSYS_PARAM_CFG_REG_5, 295 QSYS_GCL_CFG_REG_1, 296 QSYS_GCL_CFG_REG_2, 297 QSYS_PARAM_STATUS_REG_1, 298 QSYS_PARAM_STATUS_REG_2, 299 QSYS_PARAM_STATUS_REG_3, 300 QSYS_PARAM_STATUS_REG_4, 301 QSYS_PARAM_STATUS_REG_5, 302 QSYS_PARAM_STATUS_REG_6, 303 QSYS_PARAM_STATUS_REG_7, 304 QSYS_PARAM_STATUS_REG_8, 305 QSYS_PARAM_STATUS_REG_9, 306 QSYS_GCL_STATUS_REG_1, 307 QSYS_GCL_STATUS_REG_2, 308 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET, 309 REW_TAG_CFG, 310 REW_PORT_CFG, 311 REW_DSCP_CFG, 312 REW_PCP_DEI_QOS_MAP_CFG, 313 REW_PTP_CFG, 314 REW_PTP_DLY1_CFG, 315 REW_RED_TAG_CFG, 316 REW_DSCP_REMAP_DP1_CFG, 317 REW_DSCP_REMAP_CFG, 318 REW_STAT_CFG, 319 REW_REW_STICKY, 320 REW_PPT, 321 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET, 322 SYS_COUNT_RX_UNICAST, 323 SYS_COUNT_RX_MULTICAST, 324 SYS_COUNT_RX_BROADCAST, 325 SYS_COUNT_RX_SHORTS, 326 SYS_COUNT_RX_FRAGMENTS, 327 SYS_COUNT_RX_JABBERS, 328 SYS_COUNT_RX_CRC_ALIGN_ERRS, 329 SYS_COUNT_RX_SYM_ERRS, 330 SYS_COUNT_RX_64, 331 SYS_COUNT_RX_65_127, 332 SYS_COUNT_RX_128_255, 333 SYS_COUNT_RX_256_511, 334 SYS_COUNT_RX_512_1023, 335 SYS_COUNT_RX_1024_1526, 336 SYS_COUNT_RX_1527_MAX, 337 SYS_COUNT_RX_PAUSE, 338 SYS_COUNT_RX_CONTROL, 339 SYS_COUNT_RX_LONGS, 340 SYS_COUNT_RX_CLASSIFIED_DROPS, 341 SYS_COUNT_RX_RED_PRIO_0, 342 SYS_COUNT_RX_RED_PRIO_1, 343 SYS_COUNT_RX_RED_PRIO_2, 344 SYS_COUNT_RX_RED_PRIO_3, 345 SYS_COUNT_RX_RED_PRIO_4, 346 SYS_COUNT_RX_RED_PRIO_5, 347 SYS_COUNT_RX_RED_PRIO_6, 348 SYS_COUNT_RX_RED_PRIO_7, 349 SYS_COUNT_RX_YELLOW_PRIO_0, 350 SYS_COUNT_RX_YELLOW_PRIO_1, 351 SYS_COUNT_RX_YELLOW_PRIO_2, 352 SYS_COUNT_RX_YELLOW_PRIO_3, 353 SYS_COUNT_RX_YELLOW_PRIO_4, 354 SYS_COUNT_RX_YELLOW_PRIO_5, 355 SYS_COUNT_RX_YELLOW_PRIO_6, 356 SYS_COUNT_RX_YELLOW_PRIO_7, 357 SYS_COUNT_RX_GREEN_PRIO_0, 358 SYS_COUNT_RX_GREEN_PRIO_1, 359 SYS_COUNT_RX_GREEN_PRIO_2, 360 SYS_COUNT_RX_GREEN_PRIO_3, 361 SYS_COUNT_RX_GREEN_PRIO_4, 362 SYS_COUNT_RX_GREEN_PRIO_5, 363 SYS_COUNT_RX_GREEN_PRIO_6, 364 SYS_COUNT_RX_GREEN_PRIO_7, 365 SYS_COUNT_TX_OCTETS, 366 SYS_COUNT_TX_UNICAST, 367 SYS_COUNT_TX_MULTICAST, 368 SYS_COUNT_TX_BROADCAST, 369 SYS_COUNT_TX_COLLISION, 370 SYS_COUNT_TX_DROPS, 371 SYS_COUNT_TX_PAUSE, 372 SYS_COUNT_TX_64, 373 SYS_COUNT_TX_65_127, 374 SYS_COUNT_TX_128_255, 375 SYS_COUNT_TX_256_511, 376 SYS_COUNT_TX_512_1023, 377 SYS_COUNT_TX_1024_1526, 378 SYS_COUNT_TX_1527_MAX, 379 SYS_COUNT_TX_YELLOW_PRIO_0, 380 SYS_COUNT_TX_YELLOW_PRIO_1, 381 SYS_COUNT_TX_YELLOW_PRIO_2, 382 SYS_COUNT_TX_YELLOW_PRIO_3, 383 SYS_COUNT_TX_YELLOW_PRIO_4, 384 SYS_COUNT_TX_YELLOW_PRIO_5, 385 SYS_COUNT_TX_YELLOW_PRIO_6, 386 SYS_COUNT_TX_YELLOW_PRIO_7, 387 SYS_COUNT_TX_GREEN_PRIO_0, 388 SYS_COUNT_TX_GREEN_PRIO_1, 389 SYS_COUNT_TX_GREEN_PRIO_2, 390 SYS_COUNT_TX_GREEN_PRIO_3, 391 SYS_COUNT_TX_GREEN_PRIO_4, 392 SYS_COUNT_TX_GREEN_PRIO_5, 393 SYS_COUNT_TX_GREEN_PRIO_6, 394 SYS_COUNT_TX_GREEN_PRIO_7, 395 SYS_COUNT_TX_AGING, 396 SYS_COUNT_DROP_LOCAL, 397 SYS_COUNT_DROP_TAIL, 398 SYS_COUNT_DROP_YELLOW_PRIO_0, 399 SYS_COUNT_DROP_YELLOW_PRIO_1, 400 SYS_COUNT_DROP_YELLOW_PRIO_2, 401 SYS_COUNT_DROP_YELLOW_PRIO_3, 402 SYS_COUNT_DROP_YELLOW_PRIO_4, 403 SYS_COUNT_DROP_YELLOW_PRIO_5, 404 SYS_COUNT_DROP_YELLOW_PRIO_6, 405 SYS_COUNT_DROP_YELLOW_PRIO_7, 406 SYS_COUNT_DROP_GREEN_PRIO_0, 407 SYS_COUNT_DROP_GREEN_PRIO_1, 408 SYS_COUNT_DROP_GREEN_PRIO_2, 409 SYS_COUNT_DROP_GREEN_PRIO_3, 410 SYS_COUNT_DROP_GREEN_PRIO_4, 411 SYS_COUNT_DROP_GREEN_PRIO_5, 412 SYS_COUNT_DROP_GREEN_PRIO_6, 413 SYS_COUNT_DROP_GREEN_PRIO_7, 414 SYS_RESET_CFG, 415 SYS_SR_ETYPE_CFG, 416 SYS_VLAN_ETYPE_CFG, 417 SYS_PORT_MODE, 418 SYS_FRONT_PORT_MODE, 419 SYS_FRM_AGING, 420 SYS_STAT_CFG, 421 SYS_SW_STATUS, 422 SYS_MISC_CFG, 423 SYS_REW_MAC_HIGH_CFG, 424 SYS_REW_MAC_LOW_CFG, 425 SYS_TIMESTAMP_OFFSET, 426 SYS_CMID, 427 SYS_PAUSE_CFG, 428 SYS_PAUSE_TOT_CFG, 429 SYS_ATOP, 430 SYS_ATOP_TOT_CFG, 431 SYS_MAC_FC_CFG, 432 SYS_MMGT, 433 SYS_MMGT_FAST, 434 SYS_EVENTS_DIF, 435 SYS_EVENTS_CORE, 436 SYS_CNT, 437 SYS_PTP_STATUS, 438 SYS_PTP_TXSTAMP, 439 SYS_PTP_NXT, 440 SYS_PTP_CFG, 441 SYS_RAM_INIT, 442 SYS_CM_ADDR, 443 SYS_CM_DATA_WR, 444 SYS_CM_DATA_RD, 445 SYS_CM_OP, 446 SYS_CM_DATA, 447 PTP_PIN_CFG = PTP << TARGET_OFFSET, 448 PTP_PIN_TOD_SEC_MSB, 449 PTP_PIN_TOD_SEC_LSB, 450 PTP_PIN_TOD_NSEC, 451 PTP_PIN_WF_HIGH_PERIOD, 452 PTP_PIN_WF_LOW_PERIOD, 453 PTP_CFG_MISC, 454 PTP_CLK_CFG_ADJ_CFG, 455 PTP_CLK_CFG_ADJ_FREQ, 456 GCB_SOFT_RST = GCB << TARGET_OFFSET, 457 GCB_MIIM_MII_STATUS, 458 GCB_MIIM_MII_CMD, 459 GCB_MIIM_MII_DATA, 460 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET, 461 DEV_PORT_MISC, 462 DEV_EVENTS, 463 DEV_EEE_CFG, 464 DEV_RX_PATH_DELAY, 465 DEV_TX_PATH_DELAY, 466 DEV_PTP_PREDICT_CFG, 467 DEV_MAC_ENA_CFG, 468 DEV_MAC_MODE_CFG, 469 DEV_MAC_MAXLEN_CFG, 470 DEV_MAC_TAGS_CFG, 471 DEV_MAC_ADV_CHK_CFG, 472 DEV_MAC_IFG_CFG, 473 DEV_MAC_HDX_CFG, 474 DEV_MAC_DBG_CFG, 475 DEV_MAC_FC_MAC_LOW_CFG, 476 DEV_MAC_FC_MAC_HIGH_CFG, 477 DEV_MAC_STICKY, 478 PCS1G_CFG, 479 PCS1G_MODE_CFG, 480 PCS1G_SD_CFG, 481 PCS1G_ANEG_CFG, 482 PCS1G_ANEG_NP_CFG, 483 PCS1G_LB_CFG, 484 PCS1G_DBG_CFG, 485 PCS1G_CDET_CFG, 486 PCS1G_ANEG_STATUS, 487 PCS1G_ANEG_NP_STATUS, 488 PCS1G_LINK_STATUS, 489 PCS1G_LINK_DOWN_CNT, 490 PCS1G_STICKY, 491 PCS1G_DEBUG_STATUS, 492 PCS1G_LPI_CFG, 493 PCS1G_LPI_WAKE_ERROR_CNT, 494 PCS1G_LPI_STATUS, 495 PCS1G_TSTPAT_MODE_CFG, 496 PCS1G_TSTPAT_STATUS, 497 DEV_PCS_FX100_CFG, 498 DEV_PCS_FX100_STATUS, 499 }; 500 501 enum ocelot_regfield { 502 ANA_ADVLEARN_VLAN_CHK, 503 ANA_ADVLEARN_LEARN_MIRROR, 504 ANA_ANEVENTS_FLOOD_DISCARD, 505 ANA_ANEVENTS_MSTI_DROP, 506 ANA_ANEVENTS_ACLKILL, 507 ANA_ANEVENTS_ACLUSED, 508 ANA_ANEVENTS_AUTOAGE, 509 ANA_ANEVENTS_VS2TTL1, 510 ANA_ANEVENTS_STORM_DROP, 511 ANA_ANEVENTS_LEARN_DROP, 512 ANA_ANEVENTS_AGED_ENTRY, 513 ANA_ANEVENTS_CPU_LEARN_FAILED, 514 ANA_ANEVENTS_AUTO_LEARN_FAILED, 515 ANA_ANEVENTS_LEARN_REMOVE, 516 ANA_ANEVENTS_AUTO_LEARNED, 517 ANA_ANEVENTS_AUTO_MOVED, 518 ANA_ANEVENTS_DROPPED, 519 ANA_ANEVENTS_CLASSIFIED_DROP, 520 ANA_ANEVENTS_CLASSIFIED_COPY, 521 ANA_ANEVENTS_VLAN_DISCARD, 522 ANA_ANEVENTS_FWD_DISCARD, 523 ANA_ANEVENTS_MULTICAST_FLOOD, 524 ANA_ANEVENTS_UNICAST_FLOOD, 525 ANA_ANEVENTS_DEST_KNOWN, 526 ANA_ANEVENTS_BUCKET3_MATCH, 527 ANA_ANEVENTS_BUCKET2_MATCH, 528 ANA_ANEVENTS_BUCKET1_MATCH, 529 ANA_ANEVENTS_BUCKET0_MATCH, 530 ANA_ANEVENTS_CPU_OPERATION, 531 ANA_ANEVENTS_DMAC_LOOKUP, 532 ANA_ANEVENTS_SMAC_LOOKUP, 533 ANA_ANEVENTS_SEQ_GEN_ERR_0, 534 ANA_ANEVENTS_SEQ_GEN_ERR_1, 535 ANA_TABLES_MACACCESS_B_DOM, 536 ANA_TABLES_MACTINDX_BUCKET, 537 ANA_TABLES_MACTINDX_M_INDEX, 538 QSYS_SWITCH_PORT_MODE_PORT_ENA, 539 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG, 540 QSYS_SWITCH_PORT_MODE_YEL_RSRVD, 541 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE, 542 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 543 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE, 544 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD, 545 QSYS_TIMED_FRAME_ENTRY_TFRM_FP, 546 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO, 547 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL, 548 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T, 549 SYS_PORT_MODE_DATA_WO_TS, 550 SYS_PORT_MODE_INCL_INJ_HDR, 551 SYS_PORT_MODE_INCL_XTR_HDR, 552 SYS_PORT_MODE_INCL_HDR_ERR, 553 SYS_RESET_CFG_CORE_ENA, 554 SYS_RESET_CFG_MEM_ENA, 555 SYS_RESET_CFG_MEM_INIT, 556 GCB_SOFT_RST_SWC_RST, 557 GCB_MIIM_MII_STATUS_PENDING, 558 GCB_MIIM_MII_STATUS_BUSY, 559 SYS_PAUSE_CFG_PAUSE_START, 560 SYS_PAUSE_CFG_PAUSE_STOP, 561 SYS_PAUSE_CFG_PAUSE_ENA, 562 REGFIELD_MAX 563 }; 564 565 enum { 566 /* VCAP_CORE_CFG */ 567 VCAP_CORE_UPDATE_CTRL, 568 VCAP_CORE_MV_CFG, 569 /* VCAP_CORE_CACHE */ 570 VCAP_CACHE_ENTRY_DAT, 571 VCAP_CACHE_MASK_DAT, 572 VCAP_CACHE_ACTION_DAT, 573 VCAP_CACHE_CNT_DAT, 574 VCAP_CACHE_TG_DAT, 575 /* VCAP_CONST */ 576 VCAP_CONST_VCAP_VER, 577 VCAP_CONST_ENTRY_WIDTH, 578 VCAP_CONST_ENTRY_CNT, 579 VCAP_CONST_ENTRY_SWCNT, 580 VCAP_CONST_ENTRY_TG_WIDTH, 581 VCAP_CONST_ACTION_DEF_CNT, 582 VCAP_CONST_ACTION_WIDTH, 583 VCAP_CONST_CNT_WIDTH, 584 VCAP_CONST_CORE_CNT, 585 VCAP_CONST_IF_CNT, 586 }; 587 588 enum ocelot_ptp_pins { 589 PTP_PIN_0, 590 PTP_PIN_1, 591 PTP_PIN_2, 592 PTP_PIN_3, 593 TOD_ACC_PIN 594 }; 595 596 enum ocelot_stat { 597 OCELOT_STAT_RX_OCTETS, 598 OCELOT_STAT_RX_UNICAST, 599 OCELOT_STAT_RX_MULTICAST, 600 OCELOT_STAT_RX_BROADCAST, 601 OCELOT_STAT_RX_SHORTS, 602 OCELOT_STAT_RX_FRAGMENTS, 603 OCELOT_STAT_RX_JABBERS, 604 OCELOT_STAT_RX_CRC_ALIGN_ERRS, 605 OCELOT_STAT_RX_SYM_ERRS, 606 OCELOT_STAT_RX_64, 607 OCELOT_STAT_RX_65_127, 608 OCELOT_STAT_RX_128_255, 609 OCELOT_STAT_RX_256_511, 610 OCELOT_STAT_RX_512_1023, 611 OCELOT_STAT_RX_1024_1526, 612 OCELOT_STAT_RX_1527_MAX, 613 OCELOT_STAT_RX_PAUSE, 614 OCELOT_STAT_RX_CONTROL, 615 OCELOT_STAT_RX_LONGS, 616 OCELOT_STAT_RX_CLASSIFIED_DROPS, 617 OCELOT_STAT_RX_RED_PRIO_0, 618 OCELOT_STAT_RX_RED_PRIO_1, 619 OCELOT_STAT_RX_RED_PRIO_2, 620 OCELOT_STAT_RX_RED_PRIO_3, 621 OCELOT_STAT_RX_RED_PRIO_4, 622 OCELOT_STAT_RX_RED_PRIO_5, 623 OCELOT_STAT_RX_RED_PRIO_6, 624 OCELOT_STAT_RX_RED_PRIO_7, 625 OCELOT_STAT_RX_YELLOW_PRIO_0, 626 OCELOT_STAT_RX_YELLOW_PRIO_1, 627 OCELOT_STAT_RX_YELLOW_PRIO_2, 628 OCELOT_STAT_RX_YELLOW_PRIO_3, 629 OCELOT_STAT_RX_YELLOW_PRIO_4, 630 OCELOT_STAT_RX_YELLOW_PRIO_5, 631 OCELOT_STAT_RX_YELLOW_PRIO_6, 632 OCELOT_STAT_RX_YELLOW_PRIO_7, 633 OCELOT_STAT_RX_GREEN_PRIO_0, 634 OCELOT_STAT_RX_GREEN_PRIO_1, 635 OCELOT_STAT_RX_GREEN_PRIO_2, 636 OCELOT_STAT_RX_GREEN_PRIO_3, 637 OCELOT_STAT_RX_GREEN_PRIO_4, 638 OCELOT_STAT_RX_GREEN_PRIO_5, 639 OCELOT_STAT_RX_GREEN_PRIO_6, 640 OCELOT_STAT_RX_GREEN_PRIO_7, 641 OCELOT_STAT_TX_OCTETS, 642 OCELOT_STAT_TX_UNICAST, 643 OCELOT_STAT_TX_MULTICAST, 644 OCELOT_STAT_TX_BROADCAST, 645 OCELOT_STAT_TX_COLLISION, 646 OCELOT_STAT_TX_DROPS, 647 OCELOT_STAT_TX_PAUSE, 648 OCELOT_STAT_TX_64, 649 OCELOT_STAT_TX_65_127, 650 OCELOT_STAT_TX_128_255, 651 OCELOT_STAT_TX_256_511, 652 OCELOT_STAT_TX_512_1023, 653 OCELOT_STAT_TX_1024_1526, 654 OCELOT_STAT_TX_1527_MAX, 655 OCELOT_STAT_TX_YELLOW_PRIO_0, 656 OCELOT_STAT_TX_YELLOW_PRIO_1, 657 OCELOT_STAT_TX_YELLOW_PRIO_2, 658 OCELOT_STAT_TX_YELLOW_PRIO_3, 659 OCELOT_STAT_TX_YELLOW_PRIO_4, 660 OCELOT_STAT_TX_YELLOW_PRIO_5, 661 OCELOT_STAT_TX_YELLOW_PRIO_6, 662 OCELOT_STAT_TX_YELLOW_PRIO_7, 663 OCELOT_STAT_TX_GREEN_PRIO_0, 664 OCELOT_STAT_TX_GREEN_PRIO_1, 665 OCELOT_STAT_TX_GREEN_PRIO_2, 666 OCELOT_STAT_TX_GREEN_PRIO_3, 667 OCELOT_STAT_TX_GREEN_PRIO_4, 668 OCELOT_STAT_TX_GREEN_PRIO_5, 669 OCELOT_STAT_TX_GREEN_PRIO_6, 670 OCELOT_STAT_TX_GREEN_PRIO_7, 671 OCELOT_STAT_TX_AGED, 672 OCELOT_STAT_DROP_LOCAL, 673 OCELOT_STAT_DROP_TAIL, 674 OCELOT_STAT_DROP_YELLOW_PRIO_0, 675 OCELOT_STAT_DROP_YELLOW_PRIO_1, 676 OCELOT_STAT_DROP_YELLOW_PRIO_2, 677 OCELOT_STAT_DROP_YELLOW_PRIO_3, 678 OCELOT_STAT_DROP_YELLOW_PRIO_4, 679 OCELOT_STAT_DROP_YELLOW_PRIO_5, 680 OCELOT_STAT_DROP_YELLOW_PRIO_6, 681 OCELOT_STAT_DROP_YELLOW_PRIO_7, 682 OCELOT_STAT_DROP_GREEN_PRIO_0, 683 OCELOT_STAT_DROP_GREEN_PRIO_1, 684 OCELOT_STAT_DROP_GREEN_PRIO_2, 685 OCELOT_STAT_DROP_GREEN_PRIO_3, 686 OCELOT_STAT_DROP_GREEN_PRIO_4, 687 OCELOT_STAT_DROP_GREEN_PRIO_5, 688 OCELOT_STAT_DROP_GREEN_PRIO_6, 689 OCELOT_STAT_DROP_GREEN_PRIO_7, 690 OCELOT_NUM_STATS, 691 }; 692 693 struct ocelot_stat_layout { 694 u32 reg; 695 char name[ETH_GSTRING_LEN]; 696 }; 697 698 struct ocelot_stats_region { 699 struct list_head node; 700 u32 base; 701 int count; 702 u32 *buf; 703 }; 704 705 enum ocelot_tag_prefix { 706 OCELOT_TAG_PREFIX_DISABLED = 0, 707 OCELOT_TAG_PREFIX_NONE, 708 OCELOT_TAG_PREFIX_SHORT, 709 OCELOT_TAG_PREFIX_LONG, 710 }; 711 712 struct ocelot; 713 714 struct ocelot_ops { 715 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port); 716 int (*netdev_to_port)(struct net_device *dev); 717 int (*reset)(struct ocelot *ocelot); 718 u16 (*wm_enc)(u16 value); 719 u16 (*wm_dec)(u16 value); 720 void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse); 721 void (*psfp_init)(struct ocelot *ocelot); 722 int (*psfp_filter_add)(struct ocelot *ocelot, int port, 723 struct flow_cls_offload *f); 724 int (*psfp_filter_del)(struct ocelot *ocelot, struct flow_cls_offload *f); 725 int (*psfp_stats_get)(struct ocelot *ocelot, struct flow_cls_offload *f, 726 struct flow_stats *stats); 727 void (*cut_through_fwd)(struct ocelot *ocelot); 728 void (*tas_clock_adjust)(struct ocelot *ocelot); 729 }; 730 731 struct ocelot_vcap_policer { 732 struct list_head pol_list; 733 u16 base; 734 u16 max; 735 u16 base2; 736 u16 max2; 737 }; 738 739 struct ocelot_vcap_block { 740 struct list_head rules; 741 int count; 742 }; 743 744 struct ocelot_bridge_vlan { 745 u16 vid; 746 unsigned long portmask; 747 unsigned long untagged; 748 struct list_head list; 749 }; 750 751 enum ocelot_port_tag_config { 752 /* all VLANs are egress-untagged */ 753 OCELOT_PORT_TAG_DISABLED = 0, 754 /* all VLANs except the native VLAN and VID 0 are egress-tagged */ 755 OCELOT_PORT_TAG_NATIVE = 1, 756 /* all VLANs except VID 0 are egress-tagged */ 757 OCELOT_PORT_TAG_TRUNK_NO_VID0 = 2, 758 /* all VLANs are egress-tagged */ 759 OCELOT_PORT_TAG_TRUNK = 3, 760 }; 761 762 struct ocelot_psfp_list { 763 struct list_head stream_list; 764 struct list_head sfi_list; 765 struct list_head sgi_list; 766 }; 767 768 enum ocelot_sb { 769 OCELOT_SB_BUF, 770 OCELOT_SB_REF, 771 OCELOT_SB_NUM, 772 }; 773 774 enum ocelot_sb_pool { 775 OCELOT_SB_POOL_ING, 776 OCELOT_SB_POOL_EGR, 777 OCELOT_SB_POOL_NUM, 778 }; 779 780 /* MAC table entry types. 781 * ENTRYTYPE_NORMAL is subject to aging. 782 * ENTRYTYPE_LOCKED is not subject to aging. 783 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 784 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 785 */ 786 enum macaccess_entry_type { 787 ENTRYTYPE_NORMAL = 0, 788 ENTRYTYPE_LOCKED, 789 ENTRYTYPE_MACv4, 790 ENTRYTYPE_MACv6, 791 }; 792 793 #define OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION BIT(0) 794 #define OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP BIT(1) 795 796 struct ocelot_lag_fdb { 797 unsigned char addr[ETH_ALEN]; 798 u16 vid; 799 struct net_device *bond; 800 struct list_head list; 801 }; 802 803 struct ocelot_mirror { 804 refcount_t refcount; 805 int to; 806 }; 807 808 struct ocelot_port; 809 810 struct ocelot_port { 811 struct ocelot *ocelot; 812 813 struct regmap *target; 814 815 struct net_device *bond; 816 struct net_device *bridge; 817 818 struct ocelot_port *dsa_8021q_cpu; 819 820 /* VLAN that untagged frames are classified to, on ingress */ 821 const struct ocelot_bridge_vlan *pvid_vlan; 822 823 struct tc_taprio_qopt_offload *taprio; 824 825 phy_interface_t phy_mode; 826 827 unsigned int ptp_skbs_in_flight; 828 struct sk_buff_head tx_skbs; 829 830 u16 mrp_ring_id; 831 832 u8 ptp_cmd; 833 u8 ts_id; 834 835 u8 index; 836 837 u8 stp_state; 838 bool vlan_aware; 839 bool is_dsa_8021q_cpu; 840 bool learn_ena; 841 842 bool lag_tx_active; 843 844 int bridge_num; 845 846 int speed; 847 }; 848 849 struct ocelot { 850 struct device *dev; 851 struct devlink *devlink; 852 struct devlink_port *devlink_ports; 853 854 const struct ocelot_ops *ops; 855 struct regmap *targets[TARGET_MAX]; 856 struct regmap_field *regfields[REGFIELD_MAX]; 857 const u32 *const *map; 858 const struct ocelot_stat_layout *stats_layout; 859 struct list_head stats_regions; 860 861 u32 pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM]; 862 int packet_buffer_size; 863 int num_frame_refs; 864 int num_mact_rows; 865 866 struct ocelot_port **ports; 867 868 u8 base_mac[ETH_ALEN]; 869 870 struct list_head vlans; 871 struct list_head traps; 872 struct list_head lag_fdbs; 873 874 /* Switches like VSC9959 have flooding per traffic class */ 875 int num_flooding_pgids; 876 877 /* In tables like ANA:PORT and the ANA:PGID:PGID mask, 878 * the CPU is located after the physical ports (at the 879 * num_phys_ports index). 880 */ 881 u8 num_phys_ports; 882 883 int npi; 884 885 enum ocelot_tag_prefix npi_inj_prefix; 886 enum ocelot_tag_prefix npi_xtr_prefix; 887 888 unsigned long bridges; 889 890 struct list_head multicast; 891 struct list_head pgids; 892 893 struct list_head dummy_rules; 894 struct ocelot_vcap_block block[3]; 895 struct ocelot_vcap_policer vcap_pol; 896 struct vcap_props *vcap; 897 struct ocelot_mirror *mirror; 898 899 struct ocelot_psfp_list psfp; 900 901 /* Workqueue to check statistics for overflow with its lock */ 902 spinlock_t stats_lock; 903 u64 *stats; 904 struct delayed_work stats_work; 905 struct workqueue_struct *stats_queue; 906 907 /* Lock for serializing access to the MAC table */ 908 struct mutex mact_lock; 909 /* Lock for serializing forwarding domain changes */ 910 struct mutex fwd_domain_lock; 911 912 /* Lock for serializing Time-Aware Shaper changes */ 913 struct mutex tas_lock; 914 915 struct workqueue_struct *owq; 916 917 u8 ptp:1; 918 struct ptp_clock *ptp_clock; 919 struct ptp_clock_info ptp_info; 920 struct hwtstamp_config hwtstamp_config; 921 unsigned int ptp_skbs_in_flight; 922 /* Protects the 2-step TX timestamp ID logic */ 923 spinlock_t ts_id_lock; 924 /* Protects the PTP interface state */ 925 struct mutex ptp_lock; 926 /* Protects the PTP clock */ 927 spinlock_t ptp_clock_lock; 928 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM]; 929 930 struct ocelot_fdma *fdma; 931 }; 932 933 struct ocelot_policer { 934 u32 rate; /* kilobit per second */ 935 u32 burst; /* bytes */ 936 }; 937 938 #define ocelot_bulk_read(ocelot, reg, buf, count) \ 939 __ocelot_bulk_read_ix(ocelot, reg, 0, buf, count) 940 941 #define ocelot_read_ix(ocelot, reg, gi, ri) \ 942 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 943 #define ocelot_read_gix(ocelot, reg, gi) \ 944 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi)) 945 #define ocelot_read_rix(ocelot, reg, ri) \ 946 __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri)) 947 #define ocelot_read(ocelot, reg) \ 948 __ocelot_read_ix(ocelot, reg, 0) 949 950 #define ocelot_write_ix(ocelot, val, reg, gi, ri) \ 951 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 952 #define ocelot_write_gix(ocelot, val, reg, gi) \ 953 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) 954 #define ocelot_write_rix(ocelot, val, reg, ri) \ 955 __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) 956 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) 957 958 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) \ 959 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 960 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) \ 961 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) 962 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) \ 963 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) 964 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) 965 966 #define ocelot_field_write(ocelot, reg, val) \ 967 regmap_field_write((ocelot)->regfields[(reg)], (val)) 968 #define ocelot_field_read(ocelot, reg, val) \ 969 regmap_field_read((ocelot)->regfields[(reg)], (val)) 970 #define ocelot_fields_write(ocelot, id, reg, val) \ 971 regmap_fields_write((ocelot)->regfields[(reg)], (id), (val)) 972 #define ocelot_fields_read(ocelot, id, reg, val) \ 973 regmap_fields_read((ocelot)->regfields[(reg)], (id), (val)) 974 975 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \ 976 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 977 #define ocelot_target_read_gix(ocelot, target, reg, gi) \ 978 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi)) 979 #define ocelot_target_read_rix(ocelot, target, reg, ri) \ 980 __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri)) 981 #define ocelot_target_read(ocelot, target, reg) \ 982 __ocelot_target_read_ix(ocelot, target, reg, 0) 983 984 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \ 985 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 986 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \ 987 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi)) 988 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \ 989 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri)) 990 #define ocelot_target_write(ocelot, target, val, reg) \ 991 __ocelot_target_write_ix(ocelot, target, val, reg, 0) 992 993 /* I/O */ 994 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg); 995 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg); 996 void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask, u32 reg); 997 int __ocelot_bulk_read_ix(struct ocelot *ocelot, u32 reg, u32 offset, void *buf, 998 int count); 999 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset); 1000 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset); 1001 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, 1002 u32 offset); 1003 u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target, 1004 u32 reg, u32 offset); 1005 void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target, 1006 u32 val, u32 reg, u32 offset); 1007 1008 /* Packet I/O */ 1009 bool ocelot_can_inject(struct ocelot *ocelot, int grp); 1010 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 1011 u32 rew_op, struct sk_buff *skb); 1012 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag); 1013 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **skb); 1014 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp); 1015 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb, 1016 u64 timestamp); 1017 1018 /* Hardware initialization */ 1019 int ocelot_regfields_init(struct ocelot *ocelot, 1020 const struct reg_field *const regfields); 1021 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res); 1022 int ocelot_init(struct ocelot *ocelot); 1023 void ocelot_deinit(struct ocelot *ocelot); 1024 void ocelot_init_port(struct ocelot *ocelot, int port); 1025 void ocelot_deinit_port(struct ocelot *ocelot, int port); 1026 1027 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, int cpu); 1028 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port); 1029 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port); 1030 1031 /* DSA callbacks */ 1032 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data); 1033 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data); 1034 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset); 1035 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1036 struct ethtool_ts_info *info); 1037 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs); 1038 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled, 1039 struct netlink_ext_ack *extack); 1040 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state); 1041 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port); 1042 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 1043 struct switchdev_brport_flags val); 1044 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 1045 struct switchdev_brport_flags val); 1046 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port); 1047 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio); 1048 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp); 1049 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio); 1050 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio); 1051 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1052 struct net_device *bridge, int bridge_num, 1053 struct netlink_ext_ack *extack); 1054 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1055 struct net_device *bridge); 1056 int ocelot_mact_flush(struct ocelot *ocelot, int port); 1057 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1058 dsa_fdb_dump_cb_t *cb, void *data); 1059 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr, 1060 u16 vid, const struct net_device *bridge); 1061 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr, 1062 u16 vid, const struct net_device *bridge); 1063 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond, 1064 const unsigned char *addr, u16 vid, 1065 const struct net_device *bridge); 1066 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond, 1067 const unsigned char *addr, u16 vid, 1068 const struct net_device *bridge); 1069 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 1070 bool untagged, struct netlink_ext_ack *extack); 1071 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 1072 bool untagged); 1073 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid); 1074 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr); 1075 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr); 1076 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 1077 struct sk_buff *skb, 1078 struct sk_buff **clone); 1079 void ocelot_get_txtstamp(struct ocelot *ocelot); 1080 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu); 1081 int ocelot_get_max_mtu(struct ocelot *ocelot, int port); 1082 int ocelot_port_policer_add(struct ocelot *ocelot, int port, 1083 struct ocelot_policer *pol); 1084 int ocelot_port_policer_del(struct ocelot *ocelot, int port); 1085 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to, 1086 bool ingress, struct netlink_ext_ack *extack); 1087 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress); 1088 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port, 1089 struct flow_cls_offload *f, bool ingress); 1090 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port, 1091 struct flow_cls_offload *f, bool ingress); 1092 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port, 1093 struct flow_cls_offload *f, bool ingress); 1094 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1095 const struct switchdev_obj_port_mdb *mdb, 1096 const struct net_device *bridge); 1097 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1098 const struct switchdev_obj_port_mdb *mdb, 1099 const struct net_device *bridge); 1100 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1101 struct net_device *bond, 1102 struct netdev_lag_upper_info *info); 1103 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1104 struct net_device *bond); 1105 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active); 1106 1107 int ocelot_devlink_sb_register(struct ocelot *ocelot); 1108 void ocelot_devlink_sb_unregister(struct ocelot *ocelot); 1109 int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index, 1110 u16 pool_index, 1111 struct devlink_sb_pool_info *pool_info); 1112 int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index, 1113 u16 pool_index, u32 size, 1114 enum devlink_sb_threshold_type threshold_type, 1115 struct netlink_ext_ack *extack); 1116 int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port, 1117 unsigned int sb_index, u16 pool_index, 1118 u32 *p_threshold); 1119 int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port, 1120 unsigned int sb_index, u16 pool_index, 1121 u32 threshold, struct netlink_ext_ack *extack); 1122 int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port, 1123 unsigned int sb_index, u16 tc_index, 1124 enum devlink_sb_pool_type pool_type, 1125 u16 *p_pool_index, u32 *p_threshold); 1126 int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port, 1127 unsigned int sb_index, u16 tc_index, 1128 enum devlink_sb_pool_type pool_type, 1129 u16 pool_index, u32 threshold, 1130 struct netlink_ext_ack *extack); 1131 int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index); 1132 int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index); 1133 int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port, 1134 unsigned int sb_index, u16 pool_index, 1135 u32 *p_cur, u32 *p_max); 1136 int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port, 1137 unsigned int sb_index, u16 tc_index, 1138 enum devlink_sb_pool_type pool_type, 1139 u32 *p_cur, u32 *p_max); 1140 1141 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 1142 unsigned int link_an_mode, 1143 phy_interface_t interface, 1144 unsigned long quirks); 1145 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 1146 struct phy_device *phydev, 1147 unsigned int link_an_mode, 1148 phy_interface_t interface, 1149 int speed, int duplex, 1150 bool tx_pause, bool rx_pause, 1151 unsigned long quirks); 1152 1153 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx, 1154 const unsigned char mac[ETH_ALEN], 1155 unsigned int vid, enum macaccess_entry_type *type); 1156 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx, 1157 const unsigned char mac[ETH_ALEN], 1158 unsigned int vid, 1159 enum macaccess_entry_type type, 1160 int sfid, int ssid); 1161 1162 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask, 1163 unsigned long to_mask); 1164 1165 int ocelot_vcap_policer_add(struct ocelot *ocelot, u32 pol_ix, 1166 struct ocelot_policer *pol); 1167 int ocelot_vcap_policer_del(struct ocelot *ocelot, u32 pol_ix); 1168 1169 #if IS_ENABLED(CONFIG_BRIDGE_MRP) 1170 int ocelot_mrp_add(struct ocelot *ocelot, int port, 1171 const struct switchdev_obj_mrp *mrp); 1172 int ocelot_mrp_del(struct ocelot *ocelot, int port, 1173 const struct switchdev_obj_mrp *mrp); 1174 int ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port, 1175 const struct switchdev_obj_ring_role_mrp *mrp); 1176 int ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, 1177 const struct switchdev_obj_ring_role_mrp *mrp); 1178 #else 1179 static inline int ocelot_mrp_add(struct ocelot *ocelot, int port, 1180 const struct switchdev_obj_mrp *mrp) 1181 { 1182 return -EOPNOTSUPP; 1183 } 1184 1185 static inline int ocelot_mrp_del(struct ocelot *ocelot, int port, 1186 const struct switchdev_obj_mrp *mrp) 1187 { 1188 return -EOPNOTSUPP; 1189 } 1190 1191 static inline int 1192 ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port, 1193 const struct switchdev_obj_ring_role_mrp *mrp) 1194 { 1195 return -EOPNOTSUPP; 1196 } 1197 1198 static inline int 1199 ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, 1200 const struct switchdev_obj_ring_role_mrp *mrp) 1201 { 1202 return -EOPNOTSUPP; 1203 } 1204 #endif 1205 1206 #endif 1207