1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* Copyright (c) 2017 Microsemi Corporation 3 */ 4 5 #ifndef _SOC_MSCC_OCELOT_H 6 #define _SOC_MSCC_OCELOT_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/net_tstamp.h> 10 #include <linux/if_vlan.h> 11 #include <linux/regmap.h> 12 #include <net/dsa.h> 13 14 /* Port Group IDs (PGID) are masks of destination ports. 15 * 16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each 17 * frame, and forwards the frame to the ports that are present in the logical 18 * AND of all 3 PGIDs. 19 * 20 * These PGID lookups are: 21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by 22 * which the switch selects a destination PGID: 23 * - The {DMAC, VID} is present in the MAC table. In that case, the 24 * destination PGID is given by the DEST_IDX field of the MAC table entry 25 * that matched. 26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The 27 * frame is disseminated as being either unicast, multicast or broadcast, 28 * and according to that, the destination PGID is chosen as being the 29 * value contained by ANA_FLOODING_FLD_UNICAST, 30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST. 31 * The destination PGID can be an unicast set: the first PGIDs, 0 to 32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from 33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to 34 * a physical port and has a single bit set in the destination ports mask: 35 * that corresponding to the port number itself. In contrast, a multicast 36 * PGID will have potentially more than one single bit set in the destination 37 * ports mask. 38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier 39 * dissects each frame and generates a 4-bit Link Aggregation Code which is 40 * used for this second PGID table lookup. The goal of link aggregation is to 41 * hash multiple flows within the same LAG on to different destination ports. 42 * The first lookup will result in a PGID with all the LAG members present in 43 * the destination ports mask, and the second lookup, by Link Aggregation 44 * Code, will ensure that each flow gets forwarded only to a single port out 45 * of that mask (there are no duplicates). 46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table 47 * is indexed with the ingress port (plus 80). These PGIDs answer the 48 * question "is port i allowed to forward traffic to port j?" If yes, then 49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used 50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge. 51 */ 52 53 /* Reserve some destination PGIDs at the end of the range: 54 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses 55 * of the switch port net devices, towards the CPU port module. 56 * PGID_UC: the flooding destinations for unknown unicast traffic. 57 * PGID_MC: the flooding destinations for broadcast and non-IP multicast 58 * traffic. 59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic. 60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic. 61 */ 62 #define PGID_CPU 59 63 #define PGID_UC 60 64 #define PGID_MC 61 65 #define PGID_MCIPV4 62 66 #define PGID_MCIPV6 63 67 68 #define for_each_unicast_dest_pgid(ocelot, pgid) \ 69 for ((pgid) = 0; \ 70 (pgid) < (ocelot)->num_phys_ports; \ 71 (pgid)++) 72 73 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \ 74 for ((pgid) = (ocelot)->num_phys_ports + 1; \ 75 (pgid) < PGID_CPU; \ 76 (pgid)++) 77 78 #define for_each_aggr_pgid(ocelot, pgid) \ 79 for ((pgid) = PGID_AGGR; \ 80 (pgid) < PGID_SRC; \ 81 (pgid)++) 82 83 /* Aggregation PGIDs, one per Link Aggregation Code */ 84 #define PGID_AGGR 64 85 86 /* Source PGIDs, one per physical port */ 87 #define PGID_SRC 80 88 89 #define IFH_INJ_BYPASS BIT(31) 90 #define IFH_INJ_POP_CNT_DISABLE (3 << 28) 91 92 #define IFH_TAG_TYPE_C 0 93 #define IFH_TAG_TYPE_S 1 94 95 #define IFH_REW_OP_NOOP 0x0 96 #define IFH_REW_OP_DSCP 0x1 97 #define IFH_REW_OP_ONE_STEP_PTP 0x2 98 #define IFH_REW_OP_TWO_STEP_PTP 0x3 99 #define IFH_REW_OP_ORIGIN_PTP 0x5 100 101 #define OCELOT_TAG_LEN 16 102 #define OCELOT_SHORT_PREFIX_LEN 4 103 #define OCELOT_LONG_PREFIX_LEN 16 104 105 #define OCELOT_SPEED_2500 0 106 #define OCELOT_SPEED_1000 1 107 #define OCELOT_SPEED_100 2 108 #define OCELOT_SPEED_10 3 109 110 #define OCELOT_PTP_PINS_NUM 4 111 112 #define TARGET_OFFSET 24 113 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0) 114 #define REG(reg, offset) [reg & REG_MASK] = offset 115 116 #define REG_RESERVED_ADDR 0xffffffff 117 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR) 118 119 enum ocelot_target { 120 ANA = 1, 121 QS, 122 QSYS, 123 REW, 124 SYS, 125 S2, 126 HSIO, 127 PTP, 128 GCB, 129 TARGET_MAX, 130 }; 131 132 enum ocelot_reg { 133 ANA_ADVLEARN = ANA << TARGET_OFFSET, 134 ANA_VLANMASK, 135 ANA_PORT_B_DOMAIN, 136 ANA_ANAGEFIL, 137 ANA_ANEVENTS, 138 ANA_STORMLIMIT_BURST, 139 ANA_STORMLIMIT_CFG, 140 ANA_ISOLATED_PORTS, 141 ANA_COMMUNITY_PORTS, 142 ANA_AUTOAGE, 143 ANA_MACTOPTIONS, 144 ANA_LEARNDISC, 145 ANA_AGENCTRL, 146 ANA_MIRRORPORTS, 147 ANA_EMIRRORPORTS, 148 ANA_FLOODING, 149 ANA_FLOODING_IPMC, 150 ANA_SFLOW_CFG, 151 ANA_PORT_MODE, 152 ANA_CUT_THRU_CFG, 153 ANA_PGID_PGID, 154 ANA_TABLES_ANMOVED, 155 ANA_TABLES_MACHDATA, 156 ANA_TABLES_MACLDATA, 157 ANA_TABLES_STREAMDATA, 158 ANA_TABLES_MACACCESS, 159 ANA_TABLES_MACTINDX, 160 ANA_TABLES_VLANACCESS, 161 ANA_TABLES_VLANTIDX, 162 ANA_TABLES_ISDXACCESS, 163 ANA_TABLES_ISDXTIDX, 164 ANA_TABLES_ENTRYLIM, 165 ANA_TABLES_PTP_ID_HIGH, 166 ANA_TABLES_PTP_ID_LOW, 167 ANA_TABLES_STREAMACCESS, 168 ANA_TABLES_STREAMTIDX, 169 ANA_TABLES_SEQ_HISTORY, 170 ANA_TABLES_SEQ_MASK, 171 ANA_TABLES_SFID_MASK, 172 ANA_TABLES_SFIDACCESS, 173 ANA_TABLES_SFIDTIDX, 174 ANA_MSTI_STATE, 175 ANA_OAM_UPM_LM_CNT, 176 ANA_SG_ACCESS_CTRL, 177 ANA_SG_CONFIG_REG_1, 178 ANA_SG_CONFIG_REG_2, 179 ANA_SG_CONFIG_REG_3, 180 ANA_SG_CONFIG_REG_4, 181 ANA_SG_CONFIG_REG_5, 182 ANA_SG_GCL_GS_CONFIG, 183 ANA_SG_GCL_TI_CONFIG, 184 ANA_SG_STATUS_REG_1, 185 ANA_SG_STATUS_REG_2, 186 ANA_SG_STATUS_REG_3, 187 ANA_PORT_VLAN_CFG, 188 ANA_PORT_DROP_CFG, 189 ANA_PORT_QOS_CFG, 190 ANA_PORT_VCAP_CFG, 191 ANA_PORT_VCAP_S1_KEY_CFG, 192 ANA_PORT_VCAP_S2_CFG, 193 ANA_PORT_PCP_DEI_MAP, 194 ANA_PORT_CPU_FWD_CFG, 195 ANA_PORT_CPU_FWD_BPDU_CFG, 196 ANA_PORT_CPU_FWD_GARP_CFG, 197 ANA_PORT_CPU_FWD_CCM_CFG, 198 ANA_PORT_PORT_CFG, 199 ANA_PORT_POL_CFG, 200 ANA_PORT_PTP_CFG, 201 ANA_PORT_PTP_DLY1_CFG, 202 ANA_PORT_PTP_DLY2_CFG, 203 ANA_PORT_SFID_CFG, 204 ANA_PFC_PFC_CFG, 205 ANA_PFC_PFC_TIMER, 206 ANA_IPT_OAM_MEP_CFG, 207 ANA_IPT_IPT, 208 ANA_PPT_PPT, 209 ANA_FID_MAP_FID_MAP, 210 ANA_AGGR_CFG, 211 ANA_CPUQ_CFG, 212 ANA_CPUQ_CFG2, 213 ANA_CPUQ_8021_CFG, 214 ANA_DSCP_CFG, 215 ANA_DSCP_REWR_CFG, 216 ANA_VCAP_RNG_TYPE_CFG, 217 ANA_VCAP_RNG_VAL_CFG, 218 ANA_VRAP_CFG, 219 ANA_VRAP_HDR_DATA, 220 ANA_VRAP_HDR_MASK, 221 ANA_DISCARD_CFG, 222 ANA_FID_CFG, 223 ANA_POL_PIR_CFG, 224 ANA_POL_CIR_CFG, 225 ANA_POL_MODE_CFG, 226 ANA_POL_PIR_STATE, 227 ANA_POL_CIR_STATE, 228 ANA_POL_STATE, 229 ANA_POL_FLOWC, 230 ANA_POL_HYST, 231 ANA_POL_MISC_CFG, 232 QS_XTR_GRP_CFG = QS << TARGET_OFFSET, 233 QS_XTR_RD, 234 QS_XTR_FRM_PRUNING, 235 QS_XTR_FLUSH, 236 QS_XTR_DATA_PRESENT, 237 QS_XTR_CFG, 238 QS_INJ_GRP_CFG, 239 QS_INJ_WR, 240 QS_INJ_CTRL, 241 QS_INJ_STATUS, 242 QS_INJ_ERR, 243 QS_INH_DBG, 244 QSYS_PORT_MODE = QSYS << TARGET_OFFSET, 245 QSYS_SWITCH_PORT_MODE, 246 QSYS_STAT_CNT_CFG, 247 QSYS_EEE_CFG, 248 QSYS_EEE_THRES, 249 QSYS_IGR_NO_SHARING, 250 QSYS_EGR_NO_SHARING, 251 QSYS_SW_STATUS, 252 QSYS_EXT_CPU_CFG, 253 QSYS_PAD_CFG, 254 QSYS_CPU_GROUP_MAP, 255 QSYS_QMAP, 256 QSYS_ISDX_SGRP, 257 QSYS_TIMED_FRAME_ENTRY, 258 QSYS_TFRM_MISC, 259 QSYS_TFRM_PORT_DLY, 260 QSYS_TFRM_TIMER_CFG_1, 261 QSYS_TFRM_TIMER_CFG_2, 262 QSYS_TFRM_TIMER_CFG_3, 263 QSYS_TFRM_TIMER_CFG_4, 264 QSYS_TFRM_TIMER_CFG_5, 265 QSYS_TFRM_TIMER_CFG_6, 266 QSYS_TFRM_TIMER_CFG_7, 267 QSYS_TFRM_TIMER_CFG_8, 268 QSYS_RED_PROFILE, 269 QSYS_RES_QOS_MODE, 270 QSYS_RES_CFG, 271 QSYS_RES_STAT, 272 QSYS_EGR_DROP_MODE, 273 QSYS_EQ_CTRL, 274 QSYS_EVENTS_CORE, 275 QSYS_QMAXSDU_CFG_0, 276 QSYS_QMAXSDU_CFG_1, 277 QSYS_QMAXSDU_CFG_2, 278 QSYS_QMAXSDU_CFG_3, 279 QSYS_QMAXSDU_CFG_4, 280 QSYS_QMAXSDU_CFG_5, 281 QSYS_QMAXSDU_CFG_6, 282 QSYS_QMAXSDU_CFG_7, 283 QSYS_PREEMPTION_CFG, 284 QSYS_CIR_CFG, 285 QSYS_EIR_CFG, 286 QSYS_SE_CFG, 287 QSYS_SE_DWRR_CFG, 288 QSYS_SE_CONNECT, 289 QSYS_SE_DLB_SENSE, 290 QSYS_CIR_STATE, 291 QSYS_EIR_STATE, 292 QSYS_SE_STATE, 293 QSYS_HSCH_MISC_CFG, 294 QSYS_TAG_CONFIG, 295 QSYS_TAS_PARAM_CFG_CTRL, 296 QSYS_PORT_MAX_SDU, 297 QSYS_PARAM_CFG_REG_1, 298 QSYS_PARAM_CFG_REG_2, 299 QSYS_PARAM_CFG_REG_3, 300 QSYS_PARAM_CFG_REG_4, 301 QSYS_PARAM_CFG_REG_5, 302 QSYS_GCL_CFG_REG_1, 303 QSYS_GCL_CFG_REG_2, 304 QSYS_PARAM_STATUS_REG_1, 305 QSYS_PARAM_STATUS_REG_2, 306 QSYS_PARAM_STATUS_REG_3, 307 QSYS_PARAM_STATUS_REG_4, 308 QSYS_PARAM_STATUS_REG_5, 309 QSYS_PARAM_STATUS_REG_6, 310 QSYS_PARAM_STATUS_REG_7, 311 QSYS_PARAM_STATUS_REG_8, 312 QSYS_PARAM_STATUS_REG_9, 313 QSYS_GCL_STATUS_REG_1, 314 QSYS_GCL_STATUS_REG_2, 315 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET, 316 REW_TAG_CFG, 317 REW_PORT_CFG, 318 REW_DSCP_CFG, 319 REW_PCP_DEI_QOS_MAP_CFG, 320 REW_PTP_CFG, 321 REW_PTP_DLY1_CFG, 322 REW_RED_TAG_CFG, 323 REW_DSCP_REMAP_DP1_CFG, 324 REW_DSCP_REMAP_CFG, 325 REW_STAT_CFG, 326 REW_REW_STICKY, 327 REW_PPT, 328 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET, 329 SYS_COUNT_RX_UNICAST, 330 SYS_COUNT_RX_MULTICAST, 331 SYS_COUNT_RX_BROADCAST, 332 SYS_COUNT_RX_SHORTS, 333 SYS_COUNT_RX_FRAGMENTS, 334 SYS_COUNT_RX_JABBERS, 335 SYS_COUNT_RX_CRC_ALIGN_ERRS, 336 SYS_COUNT_RX_SYM_ERRS, 337 SYS_COUNT_RX_64, 338 SYS_COUNT_RX_65_127, 339 SYS_COUNT_RX_128_255, 340 SYS_COUNT_RX_256_1023, 341 SYS_COUNT_RX_1024_1526, 342 SYS_COUNT_RX_1527_MAX, 343 SYS_COUNT_RX_PAUSE, 344 SYS_COUNT_RX_CONTROL, 345 SYS_COUNT_RX_LONGS, 346 SYS_COUNT_RX_CLASSIFIED_DROPS, 347 SYS_COUNT_TX_OCTETS, 348 SYS_COUNT_TX_UNICAST, 349 SYS_COUNT_TX_MULTICAST, 350 SYS_COUNT_TX_BROADCAST, 351 SYS_COUNT_TX_COLLISION, 352 SYS_COUNT_TX_DROPS, 353 SYS_COUNT_TX_PAUSE, 354 SYS_COUNT_TX_64, 355 SYS_COUNT_TX_65_127, 356 SYS_COUNT_TX_128_511, 357 SYS_COUNT_TX_512_1023, 358 SYS_COUNT_TX_1024_1526, 359 SYS_COUNT_TX_1527_MAX, 360 SYS_COUNT_TX_AGING, 361 SYS_RESET_CFG, 362 SYS_SR_ETYPE_CFG, 363 SYS_VLAN_ETYPE_CFG, 364 SYS_PORT_MODE, 365 SYS_FRONT_PORT_MODE, 366 SYS_FRM_AGING, 367 SYS_STAT_CFG, 368 SYS_SW_STATUS, 369 SYS_MISC_CFG, 370 SYS_REW_MAC_HIGH_CFG, 371 SYS_REW_MAC_LOW_CFG, 372 SYS_TIMESTAMP_OFFSET, 373 SYS_CMID, 374 SYS_PAUSE_CFG, 375 SYS_PAUSE_TOT_CFG, 376 SYS_ATOP, 377 SYS_ATOP_TOT_CFG, 378 SYS_MAC_FC_CFG, 379 SYS_MMGT, 380 SYS_MMGT_FAST, 381 SYS_EVENTS_DIF, 382 SYS_EVENTS_CORE, 383 SYS_CNT, 384 SYS_PTP_STATUS, 385 SYS_PTP_TXSTAMP, 386 SYS_PTP_NXT, 387 SYS_PTP_CFG, 388 SYS_RAM_INIT, 389 SYS_CM_ADDR, 390 SYS_CM_DATA_WR, 391 SYS_CM_DATA_RD, 392 SYS_CM_OP, 393 SYS_CM_DATA, 394 S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET, 395 S2_CORE_MV_CFG, 396 S2_CACHE_ENTRY_DAT, 397 S2_CACHE_MASK_DAT, 398 S2_CACHE_ACTION_DAT, 399 S2_CACHE_CNT_DAT, 400 S2_CACHE_TG_DAT, 401 PTP_PIN_CFG = PTP << TARGET_OFFSET, 402 PTP_PIN_TOD_SEC_MSB, 403 PTP_PIN_TOD_SEC_LSB, 404 PTP_PIN_TOD_NSEC, 405 PTP_PIN_WF_HIGH_PERIOD, 406 PTP_PIN_WF_LOW_PERIOD, 407 PTP_CFG_MISC, 408 PTP_CLK_CFG_ADJ_CFG, 409 PTP_CLK_CFG_ADJ_FREQ, 410 GCB_SOFT_RST = GCB << TARGET_OFFSET, 411 }; 412 413 enum ocelot_regfield { 414 ANA_ADVLEARN_VLAN_CHK, 415 ANA_ADVLEARN_LEARN_MIRROR, 416 ANA_ANEVENTS_FLOOD_DISCARD, 417 ANA_ANEVENTS_MSTI_DROP, 418 ANA_ANEVENTS_ACLKILL, 419 ANA_ANEVENTS_ACLUSED, 420 ANA_ANEVENTS_AUTOAGE, 421 ANA_ANEVENTS_VS2TTL1, 422 ANA_ANEVENTS_STORM_DROP, 423 ANA_ANEVENTS_LEARN_DROP, 424 ANA_ANEVENTS_AGED_ENTRY, 425 ANA_ANEVENTS_CPU_LEARN_FAILED, 426 ANA_ANEVENTS_AUTO_LEARN_FAILED, 427 ANA_ANEVENTS_LEARN_REMOVE, 428 ANA_ANEVENTS_AUTO_LEARNED, 429 ANA_ANEVENTS_AUTO_MOVED, 430 ANA_ANEVENTS_DROPPED, 431 ANA_ANEVENTS_CLASSIFIED_DROP, 432 ANA_ANEVENTS_CLASSIFIED_COPY, 433 ANA_ANEVENTS_VLAN_DISCARD, 434 ANA_ANEVENTS_FWD_DISCARD, 435 ANA_ANEVENTS_MULTICAST_FLOOD, 436 ANA_ANEVENTS_UNICAST_FLOOD, 437 ANA_ANEVENTS_DEST_KNOWN, 438 ANA_ANEVENTS_BUCKET3_MATCH, 439 ANA_ANEVENTS_BUCKET2_MATCH, 440 ANA_ANEVENTS_BUCKET1_MATCH, 441 ANA_ANEVENTS_BUCKET0_MATCH, 442 ANA_ANEVENTS_CPU_OPERATION, 443 ANA_ANEVENTS_DMAC_LOOKUP, 444 ANA_ANEVENTS_SMAC_LOOKUP, 445 ANA_ANEVENTS_SEQ_GEN_ERR_0, 446 ANA_ANEVENTS_SEQ_GEN_ERR_1, 447 ANA_TABLES_MACACCESS_B_DOM, 448 ANA_TABLES_MACTINDX_BUCKET, 449 ANA_TABLES_MACTINDX_M_INDEX, 450 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD, 451 QSYS_TIMED_FRAME_ENTRY_TFRM_FP, 452 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO, 453 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL, 454 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T, 455 SYS_RESET_CFG_CORE_ENA, 456 SYS_RESET_CFG_MEM_ENA, 457 SYS_RESET_CFG_MEM_INIT, 458 GCB_SOFT_RST_SWC_RST, 459 REGFIELD_MAX 460 }; 461 462 enum ocelot_ptp_pins { 463 PTP_PIN_0, 464 PTP_PIN_1, 465 PTP_PIN_2, 466 PTP_PIN_3, 467 TOD_ACC_PIN 468 }; 469 470 struct ocelot_stat_layout { 471 u32 offset; 472 char name[ETH_GSTRING_LEN]; 473 }; 474 475 enum ocelot_tag_prefix { 476 OCELOT_TAG_PREFIX_DISABLED = 0, 477 OCELOT_TAG_PREFIX_NONE, 478 OCELOT_TAG_PREFIX_SHORT, 479 OCELOT_TAG_PREFIX_LONG, 480 }; 481 482 struct ocelot; 483 484 struct ocelot_ops { 485 int (*reset)(struct ocelot *ocelot); 486 }; 487 488 struct ocelot_vcap_block { 489 struct list_head rules; 490 int count; 491 int pol_lpr; 492 }; 493 494 struct ocelot_port { 495 struct ocelot *ocelot; 496 497 void __iomem *regs; 498 499 bool vlan_aware; 500 501 /* Ingress default VLAN (pvid) */ 502 u16 pvid; 503 504 /* Egress default VLAN (vid) */ 505 u16 vid; 506 507 u8 ptp_cmd; 508 struct sk_buff_head tx_skbs; 509 u8 ts_id; 510 511 phy_interface_t phy_mode; 512 }; 513 514 struct ocelot { 515 struct device *dev; 516 517 const struct ocelot_ops *ops; 518 struct regmap *targets[TARGET_MAX]; 519 struct regmap_field *regfields[REGFIELD_MAX]; 520 const u32 *const *map; 521 const struct ocelot_stat_layout *stats_layout; 522 unsigned int num_stats; 523 524 int shared_queue_sz; 525 int num_mact_rows; 526 527 struct net_device *hw_bridge_dev; 528 u16 bridge_mask; 529 u16 bridge_fwd_mask; 530 531 struct ocelot_port **ports; 532 533 u8 base_mac[ETH_ALEN]; 534 535 /* Keep track of the vlan port masks */ 536 u32 vlan_mask[VLAN_N_VID]; 537 538 /* In tables like ANA:PORT and the ANA:PGID:PGID mask, 539 * the CPU is located after the physical ports (at the 540 * num_phys_ports index). 541 */ 542 u8 num_phys_ports; 543 544 int npi; 545 546 enum ocelot_tag_prefix inj_prefix; 547 enum ocelot_tag_prefix xtr_prefix; 548 549 u32 *lags; 550 551 struct list_head multicast; 552 553 struct ocelot_vcap_block block; 554 555 const struct vcap_field *vcap_is2_keys; 556 const struct vcap_field *vcap_is2_actions; 557 const struct vcap_props *vcap; 558 559 /* Workqueue to check statistics for overflow with its lock */ 560 struct mutex stats_lock; 561 u64 *stats; 562 struct delayed_work stats_work; 563 struct workqueue_struct *stats_queue; 564 565 u8 ptp:1; 566 struct ptp_clock *ptp_clock; 567 struct ptp_clock_info ptp_info; 568 struct hwtstamp_config hwtstamp_config; 569 /* Protects the PTP interface state */ 570 struct mutex ptp_lock; 571 /* Protects the PTP clock */ 572 spinlock_t ptp_clock_lock; 573 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM]; 574 }; 575 576 struct ocelot_policer { 577 u32 rate; /* kilobit per second */ 578 u32 burst; /* bytes */ 579 }; 580 581 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 582 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi)) 583 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri)) 584 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0) 585 586 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 587 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) 588 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) 589 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) 590 591 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 592 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) 593 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) 594 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) 595 596 /* I/O */ 597 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg); 598 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg); 599 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset); 600 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset); 601 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, 602 u32 offset); 603 604 /* Hardware initialization */ 605 int ocelot_regfields_init(struct ocelot *ocelot, 606 const struct reg_field *const regfields); 607 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res); 608 void ocelot_configure_cpu(struct ocelot *ocelot, int npi, 609 enum ocelot_tag_prefix injection, 610 enum ocelot_tag_prefix extraction); 611 int ocelot_init(struct ocelot *ocelot); 612 void ocelot_deinit(struct ocelot *ocelot); 613 void ocelot_init_port(struct ocelot *ocelot, int port); 614 615 /* DSA callbacks */ 616 void ocelot_port_enable(struct ocelot *ocelot, int port, 617 struct phy_device *phy); 618 void ocelot_port_disable(struct ocelot *ocelot, int port); 619 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data); 620 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data); 621 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset); 622 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 623 struct ethtool_ts_info *info); 624 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs); 625 void ocelot_adjust_link(struct ocelot *ocelot, int port, 626 struct phy_device *phydev); 627 void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 628 bool vlan_aware); 629 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state); 630 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 631 struct net_device *bridge); 632 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 633 struct net_device *bridge); 634 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 635 dsa_fdb_dump_cb_t *cb, void *data); 636 int ocelot_fdb_add(struct ocelot *ocelot, int port, 637 const unsigned char *addr, u16 vid); 638 int ocelot_fdb_del(struct ocelot *ocelot, int port, 639 const unsigned char *addr, u16 vid); 640 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 641 bool untagged); 642 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid); 643 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr); 644 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr); 645 int ocelot_port_add_txtstamp_skb(struct ocelot_port *ocelot_port, 646 struct sk_buff *skb); 647 void ocelot_get_txtstamp(struct ocelot *ocelot); 648 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu); 649 int ocelot_get_max_mtu(struct ocelot *ocelot, int port); 650 int ocelot_port_policer_add(struct ocelot *ocelot, int port, 651 struct ocelot_policer *pol); 652 int ocelot_port_policer_del(struct ocelot *ocelot, int port); 653 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port, 654 struct flow_cls_offload *f, bool ingress); 655 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port, 656 struct flow_cls_offload *f, bool ingress); 657 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port, 658 struct flow_cls_offload *f, bool ingress); 659 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 660 const struct switchdev_obj_port_mdb *mdb); 661 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 662 const struct switchdev_obj_port_mdb *mdb); 663 664 #endif 665