1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. 3 * 4 * Authors: Shlomi Gridish <gridish@freescale.com> 5 * Li Yang <leoli@freescale.com> 6 * 7 * Description: 8 * QUICC Engine (QE) external definitions and structure. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 #ifndef _ASM_POWERPC_QE_H 16 #define _ASM_POWERPC_QE_H 17 #ifdef __KERNEL__ 18 19 #include <linux/compiler.h> 20 #include <linux/genalloc.h> 21 #include <linux/spinlock.h> 22 #include <linux/errno.h> 23 #include <linux/err.h> 24 #include <asm/cpm.h> 25 #include <soc/fsl/qe/immap_qe.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 #include <linux/types.h> 29 30 #define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */ 31 #define QE_NUM_OF_BRGS 16 32 #define QE_NUM_OF_PORTS 1024 33 34 /* Memory partitions 35 */ 36 #define MEM_PART_SYSTEM 0 37 #define MEM_PART_SECONDARY 1 38 #define MEM_PART_MURAM 2 39 40 /* Clocks and BRGs */ 41 enum qe_clock { 42 QE_CLK_NONE = 0, 43 QE_BRG1, /* Baud Rate Generator 1 */ 44 QE_BRG2, /* Baud Rate Generator 2 */ 45 QE_BRG3, /* Baud Rate Generator 3 */ 46 QE_BRG4, /* Baud Rate Generator 4 */ 47 QE_BRG5, /* Baud Rate Generator 5 */ 48 QE_BRG6, /* Baud Rate Generator 6 */ 49 QE_BRG7, /* Baud Rate Generator 7 */ 50 QE_BRG8, /* Baud Rate Generator 8 */ 51 QE_BRG9, /* Baud Rate Generator 9 */ 52 QE_BRG10, /* Baud Rate Generator 10 */ 53 QE_BRG11, /* Baud Rate Generator 11 */ 54 QE_BRG12, /* Baud Rate Generator 12 */ 55 QE_BRG13, /* Baud Rate Generator 13 */ 56 QE_BRG14, /* Baud Rate Generator 14 */ 57 QE_BRG15, /* Baud Rate Generator 15 */ 58 QE_BRG16, /* Baud Rate Generator 16 */ 59 QE_CLK1, /* Clock 1 */ 60 QE_CLK2, /* Clock 2 */ 61 QE_CLK3, /* Clock 3 */ 62 QE_CLK4, /* Clock 4 */ 63 QE_CLK5, /* Clock 5 */ 64 QE_CLK6, /* Clock 6 */ 65 QE_CLK7, /* Clock 7 */ 66 QE_CLK8, /* Clock 8 */ 67 QE_CLK9, /* Clock 9 */ 68 QE_CLK10, /* Clock 10 */ 69 QE_CLK11, /* Clock 11 */ 70 QE_CLK12, /* Clock 12 */ 71 QE_CLK13, /* Clock 13 */ 72 QE_CLK14, /* Clock 14 */ 73 QE_CLK15, /* Clock 15 */ 74 QE_CLK16, /* Clock 16 */ 75 QE_CLK17, /* Clock 17 */ 76 QE_CLK18, /* Clock 18 */ 77 QE_CLK19, /* Clock 19 */ 78 QE_CLK20, /* Clock 20 */ 79 QE_CLK21, /* Clock 21 */ 80 QE_CLK22, /* Clock 22 */ 81 QE_CLK23, /* Clock 23 */ 82 QE_CLK24, /* Clock 24 */ 83 QE_CLK_DUMMY 84 }; 85 86 static inline bool qe_clock_is_brg(enum qe_clock clk) 87 { 88 return clk >= QE_BRG1 && clk <= QE_BRG16; 89 } 90 91 extern spinlock_t cmxgcr_lock; 92 93 /* Export QE common operations */ 94 #ifdef CONFIG_QUICC_ENGINE 95 extern void qe_reset(void); 96 #else 97 static inline void qe_reset(void) {} 98 #endif 99 100 int cpm_muram_init(void); 101 102 #if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) 103 unsigned long cpm_muram_alloc(unsigned long size, unsigned long align); 104 int cpm_muram_free(unsigned long offset); 105 unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); 106 unsigned long cpm_muram_alloc_common(unsigned long size, genpool_algo_t algo, 107 void *data); 108 void __iomem *cpm_muram_addr(unsigned long offset); 109 unsigned long cpm_muram_offset(void __iomem *addr); 110 dma_addr_t cpm_muram_dma(void __iomem *addr); 111 #else 112 static inline unsigned long cpm_muram_alloc(unsigned long size, 113 unsigned long align) 114 { 115 return -ENOSYS; 116 } 117 118 static inline int cpm_muram_free(unsigned long offset) 119 { 120 return -ENOSYS; 121 } 122 123 static inline unsigned long cpm_muram_alloc_fixed(unsigned long offset, 124 unsigned long size) 125 { 126 return -ENOSYS; 127 } 128 129 static inline void __iomem *cpm_muram_addr(unsigned long offset) 130 { 131 return NULL; 132 } 133 134 static inline unsigned long cpm_muram_offset(void __iomem *addr) 135 { 136 return -ENOSYS; 137 } 138 139 static inline dma_addr_t cpm_muram_dma(void __iomem *addr) 140 { 141 return 0; 142 } 143 #endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */ 144 145 /* QE PIO */ 146 #define QE_PIO_PINS 32 147 148 struct qe_pio_regs { 149 __be32 cpodr; /* Open drain register */ 150 __be32 cpdata; /* Data register */ 151 __be32 cpdir1; /* Direction register */ 152 __be32 cpdir2; /* Direction register */ 153 __be32 cppar1; /* Pin assignment register */ 154 __be32 cppar2; /* Pin assignment register */ 155 #ifdef CONFIG_PPC_85xx 156 u8 pad[8]; 157 #endif 158 }; 159 160 #define QE_PIO_DIR_IN 2 161 #define QE_PIO_DIR_OUT 1 162 extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, 163 int dir, int open_drain, int assignment, 164 int has_irq); 165 #ifdef CONFIG_QUICC_ENGINE 166 extern int par_io_init(struct device_node *np); 167 extern int par_io_of_config(struct device_node *np); 168 extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, 169 int assignment, int has_irq); 170 extern int par_io_data_set(u8 port, u8 pin, u8 val); 171 #else 172 static inline int par_io_init(struct device_node *np) { return -ENOSYS; } 173 static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; } 174 static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, 175 int assignment, int has_irq) { return -ENOSYS; } 176 static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; } 177 #endif /* CONFIG_QUICC_ENGINE */ 178 179 /* 180 * Pin multiplexing functions. 181 */ 182 struct qe_pin; 183 #ifdef CONFIG_QE_GPIO 184 extern struct qe_pin *qe_pin_request(struct device_node *np, int index); 185 extern void qe_pin_free(struct qe_pin *qe_pin); 186 extern void qe_pin_set_gpio(struct qe_pin *qe_pin); 187 extern void qe_pin_set_dedicated(struct qe_pin *pin); 188 #else 189 static inline struct qe_pin *qe_pin_request(struct device_node *np, int index) 190 { 191 return ERR_PTR(-ENOSYS); 192 } 193 static inline void qe_pin_free(struct qe_pin *qe_pin) {} 194 static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {} 195 static inline void qe_pin_set_dedicated(struct qe_pin *pin) {} 196 #endif /* CONFIG_QE_GPIO */ 197 198 #ifdef CONFIG_QUICC_ENGINE 199 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); 200 #else 201 static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, 202 u32 cmd_input) 203 { 204 return -ENOSYS; 205 } 206 #endif /* CONFIG_QUICC_ENGINE */ 207 208 /* QE internal API */ 209 enum qe_clock qe_clock_source(const char *source); 210 unsigned int qe_get_brg_clk(void); 211 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); 212 int qe_get_snum(void); 213 void qe_put_snum(u8 snum); 214 unsigned int qe_get_num_of_risc(void); 215 unsigned int qe_get_num_of_snums(void); 216 217 static inline int qe_alive_during_sleep(void) 218 { 219 /* 220 * MPC8568E reference manual says: 221 * 222 * "...power down sequence waits for all I/O interfaces to become idle. 223 * In some applications this may happen eventually without actively 224 * shutting down interfaces, but most likely, software will have to 225 * take steps to shut down the eTSEC, QUICC Engine Block, and PCI 226 * interfaces before issuing the command (either the write to the core 227 * MSR[WE] as described above or writing to POWMGTCSR) to put the 228 * device into sleep state." 229 * 230 * MPC8569E reference manual has a similar paragraph. 231 */ 232 #ifdef CONFIG_PPC_85xx 233 return 0; 234 #else 235 return 1; 236 #endif 237 } 238 239 /* we actually use cpm_muram implementation, define this for convenience */ 240 #define qe_muram_init cpm_muram_init 241 #define qe_muram_alloc cpm_muram_alloc 242 #define qe_muram_alloc_fixed cpm_muram_alloc_fixed 243 #define qe_muram_free cpm_muram_free 244 #define qe_muram_addr cpm_muram_addr 245 #define qe_muram_offset cpm_muram_offset 246 247 /* Structure that defines QE firmware binary files. 248 * 249 * See Documentation/powerpc/qe_firmware.txt for a description of these 250 * fields. 251 */ 252 struct qe_firmware { 253 struct qe_header { 254 __be32 length; /* Length of the entire structure, in bytes */ 255 u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ 256 u8 version; /* Version of this layout. First ver is '1' */ 257 } header; 258 u8 id[62]; /* Null-terminated identifier string */ 259 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ 260 u8 count; /* Number of microcode[] structures */ 261 struct { 262 __be16 model; /* The SOC model */ 263 u8 major; /* The SOC revision major */ 264 u8 minor; /* The SOC revision minor */ 265 } __attribute__ ((packed)) soc; 266 u8 padding[4]; /* Reserved, for alignment */ 267 __be64 extended_modes; /* Extended modes */ 268 __be32 vtraps[8]; /* Virtual trap addresses */ 269 u8 reserved[4]; /* Reserved, for future expansion */ 270 struct qe_microcode { 271 u8 id[32]; /* Null-terminated identifier */ 272 __be32 traps[16]; /* Trap addresses, 0 == ignore */ 273 __be32 eccr; /* The value for the ECCR register */ 274 __be32 iram_offset; /* Offset into I-RAM for the code */ 275 __be32 count; /* Number of 32-bit words of the code */ 276 __be32 code_offset; /* Offset of the actual microcode */ 277 u8 major; /* The microcode version major */ 278 u8 minor; /* The microcode version minor */ 279 u8 revision; /* The microcode version revision */ 280 u8 padding; /* Reserved, for alignment */ 281 u8 reserved[4]; /* Reserved, for future expansion */ 282 } __attribute__ ((packed)) microcode[1]; 283 /* All microcode binaries should be located here */ 284 /* CRC32 should be located here, after the microcode binaries */ 285 } __attribute__ ((packed)); 286 287 struct qe_firmware_info { 288 char id[64]; /* Firmware name */ 289 u32 vtraps[8]; /* Virtual trap addresses */ 290 u64 extended_modes; /* Extended modes */ 291 }; 292 293 #ifdef CONFIG_QUICC_ENGINE 294 /* Upload a firmware to the QE */ 295 int qe_upload_firmware(const struct qe_firmware *firmware); 296 #else 297 static inline int qe_upload_firmware(const struct qe_firmware *firmware) 298 { 299 return -ENOSYS; 300 } 301 #endif /* CONFIG_QUICC_ENGINE */ 302 303 /* Obtain information on the uploaded firmware */ 304 struct qe_firmware_info *qe_get_firmware_info(void); 305 306 /* QE USB */ 307 int qe_usb_clock_set(enum qe_clock clk, int rate); 308 309 /* Buffer descriptors */ 310 struct qe_bd { 311 __be16 status; 312 __be16 length; 313 __be32 buf; 314 } __attribute__ ((packed)); 315 316 #define BD_STATUS_MASK 0xffff0000 317 #define BD_LENGTH_MASK 0x0000ffff 318 319 /* Alignment */ 320 #define QE_INTR_TABLE_ALIGN 16 /* ??? */ 321 #define QE_ALIGNMENT_OF_BD 8 322 #define QE_ALIGNMENT_OF_PRAM 64 323 324 /* RISC allocation */ 325 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ 326 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ 327 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ 328 #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ 329 #define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ 330 QE_RISC_ALLOCATION_RISC2) 331 #define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ 332 QE_RISC_ALLOCATION_RISC2 | \ 333 QE_RISC_ALLOCATION_RISC3 | \ 334 QE_RISC_ALLOCATION_RISC4) 335 336 /* QE extended filtering Table Lookup Key Size */ 337 enum qe_fltr_tbl_lookup_key_size { 338 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES 339 = 0x3f, /* LookupKey parsed by the Generate LookupKey 340 CMD is truncated to 8 bytes */ 341 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES 342 = 0x5f, /* LookupKey parsed by the Generate LookupKey 343 CMD is truncated to 16 bytes */ 344 }; 345 346 /* QE FLTR extended filtering Largest External Table Lookup Key Size */ 347 enum qe_fltr_largest_external_tbl_lookup_key_size { 348 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE 349 = 0x0,/* not used */ 350 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES 351 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */ 352 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES 353 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */ 354 }; 355 356 /* structure representing QE parameter RAM */ 357 struct qe_timer_tables { 358 u16 tm_base; /* QE timer table base adr */ 359 u16 tm_ptr; /* QE timer table pointer */ 360 u16 r_tmr; /* QE timer mode register */ 361 u16 r_tmv; /* QE timer valid register */ 362 u32 tm_cmd; /* QE timer cmd register */ 363 u32 tm_cnt; /* QE timer internal cnt */ 364 } __attribute__ ((packed)); 365 366 #define QE_FLTR_TAD_SIZE 8 367 368 /* QE extended filtering Termination Action Descriptor (TAD) */ 369 struct qe_fltr_tad { 370 u8 serialized[QE_FLTR_TAD_SIZE]; 371 } __attribute__ ((packed)); 372 373 /* Communication Direction */ 374 enum comm_dir { 375 COMM_DIR_NONE = 0, 376 COMM_DIR_RX = 1, 377 COMM_DIR_TX = 2, 378 COMM_DIR_RX_AND_TX = 3 379 }; 380 381 /* QE CMXUCR Registers. 382 * There are two UCCs represented in each of the four CMXUCR registers. 383 * These values are for the UCC in the LSBs 384 */ 385 #define QE_CMXUCR_MII_ENET_MNG 0x00007000 386 #define QE_CMXUCR_MII_ENET_MNG_SHIFT 12 387 #define QE_CMXUCR_GRANT 0x00008000 388 #define QE_CMXUCR_TSA 0x00004000 389 #define QE_CMXUCR_BKPT 0x00000100 390 #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F 391 392 /* QE CMXGCR Registers. 393 */ 394 #define QE_CMXGCR_MII_ENET_MNG 0x00007000 395 #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 396 #define QE_CMXGCR_USBCS 0x0000000f 397 #define QE_CMXGCR_USBCS_CLK3 0x1 398 #define QE_CMXGCR_USBCS_CLK5 0x2 399 #define QE_CMXGCR_USBCS_CLK7 0x3 400 #define QE_CMXGCR_USBCS_CLK9 0x4 401 #define QE_CMXGCR_USBCS_CLK13 0x5 402 #define QE_CMXGCR_USBCS_CLK17 0x6 403 #define QE_CMXGCR_USBCS_CLK19 0x7 404 #define QE_CMXGCR_USBCS_CLK21 0x8 405 #define QE_CMXGCR_USBCS_BRG9 0x9 406 #define QE_CMXGCR_USBCS_BRG10 0xa 407 408 /* QE CECR Commands. 409 */ 410 #define QE_CR_FLG 0x00010000 411 #define QE_RESET 0x80000000 412 #define QE_INIT_TX_RX 0x00000000 413 #define QE_INIT_RX 0x00000001 414 #define QE_INIT_TX 0x00000002 415 #define QE_ENTER_HUNT_MODE 0x00000003 416 #define QE_STOP_TX 0x00000004 417 #define QE_GRACEFUL_STOP_TX 0x00000005 418 #define QE_RESTART_TX 0x00000006 419 #define QE_CLOSE_RX_BD 0x00000007 420 #define QE_SWITCH_COMMAND 0x00000007 421 #define QE_SET_GROUP_ADDRESS 0x00000008 422 #define QE_START_IDMA 0x00000009 423 #define QE_MCC_STOP_RX 0x00000009 424 #define QE_ATM_TRANSMIT 0x0000000a 425 #define QE_HPAC_CLEAR_ALL 0x0000000b 426 #define QE_GRACEFUL_STOP_RX 0x0000001a 427 #define QE_RESTART_RX 0x0000001b 428 #define QE_HPAC_SET_PRIORITY 0x0000010b 429 #define QE_HPAC_STOP_TX 0x0000020b 430 #define QE_HPAC_STOP_RX 0x0000030b 431 #define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b 432 #define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b 433 #define QE_HPAC_START_TX 0x0000060b 434 #define QE_HPAC_START_RX 0x0000070b 435 #define QE_USB_STOP_TX 0x0000000a 436 #define QE_USB_RESTART_TX 0x0000000c 437 #define QE_QMC_STOP_TX 0x0000000c 438 #define QE_QMC_STOP_RX 0x0000000d 439 #define QE_SS7_SU_FIL_RESET 0x0000000e 440 /* jonathbr added from here down for 83xx */ 441 #define QE_RESET_BCS 0x0000000a 442 #define QE_MCC_INIT_TX_RX_16 0x00000003 443 #define QE_MCC_STOP_TX 0x00000004 444 #define QE_MCC_INIT_TX_1 0x00000005 445 #define QE_MCC_INIT_RX_1 0x00000006 446 #define QE_MCC_RESET 0x00000007 447 #define QE_SET_TIMER 0x00000008 448 #define QE_RANDOM_NUMBER 0x0000000c 449 #define QE_ATM_MULTI_THREAD_INIT 0x00000011 450 #define QE_ASSIGN_PAGE 0x00000012 451 #define QE_ADD_REMOVE_HASH_ENTRY 0x00000013 452 #define QE_START_FLOW_CONTROL 0x00000014 453 #define QE_STOP_FLOW_CONTROL 0x00000015 454 #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 455 456 #define QE_ASSIGN_RISC 0x00000010 457 #define QE_CR_MCN_NORMAL_SHIFT 6 458 #define QE_CR_MCN_USB_SHIFT 4 459 #define QE_CR_MCN_RISC_ASSIGN_SHIFT 8 460 #define QE_CR_SNUM_SHIFT 17 461 462 /* QE CECR Sub Block - sub block of QE command. 463 */ 464 #define QE_CR_SUBBLOCK_INVALID 0x00000000 465 #define QE_CR_SUBBLOCK_USB 0x03200000 466 #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 467 #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 468 #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 469 #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 470 #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 471 #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 472 #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 473 #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 474 #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 475 #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 476 #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 477 #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 478 #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 479 #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 480 #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 481 #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 482 #define QE_CR_SUBBLOCK_MCC1 0x03800000 483 #define QE_CR_SUBBLOCK_MCC2 0x03a00000 484 #define QE_CR_SUBBLOCK_MCC3 0x03000000 485 #define QE_CR_SUBBLOCK_IDMA1 0x02800000 486 #define QE_CR_SUBBLOCK_IDMA2 0x02a00000 487 #define QE_CR_SUBBLOCK_IDMA3 0x02c00000 488 #define QE_CR_SUBBLOCK_IDMA4 0x02e00000 489 #define QE_CR_SUBBLOCK_HPAC 0x01e00000 490 #define QE_CR_SUBBLOCK_SPI1 0x01400000 491 #define QE_CR_SUBBLOCK_SPI2 0x01600000 492 #define QE_CR_SUBBLOCK_RAND 0x01c00000 493 #define QE_CR_SUBBLOCK_TIMER 0x01e00000 494 #define QE_CR_SUBBLOCK_GENERAL 0x03c00000 495 496 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */ 497 #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ 498 #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 499 #define QE_CR_PROTOCOL_QMC 0x02 500 #define QE_CR_PROTOCOL_UART 0x04 501 #define QE_CR_PROTOCOL_ATM_POS 0x0A 502 #define QE_CR_PROTOCOL_ETHERNET 0x0C 503 #define QE_CR_PROTOCOL_L2_SWITCH 0x0D 504 505 /* BRG configuration register */ 506 #define QE_BRGC_ENABLE 0x00010000 507 #define QE_BRGC_DIVISOR_SHIFT 1 508 #define QE_BRGC_DIVISOR_MAX 0xFFF 509 #define QE_BRGC_DIV16 1 510 511 /* QE Timers registers */ 512 #define QE_GTCFR1_PCAS 0x80 513 #define QE_GTCFR1_STP2 0x20 514 #define QE_GTCFR1_RST2 0x10 515 #define QE_GTCFR1_GM2 0x08 516 #define QE_GTCFR1_GM1 0x04 517 #define QE_GTCFR1_STP1 0x02 518 #define QE_GTCFR1_RST1 0x01 519 520 /* SDMA registers */ 521 #define QE_SDSR_BER1 0x02000000 522 #define QE_SDSR_BER2 0x01000000 523 524 #define QE_SDMR_GLB_1_MSK 0x80000000 525 #define QE_SDMR_ADR_SEL 0x20000000 526 #define QE_SDMR_BER1_MSK 0x02000000 527 #define QE_SDMR_BER2_MSK 0x01000000 528 #define QE_SDMR_EB1_MSK 0x00800000 529 #define QE_SDMR_ER1_MSK 0x00080000 530 #define QE_SDMR_ER2_MSK 0x00040000 531 #define QE_SDMR_CEN_MASK 0x0000E000 532 #define QE_SDMR_SBER_1 0x00000200 533 #define QE_SDMR_SBER_2 0x00000200 534 #define QE_SDMR_EB1_PR_MASK 0x000000C0 535 #define QE_SDMR_ER1_PR 0x00000008 536 537 #define QE_SDMR_CEN_SHIFT 13 538 #define QE_SDMR_EB1_PR_SHIFT 6 539 540 #define QE_SDTM_MSNUM_SHIFT 24 541 542 #define QE_SDEBCR_BA_MASK 0x01FFFFFF 543 544 /* Communication Processor */ 545 #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ 546 #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ 547 #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ 548 549 /* I-RAM */ 550 #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ 551 #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ 552 #define QE_IRAM_READY 0x80000000 /* Ready */ 553 554 /* UPC */ 555 #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ 556 #define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ 557 #define UPGCR_RMS 0x20000000 /* Receive master/slave mode */ 558 #define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */ 559 #define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ 560 561 /* UCC GUEMR register */ 562 #define UCC_GUEMR_MODE_MASK_RX 0x02 563 #define UCC_GUEMR_MODE_FAST_RX 0x02 564 #define UCC_GUEMR_MODE_SLOW_RX 0x00 565 #define UCC_GUEMR_MODE_MASK_TX 0x01 566 #define UCC_GUEMR_MODE_FAST_TX 0x01 567 #define UCC_GUEMR_MODE_SLOW_TX 0x00 568 #define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX) 569 #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but 570 must be set 1 */ 571 572 /* structure representing UCC SLOW parameter RAM */ 573 struct ucc_slow_pram { 574 __be16 rbase; /* RX BD base address */ 575 __be16 tbase; /* TX BD base address */ 576 u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */ 577 u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */ 578 __be16 mrblr; /* Rx buffer length */ 579 __be32 rstate; /* Rx internal state */ 580 __be32 rptr; /* Rx internal data pointer */ 581 __be16 rbptr; /* rb BD Pointer */ 582 __be16 rcount; /* Rx internal byte count */ 583 __be32 rtemp; /* Rx temp */ 584 __be32 tstate; /* Tx internal state */ 585 __be32 tptr; /* Tx internal data pointer */ 586 __be16 tbptr; /* Tx BD pointer */ 587 __be16 tcount; /* Tx byte count */ 588 __be32 ttemp; /* Tx temp */ 589 __be32 rcrc; /* temp receive CRC */ 590 __be32 tcrc; /* temp transmit CRC */ 591 } __attribute__ ((packed)); 592 593 /* General UCC SLOW Mode Register (GUMRH & GUMRL) */ 594 #define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000 595 #define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000 596 #define UCC_SLOW_GUMR_H_REVD 0x00002000 597 #define UCC_SLOW_GUMR_H_TRX 0x00001000 598 #define UCC_SLOW_GUMR_H_TTX 0x00000800 599 #define UCC_SLOW_GUMR_H_CDP 0x00000400 600 #define UCC_SLOW_GUMR_H_CTSP 0x00000200 601 #define UCC_SLOW_GUMR_H_CDS 0x00000100 602 #define UCC_SLOW_GUMR_H_CTSS 0x00000080 603 #define UCC_SLOW_GUMR_H_TFL 0x00000040 604 #define UCC_SLOW_GUMR_H_RFW 0x00000020 605 #define UCC_SLOW_GUMR_H_TXSY 0x00000010 606 #define UCC_SLOW_GUMR_H_4SYNC 0x00000004 607 #define UCC_SLOW_GUMR_H_8SYNC 0x00000008 608 #define UCC_SLOW_GUMR_H_16SYNC 0x0000000c 609 #define UCC_SLOW_GUMR_H_RTSM 0x00000002 610 #define UCC_SLOW_GUMR_H_RSYN 0x00000001 611 612 #define UCC_SLOW_GUMR_L_TCI 0x10000000 613 #define UCC_SLOW_GUMR_L_RINV 0x02000000 614 #define UCC_SLOW_GUMR_L_TINV 0x01000000 615 #define UCC_SLOW_GUMR_L_TEND 0x00040000 616 #define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000 617 #define UCC_SLOW_GUMR_L_TDCR_32 0x00030000 618 #define UCC_SLOW_GUMR_L_TDCR_16 0x00020000 619 #define UCC_SLOW_GUMR_L_TDCR_8 0x00010000 620 #define UCC_SLOW_GUMR_L_TDCR_1 0x00000000 621 #define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000 622 #define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000 623 #define UCC_SLOW_GUMR_L_RDCR_16 0x00008000 624 #define UCC_SLOW_GUMR_L_RDCR_8 0x00004000 625 #define UCC_SLOW_GUMR_L_RDCR_1 0x00000000 626 #define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800 627 #define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000 628 #define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100 629 #define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000 630 #define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0 631 #define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0 632 #define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080 633 #define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040 634 #define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000 635 #define UCC_SLOW_GUMR_L_ENR 0x00000020 636 #define UCC_SLOW_GUMR_L_ENT 0x00000010 637 #define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F 638 #define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008 639 #define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006 640 #define UCC_SLOW_GUMR_L_MODE_UART 0x00000004 641 #define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002 642 643 /* General UCC FAST Mode Register */ 644 #define UCC_FAST_GUMR_TCI 0x20000000 645 #define UCC_FAST_GUMR_TRX 0x10000000 646 #define UCC_FAST_GUMR_TTX 0x08000000 647 #define UCC_FAST_GUMR_CDP 0x04000000 648 #define UCC_FAST_GUMR_CTSP 0x02000000 649 #define UCC_FAST_GUMR_CDS 0x01000000 650 #define UCC_FAST_GUMR_CTSS 0x00800000 651 #define UCC_FAST_GUMR_TXSY 0x00020000 652 #define UCC_FAST_GUMR_RSYN 0x00010000 653 #define UCC_FAST_GUMR_RTSM 0x00002000 654 #define UCC_FAST_GUMR_REVD 0x00000400 655 #define UCC_FAST_GUMR_ENR 0x00000020 656 #define UCC_FAST_GUMR_ENT 0x00000010 657 658 /* UART Slow UCC Event Register (UCCE) */ 659 #define UCC_UART_UCCE_AB 0x0200 660 #define UCC_UART_UCCE_IDLE 0x0100 661 #define UCC_UART_UCCE_GRA 0x0080 662 #define UCC_UART_UCCE_BRKE 0x0040 663 #define UCC_UART_UCCE_BRKS 0x0020 664 #define UCC_UART_UCCE_CCR 0x0008 665 #define UCC_UART_UCCE_BSY 0x0004 666 #define UCC_UART_UCCE_TX 0x0002 667 #define UCC_UART_UCCE_RX 0x0001 668 669 /* HDLC Slow UCC Event Register (UCCE) */ 670 #define UCC_HDLC_UCCE_GLR 0x1000 671 #define UCC_HDLC_UCCE_GLT 0x0800 672 #define UCC_HDLC_UCCE_IDLE 0x0100 673 #define UCC_HDLC_UCCE_BRKE 0x0040 674 #define UCC_HDLC_UCCE_BRKS 0x0020 675 #define UCC_HDLC_UCCE_TXE 0x0010 676 #define UCC_HDLC_UCCE_RXF 0x0008 677 #define UCC_HDLC_UCCE_BSY 0x0004 678 #define UCC_HDLC_UCCE_TXB 0x0002 679 #define UCC_HDLC_UCCE_RXB 0x0001 680 681 /* BISYNC Slow UCC Event Register (UCCE) */ 682 #define UCC_BISYNC_UCCE_GRA 0x0080 683 #define UCC_BISYNC_UCCE_TXE 0x0010 684 #define UCC_BISYNC_UCCE_RCH 0x0008 685 #define UCC_BISYNC_UCCE_BSY 0x0004 686 #define UCC_BISYNC_UCCE_TXB 0x0002 687 #define UCC_BISYNC_UCCE_RXB 0x0001 688 689 /* Gigabit Ethernet Fast UCC Event Register (UCCE) */ 690 #define UCC_GETH_UCCE_MPD 0x80000000 691 #define UCC_GETH_UCCE_SCAR 0x40000000 692 #define UCC_GETH_UCCE_GRA 0x20000000 693 #define UCC_GETH_UCCE_CBPR 0x10000000 694 #define UCC_GETH_UCCE_BSY 0x08000000 695 #define UCC_GETH_UCCE_RXC 0x04000000 696 #define UCC_GETH_UCCE_TXC 0x02000000 697 #define UCC_GETH_UCCE_TXE 0x01000000 698 #define UCC_GETH_UCCE_TXB7 0x00800000 699 #define UCC_GETH_UCCE_TXB6 0x00400000 700 #define UCC_GETH_UCCE_TXB5 0x00200000 701 #define UCC_GETH_UCCE_TXB4 0x00100000 702 #define UCC_GETH_UCCE_TXB3 0x00080000 703 #define UCC_GETH_UCCE_TXB2 0x00040000 704 #define UCC_GETH_UCCE_TXB1 0x00020000 705 #define UCC_GETH_UCCE_TXB0 0x00010000 706 #define UCC_GETH_UCCE_RXB7 0x00008000 707 #define UCC_GETH_UCCE_RXB6 0x00004000 708 #define UCC_GETH_UCCE_RXB5 0x00002000 709 #define UCC_GETH_UCCE_RXB4 0x00001000 710 #define UCC_GETH_UCCE_RXB3 0x00000800 711 #define UCC_GETH_UCCE_RXB2 0x00000400 712 #define UCC_GETH_UCCE_RXB1 0x00000200 713 #define UCC_GETH_UCCE_RXB0 0x00000100 714 #define UCC_GETH_UCCE_RXF7 0x00000080 715 #define UCC_GETH_UCCE_RXF6 0x00000040 716 #define UCC_GETH_UCCE_RXF5 0x00000020 717 #define UCC_GETH_UCCE_RXF4 0x00000010 718 #define UCC_GETH_UCCE_RXF3 0x00000008 719 #define UCC_GETH_UCCE_RXF2 0x00000004 720 #define UCC_GETH_UCCE_RXF1 0x00000002 721 #define UCC_GETH_UCCE_RXF0 0x00000001 722 723 /* UCC Protocol Specific Mode Register (UPSMR), when used for UART */ 724 #define UCC_UART_UPSMR_FLC 0x8000 725 #define UCC_UART_UPSMR_SL 0x4000 726 #define UCC_UART_UPSMR_CL_MASK 0x3000 727 #define UCC_UART_UPSMR_CL_8 0x3000 728 #define UCC_UART_UPSMR_CL_7 0x2000 729 #define UCC_UART_UPSMR_CL_6 0x1000 730 #define UCC_UART_UPSMR_CL_5 0x0000 731 #define UCC_UART_UPSMR_UM_MASK 0x0c00 732 #define UCC_UART_UPSMR_UM_NORMAL 0x0000 733 #define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400 734 #define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00 735 #define UCC_UART_UPSMR_FRZ 0x0200 736 #define UCC_UART_UPSMR_RZS 0x0100 737 #define UCC_UART_UPSMR_SYN 0x0080 738 #define UCC_UART_UPSMR_DRT 0x0040 739 #define UCC_UART_UPSMR_PEN 0x0010 740 #define UCC_UART_UPSMR_RPM_MASK 0x000c 741 #define UCC_UART_UPSMR_RPM_ODD 0x0000 742 #define UCC_UART_UPSMR_RPM_LOW 0x0004 743 #define UCC_UART_UPSMR_RPM_EVEN 0x0008 744 #define UCC_UART_UPSMR_RPM_HIGH 0x000C 745 #define UCC_UART_UPSMR_TPM_MASK 0x0003 746 #define UCC_UART_UPSMR_TPM_ODD 0x0000 747 #define UCC_UART_UPSMR_TPM_LOW 0x0001 748 #define UCC_UART_UPSMR_TPM_EVEN 0x0002 749 #define UCC_UART_UPSMR_TPM_HIGH 0x0003 750 751 /* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */ 752 #define UCC_GETH_UPSMR_FTFE 0x80000000 753 #define UCC_GETH_UPSMR_PTPE 0x40000000 754 #define UCC_GETH_UPSMR_ECM 0x04000000 755 #define UCC_GETH_UPSMR_HSE 0x02000000 756 #define UCC_GETH_UPSMR_PRO 0x00400000 757 #define UCC_GETH_UPSMR_CAP 0x00200000 758 #define UCC_GETH_UPSMR_RSH 0x00100000 759 #define UCC_GETH_UPSMR_RPM 0x00080000 760 #define UCC_GETH_UPSMR_R10M 0x00040000 761 #define UCC_GETH_UPSMR_RLPB 0x00020000 762 #define UCC_GETH_UPSMR_TBIM 0x00010000 763 #define UCC_GETH_UPSMR_RES1 0x00002000 764 #define UCC_GETH_UPSMR_RMM 0x00001000 765 #define UCC_GETH_UPSMR_CAM 0x00000400 766 #define UCC_GETH_UPSMR_BRO 0x00000200 767 #define UCC_GETH_UPSMR_SMM 0x00000080 768 #define UCC_GETH_UPSMR_SGMM 0x00000020 769 770 /* UCC Transmit On Demand Register (UTODR) */ 771 #define UCC_SLOW_TOD 0x8000 772 #define UCC_FAST_TOD 0x8000 773 774 /* UCC Bus Mode Register masks */ 775 /* Not to be confused with the Bundle Mode Register */ 776 #define UCC_BMR_GBL 0x20 777 #define UCC_BMR_BO_BE 0x10 778 #define UCC_BMR_CETM 0x04 779 #define UCC_BMR_DTB 0x02 780 #define UCC_BMR_BDB 0x01 781 782 /* Function code masks */ 783 #define FC_GBL 0x20 784 #define FC_DTB_LCL 0x02 785 #define UCC_FAST_FUNCTION_CODE_GBL 0x20 786 #define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02 787 #define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01 788 789 #endif /* __KERNEL__ */ 790 #endif /* _ASM_POWERPC_QE_H */ 791