1*96abf168SClaudiu Beznea /* SPDX-License-Identifier: GPL-2.0-only */ 2*96abf168SClaudiu Beznea /* 3*96abf168SClaudiu Beznea * Microchip SAMA7 SFRBU registers offsets and bit definitions. 4*96abf168SClaudiu Beznea * 5*96abf168SClaudiu Beznea * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries 6*96abf168SClaudiu Beznea * 7*96abf168SClaudiu Beznea * Author: Claudu Beznea <claudiu.beznea@microchip.com> 8*96abf168SClaudiu Beznea */ 9*96abf168SClaudiu Beznea 10*96abf168SClaudiu Beznea #ifndef __SAMA7_SFRBU_H__ 11*96abf168SClaudiu Beznea #define __SAMA7_SFRBU_H__ 12*96abf168SClaudiu Beznea 13*96abf168SClaudiu Beznea #ifdef CONFIG_SOC_SAMA7 14*96abf168SClaudiu Beznea 15*96abf168SClaudiu Beznea #define AT91_SFRBU_PSWBU (0x00) /* SFRBU Power Switch BU Control Register */ 16*96abf168SClaudiu Beznea #define AT91_SFRBU_PSWBU_PSWKEY (0x4BD20C << 8) /* Specific value mandatory to allow writing of other register bits */ 17*96abf168SClaudiu Beznea #define AT91_SFRBU_PSWBU_STATE (1 << 2) /* Power switch BU state */ 18*96abf168SClaudiu Beznea #define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */ 19*96abf168SClaudiu Beznea #define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */ 20*96abf168SClaudiu Beznea 21*96abf168SClaudiu Beznea #define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */ 22*96abf168SClaudiu Beznea #define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */ 23*96abf168SClaudiu Beznea #define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control */ 24*96abf168SClaudiu Beznea #define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control */ 25*96abf168SClaudiu Beznea #define AT91_SFRBU_PD_VALUE_MSK (0x3) 26*96abf168SClaudiu Beznea #define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */ 27*96abf168SClaudiu Beznea 28*96abf168SClaudiu Beznea #define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */ 29*96abf168SClaudiu Beznea #define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */ 30*96abf168SClaudiu Beznea 31*96abf168SClaudiu Beznea #endif /* CONFIG_SOC_SAMA7 */ 32*96abf168SClaudiu Beznea 33*96abf168SClaudiu Beznea #endif /* __SAMA7_SFRBU_H__ */ 34*96abf168SClaudiu Beznea 35