1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #ifndef _MANA_H 5 #define _MANA_H 6 7 #include <net/xdp.h> 8 #include <net/net_shaper.h> 9 10 #include "gdma.h" 11 #include "hw_channel.h" 12 13 /* Microsoft Azure Network Adapter (MANA)'s definitions 14 * 15 * Structures labeled with "HW DATA" are exchanged with the hardware. All of 16 * them are naturally aligned and hence don't need __packed. 17 */ 18 19 /* MANA protocol version */ 20 #define MANA_MAJOR_VERSION 0 21 #define MANA_MINOR_VERSION 1 22 #define MANA_MICRO_VERSION 1 23 24 typedef u64 mana_handle_t; 25 #define INVALID_MANA_HANDLE ((mana_handle_t)-1) 26 27 enum TRI_STATE { 28 TRI_STATE_UNKNOWN = -1, 29 TRI_STATE_FALSE = 0, 30 TRI_STATE_TRUE = 1 31 }; 32 33 /* Number of entries for hardware indirection table must be in power of 2 */ 34 #define MANA_INDIRECT_TABLE_MAX_SIZE 512 35 #define MANA_INDIRECT_TABLE_DEF_SIZE 64 36 37 /* The Toeplitz hash key's length in bytes: should be multiple of 8 */ 38 #define MANA_HASH_KEY_SIZE 40 39 40 #define COMP_ENTRY_SIZE 64 41 42 /* This Max value for RX buffers is derived from __alloc_page()'s max page 43 * allocation calculation. It allows maximum 2^(MAX_ORDER -1) pages. RX buffer 44 * size beyond this value gets rejected by __alloc_page() call. 45 */ 46 #define MAX_RX_BUFFERS_PER_QUEUE 8192 47 #define DEF_RX_BUFFERS_PER_QUEUE 1024 48 #define MIN_RX_BUFFERS_PER_QUEUE 128 49 50 /* This max value for TX buffers is derived as the maximum allocatable 51 * pages supported on host per guest through testing. TX buffer size beyond 52 * this value is rejected by the hardware. 53 */ 54 #define MAX_TX_BUFFERS_PER_QUEUE 16384 55 #define DEF_TX_BUFFERS_PER_QUEUE 256 56 #define MIN_TX_BUFFERS_PER_QUEUE 128 57 58 #define EQ_SIZE (8 * MANA_PAGE_SIZE) 59 60 #define LOG2_EQ_THROTTLE 3 61 62 #define MAX_PORTS_IN_MANA_DEV 256 63 64 /* Maximum number of packets per coalesced CQE */ 65 #define MANA_RXCOMP_OOB_NUM_PPI 4 66 67 /* Update this count whenever the respective structures are changed */ 68 #define MANA_STATS_RX_COUNT (6 + MANA_RXCOMP_OOB_NUM_PPI - 1) 69 #define MANA_STATS_TX_COUNT 11 70 71 #define MANA_RX_FRAG_ALIGNMENT 64 72 73 struct mana_stats_rx { 74 u64 packets; 75 u64 bytes; 76 u64 xdp_drop; 77 u64 xdp_tx; 78 u64 xdp_redirect; 79 u64 pkt_len0_err; 80 u64 coalesced_cqe[MANA_RXCOMP_OOB_NUM_PPI - 1]; 81 struct u64_stats_sync syncp; 82 }; 83 84 struct mana_stats_tx { 85 u64 packets; 86 u64 bytes; 87 u64 xdp_xmit; 88 u64 tso_packets; 89 u64 tso_bytes; 90 u64 tso_inner_packets; 91 u64 tso_inner_bytes; 92 u64 short_pkt_fmt; 93 u64 long_pkt_fmt; 94 u64 csum_partial; 95 u64 mana_map_err; 96 struct u64_stats_sync syncp; 97 }; 98 99 struct mana_txq { 100 struct gdma_queue *gdma_sq; 101 102 union { 103 u32 gdma_txq_id; 104 struct { 105 u32 reserved1 : 10; 106 u32 vsq_frame : 14; 107 u32 reserved2 : 8; 108 }; 109 }; 110 111 u16 vp_offset; 112 113 struct net_device *ndev; 114 115 /* The SKBs are sent to the HW and we are waiting for the CQEs. */ 116 struct sk_buff_head pending_skbs; 117 struct netdev_queue *net_txq; 118 119 atomic_t pending_sends; 120 121 bool napi_initialized; 122 123 struct mana_stats_tx stats; 124 }; 125 126 /* skb data and frags dma mappings */ 127 struct mana_skb_head { 128 /* GSO pkts may have 2 SGEs for the linear part*/ 129 dma_addr_t dma_handle[MAX_SKB_FRAGS + 2]; 130 131 u32 size[MAX_SKB_FRAGS + 2]; 132 }; 133 134 #define MANA_HEADROOM sizeof(struct mana_skb_head) 135 136 enum mana_tx_pkt_format { 137 MANA_SHORT_PKT_FMT = 0, 138 MANA_LONG_PKT_FMT = 1, 139 }; 140 141 struct mana_tx_short_oob { 142 u32 pkt_fmt : 2; 143 u32 is_outer_ipv4 : 1; 144 u32 is_outer_ipv6 : 1; 145 u32 comp_iphdr_csum : 1; 146 u32 comp_tcp_csum : 1; 147 u32 comp_udp_csum : 1; 148 u32 supress_txcqe_gen : 1; 149 u32 vcq_num : 24; 150 151 u32 trans_off : 10; /* Transport header offset */ 152 u32 vsq_frame : 14; 153 u32 short_vp_offset : 8; 154 }; /* HW DATA */ 155 156 struct mana_tx_long_oob { 157 u32 is_encap : 1; 158 u32 inner_is_ipv6 : 1; 159 u32 inner_tcp_opt : 1; 160 u32 inject_vlan_pri_tag : 1; 161 u32 reserved1 : 12; 162 u32 pcp : 3; /* 802.1Q */ 163 u32 dei : 1; /* 802.1Q */ 164 u32 vlan_id : 12; /* 802.1Q */ 165 166 u32 inner_frame_offset : 10; 167 u32 inner_ip_rel_offset : 6; 168 u32 long_vp_offset : 12; 169 u32 reserved2 : 4; 170 171 u32 reserved3; 172 u32 reserved4; 173 }; /* HW DATA */ 174 175 struct mana_tx_oob { 176 struct mana_tx_short_oob s_oob; 177 struct mana_tx_long_oob l_oob; 178 }; /* HW DATA */ 179 180 enum mana_cq_type { 181 MANA_CQ_TYPE_RX, 182 MANA_CQ_TYPE_TX, 183 }; 184 185 enum mana_cqe_type { 186 CQE_INVALID = 0, 187 CQE_RX_OKAY = 1, 188 CQE_RX_COALESCED_4 = 2, 189 CQE_RX_OBJECT_FENCE = 3, 190 CQE_RX_TRUNCATED = 4, 191 192 CQE_TX_OKAY = 32, 193 CQE_TX_SA_DROP = 33, 194 CQE_TX_MTU_DROP = 34, 195 CQE_TX_INVALID_OOB = 35, 196 CQE_TX_INVALID_ETH_TYPE = 36, 197 CQE_TX_HDR_PROCESSING_ERROR = 37, 198 CQE_TX_VF_DISABLED = 38, 199 CQE_TX_VPORT_IDX_OUT_OF_RANGE = 39, 200 CQE_TX_VPORT_DISABLED = 40, 201 CQE_TX_VLAN_TAGGING_VIOLATION = 41, 202 }; 203 204 #define MANA_CQE_COMPLETION 1 205 206 struct mana_cqe_header { 207 u32 cqe_type : 6; 208 u32 client_type : 2; 209 u32 vendor_err : 24; 210 }; /* HW DATA */ 211 212 /* NDIS HASH Types */ 213 #define NDIS_HASH_IPV4 BIT(0) 214 #define NDIS_HASH_TCP_IPV4 BIT(1) 215 #define NDIS_HASH_UDP_IPV4 BIT(2) 216 #define NDIS_HASH_IPV6 BIT(3) 217 #define NDIS_HASH_TCP_IPV6 BIT(4) 218 #define NDIS_HASH_UDP_IPV6 BIT(5) 219 #define NDIS_HASH_IPV6_EX BIT(6) 220 #define NDIS_HASH_TCP_IPV6_EX BIT(7) 221 #define NDIS_HASH_UDP_IPV6_EX BIT(8) 222 223 #define MANA_HASH_L3 (NDIS_HASH_IPV4 | NDIS_HASH_IPV6 | NDIS_HASH_IPV6_EX) 224 #define MANA_HASH_L4 \ 225 (NDIS_HASH_TCP_IPV4 | NDIS_HASH_UDP_IPV4 | NDIS_HASH_TCP_IPV6 | \ 226 NDIS_HASH_UDP_IPV6 | NDIS_HASH_TCP_IPV6_EX | NDIS_HASH_UDP_IPV6_EX) 227 228 struct mana_rxcomp_perpkt_info { 229 u32 pkt_len : 16; 230 u32 reserved1 : 16; 231 u32 reserved2; 232 u32 pkt_hash; 233 }; /* HW DATA */ 234 235 /* Receive completion OOB */ 236 struct mana_rxcomp_oob { 237 struct mana_cqe_header cqe_hdr; 238 239 u32 rx_vlan_id : 12; 240 u32 rx_vlantag_present : 1; 241 u32 rx_outer_iphdr_csum_succeed : 1; 242 u32 rx_outer_iphdr_csum_fail : 1; 243 u32 reserved1 : 1; 244 u32 rx_hashtype : 9; 245 u32 rx_iphdr_csum_succeed : 1; 246 u32 rx_iphdr_csum_fail : 1; 247 u32 rx_tcp_csum_succeed : 1; 248 u32 rx_tcp_csum_fail : 1; 249 u32 rx_udp_csum_succeed : 1; 250 u32 rx_udp_csum_fail : 1; 251 u32 reserved2 : 1; 252 253 struct mana_rxcomp_perpkt_info ppi[MANA_RXCOMP_OOB_NUM_PPI]; 254 255 u32 rx_wqe_offset; 256 }; /* HW DATA */ 257 258 struct mana_tx_comp_oob { 259 struct mana_cqe_header cqe_hdr; 260 261 u32 tx_data_offset; 262 263 u32 tx_sgl_offset : 5; 264 u32 tx_wqe_offset : 27; 265 266 u32 reserved[12]; 267 }; /* HW DATA */ 268 269 struct mana_rxq; 270 271 #define CQE_POLLING_BUFFER 512 272 273 struct mana_cq { 274 struct gdma_queue *gdma_cq; 275 276 /* Cache the CQ id (used to verify if each CQE comes to the right CQ. */ 277 u32 gdma_id; 278 279 /* Type of the CQ: TX or RX */ 280 enum mana_cq_type type; 281 282 /* Pointer to the mana_rxq that is pushing RX CQEs to the queue. 283 * Only and must be non-NULL if type is MANA_CQ_TYPE_RX. 284 */ 285 struct mana_rxq *rxq; 286 287 /* Pointer to the mana_txq that is pushing TX CQEs to the queue. 288 * Only and must be non-NULL if type is MANA_CQ_TYPE_TX. 289 */ 290 struct mana_txq *txq; 291 292 /* Buffer which the CQ handler can copy the CQE's into. */ 293 struct gdma_comp gdma_comp_buf[CQE_POLLING_BUFFER]; 294 295 /* NAPI data */ 296 struct napi_struct napi; 297 int work_done; 298 int work_done_since_doorbell; 299 int budget; 300 }; 301 302 struct mana_recv_buf_oob { 303 /* A valid GDMA work request representing the data buffer. */ 304 struct gdma_wqe_request wqe_req; 305 306 void *buf_va; 307 bool from_pool; /* allocated from a page pool */ 308 /* head page of the page_pool fragment; valid only when 309 * from_pool && frag_count > 1. 310 */ 311 struct page *pp_page; 312 /* Fragment offset plus rxq->headroom, passed to 313 * page_pool_dma_sync_for_cpu(). 314 */ 315 u32 dma_sync_offset; 316 317 /* SGL of the buffer going to be sent as part of the work request. */ 318 u32 num_sge; 319 struct gdma_sge sgl[MAX_RX_WQE_SGL_ENTRIES]; 320 321 /* Required to store the result of mana_gd_post_work_request. 322 * gdma_posted_wqe_info.wqe_size_in_bu is required for progressing the 323 * work queue when the WQE is consumed. 324 */ 325 struct gdma_posted_wqe_info wqe_inf; 326 }; 327 328 #define MANA_RXBUF_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) \ 329 + ETH_HLEN) 330 331 #define MANA_XDP_MTU_MAX (PAGE_SIZE - MANA_RXBUF_PAD - XDP_PACKET_HEADROOM) 332 333 struct mana_rxq { 334 struct gdma_queue *gdma_rq; 335 /* Cache the gdma receive queue id */ 336 u32 gdma_id; 337 338 /* Index of RQ in the vPort, not gdma receive queue id */ 339 u32 rxq_idx; 340 341 u32 datasize; 342 u32 alloc_size; 343 u32 headroom; 344 u32 frag_count; 345 346 mana_handle_t rxobj; 347 348 struct mana_cq rx_cq; 349 350 struct completion fence_event; 351 352 struct net_device *ndev; 353 354 /* Total number of receive buffers to be allocated */ 355 u32 num_rx_buf; 356 357 u32 buf_index; 358 359 struct mana_stats_rx stats; 360 361 struct bpf_prog __rcu *bpf_prog; 362 struct xdp_rxq_info xdp_rxq; 363 void *xdp_save_va; /* for reusing */ 364 bool xdp_flush; 365 int xdp_rc; /* XDP redirect return code */ 366 367 struct page_pool *page_pool; 368 struct dentry *mana_rx_debugfs; 369 370 /* MUST BE THE LAST MEMBER: 371 * Each receive buffer has an associated mana_recv_buf_oob. 372 */ 373 struct mana_recv_buf_oob rx_oobs[] __counted_by(num_rx_buf); 374 }; 375 376 struct mana_tx_qp { 377 struct mana_txq txq; 378 379 struct mana_cq tx_cq; 380 381 mana_handle_t tx_object; 382 383 struct dentry *mana_tx_debugfs; 384 }; 385 386 struct mana_ethtool_stats { 387 u64 stop_queue; 388 u64 wake_queue; 389 u64 tx_cqe_err; 390 u64 tx_cqe_unknown_type; 391 u64 tx_linear_pkt_cnt; 392 u64 rx_cqe_unknown_type; 393 }; 394 395 struct mana_ethtool_hc_stats { 396 u64 hc_rx_discards_no_wqe; 397 u64 hc_rx_err_vport_disabled; 398 u64 hc_rx_bytes; 399 u64 hc_rx_ucast_pkts; 400 u64 hc_rx_ucast_bytes; 401 u64 hc_rx_bcast_pkts; 402 u64 hc_rx_bcast_bytes; 403 u64 hc_rx_mcast_pkts; 404 u64 hc_rx_mcast_bytes; 405 u64 hc_tx_err_gf_disabled; 406 u64 hc_tx_err_vport_disabled; 407 u64 hc_tx_err_inval_vportoffset_pkt; 408 u64 hc_tx_err_vlan_enforcement; 409 u64 hc_tx_err_eth_type_enforcement; 410 u64 hc_tx_err_sa_enforcement; 411 u64 hc_tx_err_sqpdid_enforcement; 412 u64 hc_tx_err_cqpdid_enforcement; 413 u64 hc_tx_err_mtu_violation; 414 u64 hc_tx_err_inval_oob; 415 u64 hc_tx_bytes; 416 u64 hc_tx_ucast_pkts; 417 u64 hc_tx_ucast_bytes; 418 u64 hc_tx_bcast_pkts; 419 u64 hc_tx_bcast_bytes; 420 u64 hc_tx_mcast_pkts; 421 u64 hc_tx_mcast_bytes; 422 u64 hc_tx_err_gdma; 423 }; 424 425 struct mana_ethtool_phy_stats { 426 /* Drop Counters */ 427 u64 rx_pkt_drop_phy; 428 u64 tx_pkt_drop_phy; 429 430 /* Per TC traffic Counters */ 431 u64 rx_pkt_tc0_phy; 432 u64 tx_pkt_tc0_phy; 433 u64 rx_pkt_tc1_phy; 434 u64 tx_pkt_tc1_phy; 435 u64 rx_pkt_tc2_phy; 436 u64 tx_pkt_tc2_phy; 437 u64 rx_pkt_tc3_phy; 438 u64 tx_pkt_tc3_phy; 439 u64 rx_pkt_tc4_phy; 440 u64 tx_pkt_tc4_phy; 441 u64 rx_pkt_tc5_phy; 442 u64 tx_pkt_tc5_phy; 443 u64 rx_pkt_tc6_phy; 444 u64 tx_pkt_tc6_phy; 445 u64 rx_pkt_tc7_phy; 446 u64 tx_pkt_tc7_phy; 447 448 u64 rx_byte_tc0_phy; 449 u64 tx_byte_tc0_phy; 450 u64 rx_byte_tc1_phy; 451 u64 tx_byte_tc1_phy; 452 u64 rx_byte_tc2_phy; 453 u64 tx_byte_tc2_phy; 454 u64 rx_byte_tc3_phy; 455 u64 tx_byte_tc3_phy; 456 u64 rx_byte_tc4_phy; 457 u64 tx_byte_tc4_phy; 458 u64 rx_byte_tc5_phy; 459 u64 tx_byte_tc5_phy; 460 u64 rx_byte_tc6_phy; 461 u64 tx_byte_tc6_phy; 462 u64 rx_byte_tc7_phy; 463 u64 tx_byte_tc7_phy; 464 465 /* Per TC pause Counters */ 466 u64 rx_pause_tc0_phy; 467 u64 tx_pause_tc0_phy; 468 u64 rx_pause_tc1_phy; 469 u64 tx_pause_tc1_phy; 470 u64 rx_pause_tc2_phy; 471 u64 tx_pause_tc2_phy; 472 u64 rx_pause_tc3_phy; 473 u64 tx_pause_tc3_phy; 474 u64 rx_pause_tc4_phy; 475 u64 tx_pause_tc4_phy; 476 u64 rx_pause_tc5_phy; 477 u64 tx_pause_tc5_phy; 478 u64 rx_pause_tc6_phy; 479 u64 tx_pause_tc6_phy; 480 u64 rx_pause_tc7_phy; 481 u64 tx_pause_tc7_phy; 482 }; 483 484 struct mana_context { 485 struct gdma_dev *gdma_dev; 486 487 u16 num_ports; 488 u8 bm_hostmode; 489 490 struct mana_ethtool_hc_stats hc_stats; 491 struct workqueue_struct *per_port_queue_reset_wq; 492 /* Workqueue for querying hardware stats */ 493 struct delayed_work gf_stats_work; 494 bool hwc_timeout_occurred; 495 496 struct net_device *ports[MAX_PORTS_IN_MANA_DEV]; 497 498 /* Link state change work */ 499 struct work_struct link_change_work; 500 u32 link_event; 501 }; 502 503 struct mana_port_context { 504 struct mana_context *ac; 505 struct net_device *ndev; 506 struct work_struct queue_reset_work; 507 508 u8 mac_addr[ETH_ALEN]; 509 510 struct mana_eq *eqs; 511 struct dentry *mana_eqs_debugfs; 512 513 enum TRI_STATE rss_state; 514 515 mana_handle_t default_rxobj; 516 bool tx_shortform_allowed; 517 u16 tx_vp_offset; 518 519 struct mana_tx_qp **tx_qp; 520 521 /* Indirection Table for RX & TX. The values are queue indexes */ 522 u32 *indir_table; 523 u32 indir_table_sz; 524 525 /* Indirection table containing RxObject Handles */ 526 mana_handle_t *rxobj_table; 527 528 /* Hash key used by the NIC */ 529 u8 hashkey[MANA_HASH_KEY_SIZE]; 530 531 /* This points to an array of num_queues of RQ pointers. */ 532 struct mana_rxq **rxqs; 533 534 /* pre-allocated rx buffer array */ 535 void **rxbufs_pre; 536 dma_addr_t *das_pre; 537 int rxbpre_total; 538 u32 rxbpre_datasize; 539 u32 rxbpre_alloc_size; 540 u32 rxbpre_headroom; 541 u32 rxbpre_frag_count; 542 543 struct bpf_prog *bpf_prog; 544 545 /* Create num_queues EQs, SQs, SQ-CQs, RQs and RQ-CQs, respectively. */ 546 unsigned int max_queues; 547 unsigned int num_queues; 548 549 unsigned int rx_queue_size; 550 unsigned int tx_queue_size; 551 552 mana_handle_t port_handle; 553 mana_handle_t pf_filter_handle; 554 555 /* Mutex for sharing access to vport_use_count */ 556 struct mutex vport_mutex; 557 int vport_use_count; 558 559 /* Set by mana_set_channels() under vport_mutex to block RDMA 560 * from grabbing the vport during the detach/attach window. 561 * Checked by mana_cfg_vport() when called from the RDMA path. 562 */ 563 bool channel_changing; 564 565 /* Net shaper handle*/ 566 struct net_shaper_handle handle; 567 568 u16 port_idx; 569 /* Currently configured speed (mbps) */ 570 u32 speed; 571 /* Maximum speed supported by the SKU (mbps) */ 572 u32 max_speed; 573 /* 1 = not queried, 0 = cached success, negative = permanent error. 574 * Protected by the netdev instance lock. 575 */ 576 int link_cfg_error; 577 578 bool port_is_up; 579 bool port_st_save; /* Saved port state */ 580 581 u8 cqe_coalescing_enable; 582 u32 cqe_coalescing_timeout_ns; 583 584 struct mana_ethtool_stats eth_stats; 585 586 struct mana_ethtool_phy_stats phy_stats; 587 588 /* Debugfs */ 589 struct dentry *mana_port_debugfs; 590 591 /* Cached vport/steering config for debugfs */ 592 u32 vport_max_sq; 593 u32 vport_max_rq; 594 u32 steer_rx; 595 u32 steer_rss; 596 bool steer_update_tab; 597 u32 steer_cqe_coalescing; 598 }; 599 600 netdev_tx_t mana_start_xmit(struct sk_buff *skb, struct net_device *ndev); 601 int mana_config_rss(struct mana_port_context *ac, enum TRI_STATE rx, 602 bool update_hash, bool update_tab); 603 int mana_disable_vport_rx(struct mana_port_context *apc); 604 605 int mana_alloc_queues(struct net_device *ndev); 606 int mana_attach(struct net_device *ndev); 607 int mana_detach(struct net_device *ndev, bool from_close); 608 609 int mana_probe(struct gdma_dev *gd, bool resuming); 610 void mana_remove(struct gdma_dev *gd, bool suspending); 611 612 int mana_rdma_probe(struct gdma_dev *gd); 613 void mana_rdma_remove(struct gdma_dev *gd); 614 615 void mana_xdp_tx(struct sk_buff *skb, struct net_device *ndev); 616 int mana_xdp_xmit(struct net_device *ndev, int n, struct xdp_frame **frames, 617 u32 flags); 618 u32 mana_run_xdp(struct net_device *ndev, struct mana_rxq *rxq, 619 struct xdp_buff *xdp, void *buf_va, uint pkt_len); 620 struct bpf_prog *mana_xdp_get(struct mana_port_context *apc); 621 void mana_chn_setxdp(struct mana_port_context *apc, struct bpf_prog *prog); 622 int mana_bpf(struct net_device *ndev, struct netdev_bpf *bpf); 623 int mana_query_gf_stats(struct mana_context *ac); 624 int mana_query_link_cfg(struct mana_port_context *apc); 625 int mana_set_bw_clamp(struct mana_port_context *apc, u32 speed, 626 int enable_clamping); 627 void mana_query_phy_stats(struct mana_port_context *apc); 628 int mana_pre_alloc_rxbufs(struct mana_port_context *apc, int mtu, int num_queues); 629 void mana_pre_dealloc_rxbufs(struct mana_port_context *apc); 630 void mana_unmap_skb(struct sk_buff *skb, struct mana_port_context *apc); 631 632 extern const struct ethtool_ops mana_ethtool_ops; 633 extern struct dentry *mana_debugfs_root; 634 635 /* A CQ can be created not associated with any EQ */ 636 #define GDMA_CQ_NO_EQ 0xffff 637 638 struct mana_obj_spec { 639 u32 queue_index; 640 u64 gdma_region; 641 u32 queue_size; 642 u32 attached_eq; 643 u32 modr_ctx_id; 644 }; 645 646 enum mana_command_code { 647 MANA_QUERY_DEV_CONFIG = 0x20001, 648 MANA_QUERY_GF_STAT = 0x20002, 649 MANA_CONFIG_VPORT_TX = 0x20003, 650 MANA_CREATE_WQ_OBJ = 0x20004, 651 MANA_DESTROY_WQ_OBJ = 0x20005, 652 MANA_FENCE_RQ = 0x20006, 653 MANA_CONFIG_VPORT_RX = 0x20007, 654 MANA_QUERY_VPORT_CONFIG = 0x20008, 655 MANA_QUERY_LINK_CONFIG = 0x2000A, 656 MANA_SET_BW_CLAMP = 0x2000B, 657 MANA_QUERY_PHY_STAT = 0x2000c, 658 659 /* Privileged commands for the PF mode */ 660 MANA_REGISTER_FILTER = 0x28000, 661 MANA_DEREGISTER_FILTER = 0x28001, 662 MANA_REGISTER_HW_PORT = 0x28003, 663 MANA_DEREGISTER_HW_PORT = 0x28004, 664 }; 665 666 /* Query Link Configuration*/ 667 struct mana_query_link_config_req { 668 struct gdma_req_hdr hdr; 669 mana_handle_t vport; 670 }; /* HW DATA */ 671 672 struct mana_query_link_config_resp { 673 struct gdma_resp_hdr hdr; 674 u32 qos_speed_mbps; 675 u8 qos_unconfigured; 676 u8 reserved1[3]; 677 u32 link_speed_mbps; 678 u8 reserved2[4]; 679 }; /* HW DATA */ 680 681 /* Set Bandwidth Clamp*/ 682 struct mana_set_bw_clamp_req { 683 struct gdma_req_hdr hdr; 684 mana_handle_t vport; 685 enum TRI_STATE enable_clamping; 686 u32 link_speed_mbps; 687 }; /* HW DATA */ 688 689 struct mana_set_bw_clamp_resp { 690 struct gdma_resp_hdr hdr; 691 u8 qos_unconfigured; 692 u8 reserved[7]; 693 }; /* HW DATA */ 694 695 /* Query Device Configuration */ 696 struct mana_query_device_cfg_req { 697 struct gdma_req_hdr hdr; 698 699 /* MANA Nic Driver Capability flags */ 700 u64 mn_drv_cap_flags1; 701 u64 mn_drv_cap_flags2; 702 u64 mn_drv_cap_flags3; 703 u64 mn_drv_cap_flags4; 704 705 u32 proto_major_ver; 706 u32 proto_minor_ver; 707 u32 proto_micro_ver; 708 709 u32 reserved; 710 }; /* HW DATA */ 711 712 struct mana_query_device_cfg_resp { 713 struct gdma_resp_hdr hdr; 714 715 u64 pf_cap_flags1; 716 u64 pf_cap_flags2; 717 u64 pf_cap_flags3; 718 u64 pf_cap_flags4; 719 720 u16 max_num_vports; 721 u8 bm_hostmode; /* response v3: Bare Metal Host Mode */ 722 u8 reserved; 723 u32 max_num_eqs; 724 725 /* response v2: */ 726 u16 adapter_mtu; 727 u16 reserved2; 728 u32 reserved3; 729 }; /* HW DATA */ 730 731 /* Query vPort Configuration */ 732 struct mana_query_vport_cfg_req { 733 struct gdma_req_hdr hdr; 734 u32 vport_index; 735 }; /* HW DATA */ 736 737 struct mana_query_vport_cfg_resp { 738 struct gdma_resp_hdr hdr; 739 u32 max_num_sq; 740 u32 max_num_rq; 741 u32 num_indirection_ent; 742 u32 reserved1; 743 u8 mac_addr[6]; 744 u8 reserved2[2]; 745 mana_handle_t vport; 746 }; /* HW DATA */ 747 748 /* Configure vPort */ 749 struct mana_config_vport_req { 750 struct gdma_req_hdr hdr; 751 mana_handle_t vport; 752 u32 pdid; 753 u32 doorbell_pageid; 754 }; /* HW DATA */ 755 756 struct mana_config_vport_resp { 757 struct gdma_resp_hdr hdr; 758 u16 tx_vport_offset; 759 u8 short_form_allowed; 760 u8 reserved; 761 }; /* HW DATA */ 762 763 /* Create WQ Object */ 764 struct mana_create_wqobj_req { 765 struct gdma_req_hdr hdr; 766 mana_handle_t vport; 767 u32 wq_type; 768 u32 reserved; 769 u64 wq_gdma_region; 770 u64 cq_gdma_region; 771 u32 wq_size; 772 u32 cq_size; 773 u32 cq_moderation_ctx_id; 774 u32 cq_parent_qid; 775 }; /* HW DATA */ 776 777 struct mana_create_wqobj_resp { 778 struct gdma_resp_hdr hdr; 779 u32 wq_id; 780 u32 cq_id; 781 mana_handle_t wq_obj; 782 }; /* HW DATA */ 783 784 /* Destroy WQ Object */ 785 struct mana_destroy_wqobj_req { 786 struct gdma_req_hdr hdr; 787 u32 wq_type; 788 u32 reserved; 789 mana_handle_t wq_obj_handle; 790 }; /* HW DATA */ 791 792 struct mana_destroy_wqobj_resp { 793 struct gdma_resp_hdr hdr; 794 }; /* HW DATA */ 795 796 /* Fence RQ */ 797 struct mana_fence_rq_req { 798 struct gdma_req_hdr hdr; 799 mana_handle_t wq_obj_handle; 800 }; /* HW DATA */ 801 802 struct mana_fence_rq_resp { 803 struct gdma_resp_hdr hdr; 804 }; /* HW DATA */ 805 806 /* Query stats RQ */ 807 struct mana_query_gf_stat_req { 808 struct gdma_req_hdr hdr; 809 u64 req_stats; 810 }; /* HW DATA */ 811 812 struct mana_query_gf_stat_resp { 813 struct gdma_resp_hdr hdr; 814 u64 reported_stats; 815 /* rx errors/discards */ 816 u64 rx_discards_nowqe; 817 u64 rx_err_vport_disabled; 818 /* rx bytes/packets */ 819 u64 hc_rx_bytes; 820 u64 hc_rx_ucast_pkts; 821 u64 hc_rx_ucast_bytes; 822 u64 hc_rx_bcast_pkts; 823 u64 hc_rx_bcast_bytes; 824 u64 hc_rx_mcast_pkts; 825 u64 hc_rx_mcast_bytes; 826 /* tx errors */ 827 u64 tx_err_gf_disabled; 828 u64 tx_err_vport_disabled; 829 u64 tx_err_inval_vport_offset_pkt; 830 u64 tx_err_vlan_enforcement; 831 u64 tx_err_ethtype_enforcement; 832 u64 tx_err_SA_enforcement; 833 u64 tx_err_SQPDID_enforcement; 834 u64 tx_err_CQPDID_enforcement; 835 u64 tx_err_mtu_violation; 836 u64 tx_err_inval_oob; 837 /* tx bytes/packets */ 838 u64 hc_tx_bytes; 839 u64 hc_tx_ucast_pkts; 840 u64 hc_tx_ucast_bytes; 841 u64 hc_tx_bcast_pkts; 842 u64 hc_tx_bcast_bytes; 843 u64 hc_tx_mcast_pkts; 844 u64 hc_tx_mcast_bytes; 845 /* tx error */ 846 u64 tx_err_gdma; 847 }; /* HW DATA */ 848 849 /* Query phy stats */ 850 struct mana_query_phy_stat_req { 851 struct gdma_req_hdr hdr; 852 u64 req_stats; 853 }; /* HW DATA */ 854 855 struct mana_query_phy_stat_resp { 856 struct gdma_resp_hdr hdr; 857 u64 reported_stats; 858 859 /* Aggregate Drop Counters */ 860 u64 rx_pkt_drop_phy; 861 u64 tx_pkt_drop_phy; 862 863 /* Per TC(Traffic class) traffic Counters */ 864 u64 rx_pkt_tc0_phy; 865 u64 tx_pkt_tc0_phy; 866 u64 rx_pkt_tc1_phy; 867 u64 tx_pkt_tc1_phy; 868 u64 rx_pkt_tc2_phy; 869 u64 tx_pkt_tc2_phy; 870 u64 rx_pkt_tc3_phy; 871 u64 tx_pkt_tc3_phy; 872 u64 rx_pkt_tc4_phy; 873 u64 tx_pkt_tc4_phy; 874 u64 rx_pkt_tc5_phy; 875 u64 tx_pkt_tc5_phy; 876 u64 rx_pkt_tc6_phy; 877 u64 tx_pkt_tc6_phy; 878 u64 rx_pkt_tc7_phy; 879 u64 tx_pkt_tc7_phy; 880 881 u64 rx_byte_tc0_phy; 882 u64 tx_byte_tc0_phy; 883 u64 rx_byte_tc1_phy; 884 u64 tx_byte_tc1_phy; 885 u64 rx_byte_tc2_phy; 886 u64 tx_byte_tc2_phy; 887 u64 rx_byte_tc3_phy; 888 u64 tx_byte_tc3_phy; 889 u64 rx_byte_tc4_phy; 890 u64 tx_byte_tc4_phy; 891 u64 rx_byte_tc5_phy; 892 u64 tx_byte_tc5_phy; 893 u64 rx_byte_tc6_phy; 894 u64 tx_byte_tc6_phy; 895 u64 rx_byte_tc7_phy; 896 u64 tx_byte_tc7_phy; 897 898 /* Per TC(Traffic Class) pause Counters */ 899 u64 rx_pause_tc0_phy; 900 u64 tx_pause_tc0_phy; 901 u64 rx_pause_tc1_phy; 902 u64 tx_pause_tc1_phy; 903 u64 rx_pause_tc2_phy; 904 u64 tx_pause_tc2_phy; 905 u64 rx_pause_tc3_phy; 906 u64 tx_pause_tc3_phy; 907 u64 rx_pause_tc4_phy; 908 u64 tx_pause_tc4_phy; 909 u64 rx_pause_tc5_phy; 910 u64 tx_pause_tc5_phy; 911 u64 rx_pause_tc6_phy; 912 u64 tx_pause_tc6_phy; 913 u64 rx_pause_tc7_phy; 914 u64 tx_pause_tc7_phy; 915 }; /* HW DATA */ 916 917 /* Configure vPort Rx Steering */ 918 struct mana_cfg_rx_steer_req_v2 { 919 struct gdma_req_hdr hdr; 920 mana_handle_t vport; 921 u16 num_indir_entries; 922 u16 indir_tab_offset; 923 u32 rx_enable; 924 u32 rss_enable; 925 u8 update_default_rxobj; 926 u8 update_hashkey; 927 u8 update_indir_tab; 928 u8 reserved; 929 mana_handle_t default_rxobj; 930 u8 hashkey[MANA_HASH_KEY_SIZE]; 931 u8 cqe_coalescing_enable; 932 u8 reserved2[7]; 933 mana_handle_t indir_tab[] __counted_by(num_indir_entries); 934 }; /* HW DATA */ 935 936 struct mana_cfg_rx_steer_resp { 937 struct gdma_resp_hdr hdr; 938 939 /* V2 */ 940 u32 cqe_coalescing_timeout_ns; 941 u32 reserved1; 942 }; /* HW DATA */ 943 944 /* Register HW vPort */ 945 struct mana_register_hw_vport_req { 946 struct gdma_req_hdr hdr; 947 u16 attached_gfid; 948 u8 is_pf_default_vport; 949 u8 reserved1; 950 u8 allow_all_ether_types; 951 u8 reserved2; 952 u8 reserved3; 953 u8 reserved4; 954 }; /* HW DATA */ 955 956 struct mana_register_hw_vport_resp { 957 struct gdma_resp_hdr hdr; 958 mana_handle_t hw_vport_handle; 959 }; /* HW DATA */ 960 961 /* Deregister HW vPort */ 962 struct mana_deregister_hw_vport_req { 963 struct gdma_req_hdr hdr; 964 mana_handle_t hw_vport_handle; 965 }; /* HW DATA */ 966 967 struct mana_deregister_hw_vport_resp { 968 struct gdma_resp_hdr hdr; 969 }; /* HW DATA */ 970 971 /* Register filter */ 972 struct mana_register_filter_req { 973 struct gdma_req_hdr hdr; 974 mana_handle_t vport; 975 u8 mac_addr[6]; 976 u8 reserved1; 977 u8 reserved2; 978 u8 reserved3; 979 u8 reserved4; 980 u16 reserved5; 981 u32 reserved6; 982 u32 reserved7; 983 u32 reserved8; 984 }; /* HW DATA */ 985 986 struct mana_register_filter_resp { 987 struct gdma_resp_hdr hdr; 988 mana_handle_t filter_handle; 989 }; /* HW DATA */ 990 991 /* Deregister filter */ 992 struct mana_deregister_filter_req { 993 struct gdma_req_hdr hdr; 994 mana_handle_t filter_handle; 995 }; /* HW DATA */ 996 997 struct mana_deregister_filter_resp { 998 struct gdma_resp_hdr hdr; 999 }; /* HW DATA */ 1000 1001 /* Requested GF stats Flags */ 1002 /* Rx discards/Errors */ 1003 #define STATISTICS_FLAGS_RX_DISCARDS_NO_WQE 0x0000000000000001 1004 #define STATISTICS_FLAGS_RX_ERRORS_VPORT_DISABLED 0x0000000000000002 1005 /* Rx bytes/pkts */ 1006 #define STATISTICS_FLAGS_HC_RX_BYTES 0x0000000000000004 1007 #define STATISTICS_FLAGS_HC_RX_UCAST_PACKETS 0x0000000000000008 1008 #define STATISTICS_FLAGS_HC_RX_UCAST_BYTES 0x0000000000000010 1009 #define STATISTICS_FLAGS_HC_RX_MCAST_PACKETS 0x0000000000000020 1010 #define STATISTICS_FLAGS_HC_RX_MCAST_BYTES 0x0000000000000040 1011 #define STATISTICS_FLAGS_HC_RX_BCAST_PACKETS 0x0000000000000080 1012 #define STATISTICS_FLAGS_HC_RX_BCAST_BYTES 0x0000000000000100 1013 /* Tx errors */ 1014 #define STATISTICS_FLAGS_TX_ERRORS_GF_DISABLED 0x0000000000000200 1015 #define STATISTICS_FLAGS_TX_ERRORS_VPORT_DISABLED 0x0000000000000400 1016 #define STATISTICS_FLAGS_TX_ERRORS_INVAL_VPORT_OFFSET_PACKETS \ 1017 0x0000000000000800 1018 #define STATISTICS_FLAGS_TX_ERRORS_VLAN_ENFORCEMENT 0x0000000000001000 1019 #define STATISTICS_FLAGS_TX_ERRORS_ETH_TYPE_ENFORCEMENT \ 1020 0x0000000000002000 1021 #define STATISTICS_FLAGS_TX_ERRORS_SA_ENFORCEMENT 0x0000000000004000 1022 #define STATISTICS_FLAGS_TX_ERRORS_SQPDID_ENFORCEMENT 0x0000000000008000 1023 #define STATISTICS_FLAGS_TX_ERRORS_CQPDID_ENFORCEMENT 0x0000000000010000 1024 #define STATISTICS_FLAGS_TX_ERRORS_MTU_VIOLATION 0x0000000000020000 1025 #define STATISTICS_FLAGS_TX_ERRORS_INVALID_OOB 0x0000000000040000 1026 /* Tx bytes/pkts */ 1027 #define STATISTICS_FLAGS_HC_TX_BYTES 0x0000000000080000 1028 #define STATISTICS_FLAGS_HC_TX_UCAST_PACKETS 0x0000000000100000 1029 #define STATISTICS_FLAGS_HC_TX_UCAST_BYTES 0x0000000000200000 1030 #define STATISTICS_FLAGS_HC_TX_MCAST_PACKETS 0x0000000000400000 1031 #define STATISTICS_FLAGS_HC_TX_MCAST_BYTES 0x0000000000800000 1032 #define STATISTICS_FLAGS_HC_TX_BCAST_PACKETS 0x0000000001000000 1033 #define STATISTICS_FLAGS_HC_TX_BCAST_BYTES 0x0000000002000000 1034 /* Tx error */ 1035 #define STATISTICS_FLAGS_TX_ERRORS_GDMA_ERROR 0x0000000004000000 1036 1037 #define MANA_MAX_NUM_QUEUES 64 1038 #define MANA_DEF_NUM_QUEUES 16 1039 1040 #define MANA_SHORT_VPORT_OFFSET_MAX ((1U << 8) - 1) 1041 1042 struct mana_tx_package { 1043 struct gdma_wqe_request wqe_req; 1044 struct gdma_sge sgl_array[5]; 1045 struct gdma_sge *sgl_ptr; 1046 1047 struct mana_tx_oob tx_oob; 1048 1049 struct gdma_posted_wqe_info wqe_info; 1050 }; 1051 1052 int mana_create_wq_obj(struct mana_port_context *apc, 1053 mana_handle_t vport, 1054 u32 wq_type, struct mana_obj_spec *wq_spec, 1055 struct mana_obj_spec *cq_spec, 1056 mana_handle_t *wq_obj); 1057 1058 void mana_destroy_wq_obj(struct mana_port_context *apc, u32 wq_type, 1059 mana_handle_t wq_obj); 1060 1061 int mana_cfg_vport(struct mana_port_context *apc, u32 protection_dom_id, 1062 u32 doorbell_pg_id, bool check_channel_changing); 1063 void mana_uncfg_vport(struct mana_port_context *apc); 1064 int mana_create_eq(struct mana_port_context *apc); 1065 void mana_destroy_eq(struct mana_port_context *apc); 1066 1067 struct net_device *mana_get_primary_netdev(struct mana_context *ac, 1068 u32 port_index, 1069 netdevice_tracker *tracker); 1070 #endif /* _MANA_H */ 1071