1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #ifndef _MANA_H 5 #define _MANA_H 6 7 #include <net/xdp.h> 8 9 #include "gdma.h" 10 #include "hw_channel.h" 11 12 /* Microsoft Azure Network Adapter (MANA)'s definitions 13 * 14 * Structures labeled with "HW DATA" are exchanged with the hardware. All of 15 * them are naturally aligned and hence don't need __packed. 16 */ 17 18 /* MANA protocol version */ 19 #define MANA_MAJOR_VERSION 0 20 #define MANA_MINOR_VERSION 1 21 #define MANA_MICRO_VERSION 1 22 23 typedef u64 mana_handle_t; 24 #define INVALID_MANA_HANDLE ((mana_handle_t)-1) 25 26 enum TRI_STATE { 27 TRI_STATE_UNKNOWN = -1, 28 TRI_STATE_FALSE = 0, 29 TRI_STATE_TRUE = 1 30 }; 31 32 /* Number of entries for hardware indirection table must be in power of 2 */ 33 #define MANA_INDIRECT_TABLE_SIZE 64 34 #define MANA_INDIRECT_TABLE_MASK (MANA_INDIRECT_TABLE_SIZE - 1) 35 36 /* The Toeplitz hash key's length in bytes: should be multiple of 8 */ 37 #define MANA_HASH_KEY_SIZE 40 38 39 #define COMP_ENTRY_SIZE 64 40 41 #define RX_BUFFERS_PER_QUEUE 512 42 #define MANA_RX_DATA_ALIGN 64 43 44 #define MAX_SEND_BUFFERS_PER_QUEUE 256 45 46 #define EQ_SIZE (8 * PAGE_SIZE) 47 #define LOG2_EQ_THROTTLE 3 48 49 #define MAX_PORTS_IN_MANA_DEV 256 50 51 /* Update this count whenever the respective structures are changed */ 52 #define MANA_STATS_RX_COUNT 5 53 #define MANA_STATS_TX_COUNT 11 54 55 struct mana_stats_rx { 56 u64 packets; 57 u64 bytes; 58 u64 xdp_drop; 59 u64 xdp_tx; 60 u64 xdp_redirect; 61 struct u64_stats_sync syncp; 62 }; 63 64 struct mana_stats_tx { 65 u64 packets; 66 u64 bytes; 67 u64 xdp_xmit; 68 u64 tso_packets; 69 u64 tso_bytes; 70 u64 tso_inner_packets; 71 u64 tso_inner_bytes; 72 u64 short_pkt_fmt; 73 u64 long_pkt_fmt; 74 u64 csum_partial; 75 u64 mana_map_err; 76 struct u64_stats_sync syncp; 77 }; 78 79 struct mana_txq { 80 struct gdma_queue *gdma_sq; 81 82 union { 83 u32 gdma_txq_id; 84 struct { 85 u32 reserved1 : 10; 86 u32 vsq_frame : 14; 87 u32 reserved2 : 8; 88 }; 89 }; 90 91 u16 vp_offset; 92 93 struct net_device *ndev; 94 95 /* The SKBs are sent to the HW and we are waiting for the CQEs. */ 96 struct sk_buff_head pending_skbs; 97 struct netdev_queue *net_txq; 98 99 atomic_t pending_sends; 100 101 struct mana_stats_tx stats; 102 }; 103 104 /* skb data and frags dma mappings */ 105 struct mana_skb_head { 106 dma_addr_t dma_handle[MAX_SKB_FRAGS + 1]; 107 108 u32 size[MAX_SKB_FRAGS + 1]; 109 }; 110 111 #define MANA_HEADROOM sizeof(struct mana_skb_head) 112 113 enum mana_tx_pkt_format { 114 MANA_SHORT_PKT_FMT = 0, 115 MANA_LONG_PKT_FMT = 1, 116 }; 117 118 struct mana_tx_short_oob { 119 u32 pkt_fmt : 2; 120 u32 is_outer_ipv4 : 1; 121 u32 is_outer_ipv6 : 1; 122 u32 comp_iphdr_csum : 1; 123 u32 comp_tcp_csum : 1; 124 u32 comp_udp_csum : 1; 125 u32 supress_txcqe_gen : 1; 126 u32 vcq_num : 24; 127 128 u32 trans_off : 10; /* Transport header offset */ 129 u32 vsq_frame : 14; 130 u32 short_vp_offset : 8; 131 }; /* HW DATA */ 132 133 struct mana_tx_long_oob { 134 u32 is_encap : 1; 135 u32 inner_is_ipv6 : 1; 136 u32 inner_tcp_opt : 1; 137 u32 inject_vlan_pri_tag : 1; 138 u32 reserved1 : 12; 139 u32 pcp : 3; /* 802.1Q */ 140 u32 dei : 1; /* 802.1Q */ 141 u32 vlan_id : 12; /* 802.1Q */ 142 143 u32 inner_frame_offset : 10; 144 u32 inner_ip_rel_offset : 6; 145 u32 long_vp_offset : 12; 146 u32 reserved2 : 4; 147 148 u32 reserved3; 149 u32 reserved4; 150 }; /* HW DATA */ 151 152 struct mana_tx_oob { 153 struct mana_tx_short_oob s_oob; 154 struct mana_tx_long_oob l_oob; 155 }; /* HW DATA */ 156 157 enum mana_cq_type { 158 MANA_CQ_TYPE_RX, 159 MANA_CQ_TYPE_TX, 160 }; 161 162 enum mana_cqe_type { 163 CQE_INVALID = 0, 164 CQE_RX_OKAY = 1, 165 CQE_RX_COALESCED_4 = 2, 166 CQE_RX_OBJECT_FENCE = 3, 167 CQE_RX_TRUNCATED = 4, 168 169 CQE_TX_OKAY = 32, 170 CQE_TX_SA_DROP = 33, 171 CQE_TX_MTU_DROP = 34, 172 CQE_TX_INVALID_OOB = 35, 173 CQE_TX_INVALID_ETH_TYPE = 36, 174 CQE_TX_HDR_PROCESSING_ERROR = 37, 175 CQE_TX_VF_DISABLED = 38, 176 CQE_TX_VPORT_IDX_OUT_OF_RANGE = 39, 177 CQE_TX_VPORT_DISABLED = 40, 178 CQE_TX_VLAN_TAGGING_VIOLATION = 41, 179 }; 180 181 #define MANA_CQE_COMPLETION 1 182 183 struct mana_cqe_header { 184 u32 cqe_type : 6; 185 u32 client_type : 2; 186 u32 vendor_err : 24; 187 }; /* HW DATA */ 188 189 /* NDIS HASH Types */ 190 #define NDIS_HASH_IPV4 BIT(0) 191 #define NDIS_HASH_TCP_IPV4 BIT(1) 192 #define NDIS_HASH_UDP_IPV4 BIT(2) 193 #define NDIS_HASH_IPV6 BIT(3) 194 #define NDIS_HASH_TCP_IPV6 BIT(4) 195 #define NDIS_HASH_UDP_IPV6 BIT(5) 196 #define NDIS_HASH_IPV6_EX BIT(6) 197 #define NDIS_HASH_TCP_IPV6_EX BIT(7) 198 #define NDIS_HASH_UDP_IPV6_EX BIT(8) 199 200 #define MANA_HASH_L3 (NDIS_HASH_IPV4 | NDIS_HASH_IPV6 | NDIS_HASH_IPV6_EX) 201 #define MANA_HASH_L4 \ 202 (NDIS_HASH_TCP_IPV4 | NDIS_HASH_UDP_IPV4 | NDIS_HASH_TCP_IPV6 | \ 203 NDIS_HASH_UDP_IPV6 | NDIS_HASH_TCP_IPV6_EX | NDIS_HASH_UDP_IPV6_EX) 204 205 struct mana_rxcomp_perpkt_info { 206 u32 pkt_len : 16; 207 u32 reserved1 : 16; 208 u32 reserved2; 209 u32 pkt_hash; 210 }; /* HW DATA */ 211 212 #define MANA_RXCOMP_OOB_NUM_PPI 4 213 214 /* Receive completion OOB */ 215 struct mana_rxcomp_oob { 216 struct mana_cqe_header cqe_hdr; 217 218 u32 rx_vlan_id : 12; 219 u32 rx_vlantag_present : 1; 220 u32 rx_outer_iphdr_csum_succeed : 1; 221 u32 rx_outer_iphdr_csum_fail : 1; 222 u32 reserved1 : 1; 223 u32 rx_hashtype : 9; 224 u32 rx_iphdr_csum_succeed : 1; 225 u32 rx_iphdr_csum_fail : 1; 226 u32 rx_tcp_csum_succeed : 1; 227 u32 rx_tcp_csum_fail : 1; 228 u32 rx_udp_csum_succeed : 1; 229 u32 rx_udp_csum_fail : 1; 230 u32 reserved2 : 1; 231 232 struct mana_rxcomp_perpkt_info ppi[MANA_RXCOMP_OOB_NUM_PPI]; 233 234 u32 rx_wqe_offset; 235 }; /* HW DATA */ 236 237 struct mana_tx_comp_oob { 238 struct mana_cqe_header cqe_hdr; 239 240 u32 tx_data_offset; 241 242 u32 tx_sgl_offset : 5; 243 u32 tx_wqe_offset : 27; 244 245 u32 reserved[12]; 246 }; /* HW DATA */ 247 248 struct mana_rxq; 249 250 #define CQE_POLLING_BUFFER 512 251 252 struct mana_cq { 253 struct gdma_queue *gdma_cq; 254 255 /* Cache the CQ id (used to verify if each CQE comes to the right CQ. */ 256 u32 gdma_id; 257 258 /* Type of the CQ: TX or RX */ 259 enum mana_cq_type type; 260 261 /* Pointer to the mana_rxq that is pushing RX CQEs to the queue. 262 * Only and must be non-NULL if type is MANA_CQ_TYPE_RX. 263 */ 264 struct mana_rxq *rxq; 265 266 /* Pointer to the mana_txq that is pushing TX CQEs to the queue. 267 * Only and must be non-NULL if type is MANA_CQ_TYPE_TX. 268 */ 269 struct mana_txq *txq; 270 271 /* Buffer which the CQ handler can copy the CQE's into. */ 272 struct gdma_comp gdma_comp_buf[CQE_POLLING_BUFFER]; 273 274 /* NAPI data */ 275 struct napi_struct napi; 276 int work_done; 277 int budget; 278 }; 279 280 struct mana_recv_buf_oob { 281 /* A valid GDMA work request representing the data buffer. */ 282 struct gdma_wqe_request wqe_req; 283 284 void *buf_va; 285 286 /* SGL of the buffer going to be sent has part of the work request. */ 287 u32 num_sge; 288 struct gdma_sge sgl[MAX_RX_WQE_SGL_ENTRIES]; 289 290 /* Required to store the result of mana_gd_post_work_request. 291 * gdma_posted_wqe_info.wqe_size_in_bu is required for progressing the 292 * work queue when the WQE is consumed. 293 */ 294 struct gdma_posted_wqe_info wqe_inf; 295 }; 296 297 #define MANA_RXBUF_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) \ 298 + ETH_HLEN) 299 300 #define MANA_XDP_MTU_MAX (PAGE_SIZE - MANA_RXBUF_PAD - XDP_PACKET_HEADROOM) 301 302 struct mana_rxq { 303 struct gdma_queue *gdma_rq; 304 /* Cache the gdma receive queue id */ 305 u32 gdma_id; 306 307 /* Index of RQ in the vPort, not gdma receive queue id */ 308 u32 rxq_idx; 309 310 u32 datasize; 311 u32 alloc_size; 312 u32 headroom; 313 314 mana_handle_t rxobj; 315 316 struct mana_cq rx_cq; 317 318 struct completion fence_event; 319 320 struct net_device *ndev; 321 322 /* Total number of receive buffers to be allocated */ 323 u32 num_rx_buf; 324 325 u32 buf_index; 326 327 struct mana_stats_rx stats; 328 329 struct bpf_prog __rcu *bpf_prog; 330 struct xdp_rxq_info xdp_rxq; 331 void *xdp_save_va; /* for reusing */ 332 bool xdp_flush; 333 int xdp_rc; /* XDP redirect return code */ 334 335 /* MUST BE THE LAST MEMBER: 336 * Each receive buffer has an associated mana_recv_buf_oob. 337 */ 338 struct mana_recv_buf_oob rx_oobs[]; 339 }; 340 341 struct mana_tx_qp { 342 struct mana_txq txq; 343 344 struct mana_cq tx_cq; 345 346 mana_handle_t tx_object; 347 }; 348 349 struct mana_ethtool_stats { 350 u64 stop_queue; 351 u64 wake_queue; 352 u64 tx_cqe_err; 353 u64 tx_cqe_unknown_type; 354 u64 rx_coalesced_err; 355 u64 rx_cqe_unknown_type; 356 }; 357 358 struct mana_context { 359 struct gdma_dev *gdma_dev; 360 361 u16 num_ports; 362 363 struct mana_eq *eqs; 364 365 struct net_device *ports[MAX_PORTS_IN_MANA_DEV]; 366 }; 367 368 struct mana_port_context { 369 struct mana_context *ac; 370 struct net_device *ndev; 371 372 u8 mac_addr[ETH_ALEN]; 373 374 enum TRI_STATE rss_state; 375 376 mana_handle_t default_rxobj; 377 bool tx_shortform_allowed; 378 u16 tx_vp_offset; 379 380 struct mana_tx_qp *tx_qp; 381 382 /* Indirection Table for RX & TX. The values are queue indexes */ 383 u32 indir_table[MANA_INDIRECT_TABLE_SIZE]; 384 385 /* Indirection table containing RxObject Handles */ 386 mana_handle_t rxobj_table[MANA_INDIRECT_TABLE_SIZE]; 387 388 /* Hash key used by the NIC */ 389 u8 hashkey[MANA_HASH_KEY_SIZE]; 390 391 /* This points to an array of num_queues of RQ pointers. */ 392 struct mana_rxq **rxqs; 393 394 /* pre-allocated rx buffer array */ 395 void **rxbufs_pre; 396 dma_addr_t *das_pre; 397 int rxbpre_total; 398 u32 rxbpre_datasize; 399 u32 rxbpre_alloc_size; 400 u32 rxbpre_headroom; 401 402 struct bpf_prog *bpf_prog; 403 404 /* Create num_queues EQs, SQs, SQ-CQs, RQs and RQ-CQs, respectively. */ 405 unsigned int max_queues; 406 unsigned int num_queues; 407 408 mana_handle_t port_handle; 409 mana_handle_t pf_filter_handle; 410 411 /* Mutex for sharing access to vport_use_count */ 412 struct mutex vport_mutex; 413 int vport_use_count; 414 415 u16 port_idx; 416 417 bool port_is_up; 418 bool port_st_save; /* Saved port state */ 419 420 struct mana_ethtool_stats eth_stats; 421 }; 422 423 netdev_tx_t mana_start_xmit(struct sk_buff *skb, struct net_device *ndev); 424 int mana_config_rss(struct mana_port_context *ac, enum TRI_STATE rx, 425 bool update_hash, bool update_tab); 426 427 int mana_alloc_queues(struct net_device *ndev); 428 int mana_attach(struct net_device *ndev); 429 int mana_detach(struct net_device *ndev, bool from_close); 430 431 int mana_probe(struct gdma_dev *gd, bool resuming); 432 void mana_remove(struct gdma_dev *gd, bool suspending); 433 434 void mana_xdp_tx(struct sk_buff *skb, struct net_device *ndev); 435 int mana_xdp_xmit(struct net_device *ndev, int n, struct xdp_frame **frames, 436 u32 flags); 437 u32 mana_run_xdp(struct net_device *ndev, struct mana_rxq *rxq, 438 struct xdp_buff *xdp, void *buf_va, uint pkt_len); 439 struct bpf_prog *mana_xdp_get(struct mana_port_context *apc); 440 void mana_chn_setxdp(struct mana_port_context *apc, struct bpf_prog *prog); 441 int mana_bpf(struct net_device *ndev, struct netdev_bpf *bpf); 442 443 extern const struct ethtool_ops mana_ethtool_ops; 444 445 /* A CQ can be created not associated with any EQ */ 446 #define GDMA_CQ_NO_EQ 0xffff 447 448 struct mana_obj_spec { 449 u32 queue_index; 450 u64 gdma_region; 451 u32 queue_size; 452 u32 attached_eq; 453 u32 modr_ctx_id; 454 }; 455 456 enum mana_command_code { 457 MANA_QUERY_DEV_CONFIG = 0x20001, 458 MANA_QUERY_GF_STAT = 0x20002, 459 MANA_CONFIG_VPORT_TX = 0x20003, 460 MANA_CREATE_WQ_OBJ = 0x20004, 461 MANA_DESTROY_WQ_OBJ = 0x20005, 462 MANA_FENCE_RQ = 0x20006, 463 MANA_CONFIG_VPORT_RX = 0x20007, 464 MANA_QUERY_VPORT_CONFIG = 0x20008, 465 466 /* Privileged commands for the PF mode */ 467 MANA_REGISTER_FILTER = 0x28000, 468 MANA_DEREGISTER_FILTER = 0x28001, 469 MANA_REGISTER_HW_PORT = 0x28003, 470 MANA_DEREGISTER_HW_PORT = 0x28004, 471 }; 472 473 /* Query Device Configuration */ 474 struct mana_query_device_cfg_req { 475 struct gdma_req_hdr hdr; 476 477 /* MANA Nic Driver Capability flags */ 478 u64 mn_drv_cap_flags1; 479 u64 mn_drv_cap_flags2; 480 u64 mn_drv_cap_flags3; 481 u64 mn_drv_cap_flags4; 482 483 u32 proto_major_ver; 484 u32 proto_minor_ver; 485 u32 proto_micro_ver; 486 487 u32 reserved; 488 }; /* HW DATA */ 489 490 struct mana_query_device_cfg_resp { 491 struct gdma_resp_hdr hdr; 492 493 u64 pf_cap_flags1; 494 u64 pf_cap_flags2; 495 u64 pf_cap_flags3; 496 u64 pf_cap_flags4; 497 498 u16 max_num_vports; 499 u16 reserved; 500 u32 max_num_eqs; 501 502 /* response v2: */ 503 u16 adapter_mtu; 504 u16 reserved2; 505 u32 reserved3; 506 }; /* HW DATA */ 507 508 /* Query vPort Configuration */ 509 struct mana_query_vport_cfg_req { 510 struct gdma_req_hdr hdr; 511 u32 vport_index; 512 }; /* HW DATA */ 513 514 struct mana_query_vport_cfg_resp { 515 struct gdma_resp_hdr hdr; 516 u32 max_num_sq; 517 u32 max_num_rq; 518 u32 num_indirection_ent; 519 u32 reserved1; 520 u8 mac_addr[6]; 521 u8 reserved2[2]; 522 mana_handle_t vport; 523 }; /* HW DATA */ 524 525 /* Configure vPort */ 526 struct mana_config_vport_req { 527 struct gdma_req_hdr hdr; 528 mana_handle_t vport; 529 u32 pdid; 530 u32 doorbell_pageid; 531 }; /* HW DATA */ 532 533 struct mana_config_vport_resp { 534 struct gdma_resp_hdr hdr; 535 u16 tx_vport_offset; 536 u8 short_form_allowed; 537 u8 reserved; 538 }; /* HW DATA */ 539 540 /* Create WQ Object */ 541 struct mana_create_wqobj_req { 542 struct gdma_req_hdr hdr; 543 mana_handle_t vport; 544 u32 wq_type; 545 u32 reserved; 546 u64 wq_gdma_region; 547 u64 cq_gdma_region; 548 u32 wq_size; 549 u32 cq_size; 550 u32 cq_moderation_ctx_id; 551 u32 cq_parent_qid; 552 }; /* HW DATA */ 553 554 struct mana_create_wqobj_resp { 555 struct gdma_resp_hdr hdr; 556 u32 wq_id; 557 u32 cq_id; 558 mana_handle_t wq_obj; 559 }; /* HW DATA */ 560 561 /* Destroy WQ Object */ 562 struct mana_destroy_wqobj_req { 563 struct gdma_req_hdr hdr; 564 u32 wq_type; 565 u32 reserved; 566 mana_handle_t wq_obj_handle; 567 }; /* HW DATA */ 568 569 struct mana_destroy_wqobj_resp { 570 struct gdma_resp_hdr hdr; 571 }; /* HW DATA */ 572 573 /* Fence RQ */ 574 struct mana_fence_rq_req { 575 struct gdma_req_hdr hdr; 576 mana_handle_t wq_obj_handle; 577 }; /* HW DATA */ 578 579 struct mana_fence_rq_resp { 580 struct gdma_resp_hdr hdr; 581 }; /* HW DATA */ 582 583 /* Configure vPort Rx Steering */ 584 struct mana_cfg_rx_steer_req_v2 { 585 struct gdma_req_hdr hdr; 586 mana_handle_t vport; 587 u16 num_indir_entries; 588 u16 indir_tab_offset; 589 u32 rx_enable; 590 u32 rss_enable; 591 u8 update_default_rxobj; 592 u8 update_hashkey; 593 u8 update_indir_tab; 594 u8 reserved; 595 mana_handle_t default_rxobj; 596 u8 hashkey[MANA_HASH_KEY_SIZE]; 597 u8 cqe_coalescing_enable; 598 u8 reserved2[7]; 599 }; /* HW DATA */ 600 601 struct mana_cfg_rx_steer_resp { 602 struct gdma_resp_hdr hdr; 603 }; /* HW DATA */ 604 605 /* Register HW vPort */ 606 struct mana_register_hw_vport_req { 607 struct gdma_req_hdr hdr; 608 u16 attached_gfid; 609 u8 is_pf_default_vport; 610 u8 reserved1; 611 u8 allow_all_ether_types; 612 u8 reserved2; 613 u8 reserved3; 614 u8 reserved4; 615 }; /* HW DATA */ 616 617 struct mana_register_hw_vport_resp { 618 struct gdma_resp_hdr hdr; 619 mana_handle_t hw_vport_handle; 620 }; /* HW DATA */ 621 622 /* Deregister HW vPort */ 623 struct mana_deregister_hw_vport_req { 624 struct gdma_req_hdr hdr; 625 mana_handle_t hw_vport_handle; 626 }; /* HW DATA */ 627 628 struct mana_deregister_hw_vport_resp { 629 struct gdma_resp_hdr hdr; 630 }; /* HW DATA */ 631 632 /* Register filter */ 633 struct mana_register_filter_req { 634 struct gdma_req_hdr hdr; 635 mana_handle_t vport; 636 u8 mac_addr[6]; 637 u8 reserved1; 638 u8 reserved2; 639 u8 reserved3; 640 u8 reserved4; 641 u16 reserved5; 642 u32 reserved6; 643 u32 reserved7; 644 u32 reserved8; 645 }; /* HW DATA */ 646 647 struct mana_register_filter_resp { 648 struct gdma_resp_hdr hdr; 649 mana_handle_t filter_handle; 650 }; /* HW DATA */ 651 652 /* Deregister filter */ 653 struct mana_deregister_filter_req { 654 struct gdma_req_hdr hdr; 655 mana_handle_t filter_handle; 656 }; /* HW DATA */ 657 658 struct mana_deregister_filter_resp { 659 struct gdma_resp_hdr hdr; 660 }; /* HW DATA */ 661 662 #define MANA_MAX_NUM_QUEUES 64 663 664 #define MANA_SHORT_VPORT_OFFSET_MAX ((1U << 8) - 1) 665 666 struct mana_tx_package { 667 struct gdma_wqe_request wqe_req; 668 struct gdma_sge sgl_array[5]; 669 struct gdma_sge *sgl_ptr; 670 671 struct mana_tx_oob tx_oob; 672 673 struct gdma_posted_wqe_info wqe_info; 674 }; 675 676 int mana_create_wq_obj(struct mana_port_context *apc, 677 mana_handle_t vport, 678 u32 wq_type, struct mana_obj_spec *wq_spec, 679 struct mana_obj_spec *cq_spec, 680 mana_handle_t *wq_obj); 681 682 void mana_destroy_wq_obj(struct mana_port_context *apc, u32 wq_type, 683 mana_handle_t wq_obj); 684 685 int mana_cfg_vport(struct mana_port_context *apc, u32 protection_dom_id, 686 u32 doorbell_pg_id); 687 void mana_uncfg_vport(struct mana_port_context *apc); 688 #endif /* _MANA_H */ 689