1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #ifndef _GDMA_H 5 #define _GDMA_H 6 7 #include <linux/dma-mapping.h> 8 #include <linux/netdevice.h> 9 10 #include "shm_channel.h" 11 12 #define GDMA_STATUS_MORE_ENTRIES 0x00000105 13 #define GDMA_STATUS_CMD_UNSUPPORTED 0xffffffff 14 15 /* Structures labeled with "HW DATA" are exchanged with the hardware. All of 16 * them are naturally aligned and hence don't need __packed. 17 */ 18 19 enum gdma_request_type { 20 GDMA_VERIFY_VF_DRIVER_VERSION = 1, 21 GDMA_QUERY_MAX_RESOURCES = 2, 22 GDMA_LIST_DEVICES = 3, 23 GDMA_REGISTER_DEVICE = 4, 24 GDMA_DEREGISTER_DEVICE = 5, 25 GDMA_GENERATE_TEST_EQE = 10, 26 GDMA_CREATE_QUEUE = 12, 27 GDMA_DISABLE_QUEUE = 13, 28 GDMA_ALLOCATE_RESOURCE_RANGE = 22, 29 GDMA_DESTROY_RESOURCE_RANGE = 24, 30 GDMA_CREATE_DMA_REGION = 25, 31 GDMA_DMA_REGION_ADD_PAGES = 26, 32 GDMA_DESTROY_DMA_REGION = 27, 33 GDMA_CREATE_PD = 29, 34 GDMA_DESTROY_PD = 30, 35 GDMA_CREATE_MR = 31, 36 GDMA_DESTROY_MR = 32, 37 GDMA_QUERY_HWC_TIMEOUT = 84, /* 0x54 */ 38 }; 39 40 #define GDMA_RESOURCE_DOORBELL_PAGE 27 41 42 enum gdma_queue_type { 43 GDMA_INVALID_QUEUE, 44 GDMA_SQ, 45 GDMA_RQ, 46 GDMA_CQ, 47 GDMA_EQ, 48 }; 49 50 enum gdma_work_request_flags { 51 GDMA_WR_NONE = 0, 52 GDMA_WR_OOB_IN_SGL = BIT(0), 53 GDMA_WR_PAD_BY_SGE0 = BIT(1), 54 }; 55 56 enum gdma_eqe_type { 57 GDMA_EQE_COMPLETION = 3, 58 GDMA_EQE_TEST_EVENT = 64, 59 GDMA_EQE_HWC_INIT_EQ_ID_DB = 129, 60 GDMA_EQE_HWC_INIT_DATA = 130, 61 GDMA_EQE_HWC_INIT_DONE = 131, 62 GDMA_EQE_HWC_FPGA_RECONFIG = 132, 63 GDMA_EQE_HWC_SOC_RECONFIG_DATA = 133, 64 GDMA_EQE_HWC_SOC_SERVICE = 134, 65 GDMA_EQE_HWC_RESET_REQUEST = 135, 66 GDMA_EQE_RNIC_QP_FATAL = 176, 67 }; 68 69 enum { 70 GDMA_DEVICE_NONE = 0, 71 GDMA_DEVICE_HWC = 1, 72 GDMA_DEVICE_MANA = 2, 73 GDMA_DEVICE_MANA_IB = 3, 74 }; 75 76 enum gdma_service_type { 77 GDMA_SERVICE_TYPE_NONE = 0, 78 GDMA_SERVICE_TYPE_RDMA_SUSPEND = 1, 79 GDMA_SERVICE_TYPE_RDMA_RESUME = 2, 80 }; 81 82 struct mana_service_work { 83 struct work_struct work; 84 struct gdma_dev *gdma_dev; 85 enum gdma_service_type event; 86 }; 87 88 struct gdma_resource { 89 /* Protect the bitmap */ 90 spinlock_t lock; 91 92 /* The bitmap size in bits. */ 93 u32 size; 94 95 /* The bitmap tracks the resources. */ 96 unsigned long *map; 97 }; 98 99 union gdma_doorbell_entry { 100 u64 as_uint64; 101 102 struct { 103 u64 id : 24; 104 u64 reserved : 8; 105 u64 tail_ptr : 31; 106 u64 arm : 1; 107 } cq; 108 109 struct { 110 u64 id : 24; 111 u64 wqe_cnt : 8; 112 u64 tail_ptr : 32; 113 } rq; 114 115 struct { 116 u64 id : 24; 117 u64 reserved : 8; 118 u64 tail_ptr : 32; 119 } sq; 120 121 struct { 122 u64 id : 16; 123 u64 reserved : 16; 124 u64 tail_ptr : 31; 125 u64 arm : 1; 126 } eq; 127 }; /* HW DATA */ 128 129 struct gdma_msg_hdr { 130 u32 hdr_type; 131 u32 msg_type; 132 u16 msg_version; 133 u16 hwc_msg_id; 134 u32 msg_size; 135 }; /* HW DATA */ 136 137 struct gdma_dev_id { 138 union { 139 struct { 140 u16 type; 141 u16 instance; 142 }; 143 144 u32 as_uint32; 145 }; 146 }; /* HW DATA */ 147 148 struct gdma_req_hdr { 149 struct gdma_msg_hdr req; 150 struct gdma_msg_hdr resp; /* The expected response */ 151 struct gdma_dev_id dev_id; 152 u32 activity_id; 153 }; /* HW DATA */ 154 155 struct gdma_resp_hdr { 156 struct gdma_msg_hdr response; 157 struct gdma_dev_id dev_id; 158 u32 activity_id; 159 u32 status; 160 u32 reserved; 161 }; /* HW DATA */ 162 163 struct gdma_general_req { 164 struct gdma_req_hdr hdr; 165 }; /* HW DATA */ 166 167 #define GDMA_MESSAGE_V1 1 168 #define GDMA_MESSAGE_V2 2 169 #define GDMA_MESSAGE_V3 3 170 #define GDMA_MESSAGE_V4 4 171 172 struct gdma_general_resp { 173 struct gdma_resp_hdr hdr; 174 }; /* HW DATA */ 175 176 #define GDMA_STANDARD_HEADER_TYPE 0 177 178 static inline void mana_gd_init_req_hdr(struct gdma_req_hdr *hdr, u32 code, 179 u32 req_size, u32 resp_size) 180 { 181 hdr->req.hdr_type = GDMA_STANDARD_HEADER_TYPE; 182 hdr->req.msg_type = code; 183 hdr->req.msg_version = GDMA_MESSAGE_V1; 184 hdr->req.msg_size = req_size; 185 186 hdr->resp.hdr_type = GDMA_STANDARD_HEADER_TYPE; 187 hdr->resp.msg_type = code; 188 hdr->resp.msg_version = GDMA_MESSAGE_V1; 189 hdr->resp.msg_size = resp_size; 190 } 191 192 /* The 16-byte struct is part of the GDMA work queue entry (WQE). */ 193 struct gdma_sge { 194 u64 address; 195 u32 mem_key; 196 u32 size; 197 }; /* HW DATA */ 198 199 struct gdma_wqe_request { 200 struct gdma_sge *sgl; 201 u32 num_sge; 202 203 u32 inline_oob_size; 204 const void *inline_oob_data; 205 206 u32 flags; 207 u32 client_data_unit; 208 }; 209 210 enum gdma_page_type { 211 GDMA_PAGE_TYPE_4K, 212 }; 213 214 #define GDMA_INVALID_DMA_REGION 0 215 216 struct gdma_mem_info { 217 struct device *dev; 218 219 dma_addr_t dma_handle; 220 void *virt_addr; 221 u64 length; 222 223 /* Allocated by the PF driver */ 224 u64 dma_region_handle; 225 }; 226 227 #define REGISTER_ATB_MST_MKEY_LOWER_SIZE 8 228 229 struct gdma_dev { 230 struct gdma_context *gdma_context; 231 232 struct gdma_dev_id dev_id; 233 234 u32 pdid; 235 u32 doorbell; 236 u32 gpa_mkey; 237 238 /* GDMA driver specific pointer */ 239 void *driver_data; 240 241 struct auxiliary_device *adev; 242 bool is_suspended; 243 bool rdma_teardown; 244 }; 245 246 /* MANA_PAGE_SIZE is the DMA unit */ 247 #define MANA_PAGE_SHIFT 12 248 #define MANA_PAGE_SIZE BIT(MANA_PAGE_SHIFT) 249 #define MANA_PAGE_ALIGN(x) ALIGN((x), MANA_PAGE_SIZE) 250 #define MANA_PAGE_ALIGNED(addr) IS_ALIGNED((unsigned long)(addr), MANA_PAGE_SIZE) 251 #define MANA_PFN(a) ((a) >> MANA_PAGE_SHIFT) 252 253 /* Required by HW */ 254 #define MANA_MIN_QSIZE MANA_PAGE_SIZE 255 256 #define GDMA_CQE_SIZE 64 257 #define GDMA_EQE_SIZE 16 258 #define GDMA_MAX_SQE_SIZE 512 259 #define GDMA_MAX_RQE_SIZE 256 260 261 #define GDMA_COMP_DATA_SIZE 0x3C 262 263 #define GDMA_EVENT_DATA_SIZE 0xC 264 265 /* The WQE size must be a multiple of the Basic Unit, which is 32 bytes. */ 266 #define GDMA_WQE_BU_SIZE 32 267 268 #define INVALID_PDID UINT_MAX 269 #define INVALID_DOORBELL UINT_MAX 270 #define INVALID_MEM_KEY UINT_MAX 271 #define INVALID_QUEUE_ID UINT_MAX 272 #define INVALID_PCI_MSIX_INDEX UINT_MAX 273 274 struct gdma_comp { 275 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4]; 276 u32 wq_num; 277 bool is_sq; 278 }; 279 280 struct gdma_event { 281 u32 details[GDMA_EVENT_DATA_SIZE / 4]; 282 u8 type; 283 }; 284 285 struct gdma_queue; 286 287 struct mana_eq { 288 struct gdma_queue *eq; 289 struct dentry *mana_eq_debugfs; 290 }; 291 292 typedef void gdma_eq_callback(void *context, struct gdma_queue *q, 293 struct gdma_event *e); 294 295 typedef void gdma_cq_callback(void *context, struct gdma_queue *q); 296 297 /* The 'head' is the producer index. For SQ/RQ, when the driver posts a WQE 298 * (Note: the WQE size must be a multiple of the 32-byte Basic Unit), the 299 * driver increases the 'head' in BUs rather than in bytes, and notifies 300 * the HW of the updated head. For EQ/CQ, the driver uses the 'head' to track 301 * the HW head, and increases the 'head' by 1 for every processed EQE/CQE. 302 * 303 * The 'tail' is the consumer index for SQ/RQ. After the CQE of the SQ/RQ is 304 * processed, the driver increases the 'tail' to indicate that WQEs have 305 * been consumed by the HW, so the driver can post new WQEs into the SQ/RQ. 306 * 307 * The driver doesn't use the 'tail' for EQ/CQ, because the driver ensures 308 * that the EQ/CQ is big enough so they can't overflow, and the driver uses 309 * the owner bits mechanism to detect if the queue has become empty. 310 */ 311 struct gdma_queue { 312 struct gdma_dev *gdma_dev; 313 314 enum gdma_queue_type type; 315 u32 id; 316 317 struct gdma_mem_info mem_info; 318 319 void *queue_mem_ptr; 320 u32 queue_size; 321 322 bool monitor_avl_buf; 323 324 u32 head; 325 u32 tail; 326 struct list_head entry; 327 328 /* Extra fields specific to EQ/CQ. */ 329 union { 330 struct { 331 bool disable_needed; 332 333 gdma_eq_callback *callback; 334 void *context; 335 336 unsigned int msix_index; 337 338 u32 log2_throttle_limit; 339 } eq; 340 341 struct { 342 gdma_cq_callback *callback; 343 void *context; 344 345 struct gdma_queue *parent; /* For CQ/EQ relationship */ 346 } cq; 347 }; 348 }; 349 350 struct gdma_queue_spec { 351 enum gdma_queue_type type; 352 bool monitor_avl_buf; 353 unsigned int queue_size; 354 355 /* Extra fields specific to EQ/CQ. */ 356 union { 357 struct { 358 gdma_eq_callback *callback; 359 void *context; 360 361 unsigned long log2_throttle_limit; 362 unsigned int msix_index; 363 } eq; 364 365 struct { 366 gdma_cq_callback *callback; 367 void *context; 368 369 struct gdma_queue *parent_eq; 370 371 } cq; 372 }; 373 }; 374 375 #define MANA_IRQ_NAME_SZ 32 376 377 struct gdma_irq_context { 378 void (*handler)(void *arg); 379 /* Protect the eq_list */ 380 spinlock_t lock; 381 struct list_head eq_list; 382 char name[MANA_IRQ_NAME_SZ]; 383 }; 384 385 enum gdma_context_flags { 386 GC_PROBE_SUCCEEDED = 0, 387 }; 388 389 struct gdma_context { 390 struct device *dev; 391 struct dentry *mana_pci_debugfs; 392 393 /* Per-vPort max number of queues */ 394 unsigned int max_num_queues; 395 unsigned int max_num_msix; 396 unsigned int num_msix_usable; 397 struct xarray irq_contexts; 398 399 /* L2 MTU */ 400 u16 adapter_mtu; 401 402 /* This maps a CQ index to the queue structure. */ 403 unsigned int max_num_cqs; 404 struct gdma_queue **cq_table; 405 406 /* Protect eq_test_event and test_event_eq_id */ 407 struct mutex eq_test_event_mutex; 408 struct completion eq_test_event; 409 u32 test_event_eq_id; 410 411 bool is_pf; 412 bool in_service; 413 414 phys_addr_t bar0_pa; 415 void __iomem *bar0_va; 416 void __iomem *shm_base; 417 void __iomem *db_page_base; 418 phys_addr_t phys_db_page_base; 419 u32 db_page_size; 420 int numa_node; 421 422 /* Shared memory chanenl (used to bootstrap HWC) */ 423 struct shm_channel shm_channel; 424 425 /* Hardware communication channel (HWC) */ 426 struct gdma_dev hwc; 427 428 /* Azure network adapter */ 429 struct gdma_dev mana; 430 431 /* Azure RDMA adapter */ 432 struct gdma_dev mana_ib; 433 434 u64 pf_cap_flags1; 435 436 struct workqueue_struct *service_wq; 437 438 unsigned long flags; 439 }; 440 441 static inline bool mana_gd_is_mana(struct gdma_dev *gd) 442 { 443 return gd->dev_id.type == GDMA_DEVICE_MANA; 444 } 445 446 static inline bool mana_gd_is_hwc(struct gdma_dev *gd) 447 { 448 return gd->dev_id.type == GDMA_DEVICE_HWC; 449 } 450 451 u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset); 452 u32 mana_gd_wq_avail_space(struct gdma_queue *wq); 453 454 int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq); 455 456 int mana_gd_create_hwc_queue(struct gdma_dev *gd, 457 const struct gdma_queue_spec *spec, 458 struct gdma_queue **queue_ptr); 459 460 int mana_gd_create_mana_eq(struct gdma_dev *gd, 461 const struct gdma_queue_spec *spec, 462 struct gdma_queue **queue_ptr); 463 464 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 465 const struct gdma_queue_spec *spec, 466 struct gdma_queue **queue_ptr); 467 468 void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue); 469 470 int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe); 471 472 void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit); 473 474 struct gdma_wqe { 475 u32 reserved :24; 476 u32 last_vbytes :8; 477 478 union { 479 u32 flags; 480 481 struct { 482 u32 num_sge :8; 483 u32 inline_oob_size_div4:3; 484 u32 client_oob_in_sgl :1; 485 u32 reserved1 :4; 486 u32 client_data_unit :14; 487 u32 reserved2 :2; 488 }; 489 }; 490 }; /* HW DATA */ 491 492 #define INLINE_OOB_SMALL_SIZE 8 493 #define INLINE_OOB_LARGE_SIZE 24 494 495 #define MANA_MAX_TX_WQE_SGL_ENTRIES 30 496 497 #define MAX_TX_WQE_SIZE 512 498 #define MAX_RX_WQE_SIZE 256 499 500 #define MAX_TX_WQE_SGL_ENTRIES ((GDMA_MAX_SQE_SIZE - \ 501 sizeof(struct gdma_sge) - INLINE_OOB_SMALL_SIZE) / \ 502 sizeof(struct gdma_sge)) 503 504 #define MAX_RX_WQE_SGL_ENTRIES ((GDMA_MAX_RQE_SIZE - \ 505 sizeof(struct gdma_sge)) / sizeof(struct gdma_sge)) 506 507 struct gdma_cqe { 508 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4]; 509 510 union { 511 u32 as_uint32; 512 513 struct { 514 u32 wq_num : 24; 515 u32 is_sq : 1; 516 u32 reserved : 4; 517 u32 owner_bits : 3; 518 }; 519 } cqe_info; 520 }; /* HW DATA */ 521 522 #define GDMA_CQE_OWNER_BITS 3 523 524 #define GDMA_CQE_OWNER_MASK ((1 << GDMA_CQE_OWNER_BITS) - 1) 525 526 #define SET_ARM_BIT 1 527 528 #define GDMA_EQE_OWNER_BITS 3 529 530 union gdma_eqe_info { 531 u32 as_uint32; 532 533 struct { 534 u32 type : 8; 535 u32 reserved1 : 8; 536 u32 client_id : 2; 537 u32 reserved2 : 11; 538 u32 owner_bits : 3; 539 }; 540 }; /* HW DATA */ 541 542 #define GDMA_EQE_OWNER_MASK ((1 << GDMA_EQE_OWNER_BITS) - 1) 543 #define INITIALIZED_OWNER_BIT(log2_num_entries) (1UL << (log2_num_entries)) 544 545 struct gdma_eqe { 546 u32 details[GDMA_EVENT_DATA_SIZE / 4]; 547 u32 eqe_info; 548 }; /* HW DATA */ 549 550 #define GDMA_REG_DB_PAGE_OFFSET 8 551 #define GDMA_REG_DB_PAGE_SIZE 0x10 552 #define GDMA_REG_SHM_OFFSET 0x18 553 554 #define GDMA_PF_REG_DB_PAGE_SIZE 0xD0 555 #define GDMA_PF_REG_DB_PAGE_OFF 0xC8 556 #define GDMA_PF_REG_SHM_OFF 0x70 557 558 #define GDMA_SRIOV_REG_CFG_BASE_OFF 0x108 559 560 #define MANA_PF_DEVICE_ID 0x00B9 561 #define MANA_VF_DEVICE_ID 0x00BA 562 563 struct gdma_posted_wqe_info { 564 u32 wqe_size_in_bu; 565 }; 566 567 /* GDMA_GENERATE_TEST_EQE */ 568 struct gdma_generate_test_event_req { 569 struct gdma_req_hdr hdr; 570 u32 queue_index; 571 }; /* HW DATA */ 572 573 /* GDMA_VERIFY_VF_DRIVER_VERSION */ 574 enum { 575 GDMA_PROTOCOL_V1 = 1, 576 GDMA_PROTOCOL_FIRST = GDMA_PROTOCOL_V1, 577 GDMA_PROTOCOL_LAST = GDMA_PROTOCOL_V1, 578 }; 579 580 #define GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT BIT(0) 581 582 /* Advertise to the NIC firmware: the NAPI work_done variable race is fixed, 583 * so the driver is able to reliably support features like busy_poll. 584 */ 585 #define GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX BIT(2) 586 #define GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG BIT(3) 587 #define GDMA_DRV_CAP_FLAG_1_GDMA_PAGES_4MB_1GB_2GB BIT(4) 588 #define GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT BIT(5) 589 590 /* Driver can handle holes (zeros) in the device list */ 591 #define GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP BIT(11) 592 593 /* Driver supports dynamic MSI-X vector allocation */ 594 #define GDMA_DRV_CAP_FLAG_1_DYNAMIC_IRQ_ALLOC_SUPPORT BIT(13) 595 596 /* Driver can self reset on EQE notification */ 597 #define GDMA_DRV_CAP_FLAG_1_SELF_RESET_ON_EQE BIT(14) 598 599 /* Driver can self reset on FPGA Reconfig EQE notification */ 600 #define GDMA_DRV_CAP_FLAG_1_HANDLE_RECONFIG_EQE BIT(17) 601 602 /* Driver detects stalled send queues and recovers them */ 603 #define GDMA_DRV_CAP_FLAG_1_HANDLE_STALL_SQ_RECOVERY BIT(18) 604 605 #define GDMA_DRV_CAP_FLAG_1_HW_VPORT_LINK_AWARE BIT(6) 606 607 /* Driver supports linearizing the skb when num_sge exceeds hardware limit */ 608 #define GDMA_DRV_CAP_FLAG_1_SKB_LINEARIZE BIT(20) 609 610 /* Driver can send HWC periodically to query stats */ 611 #define GDMA_DRV_CAP_FLAG_1_PERIODIC_STATS_QUERY BIT(21) 612 613 /* Driver can handle hardware recovery events during probe */ 614 #define GDMA_DRV_CAP_FLAG_1_PROBE_RECOVERY BIT(22) 615 616 #define GDMA_DRV_CAP_FLAGS1 \ 617 (GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT | \ 618 GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX | \ 619 GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG | \ 620 GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT | \ 621 GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP | \ 622 GDMA_DRV_CAP_FLAG_1_DYNAMIC_IRQ_ALLOC_SUPPORT | \ 623 GDMA_DRV_CAP_FLAG_1_SELF_RESET_ON_EQE | \ 624 GDMA_DRV_CAP_FLAG_1_HANDLE_RECONFIG_EQE | \ 625 GDMA_DRV_CAP_FLAG_1_HW_VPORT_LINK_AWARE | \ 626 GDMA_DRV_CAP_FLAG_1_PERIODIC_STATS_QUERY | \ 627 GDMA_DRV_CAP_FLAG_1_SKB_LINEARIZE | \ 628 GDMA_DRV_CAP_FLAG_1_PROBE_RECOVERY | \ 629 GDMA_DRV_CAP_FLAG_1_HANDLE_STALL_SQ_RECOVERY) 630 631 #define GDMA_DRV_CAP_FLAGS2 0 632 633 #define GDMA_DRV_CAP_FLAGS3 0 634 635 #define GDMA_DRV_CAP_FLAGS4 0 636 637 struct gdma_verify_ver_req { 638 struct gdma_req_hdr hdr; 639 640 /* Mandatory fields required for protocol establishment */ 641 u64 protocol_ver_min; 642 u64 protocol_ver_max; 643 644 /* Gdma Driver Capability Flags */ 645 u64 gd_drv_cap_flags1; 646 u64 gd_drv_cap_flags2; 647 u64 gd_drv_cap_flags3; 648 u64 gd_drv_cap_flags4; 649 650 /* Advisory fields */ 651 u64 drv_ver; 652 u32 os_type; /* Linux = 0x10; Windows = 0x20; Other = 0x30 */ 653 u32 reserved; 654 u32 os_ver_major; 655 u32 os_ver_minor; 656 u32 os_ver_build; 657 u32 os_ver_platform; 658 u64 reserved_2; 659 u8 os_ver_str1[128]; 660 u8 os_ver_str2[128]; 661 u8 os_ver_str3[128]; 662 u8 os_ver_str4[128]; 663 }; /* HW DATA */ 664 665 struct gdma_verify_ver_resp { 666 struct gdma_resp_hdr hdr; 667 u64 gdma_protocol_ver; 668 u64 pf_cap_flags1; 669 u64 pf_cap_flags2; 670 u64 pf_cap_flags3; 671 u64 pf_cap_flags4; 672 }; /* HW DATA */ 673 674 /* GDMA_QUERY_MAX_RESOURCES */ 675 struct gdma_query_max_resources_resp { 676 struct gdma_resp_hdr hdr; 677 u32 status; 678 u32 max_sq; 679 u32 max_rq; 680 u32 max_cq; 681 u32 max_eq; 682 u32 max_db; 683 u32 max_mst; 684 u32 max_cq_mod_ctx; 685 u32 max_mod_cq; 686 u32 max_msix; 687 }; /* HW DATA */ 688 689 /* GDMA_LIST_DEVICES */ 690 #define GDMA_DEV_LIST_SIZE 64 691 struct gdma_list_devices_resp { 692 struct gdma_resp_hdr hdr; 693 u32 num_of_devs; 694 u32 reserved; 695 struct gdma_dev_id devs[GDMA_DEV_LIST_SIZE]; 696 }; /* HW DATA */ 697 698 /* GDMA_REGISTER_DEVICE */ 699 struct gdma_register_device_resp { 700 struct gdma_resp_hdr hdr; 701 u32 pdid; 702 u32 gpa_mkey; 703 u32 db_id; 704 }; /* HW DATA */ 705 706 struct gdma_allocate_resource_range_req { 707 struct gdma_req_hdr hdr; 708 u32 resource_type; 709 u32 num_resources; 710 u32 alignment; 711 u32 allocated_resources; 712 }; 713 714 struct gdma_allocate_resource_range_resp { 715 struct gdma_resp_hdr hdr; 716 u32 allocated_resources; 717 }; 718 719 struct gdma_destroy_resource_range_req { 720 struct gdma_req_hdr hdr; 721 u32 resource_type; 722 u32 num_resources; 723 u32 allocated_resources; 724 }; 725 726 /* GDMA_CREATE_QUEUE */ 727 struct gdma_create_queue_req { 728 struct gdma_req_hdr hdr; 729 u32 type; 730 u32 reserved1; 731 u32 pdid; 732 u32 doolbell_id; 733 u64 gdma_region; 734 u32 reserved2; 735 u32 queue_size; 736 u32 log2_throttle_limit; 737 u32 eq_pci_msix_index; 738 u32 cq_mod_ctx_id; 739 u32 cq_parent_eq_id; 740 u8 rq_drop_on_overrun; 741 u8 rq_err_on_wqe_overflow; 742 u8 rq_chain_rec_wqes; 743 u8 sq_hw_db; 744 u32 reserved3; 745 }; /* HW DATA */ 746 747 struct gdma_create_queue_resp { 748 struct gdma_resp_hdr hdr; 749 u32 queue_index; 750 }; /* HW DATA */ 751 752 /* GDMA_DISABLE_QUEUE */ 753 struct gdma_disable_queue_req { 754 struct gdma_req_hdr hdr; 755 u32 type; 756 u32 queue_index; 757 u32 alloc_res_id_on_creation; 758 }; /* HW DATA */ 759 760 /* GDMA_QUERY_HWC_TIMEOUT */ 761 struct gdma_query_hwc_timeout_req { 762 struct gdma_req_hdr hdr; 763 u32 timeout_ms; 764 u32 reserved; 765 }; 766 767 struct gdma_query_hwc_timeout_resp { 768 struct gdma_resp_hdr hdr; 769 u32 timeout_ms; 770 u32 reserved; 771 }; 772 773 enum gdma_mr_access_flags { 774 GDMA_ACCESS_FLAG_LOCAL_READ = BIT_ULL(0), 775 GDMA_ACCESS_FLAG_LOCAL_WRITE = BIT_ULL(1), 776 GDMA_ACCESS_FLAG_REMOTE_READ = BIT_ULL(2), 777 GDMA_ACCESS_FLAG_REMOTE_WRITE = BIT_ULL(3), 778 GDMA_ACCESS_FLAG_REMOTE_ATOMIC = BIT_ULL(4), 779 }; 780 781 /* GDMA_CREATE_DMA_REGION */ 782 struct gdma_create_dma_region_req { 783 struct gdma_req_hdr hdr; 784 785 /* The total size of the DMA region */ 786 u64 length; 787 788 /* The offset in the first page */ 789 u32 offset_in_page; 790 791 /* enum gdma_page_type */ 792 u32 gdma_page_type; 793 794 /* The total number of pages */ 795 u32 page_count; 796 797 /* If page_addr_list_len is smaller than page_count, 798 * the remaining page addresses will be added via the 799 * message GDMA_DMA_REGION_ADD_PAGES. 800 */ 801 u32 page_addr_list_len; 802 u64 page_addr_list[]; 803 }; /* HW DATA */ 804 805 struct gdma_create_dma_region_resp { 806 struct gdma_resp_hdr hdr; 807 u64 dma_region_handle; 808 }; /* HW DATA */ 809 810 /* GDMA_DMA_REGION_ADD_PAGES */ 811 struct gdma_dma_region_add_pages_req { 812 struct gdma_req_hdr hdr; 813 814 u64 dma_region_handle; 815 816 u32 page_addr_list_len; 817 u32 reserved3; 818 819 u64 page_addr_list[]; 820 }; /* HW DATA */ 821 822 /* GDMA_DESTROY_DMA_REGION */ 823 struct gdma_destroy_dma_region_req { 824 struct gdma_req_hdr hdr; 825 826 u64 dma_region_handle; 827 }; /* HW DATA */ 828 829 enum gdma_pd_flags { 830 GDMA_PD_FLAG_INVALID = 0, 831 GDMA_PD_FLAG_ALLOW_GPA_MR = 1, 832 }; 833 834 struct gdma_create_pd_req { 835 struct gdma_req_hdr hdr; 836 enum gdma_pd_flags flags; 837 u32 reserved; 838 };/* HW DATA */ 839 840 struct gdma_create_pd_resp { 841 struct gdma_resp_hdr hdr; 842 u64 pd_handle; 843 u32 pd_id; 844 u32 reserved; 845 };/* HW DATA */ 846 847 struct gdma_destroy_pd_req { 848 struct gdma_req_hdr hdr; 849 u64 pd_handle; 850 };/* HW DATA */ 851 852 struct gdma_destory_pd_resp { 853 struct gdma_resp_hdr hdr; 854 };/* HW DATA */ 855 856 enum gdma_mr_type { 857 /* 858 * Guest Physical Address - MRs of this type allow access 859 * to any DMA-mapped memory using bus-logical address 860 */ 861 GDMA_MR_TYPE_GPA = 1, 862 /* Guest Virtual Address - MRs of this type allow access 863 * to memory mapped by PTEs associated with this MR using a virtual 864 * address that is set up in the MST 865 */ 866 GDMA_MR_TYPE_GVA = 2, 867 /* Guest zero-based address MRs */ 868 GDMA_MR_TYPE_ZBVA = 4, 869 }; 870 871 struct gdma_create_mr_params { 872 u64 pd_handle; 873 enum gdma_mr_type mr_type; 874 union { 875 struct { 876 u64 dma_region_handle; 877 u64 virtual_address; 878 enum gdma_mr_access_flags access_flags; 879 } gva; 880 struct { 881 u64 dma_region_handle; 882 enum gdma_mr_access_flags access_flags; 883 } zbva; 884 }; 885 }; 886 887 struct gdma_create_mr_request { 888 struct gdma_req_hdr hdr; 889 u64 pd_handle; 890 enum gdma_mr_type mr_type; 891 u32 reserved_1; 892 893 union { 894 struct { 895 u64 dma_region_handle; 896 u64 virtual_address; 897 enum gdma_mr_access_flags access_flags; 898 } gva; 899 struct { 900 u64 dma_region_handle; 901 enum gdma_mr_access_flags access_flags; 902 } zbva; 903 }; 904 u32 reserved_2; 905 };/* HW DATA */ 906 907 struct gdma_create_mr_response { 908 struct gdma_resp_hdr hdr; 909 u64 mr_handle; 910 u32 lkey; 911 u32 rkey; 912 };/* HW DATA */ 913 914 struct gdma_destroy_mr_request { 915 struct gdma_req_hdr hdr; 916 u64 mr_handle; 917 };/* HW DATA */ 918 919 struct gdma_destroy_mr_response { 920 struct gdma_resp_hdr hdr; 921 };/* HW DATA */ 922 923 int mana_gd_verify_vf_version(struct pci_dev *pdev); 924 925 int mana_gd_register_device(struct gdma_dev *gd); 926 int mana_gd_deregister_device(struct gdma_dev *gd); 927 928 int mana_gd_post_work_request(struct gdma_queue *wq, 929 const struct gdma_wqe_request *wqe_req, 930 struct gdma_posted_wqe_info *wqe_info); 931 932 int mana_gd_post_and_ring(struct gdma_queue *queue, 933 const struct gdma_wqe_request *wqe, 934 struct gdma_posted_wqe_info *wqe_info); 935 936 int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r); 937 void mana_gd_free_res_map(struct gdma_resource *r); 938 939 void mana_gd_wq_ring_doorbell(struct gdma_context *gc, 940 struct gdma_queue *queue); 941 942 int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 943 struct gdma_mem_info *gmi); 944 945 void mana_gd_free_memory(struct gdma_mem_info *gmi); 946 947 int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req, 948 u32 resp_len, void *resp); 949 950 int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle); 951 void mana_register_debugfs(void); 952 void mana_unregister_debugfs(void); 953 954 int mana_rdma_service_event(struct gdma_context *gc, enum gdma_service_type event); 955 956 int mana_gd_suspend(struct pci_dev *pdev, pm_message_t state); 957 int mana_gd_resume(struct pci_dev *pdev); 958 959 bool mana_need_log(struct gdma_context *gc, int err); 960 961 #endif /* _GDMA_H */ 962