1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #ifndef _GDMA_H 5 #define _GDMA_H 6 7 #include <linux/dma-mapping.h> 8 #include <linux/netdevice.h> 9 10 #include "shm_channel.h" 11 12 #define GDMA_STATUS_MORE_ENTRIES 0x00000105 13 #define GDMA_STATUS_CMD_UNSUPPORTED 0xffffffff 14 15 /* Structures labeled with "HW DATA" are exchanged with the hardware. All of 16 * them are naturally aligned and hence don't need __packed. 17 */ 18 19 enum gdma_request_type { 20 GDMA_VERIFY_VF_DRIVER_VERSION = 1, 21 GDMA_QUERY_MAX_RESOURCES = 2, 22 GDMA_LIST_DEVICES = 3, 23 GDMA_REGISTER_DEVICE = 4, 24 GDMA_DEREGISTER_DEVICE = 5, 25 GDMA_GENERATE_TEST_EQE = 10, 26 GDMA_CREATE_QUEUE = 12, 27 GDMA_DISABLE_QUEUE = 13, 28 GDMA_ALLOCATE_RESOURCE_RANGE = 22, 29 GDMA_DESTROY_RESOURCE_RANGE = 24, 30 GDMA_CREATE_DMA_REGION = 25, 31 GDMA_DMA_REGION_ADD_PAGES = 26, 32 GDMA_DESTROY_DMA_REGION = 27, 33 GDMA_CREATE_PD = 29, 34 GDMA_DESTROY_PD = 30, 35 GDMA_CREATE_MR = 31, 36 GDMA_DESTROY_MR = 32, 37 GDMA_QUERY_HWC_TIMEOUT = 84, /* 0x54 */ 38 GDMA_ALLOC_DM = 96, /* 0x60 */ 39 GDMA_DESTROY_DM = 97, /* 0x61 */ 40 }; 41 42 #define GDMA_RESOURCE_DOORBELL_PAGE 27 43 44 enum gdma_queue_type { 45 GDMA_INVALID_QUEUE, 46 GDMA_SQ, 47 GDMA_RQ, 48 GDMA_CQ, 49 GDMA_EQ, 50 }; 51 52 enum gdma_work_request_flags { 53 GDMA_WR_NONE = 0, 54 GDMA_WR_OOB_IN_SGL = BIT(0), 55 GDMA_WR_PAD_BY_SGE0 = BIT(1), 56 }; 57 58 enum gdma_eqe_type { 59 GDMA_EQE_COMPLETION = 3, 60 GDMA_EQE_TEST_EVENT = 64, 61 GDMA_EQE_HWC_INIT_EQ_ID_DB = 129, 62 GDMA_EQE_HWC_INIT_DATA = 130, 63 GDMA_EQE_HWC_INIT_DONE = 131, 64 GDMA_EQE_HWC_FPGA_RECONFIG = 132, 65 GDMA_EQE_HWC_SOC_RECONFIG_DATA = 133, 66 GDMA_EQE_HWC_SOC_SERVICE = 134, 67 GDMA_EQE_HWC_RESET_REQUEST = 135, 68 GDMA_EQE_RNIC_QP_FATAL = 176, 69 }; 70 71 enum { 72 GDMA_DEVICE_NONE = 0, 73 GDMA_DEVICE_HWC = 1, 74 GDMA_DEVICE_MANA = 2, 75 GDMA_DEVICE_MANA_IB = 3, 76 }; 77 78 enum gdma_service_type { 79 GDMA_SERVICE_TYPE_NONE = 0, 80 GDMA_SERVICE_TYPE_RDMA_SUSPEND = 1, 81 GDMA_SERVICE_TYPE_RDMA_RESUME = 2, 82 }; 83 84 struct mana_service_work { 85 struct work_struct work; 86 struct gdma_dev *gdma_dev; 87 enum gdma_service_type event; 88 }; 89 90 struct gdma_resource { 91 /* Protect the bitmap */ 92 spinlock_t lock; 93 94 /* The bitmap size in bits. */ 95 u32 size; 96 97 /* The bitmap tracks the resources. */ 98 unsigned long *map; 99 }; 100 101 union gdma_doorbell_entry { 102 u64 as_uint64; 103 104 struct { 105 u64 id : 24; 106 u64 reserved : 8; 107 u64 tail_ptr : 31; 108 u64 arm : 1; 109 } cq; 110 111 struct { 112 u64 id : 24; 113 u64 wqe_cnt : 8; 114 u64 tail_ptr : 32; 115 } rq; 116 117 struct { 118 u64 id : 24; 119 u64 reserved : 8; 120 u64 tail_ptr : 32; 121 } sq; 122 123 struct { 124 u64 id : 16; 125 u64 reserved : 16; 126 u64 tail_ptr : 31; 127 u64 arm : 1; 128 } eq; 129 }; /* HW DATA */ 130 131 struct gdma_msg_hdr { 132 u32 hdr_type; 133 u32 msg_type; 134 u16 msg_version; 135 u16 hwc_msg_id; 136 u32 msg_size; 137 }; /* HW DATA */ 138 139 struct gdma_dev_id { 140 union { 141 struct { 142 u16 type; 143 u16 instance; 144 }; 145 146 u32 as_uint32; 147 }; 148 }; /* HW DATA */ 149 150 struct gdma_req_hdr { 151 struct gdma_msg_hdr req; 152 struct gdma_msg_hdr resp; /* The expected response */ 153 struct gdma_dev_id dev_id; 154 u32 activity_id; 155 }; /* HW DATA */ 156 157 struct gdma_resp_hdr { 158 struct gdma_msg_hdr response; 159 struct gdma_dev_id dev_id; 160 u32 activity_id; 161 u32 status; 162 u32 reserved; 163 }; /* HW DATA */ 164 165 struct gdma_general_req { 166 struct gdma_req_hdr hdr; 167 }; /* HW DATA */ 168 169 #define GDMA_MESSAGE_V1 1 170 #define GDMA_MESSAGE_V2 2 171 #define GDMA_MESSAGE_V3 3 172 #define GDMA_MESSAGE_V4 4 173 174 struct gdma_general_resp { 175 struct gdma_resp_hdr hdr; 176 }; /* HW DATA */ 177 178 #define GDMA_STANDARD_HEADER_TYPE 0 179 180 static inline void mana_gd_init_req_hdr(struct gdma_req_hdr *hdr, u32 code, 181 u32 req_size, u32 resp_size) 182 { 183 hdr->req.hdr_type = GDMA_STANDARD_HEADER_TYPE; 184 hdr->req.msg_type = code; 185 hdr->req.msg_version = GDMA_MESSAGE_V1; 186 hdr->req.msg_size = req_size; 187 188 hdr->resp.hdr_type = GDMA_STANDARD_HEADER_TYPE; 189 hdr->resp.msg_type = code; 190 hdr->resp.msg_version = GDMA_MESSAGE_V1; 191 hdr->resp.msg_size = resp_size; 192 } 193 194 /* The 16-byte struct is part of the GDMA work queue entry (WQE). */ 195 struct gdma_sge { 196 u64 address; 197 u32 mem_key; 198 u32 size; 199 }; /* HW DATA */ 200 201 struct gdma_wqe_request { 202 struct gdma_sge *sgl; 203 u32 num_sge; 204 205 u32 inline_oob_size; 206 const void *inline_oob_data; 207 208 u32 flags; 209 u32 client_data_unit; 210 }; 211 212 enum gdma_page_type { 213 GDMA_PAGE_TYPE_4K, 214 }; 215 216 #define GDMA_INVALID_DMA_REGION 0 217 218 struct mana_serv_work { 219 struct work_struct serv_work; 220 struct pci_dev *pdev; 221 enum gdma_eqe_type type; 222 }; 223 224 struct gdma_mem_info { 225 struct device *dev; 226 227 dma_addr_t dma_handle; 228 void *virt_addr; 229 u64 length; 230 231 /* Allocated by the PF driver */ 232 u64 dma_region_handle; 233 }; 234 235 #define REGISTER_ATB_MST_MKEY_LOWER_SIZE 8 236 237 struct gdma_dev { 238 struct gdma_context *gdma_context; 239 240 struct gdma_dev_id dev_id; 241 242 u32 pdid; 243 u32 doorbell; 244 u32 gpa_mkey; 245 246 /* GDMA driver specific pointer */ 247 void *driver_data; 248 249 struct auxiliary_device *adev; 250 bool is_suspended; 251 bool rdma_teardown; 252 }; 253 254 /* MANA_PAGE_SIZE is the DMA unit */ 255 #define MANA_PAGE_SHIFT 12 256 #define MANA_PAGE_SIZE BIT(MANA_PAGE_SHIFT) 257 #define MANA_PAGE_ALIGN(x) ALIGN((x), MANA_PAGE_SIZE) 258 #define MANA_PAGE_ALIGNED(addr) IS_ALIGNED((unsigned long)(addr), MANA_PAGE_SIZE) 259 #define MANA_PFN(a) ((a) >> MANA_PAGE_SHIFT) 260 261 /* Required by HW */ 262 #define MANA_MIN_QSIZE MANA_PAGE_SIZE 263 264 #define GDMA_CQE_SIZE 64 265 #define GDMA_EQE_SIZE 16 266 #define GDMA_MAX_SQE_SIZE 512 267 #define GDMA_MAX_RQE_SIZE 256 268 269 #define GDMA_COMP_DATA_SIZE 0x3C 270 271 #define GDMA_EVENT_DATA_SIZE 0xC 272 273 /* The WQE size must be a multiple of the Basic Unit, which is 32 bytes. */ 274 #define GDMA_WQE_BU_SIZE 32 275 276 #define INVALID_PDID UINT_MAX 277 #define INVALID_DOORBELL UINT_MAX 278 #define INVALID_MEM_KEY UINT_MAX 279 #define INVALID_QUEUE_ID UINT_MAX 280 #define INVALID_PCI_MSIX_INDEX UINT_MAX 281 282 struct gdma_comp { 283 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4]; 284 u32 wq_num; 285 bool is_sq; 286 }; 287 288 struct gdma_event { 289 u32 details[GDMA_EVENT_DATA_SIZE / 4]; 290 u8 type; 291 }; 292 293 struct gdma_queue; 294 295 struct mana_eq { 296 struct gdma_queue *eq; 297 struct dentry *mana_eq_debugfs; 298 }; 299 300 typedef void gdma_eq_callback(void *context, struct gdma_queue *q, 301 struct gdma_event *e); 302 303 typedef void gdma_cq_callback(void *context, struct gdma_queue *q); 304 305 /* The 'head' is the producer index. For SQ/RQ, when the driver posts a WQE 306 * (Note: the WQE size must be a multiple of the 32-byte Basic Unit), the 307 * driver increases the 'head' in BUs rather than in bytes, and notifies 308 * the HW of the updated head. For EQ/CQ, the driver uses the 'head' to track 309 * the HW head, and increases the 'head' by 1 for every processed EQE/CQE. 310 * 311 * The 'tail' is the consumer index for SQ/RQ. After the CQE of the SQ/RQ is 312 * processed, the driver increases the 'tail' to indicate that WQEs have 313 * been consumed by the HW, so the driver can post new WQEs into the SQ/RQ. 314 * 315 * The driver doesn't use the 'tail' for EQ/CQ, because the driver ensures 316 * that the EQ/CQ is big enough so they can't overflow, and the driver uses 317 * the owner bits mechanism to detect if the queue has become empty. 318 */ 319 struct gdma_queue { 320 struct gdma_dev *gdma_dev; 321 322 enum gdma_queue_type type; 323 u32 id; 324 325 struct gdma_mem_info mem_info; 326 327 void *queue_mem_ptr; 328 u32 queue_size; 329 330 bool monitor_avl_buf; 331 332 u32 head; 333 u32 tail; 334 struct list_head entry; 335 336 /* Extra fields specific to EQ/CQ. */ 337 union { 338 struct { 339 bool disable_needed; 340 341 gdma_eq_callback *callback; 342 void *context; 343 344 unsigned int msix_index; 345 346 u32 log2_throttle_limit; 347 } eq; 348 349 struct { 350 gdma_cq_callback *callback; 351 void *context; 352 353 struct gdma_queue *parent; /* For CQ/EQ relationship */ 354 } cq; 355 }; 356 }; 357 358 struct gdma_queue_spec { 359 enum gdma_queue_type type; 360 bool monitor_avl_buf; 361 unsigned int queue_size; 362 363 /* Extra fields specific to EQ/CQ. */ 364 union { 365 struct { 366 gdma_eq_callback *callback; 367 void *context; 368 369 unsigned long log2_throttle_limit; 370 unsigned int msix_index; 371 } eq; 372 373 struct { 374 gdma_cq_callback *callback; 375 void *context; 376 377 struct gdma_queue *parent_eq; 378 379 } cq; 380 }; 381 }; 382 383 #define MANA_IRQ_NAME_SZ 32 384 385 struct gdma_irq_context { 386 void (*handler)(void *arg); 387 /* Protect the eq_list */ 388 spinlock_t lock; 389 struct list_head eq_list; 390 char name[MANA_IRQ_NAME_SZ]; 391 }; 392 393 enum gdma_context_flags { 394 GC_PROBE_SUCCEEDED = 0, 395 GC_IN_SERVICE = 1, 396 }; 397 398 struct gdma_context { 399 struct device *dev; 400 struct dentry *mana_pci_debugfs; 401 402 /* Per-vPort max number of queues */ 403 unsigned int max_num_queues; 404 unsigned int max_num_msix; 405 unsigned int num_msix_usable; 406 struct xarray irq_contexts; 407 408 /* L2 MTU */ 409 u16 adapter_mtu; 410 411 /* This maps a CQ index to the queue structure. */ 412 unsigned int max_num_cqs; 413 struct gdma_queue **cq_table; 414 415 /* Protect eq_test_event and test_event_eq_id */ 416 struct mutex eq_test_event_mutex; 417 struct completion eq_test_event; 418 u32 test_event_eq_id; 419 420 bool is_pf; 421 422 phys_addr_t bar0_pa; 423 void __iomem *bar0_va; 424 resource_size_t bar0_size; 425 void __iomem *shm_base; 426 void __iomem *db_page_base; 427 phys_addr_t phys_db_page_base; 428 u64 db_page_off; 429 u64 db_page_size; 430 int numa_node; 431 432 /* Shared memory chanenl (used to bootstrap HWC) */ 433 struct shm_channel shm_channel; 434 435 /* Hardware communication channel (HWC) */ 436 struct gdma_dev hwc; 437 438 /* Azure network adapter */ 439 struct gdma_dev mana; 440 441 /* Azure RDMA adapter */ 442 struct gdma_dev mana_ib; 443 444 u64 pf_cap_flags1; 445 u64 gdma_protocol_ver; 446 447 struct workqueue_struct *service_wq; 448 449 unsigned long flags; 450 }; 451 452 static inline bool mana_gd_is_mana(struct gdma_dev *gd) 453 { 454 return gd->dev_id.type == GDMA_DEVICE_MANA; 455 } 456 457 static inline bool mana_gd_is_hwc(struct gdma_dev *gd) 458 { 459 return gd->dev_id.type == GDMA_DEVICE_HWC; 460 } 461 462 u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset); 463 u32 mana_gd_wq_avail_space(struct gdma_queue *wq); 464 465 int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq); 466 467 int mana_gd_create_hwc_queue(struct gdma_dev *gd, 468 const struct gdma_queue_spec *spec, 469 struct gdma_queue **queue_ptr); 470 471 int mana_gd_create_mana_eq(struct gdma_dev *gd, 472 const struct gdma_queue_spec *spec, 473 struct gdma_queue **queue_ptr); 474 475 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 476 const struct gdma_queue_spec *spec, 477 struct gdma_queue **queue_ptr); 478 479 void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue); 480 481 int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe); 482 483 void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit); 484 485 int mana_schedule_serv_work(struct gdma_context *gc, enum gdma_eqe_type type); 486 487 struct gdma_wqe { 488 u32 reserved :24; 489 u32 last_vbytes :8; 490 491 union { 492 u32 flags; 493 494 struct { 495 u32 num_sge :8; 496 u32 inline_oob_size_div4:3; 497 u32 client_oob_in_sgl :1; 498 u32 reserved1 :4; 499 u32 client_data_unit :14; 500 u32 reserved2 :2; 501 }; 502 }; 503 }; /* HW DATA */ 504 505 #define INLINE_OOB_SMALL_SIZE 8 506 #define INLINE_OOB_LARGE_SIZE 24 507 508 #define MANA_MAX_TX_WQE_SGL_ENTRIES 30 509 510 #define MAX_TX_WQE_SIZE 512 511 #define MAX_RX_WQE_SIZE 256 512 513 #define MAX_TX_WQE_SGL_ENTRIES ((GDMA_MAX_SQE_SIZE - \ 514 sizeof(struct gdma_sge) - INLINE_OOB_SMALL_SIZE) / \ 515 sizeof(struct gdma_sge)) 516 517 #define MAX_RX_WQE_SGL_ENTRIES ((GDMA_MAX_RQE_SIZE - \ 518 sizeof(struct gdma_sge)) / sizeof(struct gdma_sge)) 519 520 struct gdma_cqe { 521 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4]; 522 523 union { 524 u32 as_uint32; 525 526 struct { 527 u32 wq_num : 24; 528 u32 is_sq : 1; 529 u32 reserved : 4; 530 u32 owner_bits : 3; 531 }; 532 } cqe_info; 533 }; /* HW DATA */ 534 535 #define GDMA_CQE_OWNER_BITS 3 536 537 #define GDMA_CQE_OWNER_MASK ((1 << GDMA_CQE_OWNER_BITS) - 1) 538 539 #define SET_ARM_BIT 1 540 541 #define GDMA_EQE_OWNER_BITS 3 542 543 union gdma_eqe_info { 544 u32 as_uint32; 545 546 struct { 547 u32 type : 8; 548 u32 reserved1 : 8; 549 u32 client_id : 2; 550 u32 reserved2 : 11; 551 u32 owner_bits : 3; 552 }; 553 }; /* HW DATA */ 554 555 #define GDMA_EQE_OWNER_MASK ((1 << GDMA_EQE_OWNER_BITS) - 1) 556 #define INITIALIZED_OWNER_BIT(log2_num_entries) (1UL << (log2_num_entries)) 557 558 struct gdma_eqe { 559 u32 details[GDMA_EVENT_DATA_SIZE / 4]; 560 u32 eqe_info; 561 }; /* HW DATA */ 562 563 #define GDMA_REG_DB_PAGE_OFFSET 8 564 #define GDMA_REG_DB_PAGE_SIZE 0x10 565 #define GDMA_REG_SHM_OFFSET 0x18 566 567 #define GDMA_PF_REG_DB_PAGE_SIZE 0xD0 568 #define GDMA_PF_REG_DB_PAGE_OFF 0xC8 569 #define GDMA_PF_REG_SHM_OFF 0x70 570 571 #define GDMA_SRIOV_REG_CFG_BASE_OFF 0x108 572 573 #define MANA_PF_DEVICE_ID 0x00B9 574 #define MANA_VF_DEVICE_ID 0x00BA 575 576 struct gdma_posted_wqe_info { 577 u32 wqe_size_in_bu; 578 }; 579 580 /* GDMA_GENERATE_TEST_EQE */ 581 struct gdma_generate_test_event_req { 582 struct gdma_req_hdr hdr; 583 u32 queue_index; 584 }; /* HW DATA */ 585 586 /* GDMA_VERIFY_VF_DRIVER_VERSION */ 587 enum { 588 GDMA_PROTOCOL_V1 = 1, 589 GDMA_PROTOCOL_FIRST = GDMA_PROTOCOL_V1, 590 GDMA_PROTOCOL_LAST = GDMA_PROTOCOL_V1, 591 }; 592 593 #define GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT BIT(0) 594 595 /* Advertise to the NIC firmware: the NAPI work_done variable race is fixed, 596 * so the driver is able to reliably support features like busy_poll. 597 */ 598 #define GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX BIT(2) 599 #define GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG BIT(3) 600 #define GDMA_DRV_CAP_FLAG_1_GDMA_PAGES_4MB_1GB_2GB BIT(4) 601 #define GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT BIT(5) 602 603 /* Driver can handle holes (zeros) in the device list */ 604 #define GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP BIT(11) 605 606 /* Driver supports dynamic MSI-X vector allocation */ 607 #define GDMA_DRV_CAP_FLAG_1_DYNAMIC_IRQ_ALLOC_SUPPORT BIT(13) 608 609 /* Driver can self reset on EQE notification */ 610 #define GDMA_DRV_CAP_FLAG_1_SELF_RESET_ON_EQE BIT(14) 611 612 /* Driver can self reset on FPGA Reconfig EQE notification */ 613 #define GDMA_DRV_CAP_FLAG_1_HANDLE_RECONFIG_EQE BIT(17) 614 615 /* Driver detects stalled send queues and recovers them */ 616 #define GDMA_DRV_CAP_FLAG_1_HANDLE_STALL_SQ_RECOVERY BIT(18) 617 618 #define GDMA_DRV_CAP_FLAG_1_HW_VPORT_LINK_AWARE BIT(6) 619 620 /* Driver supports linearizing the skb when num_sge exceeds hardware limit */ 621 #define GDMA_DRV_CAP_FLAG_1_SKB_LINEARIZE BIT(20) 622 623 /* Driver can send HWC periodically to query stats */ 624 #define GDMA_DRV_CAP_FLAG_1_PERIODIC_STATS_QUERY BIT(21) 625 626 /* Driver can handle hardware recovery events during probe */ 627 #define GDMA_DRV_CAP_FLAG_1_PROBE_RECOVERY BIT(22) 628 629 /* Driver supports self recovery on Hardware Channel timeouts */ 630 #define GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECOVERY BIT(25) 631 632 #define GDMA_DRV_CAP_FLAGS1 \ 633 (GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT | \ 634 GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX | \ 635 GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG | \ 636 GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT | \ 637 GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP | \ 638 GDMA_DRV_CAP_FLAG_1_DYNAMIC_IRQ_ALLOC_SUPPORT | \ 639 GDMA_DRV_CAP_FLAG_1_SELF_RESET_ON_EQE | \ 640 GDMA_DRV_CAP_FLAG_1_HANDLE_RECONFIG_EQE | \ 641 GDMA_DRV_CAP_FLAG_1_HW_VPORT_LINK_AWARE | \ 642 GDMA_DRV_CAP_FLAG_1_PERIODIC_STATS_QUERY | \ 643 GDMA_DRV_CAP_FLAG_1_SKB_LINEARIZE | \ 644 GDMA_DRV_CAP_FLAG_1_PROBE_RECOVERY | \ 645 GDMA_DRV_CAP_FLAG_1_HANDLE_STALL_SQ_RECOVERY | \ 646 GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECOVERY) 647 648 #define GDMA_DRV_CAP_FLAGS2 0 649 650 #define GDMA_DRV_CAP_FLAGS3 0 651 652 #define GDMA_DRV_CAP_FLAGS4 0 653 654 struct gdma_verify_ver_req { 655 struct gdma_req_hdr hdr; 656 657 /* Mandatory fields required for protocol establishment */ 658 u64 protocol_ver_min; 659 u64 protocol_ver_max; 660 661 /* Gdma Driver Capability Flags */ 662 u64 gd_drv_cap_flags1; 663 u64 gd_drv_cap_flags2; 664 u64 gd_drv_cap_flags3; 665 u64 gd_drv_cap_flags4; 666 667 /* Advisory fields */ 668 u64 drv_ver; 669 u32 os_type; /* Linux = 0x10; Windows = 0x20; Other = 0x30 */ 670 u32 reserved; 671 u32 os_ver_major; 672 u32 os_ver_minor; 673 u32 os_ver_build; 674 u32 os_ver_platform; 675 u64 reserved_2; 676 u8 os_ver_str1[128]; 677 u8 os_ver_str2[128]; 678 u8 os_ver_str3[128]; 679 u8 os_ver_str4[128]; 680 }; /* HW DATA */ 681 682 struct gdma_verify_ver_resp { 683 struct gdma_resp_hdr hdr; 684 u64 gdma_protocol_ver; 685 u64 pf_cap_flags1; 686 u64 pf_cap_flags2; 687 u64 pf_cap_flags3; 688 u64 pf_cap_flags4; 689 }; /* HW DATA */ 690 691 /* GDMA_QUERY_MAX_RESOURCES */ 692 struct gdma_query_max_resources_resp { 693 struct gdma_resp_hdr hdr; 694 u32 status; 695 u32 max_sq; 696 u32 max_rq; 697 u32 max_cq; 698 u32 max_eq; 699 u32 max_db; 700 u32 max_mst; 701 u32 max_cq_mod_ctx; 702 u32 max_mod_cq; 703 u32 max_msix; 704 }; /* HW DATA */ 705 706 /* GDMA_LIST_DEVICES */ 707 #define GDMA_DEV_LIST_SIZE 64 708 struct gdma_list_devices_resp { 709 struct gdma_resp_hdr hdr; 710 u32 num_of_devs; 711 u32 reserved; 712 struct gdma_dev_id devs[GDMA_DEV_LIST_SIZE]; 713 }; /* HW DATA */ 714 715 /* GDMA_REGISTER_DEVICE */ 716 struct gdma_register_device_resp { 717 struct gdma_resp_hdr hdr; 718 u32 pdid; 719 u32 gpa_mkey; 720 u32 db_id; 721 }; /* HW DATA */ 722 723 struct gdma_allocate_resource_range_req { 724 struct gdma_req_hdr hdr; 725 u32 resource_type; 726 u32 num_resources; 727 u32 alignment; 728 u32 allocated_resources; 729 }; 730 731 struct gdma_allocate_resource_range_resp { 732 struct gdma_resp_hdr hdr; 733 u32 allocated_resources; 734 }; 735 736 struct gdma_destroy_resource_range_req { 737 struct gdma_req_hdr hdr; 738 u32 resource_type; 739 u32 num_resources; 740 u32 allocated_resources; 741 }; 742 743 /* GDMA_CREATE_QUEUE */ 744 struct gdma_create_queue_req { 745 struct gdma_req_hdr hdr; 746 u32 type; 747 u32 reserved1; 748 u32 pdid; 749 u32 doolbell_id; 750 u64 gdma_region; 751 u32 reserved2; 752 u32 queue_size; 753 u32 log2_throttle_limit; 754 u32 eq_pci_msix_index; 755 u32 cq_mod_ctx_id; 756 u32 cq_parent_eq_id; 757 u8 rq_drop_on_overrun; 758 u8 rq_err_on_wqe_overflow; 759 u8 rq_chain_rec_wqes; 760 u8 sq_hw_db; 761 u32 reserved3; 762 }; /* HW DATA */ 763 764 struct gdma_create_queue_resp { 765 struct gdma_resp_hdr hdr; 766 u32 queue_index; 767 }; /* HW DATA */ 768 769 /* GDMA_DISABLE_QUEUE */ 770 struct gdma_disable_queue_req { 771 struct gdma_req_hdr hdr; 772 u32 type; 773 u32 queue_index; 774 u32 alloc_res_id_on_creation; 775 }; /* HW DATA */ 776 777 /* GDMA_QUERY_HWC_TIMEOUT */ 778 struct gdma_query_hwc_timeout_req { 779 struct gdma_req_hdr hdr; 780 u32 timeout_ms; 781 u32 reserved; 782 }; 783 784 struct gdma_query_hwc_timeout_resp { 785 struct gdma_resp_hdr hdr; 786 u32 timeout_ms; 787 u32 reserved; 788 }; 789 790 enum gdma_mr_access_flags { 791 GDMA_ACCESS_FLAG_LOCAL_READ = BIT_ULL(0), 792 GDMA_ACCESS_FLAG_LOCAL_WRITE = BIT_ULL(1), 793 GDMA_ACCESS_FLAG_REMOTE_READ = BIT_ULL(2), 794 GDMA_ACCESS_FLAG_REMOTE_WRITE = BIT_ULL(3), 795 GDMA_ACCESS_FLAG_REMOTE_ATOMIC = BIT_ULL(4), 796 GDMA_ACCESS_FLAG_BIND_MW = BIT_ULL(5), 797 }; 798 799 /* GDMA_CREATE_DMA_REGION */ 800 struct gdma_create_dma_region_req { 801 struct gdma_req_hdr hdr; 802 803 /* The total size of the DMA region */ 804 u64 length; 805 806 /* The offset in the first page */ 807 u32 offset_in_page; 808 809 /* enum gdma_page_type */ 810 u32 gdma_page_type; 811 812 /* The total number of pages */ 813 u32 page_count; 814 815 /* If page_addr_list_len is smaller than page_count, 816 * the remaining page addresses will be added via the 817 * message GDMA_DMA_REGION_ADD_PAGES. 818 */ 819 u32 page_addr_list_len; 820 u64 page_addr_list[]; 821 }; /* HW DATA */ 822 823 struct gdma_create_dma_region_resp { 824 struct gdma_resp_hdr hdr; 825 u64 dma_region_handle; 826 }; /* HW DATA */ 827 828 /* GDMA_DMA_REGION_ADD_PAGES */ 829 struct gdma_dma_region_add_pages_req { 830 struct gdma_req_hdr hdr; 831 832 u64 dma_region_handle; 833 834 u32 page_addr_list_len; 835 u32 reserved3; 836 837 u64 page_addr_list[]; 838 }; /* HW DATA */ 839 840 /* GDMA_DESTROY_DMA_REGION */ 841 struct gdma_destroy_dma_region_req { 842 struct gdma_req_hdr hdr; 843 844 u64 dma_region_handle; 845 }; /* HW DATA */ 846 847 enum gdma_pd_flags { 848 GDMA_PD_FLAG_INVALID = 0, 849 GDMA_PD_FLAG_ALLOW_GPA_MR = 1, 850 }; 851 852 struct gdma_create_pd_req { 853 struct gdma_req_hdr hdr; 854 enum gdma_pd_flags flags; 855 u32 reserved; 856 };/* HW DATA */ 857 858 struct gdma_create_pd_resp { 859 struct gdma_resp_hdr hdr; 860 u64 pd_handle; 861 u32 pd_id; 862 u32 reserved; 863 };/* HW DATA */ 864 865 struct gdma_destroy_pd_req { 866 struct gdma_req_hdr hdr; 867 u64 pd_handle; 868 };/* HW DATA */ 869 870 struct gdma_destory_pd_resp { 871 struct gdma_resp_hdr hdr; 872 };/* HW DATA */ 873 874 enum gdma_mr_type { 875 /* 876 * Guest Physical Address - MRs of this type allow access 877 * to any DMA-mapped memory using bus-logical address 878 */ 879 GDMA_MR_TYPE_GPA = 1, 880 /* Guest Virtual Address - MRs of this type allow access 881 * to memory mapped by PTEs associated with this MR using a virtual 882 * address that is set up in the MST 883 */ 884 GDMA_MR_TYPE_GVA = 2, 885 /* Guest zero-based address MRs */ 886 GDMA_MR_TYPE_ZBVA = 4, 887 /* Device address MRs */ 888 GDMA_MR_TYPE_DM = 5, 889 /* Memory Window type 1 */ 890 GDMA_MR_TYPE_MW1 = 6, 891 /* Memory Window type 2 */ 892 GDMA_MR_TYPE_MW2 = 7, 893 }; 894 895 struct gdma_create_mr_params { 896 u64 pd_handle; 897 enum gdma_mr_type mr_type; 898 union { 899 struct { 900 u64 dma_region_handle; 901 u64 virtual_address; 902 enum gdma_mr_access_flags access_flags; 903 } gva; 904 struct { 905 u64 dma_region_handle; 906 enum gdma_mr_access_flags access_flags; 907 } zbva; 908 struct { 909 u64 dm_handle; 910 u64 offset; 911 u64 length; 912 enum gdma_mr_access_flags access_flags; 913 } da; 914 }; 915 }; 916 917 struct gdma_create_mr_request { 918 struct gdma_req_hdr hdr; 919 u64 pd_handle; 920 enum gdma_mr_type mr_type; 921 u32 reserved_1; 922 923 union { 924 struct { 925 u64 dma_region_handle; 926 u64 virtual_address; 927 enum gdma_mr_access_flags access_flags; 928 } __packed gva; 929 struct { 930 u64 dma_region_handle; 931 enum gdma_mr_access_flags access_flags; 932 } __packed zbva; 933 struct { 934 u64 dm_handle; 935 u64 offset; 936 enum gdma_mr_access_flags access_flags; 937 } __packed da; 938 } __packed; 939 u32 reserved_2; 940 union { 941 struct { 942 u64 length; 943 } da_ext; 944 }; 945 };/* HW DATA */ 946 947 struct gdma_create_mr_response { 948 struct gdma_resp_hdr hdr; 949 u64 mr_handle; 950 u32 lkey; 951 u32 rkey; 952 };/* HW DATA */ 953 954 struct gdma_destroy_mr_request { 955 struct gdma_req_hdr hdr; 956 u64 mr_handle; 957 };/* HW DATA */ 958 959 struct gdma_destroy_mr_response { 960 struct gdma_resp_hdr hdr; 961 };/* HW DATA */ 962 963 struct gdma_alloc_dm_req { 964 struct gdma_req_hdr hdr; 965 u64 length; 966 u32 alignment; 967 u32 flags; 968 }; /* HW Data */ 969 970 struct gdma_alloc_dm_resp { 971 struct gdma_resp_hdr hdr; 972 u64 dm_handle; 973 }; /* HW Data */ 974 975 struct gdma_destroy_dm_req { 976 struct gdma_req_hdr hdr; 977 u64 dm_handle; 978 }; /* HW Data */ 979 980 struct gdma_destroy_dm_resp { 981 struct gdma_resp_hdr hdr; 982 }; /* HW Data */ 983 984 int mana_gd_verify_vf_version(struct pci_dev *pdev); 985 986 int mana_gd_register_device(struct gdma_dev *gd); 987 int mana_gd_deregister_device(struct gdma_dev *gd); 988 989 int mana_gd_post_work_request(struct gdma_queue *wq, 990 const struct gdma_wqe_request *wqe_req, 991 struct gdma_posted_wqe_info *wqe_info); 992 993 int mana_gd_post_and_ring(struct gdma_queue *queue, 994 const struct gdma_wqe_request *wqe, 995 struct gdma_posted_wqe_info *wqe_info); 996 997 int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r); 998 void mana_gd_free_res_map(struct gdma_resource *r); 999 1000 void mana_gd_wq_ring_doorbell(struct gdma_context *gc, 1001 struct gdma_queue *queue); 1002 1003 int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 1004 struct gdma_mem_info *gmi); 1005 1006 void mana_gd_free_memory(struct gdma_mem_info *gmi); 1007 1008 int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req, 1009 u32 resp_len, void *resp); 1010 1011 int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle); 1012 void mana_register_debugfs(void); 1013 void mana_unregister_debugfs(void); 1014 1015 int mana_rdma_service_event(struct gdma_context *gc, enum gdma_service_type event); 1016 1017 int mana_gd_suspend(struct pci_dev *pdev, pm_message_t state); 1018 int mana_gd_resume(struct pci_dev *pdev); 1019 1020 bool mana_need_log(struct gdma_context *gc, int err); 1021 1022 #endif /* _GDMA_H */ 1023