1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #ifndef _GDMA_H 5 #define _GDMA_H 6 7 #include <linux/dma-mapping.h> 8 #include <linux/netdevice.h> 9 10 #include "shm_channel.h" 11 12 #define GDMA_STATUS_MORE_ENTRIES 0x00000105 13 14 /* Structures labeled with "HW DATA" are exchanged with the hardware. All of 15 * them are naturally aligned and hence don't need __packed. 16 */ 17 18 enum gdma_request_type { 19 GDMA_VERIFY_VF_DRIVER_VERSION = 1, 20 GDMA_QUERY_MAX_RESOURCES = 2, 21 GDMA_LIST_DEVICES = 3, 22 GDMA_REGISTER_DEVICE = 4, 23 GDMA_DEREGISTER_DEVICE = 5, 24 GDMA_GENERATE_TEST_EQE = 10, 25 GDMA_CREATE_QUEUE = 12, 26 GDMA_DISABLE_QUEUE = 13, 27 GDMA_ALLOCATE_RESOURCE_RANGE = 22, 28 GDMA_DESTROY_RESOURCE_RANGE = 24, 29 GDMA_CREATE_DMA_REGION = 25, 30 GDMA_DMA_REGION_ADD_PAGES = 26, 31 GDMA_DESTROY_DMA_REGION = 27, 32 GDMA_CREATE_PD = 29, 33 GDMA_DESTROY_PD = 30, 34 GDMA_CREATE_MR = 31, 35 GDMA_DESTROY_MR = 32, 36 GDMA_QUERY_HWC_TIMEOUT = 84, /* 0x54 */ 37 }; 38 39 #define GDMA_RESOURCE_DOORBELL_PAGE 27 40 41 enum gdma_queue_type { 42 GDMA_INVALID_QUEUE, 43 GDMA_SQ, 44 GDMA_RQ, 45 GDMA_CQ, 46 GDMA_EQ, 47 }; 48 49 enum gdma_work_request_flags { 50 GDMA_WR_NONE = 0, 51 GDMA_WR_OOB_IN_SGL = BIT(0), 52 GDMA_WR_PAD_BY_SGE0 = BIT(1), 53 }; 54 55 enum gdma_eqe_type { 56 GDMA_EQE_COMPLETION = 3, 57 GDMA_EQE_TEST_EVENT = 64, 58 GDMA_EQE_HWC_INIT_EQ_ID_DB = 129, 59 GDMA_EQE_HWC_INIT_DATA = 130, 60 GDMA_EQE_HWC_INIT_DONE = 131, 61 GDMA_EQE_HWC_FPGA_RECONFIG = 132, 62 GDMA_EQE_HWC_SOC_RECONFIG_DATA = 133, 63 GDMA_EQE_HWC_SOC_SERVICE = 134, 64 GDMA_EQE_RNIC_QP_FATAL = 176, 65 }; 66 67 enum { 68 GDMA_DEVICE_NONE = 0, 69 GDMA_DEVICE_HWC = 1, 70 GDMA_DEVICE_MANA = 2, 71 GDMA_DEVICE_MANA_IB = 3, 72 }; 73 74 enum gdma_service_type { 75 GDMA_SERVICE_TYPE_NONE = 0, 76 GDMA_SERVICE_TYPE_RDMA_SUSPEND = 1, 77 GDMA_SERVICE_TYPE_RDMA_RESUME = 2, 78 }; 79 80 struct mana_service_work { 81 struct work_struct work; 82 struct gdma_dev *gdma_dev; 83 enum gdma_service_type event; 84 }; 85 86 struct gdma_resource { 87 /* Protect the bitmap */ 88 spinlock_t lock; 89 90 /* The bitmap size in bits. */ 91 u32 size; 92 93 /* The bitmap tracks the resources. */ 94 unsigned long *map; 95 }; 96 97 union gdma_doorbell_entry { 98 u64 as_uint64; 99 100 struct { 101 u64 id : 24; 102 u64 reserved : 8; 103 u64 tail_ptr : 31; 104 u64 arm : 1; 105 } cq; 106 107 struct { 108 u64 id : 24; 109 u64 wqe_cnt : 8; 110 u64 tail_ptr : 32; 111 } rq; 112 113 struct { 114 u64 id : 24; 115 u64 reserved : 8; 116 u64 tail_ptr : 32; 117 } sq; 118 119 struct { 120 u64 id : 16; 121 u64 reserved : 16; 122 u64 tail_ptr : 31; 123 u64 arm : 1; 124 } eq; 125 }; /* HW DATA */ 126 127 struct gdma_msg_hdr { 128 u32 hdr_type; 129 u32 msg_type; 130 u16 msg_version; 131 u16 hwc_msg_id; 132 u32 msg_size; 133 }; /* HW DATA */ 134 135 struct gdma_dev_id { 136 union { 137 struct { 138 u16 type; 139 u16 instance; 140 }; 141 142 u32 as_uint32; 143 }; 144 }; /* HW DATA */ 145 146 struct gdma_req_hdr { 147 struct gdma_msg_hdr req; 148 struct gdma_msg_hdr resp; /* The expected response */ 149 struct gdma_dev_id dev_id; 150 u32 activity_id; 151 }; /* HW DATA */ 152 153 struct gdma_resp_hdr { 154 struct gdma_msg_hdr response; 155 struct gdma_dev_id dev_id; 156 u32 activity_id; 157 u32 status; 158 u32 reserved; 159 }; /* HW DATA */ 160 161 struct gdma_general_req { 162 struct gdma_req_hdr hdr; 163 }; /* HW DATA */ 164 165 #define GDMA_MESSAGE_V1 1 166 #define GDMA_MESSAGE_V2 2 167 #define GDMA_MESSAGE_V3 3 168 #define GDMA_MESSAGE_V4 4 169 170 struct gdma_general_resp { 171 struct gdma_resp_hdr hdr; 172 }; /* HW DATA */ 173 174 #define GDMA_STANDARD_HEADER_TYPE 0 175 176 static inline void mana_gd_init_req_hdr(struct gdma_req_hdr *hdr, u32 code, 177 u32 req_size, u32 resp_size) 178 { 179 hdr->req.hdr_type = GDMA_STANDARD_HEADER_TYPE; 180 hdr->req.msg_type = code; 181 hdr->req.msg_version = GDMA_MESSAGE_V1; 182 hdr->req.msg_size = req_size; 183 184 hdr->resp.hdr_type = GDMA_STANDARD_HEADER_TYPE; 185 hdr->resp.msg_type = code; 186 hdr->resp.msg_version = GDMA_MESSAGE_V1; 187 hdr->resp.msg_size = resp_size; 188 } 189 190 /* The 16-byte struct is part of the GDMA work queue entry (WQE). */ 191 struct gdma_sge { 192 u64 address; 193 u32 mem_key; 194 u32 size; 195 }; /* HW DATA */ 196 197 struct gdma_wqe_request { 198 struct gdma_sge *sgl; 199 u32 num_sge; 200 201 u32 inline_oob_size; 202 const void *inline_oob_data; 203 204 u32 flags; 205 u32 client_data_unit; 206 }; 207 208 enum gdma_page_type { 209 GDMA_PAGE_TYPE_4K, 210 }; 211 212 #define GDMA_INVALID_DMA_REGION 0 213 214 struct gdma_mem_info { 215 struct device *dev; 216 217 dma_addr_t dma_handle; 218 void *virt_addr; 219 u64 length; 220 221 /* Allocated by the PF driver */ 222 u64 dma_region_handle; 223 }; 224 225 #define REGISTER_ATB_MST_MKEY_LOWER_SIZE 8 226 227 struct gdma_dev { 228 struct gdma_context *gdma_context; 229 230 struct gdma_dev_id dev_id; 231 232 u32 pdid; 233 u32 doorbell; 234 u32 gpa_mkey; 235 236 /* GDMA driver specific pointer */ 237 void *driver_data; 238 239 struct auxiliary_device *adev; 240 bool is_suspended; 241 bool rdma_teardown; 242 }; 243 244 /* MANA_PAGE_SIZE is the DMA unit */ 245 #define MANA_PAGE_SHIFT 12 246 #define MANA_PAGE_SIZE BIT(MANA_PAGE_SHIFT) 247 #define MANA_PAGE_ALIGN(x) ALIGN((x), MANA_PAGE_SIZE) 248 #define MANA_PAGE_ALIGNED(addr) IS_ALIGNED((unsigned long)(addr), MANA_PAGE_SIZE) 249 #define MANA_PFN(a) ((a) >> MANA_PAGE_SHIFT) 250 251 /* Required by HW */ 252 #define MANA_MIN_QSIZE MANA_PAGE_SIZE 253 254 #define GDMA_CQE_SIZE 64 255 #define GDMA_EQE_SIZE 16 256 #define GDMA_MAX_SQE_SIZE 512 257 #define GDMA_MAX_RQE_SIZE 256 258 259 #define GDMA_COMP_DATA_SIZE 0x3C 260 261 #define GDMA_EVENT_DATA_SIZE 0xC 262 263 /* The WQE size must be a multiple of the Basic Unit, which is 32 bytes. */ 264 #define GDMA_WQE_BU_SIZE 32 265 266 #define INVALID_PDID UINT_MAX 267 #define INVALID_DOORBELL UINT_MAX 268 #define INVALID_MEM_KEY UINT_MAX 269 #define INVALID_QUEUE_ID UINT_MAX 270 #define INVALID_PCI_MSIX_INDEX UINT_MAX 271 272 struct gdma_comp { 273 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4]; 274 u32 wq_num; 275 bool is_sq; 276 }; 277 278 struct gdma_event { 279 u32 details[GDMA_EVENT_DATA_SIZE / 4]; 280 u8 type; 281 }; 282 283 struct gdma_queue; 284 285 struct mana_eq { 286 struct gdma_queue *eq; 287 struct dentry *mana_eq_debugfs; 288 }; 289 290 typedef void gdma_eq_callback(void *context, struct gdma_queue *q, 291 struct gdma_event *e); 292 293 typedef void gdma_cq_callback(void *context, struct gdma_queue *q); 294 295 /* The 'head' is the producer index. For SQ/RQ, when the driver posts a WQE 296 * (Note: the WQE size must be a multiple of the 32-byte Basic Unit), the 297 * driver increases the 'head' in BUs rather than in bytes, and notifies 298 * the HW of the updated head. For EQ/CQ, the driver uses the 'head' to track 299 * the HW head, and increases the 'head' by 1 for every processed EQE/CQE. 300 * 301 * The 'tail' is the consumer index for SQ/RQ. After the CQE of the SQ/RQ is 302 * processed, the driver increases the 'tail' to indicate that WQEs have 303 * been consumed by the HW, so the driver can post new WQEs into the SQ/RQ. 304 * 305 * The driver doesn't use the 'tail' for EQ/CQ, because the driver ensures 306 * that the EQ/CQ is big enough so they can't overflow, and the driver uses 307 * the owner bits mechanism to detect if the queue has become empty. 308 */ 309 struct gdma_queue { 310 struct gdma_dev *gdma_dev; 311 312 enum gdma_queue_type type; 313 u32 id; 314 315 struct gdma_mem_info mem_info; 316 317 void *queue_mem_ptr; 318 u32 queue_size; 319 320 bool monitor_avl_buf; 321 322 u32 head; 323 u32 tail; 324 struct list_head entry; 325 326 /* Extra fields specific to EQ/CQ. */ 327 union { 328 struct { 329 bool disable_needed; 330 331 gdma_eq_callback *callback; 332 void *context; 333 334 unsigned int msix_index; 335 336 u32 log2_throttle_limit; 337 } eq; 338 339 struct { 340 gdma_cq_callback *callback; 341 void *context; 342 343 struct gdma_queue *parent; /* For CQ/EQ relationship */ 344 } cq; 345 }; 346 }; 347 348 struct gdma_queue_spec { 349 enum gdma_queue_type type; 350 bool monitor_avl_buf; 351 unsigned int queue_size; 352 353 /* Extra fields specific to EQ/CQ. */ 354 union { 355 struct { 356 gdma_eq_callback *callback; 357 void *context; 358 359 unsigned long log2_throttle_limit; 360 unsigned int msix_index; 361 } eq; 362 363 struct { 364 gdma_cq_callback *callback; 365 void *context; 366 367 struct gdma_queue *parent_eq; 368 369 } cq; 370 }; 371 }; 372 373 #define MANA_IRQ_NAME_SZ 32 374 375 struct gdma_irq_context { 376 void (*handler)(void *arg); 377 /* Protect the eq_list */ 378 spinlock_t lock; 379 struct list_head eq_list; 380 char name[MANA_IRQ_NAME_SZ]; 381 }; 382 383 struct gdma_context { 384 struct device *dev; 385 struct dentry *mana_pci_debugfs; 386 387 /* Per-vPort max number of queues */ 388 unsigned int max_num_queues; 389 unsigned int max_num_msix; 390 unsigned int num_msix_usable; 391 struct xarray irq_contexts; 392 393 /* L2 MTU */ 394 u16 adapter_mtu; 395 396 /* This maps a CQ index to the queue structure. */ 397 unsigned int max_num_cqs; 398 struct gdma_queue **cq_table; 399 400 /* Protect eq_test_event and test_event_eq_id */ 401 struct mutex eq_test_event_mutex; 402 struct completion eq_test_event; 403 u32 test_event_eq_id; 404 405 bool is_pf; 406 bool in_service; 407 408 phys_addr_t bar0_pa; 409 void __iomem *bar0_va; 410 void __iomem *shm_base; 411 void __iomem *db_page_base; 412 phys_addr_t phys_db_page_base; 413 u32 db_page_size; 414 int numa_node; 415 416 /* Shared memory chanenl (used to bootstrap HWC) */ 417 struct shm_channel shm_channel; 418 419 /* Hardware communication channel (HWC) */ 420 struct gdma_dev hwc; 421 422 /* Azure network adapter */ 423 struct gdma_dev mana; 424 425 /* Azure RDMA adapter */ 426 struct gdma_dev mana_ib; 427 428 u64 pf_cap_flags1; 429 430 struct workqueue_struct *service_wq; 431 }; 432 433 static inline bool mana_gd_is_mana(struct gdma_dev *gd) 434 { 435 return gd->dev_id.type == GDMA_DEVICE_MANA; 436 } 437 438 static inline bool mana_gd_is_hwc(struct gdma_dev *gd) 439 { 440 return gd->dev_id.type == GDMA_DEVICE_HWC; 441 } 442 443 u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset); 444 u32 mana_gd_wq_avail_space(struct gdma_queue *wq); 445 446 int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq); 447 448 int mana_gd_create_hwc_queue(struct gdma_dev *gd, 449 const struct gdma_queue_spec *spec, 450 struct gdma_queue **queue_ptr); 451 452 int mana_gd_create_mana_eq(struct gdma_dev *gd, 453 const struct gdma_queue_spec *spec, 454 struct gdma_queue **queue_ptr); 455 456 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 457 const struct gdma_queue_spec *spec, 458 struct gdma_queue **queue_ptr); 459 460 void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue); 461 462 int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe); 463 464 void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit); 465 466 struct gdma_wqe { 467 u32 reserved :24; 468 u32 last_vbytes :8; 469 470 union { 471 u32 flags; 472 473 struct { 474 u32 num_sge :8; 475 u32 inline_oob_size_div4:3; 476 u32 client_oob_in_sgl :1; 477 u32 reserved1 :4; 478 u32 client_data_unit :14; 479 u32 reserved2 :2; 480 }; 481 }; 482 }; /* HW DATA */ 483 484 #define INLINE_OOB_SMALL_SIZE 8 485 #define INLINE_OOB_LARGE_SIZE 24 486 487 #define MAX_TX_WQE_SIZE 512 488 #define MAX_RX_WQE_SIZE 256 489 490 #define MAX_TX_WQE_SGL_ENTRIES ((GDMA_MAX_SQE_SIZE - \ 491 sizeof(struct gdma_sge) - INLINE_OOB_SMALL_SIZE) / \ 492 sizeof(struct gdma_sge)) 493 494 #define MAX_RX_WQE_SGL_ENTRIES ((GDMA_MAX_RQE_SIZE - \ 495 sizeof(struct gdma_sge)) / sizeof(struct gdma_sge)) 496 497 struct gdma_cqe { 498 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4]; 499 500 union { 501 u32 as_uint32; 502 503 struct { 504 u32 wq_num : 24; 505 u32 is_sq : 1; 506 u32 reserved : 4; 507 u32 owner_bits : 3; 508 }; 509 } cqe_info; 510 }; /* HW DATA */ 511 512 #define GDMA_CQE_OWNER_BITS 3 513 514 #define GDMA_CQE_OWNER_MASK ((1 << GDMA_CQE_OWNER_BITS) - 1) 515 516 #define SET_ARM_BIT 1 517 518 #define GDMA_EQE_OWNER_BITS 3 519 520 union gdma_eqe_info { 521 u32 as_uint32; 522 523 struct { 524 u32 type : 8; 525 u32 reserved1 : 8; 526 u32 client_id : 2; 527 u32 reserved2 : 11; 528 u32 owner_bits : 3; 529 }; 530 }; /* HW DATA */ 531 532 #define GDMA_EQE_OWNER_MASK ((1 << GDMA_EQE_OWNER_BITS) - 1) 533 #define INITIALIZED_OWNER_BIT(log2_num_entries) (1UL << (log2_num_entries)) 534 535 struct gdma_eqe { 536 u32 details[GDMA_EVENT_DATA_SIZE / 4]; 537 u32 eqe_info; 538 }; /* HW DATA */ 539 540 #define GDMA_REG_DB_PAGE_OFFSET 8 541 #define GDMA_REG_DB_PAGE_SIZE 0x10 542 #define GDMA_REG_SHM_OFFSET 0x18 543 544 #define GDMA_PF_REG_DB_PAGE_SIZE 0xD0 545 #define GDMA_PF_REG_DB_PAGE_OFF 0xC8 546 #define GDMA_PF_REG_SHM_OFF 0x70 547 548 #define GDMA_SRIOV_REG_CFG_BASE_OFF 0x108 549 550 #define MANA_PF_DEVICE_ID 0x00B9 551 #define MANA_VF_DEVICE_ID 0x00BA 552 553 struct gdma_posted_wqe_info { 554 u32 wqe_size_in_bu; 555 }; 556 557 /* GDMA_GENERATE_TEST_EQE */ 558 struct gdma_generate_test_event_req { 559 struct gdma_req_hdr hdr; 560 u32 queue_index; 561 }; /* HW DATA */ 562 563 /* GDMA_VERIFY_VF_DRIVER_VERSION */ 564 enum { 565 GDMA_PROTOCOL_V1 = 1, 566 GDMA_PROTOCOL_FIRST = GDMA_PROTOCOL_V1, 567 GDMA_PROTOCOL_LAST = GDMA_PROTOCOL_V1, 568 }; 569 570 #define GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT BIT(0) 571 572 /* Advertise to the NIC firmware: the NAPI work_done variable race is fixed, 573 * so the driver is able to reliably support features like busy_poll. 574 */ 575 #define GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX BIT(2) 576 #define GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG BIT(3) 577 #define GDMA_DRV_CAP_FLAG_1_GDMA_PAGES_4MB_1GB_2GB BIT(4) 578 #define GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT BIT(5) 579 580 /* Driver can handle holes (zeros) in the device list */ 581 #define GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP BIT(11) 582 583 /* Driver supports dynamic MSI-X vector allocation */ 584 #define GDMA_DRV_CAP_FLAG_1_DYNAMIC_IRQ_ALLOC_SUPPORT BIT(13) 585 586 /* Driver can self reset on FPGA Reconfig EQE notification */ 587 #define GDMA_DRV_CAP_FLAG_1_HANDLE_RECONFIG_EQE BIT(17) 588 589 #define GDMA_DRV_CAP_FLAGS1 \ 590 (GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT | \ 591 GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX | \ 592 GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG | \ 593 GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT | \ 594 GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP | \ 595 GDMA_DRV_CAP_FLAG_1_DYNAMIC_IRQ_ALLOC_SUPPORT | \ 596 GDMA_DRV_CAP_FLAG_1_HANDLE_RECONFIG_EQE) 597 598 #define GDMA_DRV_CAP_FLAGS2 0 599 600 #define GDMA_DRV_CAP_FLAGS3 0 601 602 #define GDMA_DRV_CAP_FLAGS4 0 603 604 struct gdma_verify_ver_req { 605 struct gdma_req_hdr hdr; 606 607 /* Mandatory fields required for protocol establishment */ 608 u64 protocol_ver_min; 609 u64 protocol_ver_max; 610 611 /* Gdma Driver Capability Flags */ 612 u64 gd_drv_cap_flags1; 613 u64 gd_drv_cap_flags2; 614 u64 gd_drv_cap_flags3; 615 u64 gd_drv_cap_flags4; 616 617 /* Advisory fields */ 618 u64 drv_ver; 619 u32 os_type; /* Linux = 0x10; Windows = 0x20; Other = 0x30 */ 620 u32 reserved; 621 u32 os_ver_major; 622 u32 os_ver_minor; 623 u32 os_ver_build; 624 u32 os_ver_platform; 625 u64 reserved_2; 626 u8 os_ver_str1[128]; 627 u8 os_ver_str2[128]; 628 u8 os_ver_str3[128]; 629 u8 os_ver_str4[128]; 630 }; /* HW DATA */ 631 632 struct gdma_verify_ver_resp { 633 struct gdma_resp_hdr hdr; 634 u64 gdma_protocol_ver; 635 u64 pf_cap_flags1; 636 u64 pf_cap_flags2; 637 u64 pf_cap_flags3; 638 u64 pf_cap_flags4; 639 }; /* HW DATA */ 640 641 /* GDMA_QUERY_MAX_RESOURCES */ 642 struct gdma_query_max_resources_resp { 643 struct gdma_resp_hdr hdr; 644 u32 status; 645 u32 max_sq; 646 u32 max_rq; 647 u32 max_cq; 648 u32 max_eq; 649 u32 max_db; 650 u32 max_mst; 651 u32 max_cq_mod_ctx; 652 u32 max_mod_cq; 653 u32 max_msix; 654 }; /* HW DATA */ 655 656 /* GDMA_LIST_DEVICES */ 657 #define GDMA_DEV_LIST_SIZE 64 658 struct gdma_list_devices_resp { 659 struct gdma_resp_hdr hdr; 660 u32 num_of_devs; 661 u32 reserved; 662 struct gdma_dev_id devs[GDMA_DEV_LIST_SIZE]; 663 }; /* HW DATA */ 664 665 /* GDMA_REGISTER_DEVICE */ 666 struct gdma_register_device_resp { 667 struct gdma_resp_hdr hdr; 668 u32 pdid; 669 u32 gpa_mkey; 670 u32 db_id; 671 }; /* HW DATA */ 672 673 struct gdma_allocate_resource_range_req { 674 struct gdma_req_hdr hdr; 675 u32 resource_type; 676 u32 num_resources; 677 u32 alignment; 678 u32 allocated_resources; 679 }; 680 681 struct gdma_allocate_resource_range_resp { 682 struct gdma_resp_hdr hdr; 683 u32 allocated_resources; 684 }; 685 686 struct gdma_destroy_resource_range_req { 687 struct gdma_req_hdr hdr; 688 u32 resource_type; 689 u32 num_resources; 690 u32 allocated_resources; 691 }; 692 693 /* GDMA_CREATE_QUEUE */ 694 struct gdma_create_queue_req { 695 struct gdma_req_hdr hdr; 696 u32 type; 697 u32 reserved1; 698 u32 pdid; 699 u32 doolbell_id; 700 u64 gdma_region; 701 u32 reserved2; 702 u32 queue_size; 703 u32 log2_throttle_limit; 704 u32 eq_pci_msix_index; 705 u32 cq_mod_ctx_id; 706 u32 cq_parent_eq_id; 707 u8 rq_drop_on_overrun; 708 u8 rq_err_on_wqe_overflow; 709 u8 rq_chain_rec_wqes; 710 u8 sq_hw_db; 711 u32 reserved3; 712 }; /* HW DATA */ 713 714 struct gdma_create_queue_resp { 715 struct gdma_resp_hdr hdr; 716 u32 queue_index; 717 }; /* HW DATA */ 718 719 /* GDMA_DISABLE_QUEUE */ 720 struct gdma_disable_queue_req { 721 struct gdma_req_hdr hdr; 722 u32 type; 723 u32 queue_index; 724 u32 alloc_res_id_on_creation; 725 }; /* HW DATA */ 726 727 /* GDMA_QUERY_HWC_TIMEOUT */ 728 struct gdma_query_hwc_timeout_req { 729 struct gdma_req_hdr hdr; 730 u32 timeout_ms; 731 u32 reserved; 732 }; 733 734 struct gdma_query_hwc_timeout_resp { 735 struct gdma_resp_hdr hdr; 736 u32 timeout_ms; 737 u32 reserved; 738 }; 739 740 enum gdma_mr_access_flags { 741 GDMA_ACCESS_FLAG_LOCAL_READ = BIT_ULL(0), 742 GDMA_ACCESS_FLAG_LOCAL_WRITE = BIT_ULL(1), 743 GDMA_ACCESS_FLAG_REMOTE_READ = BIT_ULL(2), 744 GDMA_ACCESS_FLAG_REMOTE_WRITE = BIT_ULL(3), 745 GDMA_ACCESS_FLAG_REMOTE_ATOMIC = BIT_ULL(4), 746 }; 747 748 /* GDMA_CREATE_DMA_REGION */ 749 struct gdma_create_dma_region_req { 750 struct gdma_req_hdr hdr; 751 752 /* The total size of the DMA region */ 753 u64 length; 754 755 /* The offset in the first page */ 756 u32 offset_in_page; 757 758 /* enum gdma_page_type */ 759 u32 gdma_page_type; 760 761 /* The total number of pages */ 762 u32 page_count; 763 764 /* If page_addr_list_len is smaller than page_count, 765 * the remaining page addresses will be added via the 766 * message GDMA_DMA_REGION_ADD_PAGES. 767 */ 768 u32 page_addr_list_len; 769 u64 page_addr_list[]; 770 }; /* HW DATA */ 771 772 struct gdma_create_dma_region_resp { 773 struct gdma_resp_hdr hdr; 774 u64 dma_region_handle; 775 }; /* HW DATA */ 776 777 /* GDMA_DMA_REGION_ADD_PAGES */ 778 struct gdma_dma_region_add_pages_req { 779 struct gdma_req_hdr hdr; 780 781 u64 dma_region_handle; 782 783 u32 page_addr_list_len; 784 u32 reserved3; 785 786 u64 page_addr_list[]; 787 }; /* HW DATA */ 788 789 /* GDMA_DESTROY_DMA_REGION */ 790 struct gdma_destroy_dma_region_req { 791 struct gdma_req_hdr hdr; 792 793 u64 dma_region_handle; 794 }; /* HW DATA */ 795 796 enum gdma_pd_flags { 797 GDMA_PD_FLAG_INVALID = 0, 798 GDMA_PD_FLAG_ALLOW_GPA_MR = 1, 799 }; 800 801 struct gdma_create_pd_req { 802 struct gdma_req_hdr hdr; 803 enum gdma_pd_flags flags; 804 u32 reserved; 805 };/* HW DATA */ 806 807 struct gdma_create_pd_resp { 808 struct gdma_resp_hdr hdr; 809 u64 pd_handle; 810 u32 pd_id; 811 u32 reserved; 812 };/* HW DATA */ 813 814 struct gdma_destroy_pd_req { 815 struct gdma_req_hdr hdr; 816 u64 pd_handle; 817 };/* HW DATA */ 818 819 struct gdma_destory_pd_resp { 820 struct gdma_resp_hdr hdr; 821 };/* HW DATA */ 822 823 enum gdma_mr_type { 824 /* 825 * Guest Physical Address - MRs of this type allow access 826 * to any DMA-mapped memory using bus-logical address 827 */ 828 GDMA_MR_TYPE_GPA = 1, 829 /* Guest Virtual Address - MRs of this type allow access 830 * to memory mapped by PTEs associated with this MR using a virtual 831 * address that is set up in the MST 832 */ 833 GDMA_MR_TYPE_GVA = 2, 834 /* Guest zero-based address MRs */ 835 GDMA_MR_TYPE_ZBVA = 4, 836 }; 837 838 struct gdma_create_mr_params { 839 u64 pd_handle; 840 enum gdma_mr_type mr_type; 841 union { 842 struct { 843 u64 dma_region_handle; 844 u64 virtual_address; 845 enum gdma_mr_access_flags access_flags; 846 } gva; 847 struct { 848 u64 dma_region_handle; 849 enum gdma_mr_access_flags access_flags; 850 } zbva; 851 }; 852 }; 853 854 struct gdma_create_mr_request { 855 struct gdma_req_hdr hdr; 856 u64 pd_handle; 857 enum gdma_mr_type mr_type; 858 u32 reserved_1; 859 860 union { 861 struct { 862 u64 dma_region_handle; 863 u64 virtual_address; 864 enum gdma_mr_access_flags access_flags; 865 } gva; 866 struct { 867 u64 dma_region_handle; 868 enum gdma_mr_access_flags access_flags; 869 } zbva; 870 }; 871 u32 reserved_2; 872 };/* HW DATA */ 873 874 struct gdma_create_mr_response { 875 struct gdma_resp_hdr hdr; 876 u64 mr_handle; 877 u32 lkey; 878 u32 rkey; 879 };/* HW DATA */ 880 881 struct gdma_destroy_mr_request { 882 struct gdma_req_hdr hdr; 883 u64 mr_handle; 884 };/* HW DATA */ 885 886 struct gdma_destroy_mr_response { 887 struct gdma_resp_hdr hdr; 888 };/* HW DATA */ 889 890 int mana_gd_verify_vf_version(struct pci_dev *pdev); 891 892 int mana_gd_register_device(struct gdma_dev *gd); 893 int mana_gd_deregister_device(struct gdma_dev *gd); 894 895 int mana_gd_post_work_request(struct gdma_queue *wq, 896 const struct gdma_wqe_request *wqe_req, 897 struct gdma_posted_wqe_info *wqe_info); 898 899 int mana_gd_post_and_ring(struct gdma_queue *queue, 900 const struct gdma_wqe_request *wqe, 901 struct gdma_posted_wqe_info *wqe_info); 902 903 int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r); 904 void mana_gd_free_res_map(struct gdma_resource *r); 905 906 void mana_gd_wq_ring_doorbell(struct gdma_context *gc, 907 struct gdma_queue *queue); 908 909 int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 910 struct gdma_mem_info *gmi); 911 912 void mana_gd_free_memory(struct gdma_mem_info *gmi); 913 914 int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req, 915 u32 resp_len, void *resp); 916 917 int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle); 918 void mana_register_debugfs(void); 919 void mana_unregister_debugfs(void); 920 921 int mana_rdma_service_event(struct gdma_context *gc, enum gdma_service_type event); 922 923 #endif /* _GDMA_H */ 924