1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #ifndef _GDMA_H 5 #define _GDMA_H 6 7 #include <linux/dma-mapping.h> 8 #include <linux/netdevice.h> 9 10 #include "shm_channel.h" 11 12 #define GDMA_STATUS_MORE_ENTRIES 0x00000105 13 #define GDMA_STATUS_CMD_UNSUPPORTED 0xffffffff 14 15 /* Structures labeled with "HW DATA" are exchanged with the hardware. All of 16 * them are naturally aligned and hence don't need __packed. 17 */ 18 19 enum gdma_request_type { 20 GDMA_VERIFY_VF_DRIVER_VERSION = 1, 21 GDMA_QUERY_MAX_RESOURCES = 2, 22 GDMA_LIST_DEVICES = 3, 23 GDMA_REGISTER_DEVICE = 4, 24 GDMA_DEREGISTER_DEVICE = 5, 25 GDMA_GENERATE_TEST_EQE = 10, 26 GDMA_CREATE_QUEUE = 12, 27 GDMA_DISABLE_QUEUE = 13, 28 GDMA_ALLOCATE_RESOURCE_RANGE = 22, 29 GDMA_DESTROY_RESOURCE_RANGE = 24, 30 GDMA_CREATE_DMA_REGION = 25, 31 GDMA_DMA_REGION_ADD_PAGES = 26, 32 GDMA_DESTROY_DMA_REGION = 27, 33 GDMA_CREATE_PD = 29, 34 GDMA_DESTROY_PD = 30, 35 GDMA_CREATE_MR = 31, 36 GDMA_DESTROY_MR = 32, 37 GDMA_QUERY_HWC_TIMEOUT = 84, /* 0x54 */ 38 }; 39 40 #define GDMA_RESOURCE_DOORBELL_PAGE 27 41 42 enum gdma_queue_type { 43 GDMA_INVALID_QUEUE, 44 GDMA_SQ, 45 GDMA_RQ, 46 GDMA_CQ, 47 GDMA_EQ, 48 }; 49 50 enum gdma_work_request_flags { 51 GDMA_WR_NONE = 0, 52 GDMA_WR_OOB_IN_SGL = BIT(0), 53 GDMA_WR_PAD_BY_SGE0 = BIT(1), 54 }; 55 56 enum gdma_eqe_type { 57 GDMA_EQE_COMPLETION = 3, 58 GDMA_EQE_TEST_EVENT = 64, 59 GDMA_EQE_HWC_INIT_EQ_ID_DB = 129, 60 GDMA_EQE_HWC_INIT_DATA = 130, 61 GDMA_EQE_HWC_INIT_DONE = 131, 62 GDMA_EQE_HWC_FPGA_RECONFIG = 132, 63 GDMA_EQE_HWC_SOC_RECONFIG_DATA = 133, 64 GDMA_EQE_HWC_SOC_SERVICE = 134, 65 GDMA_EQE_RNIC_QP_FATAL = 176, 66 }; 67 68 enum { 69 GDMA_DEVICE_NONE = 0, 70 GDMA_DEVICE_HWC = 1, 71 GDMA_DEVICE_MANA = 2, 72 GDMA_DEVICE_MANA_IB = 3, 73 }; 74 75 enum gdma_service_type { 76 GDMA_SERVICE_TYPE_NONE = 0, 77 GDMA_SERVICE_TYPE_RDMA_SUSPEND = 1, 78 GDMA_SERVICE_TYPE_RDMA_RESUME = 2, 79 }; 80 81 struct mana_service_work { 82 struct work_struct work; 83 struct gdma_dev *gdma_dev; 84 enum gdma_service_type event; 85 }; 86 87 struct gdma_resource { 88 /* Protect the bitmap */ 89 spinlock_t lock; 90 91 /* The bitmap size in bits. */ 92 u32 size; 93 94 /* The bitmap tracks the resources. */ 95 unsigned long *map; 96 }; 97 98 union gdma_doorbell_entry { 99 u64 as_uint64; 100 101 struct { 102 u64 id : 24; 103 u64 reserved : 8; 104 u64 tail_ptr : 31; 105 u64 arm : 1; 106 } cq; 107 108 struct { 109 u64 id : 24; 110 u64 wqe_cnt : 8; 111 u64 tail_ptr : 32; 112 } rq; 113 114 struct { 115 u64 id : 24; 116 u64 reserved : 8; 117 u64 tail_ptr : 32; 118 } sq; 119 120 struct { 121 u64 id : 16; 122 u64 reserved : 16; 123 u64 tail_ptr : 31; 124 u64 arm : 1; 125 } eq; 126 }; /* HW DATA */ 127 128 struct gdma_msg_hdr { 129 u32 hdr_type; 130 u32 msg_type; 131 u16 msg_version; 132 u16 hwc_msg_id; 133 u32 msg_size; 134 }; /* HW DATA */ 135 136 struct gdma_dev_id { 137 union { 138 struct { 139 u16 type; 140 u16 instance; 141 }; 142 143 u32 as_uint32; 144 }; 145 }; /* HW DATA */ 146 147 struct gdma_req_hdr { 148 struct gdma_msg_hdr req; 149 struct gdma_msg_hdr resp; /* The expected response */ 150 struct gdma_dev_id dev_id; 151 u32 activity_id; 152 }; /* HW DATA */ 153 154 struct gdma_resp_hdr { 155 struct gdma_msg_hdr response; 156 struct gdma_dev_id dev_id; 157 u32 activity_id; 158 u32 status; 159 u32 reserved; 160 }; /* HW DATA */ 161 162 struct gdma_general_req { 163 struct gdma_req_hdr hdr; 164 }; /* HW DATA */ 165 166 #define GDMA_MESSAGE_V1 1 167 #define GDMA_MESSAGE_V2 2 168 #define GDMA_MESSAGE_V3 3 169 #define GDMA_MESSAGE_V4 4 170 171 struct gdma_general_resp { 172 struct gdma_resp_hdr hdr; 173 }; /* HW DATA */ 174 175 #define GDMA_STANDARD_HEADER_TYPE 0 176 177 static inline void mana_gd_init_req_hdr(struct gdma_req_hdr *hdr, u32 code, 178 u32 req_size, u32 resp_size) 179 { 180 hdr->req.hdr_type = GDMA_STANDARD_HEADER_TYPE; 181 hdr->req.msg_type = code; 182 hdr->req.msg_version = GDMA_MESSAGE_V1; 183 hdr->req.msg_size = req_size; 184 185 hdr->resp.hdr_type = GDMA_STANDARD_HEADER_TYPE; 186 hdr->resp.msg_type = code; 187 hdr->resp.msg_version = GDMA_MESSAGE_V1; 188 hdr->resp.msg_size = resp_size; 189 } 190 191 /* The 16-byte struct is part of the GDMA work queue entry (WQE). */ 192 struct gdma_sge { 193 u64 address; 194 u32 mem_key; 195 u32 size; 196 }; /* HW DATA */ 197 198 struct gdma_wqe_request { 199 struct gdma_sge *sgl; 200 u32 num_sge; 201 202 u32 inline_oob_size; 203 const void *inline_oob_data; 204 205 u32 flags; 206 u32 client_data_unit; 207 }; 208 209 enum gdma_page_type { 210 GDMA_PAGE_TYPE_4K, 211 }; 212 213 #define GDMA_INVALID_DMA_REGION 0 214 215 struct gdma_mem_info { 216 struct device *dev; 217 218 dma_addr_t dma_handle; 219 void *virt_addr; 220 u64 length; 221 222 /* Allocated by the PF driver */ 223 u64 dma_region_handle; 224 }; 225 226 #define REGISTER_ATB_MST_MKEY_LOWER_SIZE 8 227 228 struct gdma_dev { 229 struct gdma_context *gdma_context; 230 231 struct gdma_dev_id dev_id; 232 233 u32 pdid; 234 u32 doorbell; 235 u32 gpa_mkey; 236 237 /* GDMA driver specific pointer */ 238 void *driver_data; 239 240 struct auxiliary_device *adev; 241 bool is_suspended; 242 bool rdma_teardown; 243 }; 244 245 /* MANA_PAGE_SIZE is the DMA unit */ 246 #define MANA_PAGE_SHIFT 12 247 #define MANA_PAGE_SIZE BIT(MANA_PAGE_SHIFT) 248 #define MANA_PAGE_ALIGN(x) ALIGN((x), MANA_PAGE_SIZE) 249 #define MANA_PAGE_ALIGNED(addr) IS_ALIGNED((unsigned long)(addr), MANA_PAGE_SIZE) 250 #define MANA_PFN(a) ((a) >> MANA_PAGE_SHIFT) 251 252 /* Required by HW */ 253 #define MANA_MIN_QSIZE MANA_PAGE_SIZE 254 255 #define GDMA_CQE_SIZE 64 256 #define GDMA_EQE_SIZE 16 257 #define GDMA_MAX_SQE_SIZE 512 258 #define GDMA_MAX_RQE_SIZE 256 259 260 #define GDMA_COMP_DATA_SIZE 0x3C 261 262 #define GDMA_EVENT_DATA_SIZE 0xC 263 264 /* The WQE size must be a multiple of the Basic Unit, which is 32 bytes. */ 265 #define GDMA_WQE_BU_SIZE 32 266 267 #define INVALID_PDID UINT_MAX 268 #define INVALID_DOORBELL UINT_MAX 269 #define INVALID_MEM_KEY UINT_MAX 270 #define INVALID_QUEUE_ID UINT_MAX 271 #define INVALID_PCI_MSIX_INDEX UINT_MAX 272 273 struct gdma_comp { 274 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4]; 275 u32 wq_num; 276 bool is_sq; 277 }; 278 279 struct gdma_event { 280 u32 details[GDMA_EVENT_DATA_SIZE / 4]; 281 u8 type; 282 }; 283 284 struct gdma_queue; 285 286 struct mana_eq { 287 struct gdma_queue *eq; 288 struct dentry *mana_eq_debugfs; 289 }; 290 291 typedef void gdma_eq_callback(void *context, struct gdma_queue *q, 292 struct gdma_event *e); 293 294 typedef void gdma_cq_callback(void *context, struct gdma_queue *q); 295 296 /* The 'head' is the producer index. For SQ/RQ, when the driver posts a WQE 297 * (Note: the WQE size must be a multiple of the 32-byte Basic Unit), the 298 * driver increases the 'head' in BUs rather than in bytes, and notifies 299 * the HW of the updated head. For EQ/CQ, the driver uses the 'head' to track 300 * the HW head, and increases the 'head' by 1 for every processed EQE/CQE. 301 * 302 * The 'tail' is the consumer index for SQ/RQ. After the CQE of the SQ/RQ is 303 * processed, the driver increases the 'tail' to indicate that WQEs have 304 * been consumed by the HW, so the driver can post new WQEs into the SQ/RQ. 305 * 306 * The driver doesn't use the 'tail' for EQ/CQ, because the driver ensures 307 * that the EQ/CQ is big enough so they can't overflow, and the driver uses 308 * the owner bits mechanism to detect if the queue has become empty. 309 */ 310 struct gdma_queue { 311 struct gdma_dev *gdma_dev; 312 313 enum gdma_queue_type type; 314 u32 id; 315 316 struct gdma_mem_info mem_info; 317 318 void *queue_mem_ptr; 319 u32 queue_size; 320 321 bool monitor_avl_buf; 322 323 u32 head; 324 u32 tail; 325 struct list_head entry; 326 327 /* Extra fields specific to EQ/CQ. */ 328 union { 329 struct { 330 bool disable_needed; 331 332 gdma_eq_callback *callback; 333 void *context; 334 335 unsigned int msix_index; 336 337 u32 log2_throttle_limit; 338 } eq; 339 340 struct { 341 gdma_cq_callback *callback; 342 void *context; 343 344 struct gdma_queue *parent; /* For CQ/EQ relationship */ 345 } cq; 346 }; 347 }; 348 349 struct gdma_queue_spec { 350 enum gdma_queue_type type; 351 bool monitor_avl_buf; 352 unsigned int queue_size; 353 354 /* Extra fields specific to EQ/CQ. */ 355 union { 356 struct { 357 gdma_eq_callback *callback; 358 void *context; 359 360 unsigned long log2_throttle_limit; 361 unsigned int msix_index; 362 } eq; 363 364 struct { 365 gdma_cq_callback *callback; 366 void *context; 367 368 struct gdma_queue *parent_eq; 369 370 } cq; 371 }; 372 }; 373 374 #define MANA_IRQ_NAME_SZ 32 375 376 struct gdma_irq_context { 377 void (*handler)(void *arg); 378 /* Protect the eq_list */ 379 spinlock_t lock; 380 struct list_head eq_list; 381 char name[MANA_IRQ_NAME_SZ]; 382 }; 383 384 struct gdma_context { 385 struct device *dev; 386 struct dentry *mana_pci_debugfs; 387 388 /* Per-vPort max number of queues */ 389 unsigned int max_num_queues; 390 unsigned int max_num_msix; 391 unsigned int num_msix_usable; 392 struct xarray irq_contexts; 393 394 /* L2 MTU */ 395 u16 adapter_mtu; 396 397 /* This maps a CQ index to the queue structure. */ 398 unsigned int max_num_cqs; 399 struct gdma_queue **cq_table; 400 401 /* Protect eq_test_event and test_event_eq_id */ 402 struct mutex eq_test_event_mutex; 403 struct completion eq_test_event; 404 u32 test_event_eq_id; 405 406 bool is_pf; 407 bool in_service; 408 409 phys_addr_t bar0_pa; 410 void __iomem *bar0_va; 411 void __iomem *shm_base; 412 void __iomem *db_page_base; 413 phys_addr_t phys_db_page_base; 414 u32 db_page_size; 415 int numa_node; 416 417 /* Shared memory chanenl (used to bootstrap HWC) */ 418 struct shm_channel shm_channel; 419 420 /* Hardware communication channel (HWC) */ 421 struct gdma_dev hwc; 422 423 /* Azure network adapter */ 424 struct gdma_dev mana; 425 426 /* Azure RDMA adapter */ 427 struct gdma_dev mana_ib; 428 429 u64 pf_cap_flags1; 430 431 struct workqueue_struct *service_wq; 432 }; 433 434 static inline bool mana_gd_is_mana(struct gdma_dev *gd) 435 { 436 return gd->dev_id.type == GDMA_DEVICE_MANA; 437 } 438 439 static inline bool mana_gd_is_hwc(struct gdma_dev *gd) 440 { 441 return gd->dev_id.type == GDMA_DEVICE_HWC; 442 } 443 444 u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset); 445 u32 mana_gd_wq_avail_space(struct gdma_queue *wq); 446 447 int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq); 448 449 int mana_gd_create_hwc_queue(struct gdma_dev *gd, 450 const struct gdma_queue_spec *spec, 451 struct gdma_queue **queue_ptr); 452 453 int mana_gd_create_mana_eq(struct gdma_dev *gd, 454 const struct gdma_queue_spec *spec, 455 struct gdma_queue **queue_ptr); 456 457 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 458 const struct gdma_queue_spec *spec, 459 struct gdma_queue **queue_ptr); 460 461 void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue); 462 463 int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe); 464 465 void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit); 466 467 struct gdma_wqe { 468 u32 reserved :24; 469 u32 last_vbytes :8; 470 471 union { 472 u32 flags; 473 474 struct { 475 u32 num_sge :8; 476 u32 inline_oob_size_div4:3; 477 u32 client_oob_in_sgl :1; 478 u32 reserved1 :4; 479 u32 client_data_unit :14; 480 u32 reserved2 :2; 481 }; 482 }; 483 }; /* HW DATA */ 484 485 #define INLINE_OOB_SMALL_SIZE 8 486 #define INLINE_OOB_LARGE_SIZE 24 487 488 #define MAX_TX_WQE_SIZE 512 489 #define MAX_RX_WQE_SIZE 256 490 491 #define MAX_TX_WQE_SGL_ENTRIES ((GDMA_MAX_SQE_SIZE - \ 492 sizeof(struct gdma_sge) - INLINE_OOB_SMALL_SIZE) / \ 493 sizeof(struct gdma_sge)) 494 495 #define MAX_RX_WQE_SGL_ENTRIES ((GDMA_MAX_RQE_SIZE - \ 496 sizeof(struct gdma_sge)) / sizeof(struct gdma_sge)) 497 498 struct gdma_cqe { 499 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4]; 500 501 union { 502 u32 as_uint32; 503 504 struct { 505 u32 wq_num : 24; 506 u32 is_sq : 1; 507 u32 reserved : 4; 508 u32 owner_bits : 3; 509 }; 510 } cqe_info; 511 }; /* HW DATA */ 512 513 #define GDMA_CQE_OWNER_BITS 3 514 515 #define GDMA_CQE_OWNER_MASK ((1 << GDMA_CQE_OWNER_BITS) - 1) 516 517 #define SET_ARM_BIT 1 518 519 #define GDMA_EQE_OWNER_BITS 3 520 521 union gdma_eqe_info { 522 u32 as_uint32; 523 524 struct { 525 u32 type : 8; 526 u32 reserved1 : 8; 527 u32 client_id : 2; 528 u32 reserved2 : 11; 529 u32 owner_bits : 3; 530 }; 531 }; /* HW DATA */ 532 533 #define GDMA_EQE_OWNER_MASK ((1 << GDMA_EQE_OWNER_BITS) - 1) 534 #define INITIALIZED_OWNER_BIT(log2_num_entries) (1UL << (log2_num_entries)) 535 536 struct gdma_eqe { 537 u32 details[GDMA_EVENT_DATA_SIZE / 4]; 538 u32 eqe_info; 539 }; /* HW DATA */ 540 541 #define GDMA_REG_DB_PAGE_OFFSET 8 542 #define GDMA_REG_DB_PAGE_SIZE 0x10 543 #define GDMA_REG_SHM_OFFSET 0x18 544 545 #define GDMA_PF_REG_DB_PAGE_SIZE 0xD0 546 #define GDMA_PF_REG_DB_PAGE_OFF 0xC8 547 #define GDMA_PF_REG_SHM_OFF 0x70 548 549 #define GDMA_SRIOV_REG_CFG_BASE_OFF 0x108 550 551 #define MANA_PF_DEVICE_ID 0x00B9 552 #define MANA_VF_DEVICE_ID 0x00BA 553 554 struct gdma_posted_wqe_info { 555 u32 wqe_size_in_bu; 556 }; 557 558 /* GDMA_GENERATE_TEST_EQE */ 559 struct gdma_generate_test_event_req { 560 struct gdma_req_hdr hdr; 561 u32 queue_index; 562 }; /* HW DATA */ 563 564 /* GDMA_VERIFY_VF_DRIVER_VERSION */ 565 enum { 566 GDMA_PROTOCOL_V1 = 1, 567 GDMA_PROTOCOL_FIRST = GDMA_PROTOCOL_V1, 568 GDMA_PROTOCOL_LAST = GDMA_PROTOCOL_V1, 569 }; 570 571 #define GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT BIT(0) 572 573 /* Advertise to the NIC firmware: the NAPI work_done variable race is fixed, 574 * so the driver is able to reliably support features like busy_poll. 575 */ 576 #define GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX BIT(2) 577 #define GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG BIT(3) 578 #define GDMA_DRV_CAP_FLAG_1_GDMA_PAGES_4MB_1GB_2GB BIT(4) 579 #define GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT BIT(5) 580 581 /* Driver can handle holes (zeros) in the device list */ 582 #define GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP BIT(11) 583 584 /* Driver supports dynamic MSI-X vector allocation */ 585 #define GDMA_DRV_CAP_FLAG_1_DYNAMIC_IRQ_ALLOC_SUPPORT BIT(13) 586 587 /* Driver can self reset on FPGA Reconfig EQE notification */ 588 #define GDMA_DRV_CAP_FLAG_1_HANDLE_RECONFIG_EQE BIT(17) 589 590 #define GDMA_DRV_CAP_FLAGS1 \ 591 (GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT | \ 592 GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX | \ 593 GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG | \ 594 GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT | \ 595 GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP | \ 596 GDMA_DRV_CAP_FLAG_1_DYNAMIC_IRQ_ALLOC_SUPPORT | \ 597 GDMA_DRV_CAP_FLAG_1_HANDLE_RECONFIG_EQE) 598 599 #define GDMA_DRV_CAP_FLAGS2 0 600 601 #define GDMA_DRV_CAP_FLAGS3 0 602 603 #define GDMA_DRV_CAP_FLAGS4 0 604 605 struct gdma_verify_ver_req { 606 struct gdma_req_hdr hdr; 607 608 /* Mandatory fields required for protocol establishment */ 609 u64 protocol_ver_min; 610 u64 protocol_ver_max; 611 612 /* Gdma Driver Capability Flags */ 613 u64 gd_drv_cap_flags1; 614 u64 gd_drv_cap_flags2; 615 u64 gd_drv_cap_flags3; 616 u64 gd_drv_cap_flags4; 617 618 /* Advisory fields */ 619 u64 drv_ver; 620 u32 os_type; /* Linux = 0x10; Windows = 0x20; Other = 0x30 */ 621 u32 reserved; 622 u32 os_ver_major; 623 u32 os_ver_minor; 624 u32 os_ver_build; 625 u32 os_ver_platform; 626 u64 reserved_2; 627 u8 os_ver_str1[128]; 628 u8 os_ver_str2[128]; 629 u8 os_ver_str3[128]; 630 u8 os_ver_str4[128]; 631 }; /* HW DATA */ 632 633 struct gdma_verify_ver_resp { 634 struct gdma_resp_hdr hdr; 635 u64 gdma_protocol_ver; 636 u64 pf_cap_flags1; 637 u64 pf_cap_flags2; 638 u64 pf_cap_flags3; 639 u64 pf_cap_flags4; 640 }; /* HW DATA */ 641 642 /* GDMA_QUERY_MAX_RESOURCES */ 643 struct gdma_query_max_resources_resp { 644 struct gdma_resp_hdr hdr; 645 u32 status; 646 u32 max_sq; 647 u32 max_rq; 648 u32 max_cq; 649 u32 max_eq; 650 u32 max_db; 651 u32 max_mst; 652 u32 max_cq_mod_ctx; 653 u32 max_mod_cq; 654 u32 max_msix; 655 }; /* HW DATA */ 656 657 /* GDMA_LIST_DEVICES */ 658 #define GDMA_DEV_LIST_SIZE 64 659 struct gdma_list_devices_resp { 660 struct gdma_resp_hdr hdr; 661 u32 num_of_devs; 662 u32 reserved; 663 struct gdma_dev_id devs[GDMA_DEV_LIST_SIZE]; 664 }; /* HW DATA */ 665 666 /* GDMA_REGISTER_DEVICE */ 667 struct gdma_register_device_resp { 668 struct gdma_resp_hdr hdr; 669 u32 pdid; 670 u32 gpa_mkey; 671 u32 db_id; 672 }; /* HW DATA */ 673 674 struct gdma_allocate_resource_range_req { 675 struct gdma_req_hdr hdr; 676 u32 resource_type; 677 u32 num_resources; 678 u32 alignment; 679 u32 allocated_resources; 680 }; 681 682 struct gdma_allocate_resource_range_resp { 683 struct gdma_resp_hdr hdr; 684 u32 allocated_resources; 685 }; 686 687 struct gdma_destroy_resource_range_req { 688 struct gdma_req_hdr hdr; 689 u32 resource_type; 690 u32 num_resources; 691 u32 allocated_resources; 692 }; 693 694 /* GDMA_CREATE_QUEUE */ 695 struct gdma_create_queue_req { 696 struct gdma_req_hdr hdr; 697 u32 type; 698 u32 reserved1; 699 u32 pdid; 700 u32 doolbell_id; 701 u64 gdma_region; 702 u32 reserved2; 703 u32 queue_size; 704 u32 log2_throttle_limit; 705 u32 eq_pci_msix_index; 706 u32 cq_mod_ctx_id; 707 u32 cq_parent_eq_id; 708 u8 rq_drop_on_overrun; 709 u8 rq_err_on_wqe_overflow; 710 u8 rq_chain_rec_wqes; 711 u8 sq_hw_db; 712 u32 reserved3; 713 }; /* HW DATA */ 714 715 struct gdma_create_queue_resp { 716 struct gdma_resp_hdr hdr; 717 u32 queue_index; 718 }; /* HW DATA */ 719 720 /* GDMA_DISABLE_QUEUE */ 721 struct gdma_disable_queue_req { 722 struct gdma_req_hdr hdr; 723 u32 type; 724 u32 queue_index; 725 u32 alloc_res_id_on_creation; 726 }; /* HW DATA */ 727 728 /* GDMA_QUERY_HWC_TIMEOUT */ 729 struct gdma_query_hwc_timeout_req { 730 struct gdma_req_hdr hdr; 731 u32 timeout_ms; 732 u32 reserved; 733 }; 734 735 struct gdma_query_hwc_timeout_resp { 736 struct gdma_resp_hdr hdr; 737 u32 timeout_ms; 738 u32 reserved; 739 }; 740 741 enum gdma_mr_access_flags { 742 GDMA_ACCESS_FLAG_LOCAL_READ = BIT_ULL(0), 743 GDMA_ACCESS_FLAG_LOCAL_WRITE = BIT_ULL(1), 744 GDMA_ACCESS_FLAG_REMOTE_READ = BIT_ULL(2), 745 GDMA_ACCESS_FLAG_REMOTE_WRITE = BIT_ULL(3), 746 GDMA_ACCESS_FLAG_REMOTE_ATOMIC = BIT_ULL(4), 747 }; 748 749 /* GDMA_CREATE_DMA_REGION */ 750 struct gdma_create_dma_region_req { 751 struct gdma_req_hdr hdr; 752 753 /* The total size of the DMA region */ 754 u64 length; 755 756 /* The offset in the first page */ 757 u32 offset_in_page; 758 759 /* enum gdma_page_type */ 760 u32 gdma_page_type; 761 762 /* The total number of pages */ 763 u32 page_count; 764 765 /* If page_addr_list_len is smaller than page_count, 766 * the remaining page addresses will be added via the 767 * message GDMA_DMA_REGION_ADD_PAGES. 768 */ 769 u32 page_addr_list_len; 770 u64 page_addr_list[]; 771 }; /* HW DATA */ 772 773 struct gdma_create_dma_region_resp { 774 struct gdma_resp_hdr hdr; 775 u64 dma_region_handle; 776 }; /* HW DATA */ 777 778 /* GDMA_DMA_REGION_ADD_PAGES */ 779 struct gdma_dma_region_add_pages_req { 780 struct gdma_req_hdr hdr; 781 782 u64 dma_region_handle; 783 784 u32 page_addr_list_len; 785 u32 reserved3; 786 787 u64 page_addr_list[]; 788 }; /* HW DATA */ 789 790 /* GDMA_DESTROY_DMA_REGION */ 791 struct gdma_destroy_dma_region_req { 792 struct gdma_req_hdr hdr; 793 794 u64 dma_region_handle; 795 }; /* HW DATA */ 796 797 enum gdma_pd_flags { 798 GDMA_PD_FLAG_INVALID = 0, 799 GDMA_PD_FLAG_ALLOW_GPA_MR = 1, 800 }; 801 802 struct gdma_create_pd_req { 803 struct gdma_req_hdr hdr; 804 enum gdma_pd_flags flags; 805 u32 reserved; 806 };/* HW DATA */ 807 808 struct gdma_create_pd_resp { 809 struct gdma_resp_hdr hdr; 810 u64 pd_handle; 811 u32 pd_id; 812 u32 reserved; 813 };/* HW DATA */ 814 815 struct gdma_destroy_pd_req { 816 struct gdma_req_hdr hdr; 817 u64 pd_handle; 818 };/* HW DATA */ 819 820 struct gdma_destory_pd_resp { 821 struct gdma_resp_hdr hdr; 822 };/* HW DATA */ 823 824 enum gdma_mr_type { 825 /* 826 * Guest Physical Address - MRs of this type allow access 827 * to any DMA-mapped memory using bus-logical address 828 */ 829 GDMA_MR_TYPE_GPA = 1, 830 /* Guest Virtual Address - MRs of this type allow access 831 * to memory mapped by PTEs associated with this MR using a virtual 832 * address that is set up in the MST 833 */ 834 GDMA_MR_TYPE_GVA = 2, 835 /* Guest zero-based address MRs */ 836 GDMA_MR_TYPE_ZBVA = 4, 837 }; 838 839 struct gdma_create_mr_params { 840 u64 pd_handle; 841 enum gdma_mr_type mr_type; 842 union { 843 struct { 844 u64 dma_region_handle; 845 u64 virtual_address; 846 enum gdma_mr_access_flags access_flags; 847 } gva; 848 struct { 849 u64 dma_region_handle; 850 enum gdma_mr_access_flags access_flags; 851 } zbva; 852 }; 853 }; 854 855 struct gdma_create_mr_request { 856 struct gdma_req_hdr hdr; 857 u64 pd_handle; 858 enum gdma_mr_type mr_type; 859 u32 reserved_1; 860 861 union { 862 struct { 863 u64 dma_region_handle; 864 u64 virtual_address; 865 enum gdma_mr_access_flags access_flags; 866 } gva; 867 struct { 868 u64 dma_region_handle; 869 enum gdma_mr_access_flags access_flags; 870 } zbva; 871 }; 872 u32 reserved_2; 873 };/* HW DATA */ 874 875 struct gdma_create_mr_response { 876 struct gdma_resp_hdr hdr; 877 u64 mr_handle; 878 u32 lkey; 879 u32 rkey; 880 };/* HW DATA */ 881 882 struct gdma_destroy_mr_request { 883 struct gdma_req_hdr hdr; 884 u64 mr_handle; 885 };/* HW DATA */ 886 887 struct gdma_destroy_mr_response { 888 struct gdma_resp_hdr hdr; 889 };/* HW DATA */ 890 891 int mana_gd_verify_vf_version(struct pci_dev *pdev); 892 893 int mana_gd_register_device(struct gdma_dev *gd); 894 int mana_gd_deregister_device(struct gdma_dev *gd); 895 896 int mana_gd_post_work_request(struct gdma_queue *wq, 897 const struct gdma_wqe_request *wqe_req, 898 struct gdma_posted_wqe_info *wqe_info); 899 900 int mana_gd_post_and_ring(struct gdma_queue *queue, 901 const struct gdma_wqe_request *wqe, 902 struct gdma_posted_wqe_info *wqe_info); 903 904 int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r); 905 void mana_gd_free_res_map(struct gdma_resource *r); 906 907 void mana_gd_wq_ring_doorbell(struct gdma_context *gc, 908 struct gdma_queue *queue); 909 910 int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 911 struct gdma_mem_info *gmi); 912 913 void mana_gd_free_memory(struct gdma_mem_info *gmi); 914 915 int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req, 916 u32 resp_len, void *resp); 917 918 int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle); 919 void mana_register_debugfs(void); 920 void mana_unregister_debugfs(void); 921 922 int mana_rdma_service_event(struct gdma_context *gc, enum gdma_service_type event); 923 924 #endif /* _GDMA_H */ 925