1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #ifndef _GDMA_H 5 #define _GDMA_H 6 7 #include <linux/dma-mapping.h> 8 #include <linux/netdevice.h> 9 #include <rdma/ib_verbs.h> 10 11 #include "shm_channel.h" 12 13 #define GDMA_STATUS_MORE_ENTRIES 0x00000105 14 #define GDMA_STATUS_CMD_UNSUPPORTED 0xffffffff 15 16 /* Structures labeled with "HW DATA" are exchanged with the hardware. All of 17 * them are naturally aligned and hence don't need __packed. 18 */ 19 20 enum gdma_request_type { 21 GDMA_VERIFY_VF_DRIVER_VERSION = 1, 22 GDMA_QUERY_MAX_RESOURCES = 2, 23 GDMA_LIST_DEVICES = 3, 24 GDMA_REGISTER_DEVICE = 4, 25 GDMA_DEREGISTER_DEVICE = 5, 26 GDMA_GENERATE_TEST_EQE = 10, 27 GDMA_CREATE_QUEUE = 12, 28 GDMA_DISABLE_QUEUE = 13, 29 GDMA_ALLOCATE_RESOURCE_RANGE = 22, 30 GDMA_DESTROY_RESOURCE_RANGE = 24, 31 GDMA_CREATE_DMA_REGION = 25, 32 GDMA_DMA_REGION_ADD_PAGES = 26, 33 GDMA_DESTROY_DMA_REGION = 27, 34 GDMA_CREATE_PD = 29, 35 GDMA_DESTROY_PD = 30, 36 GDMA_CREATE_MR = 31, 37 GDMA_DESTROY_MR = 32, 38 GDMA_QUERY_HWC_TIMEOUT = 84, /* 0x54 */ 39 GDMA_ALLOC_DM = 96, /* 0x60 */ 40 GDMA_DESTROY_DM = 97, /* 0x61 */ 41 }; 42 43 #define GDMA_RESOURCE_DOORBELL_PAGE 27 44 45 enum gdma_queue_type { 46 GDMA_INVALID_QUEUE, 47 GDMA_SQ, 48 GDMA_RQ, 49 GDMA_CQ, 50 GDMA_EQ, 51 GDMA_DIM, 52 }; 53 54 enum gdma_work_request_flags { 55 GDMA_WR_NONE = 0, 56 GDMA_WR_OOB_IN_SGL = BIT(0), 57 GDMA_WR_PAD_BY_SGE0 = BIT(1), 58 GDMA_WR_IB_SGL = BIT(2), 59 }; 60 61 enum gdma_eqe_type { 62 GDMA_EQE_COMPLETION = 3, 63 GDMA_EQE_TEST_EVENT = 64, 64 GDMA_EQE_HWC_INIT_EQ_ID_DB = 129, 65 GDMA_EQE_HWC_INIT_DATA = 130, 66 GDMA_EQE_HWC_INIT_DONE = 131, 67 GDMA_EQE_HWC_FPGA_RECONFIG = 132, 68 GDMA_EQE_HWC_SOC_RECONFIG_DATA = 133, 69 GDMA_EQE_HWC_SOC_SERVICE = 134, 70 GDMA_EQE_HWC_RESET_REQUEST = 135, 71 GDMA_EQE_RNIC_QP_FATAL = 176, 72 }; 73 74 enum { 75 GDMA_DEVICE_NONE = 0, 76 GDMA_DEVICE_HWC = 1, 77 GDMA_DEVICE_MANA = 2, 78 GDMA_DEVICE_MANA_IB = 3, 79 }; 80 81 enum gdma_service_type { 82 GDMA_SERVICE_TYPE_NONE = 0, 83 GDMA_SERVICE_TYPE_RDMA_SUSPEND = 1, 84 GDMA_SERVICE_TYPE_RDMA_RESUME = 2, 85 }; 86 87 struct mana_service_work { 88 struct work_struct work; 89 struct gdma_dev *gdma_dev; 90 enum gdma_service_type event; 91 }; 92 93 struct gdma_resource { 94 /* Protect the bitmap */ 95 spinlock_t lock; 96 97 /* The bitmap size in bits. */ 98 u32 size; 99 100 /* The bitmap tracks the resources. */ 101 unsigned long *map; 102 }; 103 104 union gdma_doorbell_entry { 105 u64 as_uint64; 106 107 struct { 108 u64 id : 24; 109 u64 reserved : 8; 110 u64 tail_ptr : 31; 111 u64 arm : 1; 112 } cq; 113 114 struct { 115 u64 id : 24; 116 u64 wqe_cnt : 8; 117 u64 tail_ptr : 32; 118 } rq; 119 120 struct { 121 u64 id : 24; 122 u64 reserved : 8; 123 u64 tail_ptr : 32; 124 } sq; 125 126 struct { 127 u64 id : 16; 128 u64 reserved : 16; 129 u64 tail_ptr : 31; 130 u64 arm : 1; 131 } eq; 132 133 struct { 134 u64 id : 24; 135 u64 reserved : 8; 136 u64 mod_usec : 10; 137 u64 reserve1 : 5; 138 u64 mod_usec_vld : 1; 139 u64 mod_comps : 8; 140 u64 reserve2 : 7; 141 u64 mod_comps_vld: 1; 142 } dim; 143 }; /* HW DATA */ 144 145 struct gdma_msg_hdr { 146 u32 hdr_type; 147 u32 msg_type; 148 u16 msg_version; 149 u16 hwc_msg_id; 150 u32 msg_size; 151 }; /* HW DATA */ 152 153 struct gdma_dev_id { 154 union { 155 struct { 156 u16 type; 157 u16 instance; 158 }; 159 160 u32 as_uint32; 161 }; 162 }; /* HW DATA */ 163 164 struct gdma_req_hdr { 165 struct gdma_msg_hdr req; 166 struct gdma_msg_hdr resp; /* The expected response */ 167 struct gdma_dev_id dev_id; 168 u32 activity_id; 169 }; /* HW DATA */ 170 171 struct gdma_resp_hdr { 172 struct gdma_msg_hdr response; 173 struct gdma_dev_id dev_id; 174 u32 activity_id; 175 u32 status; 176 u32 reserved; 177 }; /* HW DATA */ 178 179 struct gdma_general_req { 180 struct gdma_req_hdr hdr; 181 }; /* HW DATA */ 182 183 #define GDMA_MESSAGE_V1 1 184 #define GDMA_MESSAGE_V2 2 185 #define GDMA_MESSAGE_V3 3 186 #define GDMA_MESSAGE_V4 4 187 #define GDMA_MESSAGE_V5 5 188 189 struct gdma_general_resp { 190 struct gdma_resp_hdr hdr; 191 }; /* HW DATA */ 192 193 #define GDMA_STANDARD_HEADER_TYPE 0 194 195 static inline void mana_gd_init_req_hdr(struct gdma_req_hdr *hdr, u32 code, 196 u32 req_size, u32 resp_size) 197 { 198 hdr->req.hdr_type = GDMA_STANDARD_HEADER_TYPE; 199 hdr->req.msg_type = code; 200 hdr->req.msg_version = GDMA_MESSAGE_V1; 201 hdr->req.msg_size = req_size; 202 203 hdr->resp.hdr_type = GDMA_STANDARD_HEADER_TYPE; 204 hdr->resp.msg_type = code; 205 hdr->resp.msg_version = GDMA_MESSAGE_V1; 206 hdr->resp.msg_size = resp_size; 207 } 208 209 /* The 16-byte struct is part of the GDMA work queue entry (WQE). */ 210 struct gdma_sge { 211 u64 address; 212 u32 mem_key; 213 u32 size; 214 }; /* HW DATA */ 215 216 struct gdma_wqe_request { 217 union { 218 struct gdma_sge *sgl; 219 struct ib_sge *ib_sgl; 220 }; 221 u32 num_sge; 222 223 u32 inline_oob_size; 224 const void *inline_oob_data; 225 226 u32 flags; 227 u32 client_data_unit; 228 }; 229 230 enum gdma_page_type { 231 GDMA_PAGE_TYPE_4K, 232 }; 233 234 #define GDMA_INVALID_DMA_REGION 0 235 236 struct mana_serv_work { 237 struct work_struct serv_work; 238 struct pci_dev *pdev; 239 enum gdma_eqe_type type; 240 }; 241 242 struct gdma_mem_info { 243 struct device *dev; 244 245 dma_addr_t dma_handle; 246 void *virt_addr; 247 u64 length; 248 249 /* Scattered fallback: when @nr_pages > 0 the ring is that many 250 * PAGE_SIZE coherent allocations in @pages_va/@pages_dma, not 251 * @virt_addr/@dma_handle. 252 */ 253 void **pages_va; 254 dma_addr_t *pages_dma; 255 unsigned int nr_pages; 256 257 /* Allocated by the PF driver */ 258 u64 dma_region_handle; 259 }; 260 261 #define REGISTER_ATB_MST_MKEY_LOWER_SIZE 8 262 263 struct gdma_dev { 264 struct gdma_context *gdma_context; 265 266 struct gdma_dev_id dev_id; 267 268 u32 pdid; 269 u32 doorbell; 270 u32 gpa_mkey; 271 272 /* GDMA driver specific pointer */ 273 void *driver_data; 274 275 struct auxiliary_device *adev; 276 bool is_suspended; 277 bool rdma_teardown; 278 }; 279 280 /* MANA_PAGE_SIZE is the DMA unit */ 281 #define MANA_PAGE_SHIFT 12 282 #define MANA_PAGE_SIZE BIT(MANA_PAGE_SHIFT) 283 #define MANA_PAGE_ALIGN(x) ALIGN((x), MANA_PAGE_SIZE) 284 #define MANA_PAGE_ALIGNED(addr) IS_ALIGNED((unsigned long)(addr), MANA_PAGE_SIZE) 285 #define MANA_PFN(a) ((a) >> MANA_PAGE_SHIFT) 286 287 /* Required by HW */ 288 #define MANA_MIN_QSIZE MANA_PAGE_SIZE 289 290 #define GDMA_CQE_SIZE 64 291 #define GDMA_EQE_SIZE 16 292 #define GDMA_MAX_SQE_SIZE 512 293 #define GDMA_MAX_RQE_SIZE 256 294 295 #define GDMA_COMP_DATA_SIZE 0x3C 296 297 #define GDMA_EVENT_DATA_SIZE 0xC 298 299 /* The WQE size must be a multiple of the Basic Unit, which is 32 bytes. */ 300 #define GDMA_WQE_BU_SIZE 32 301 302 #define INVALID_PDID UINT_MAX 303 #define INVALID_DOORBELL UINT_MAX 304 #define INVALID_MEM_KEY UINT_MAX 305 #define INVALID_QUEUE_ID UINT_MAX 306 #define INVALID_PCI_MSIX_INDEX UINT_MAX 307 308 struct gdma_comp { 309 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4]; 310 u32 wq_num; 311 bool is_sq; 312 }; 313 314 struct gdma_event { 315 u32 details[GDMA_EVENT_DATA_SIZE / 4]; 316 u8 type; 317 }; 318 319 struct gdma_queue; 320 321 struct mana_eq { 322 struct gdma_queue *eq; 323 struct dentry *mana_eq_debugfs; 324 }; 325 326 typedef void gdma_eq_callback(void *context, struct gdma_queue *q, 327 struct gdma_event *e); 328 329 typedef void gdma_cq_callback(void *context, struct gdma_queue *q); 330 331 /* The 'head' is the producer index. For SQ/RQ, when the driver posts a WQE 332 * (Note: the WQE size must be a multiple of the 32-byte Basic Unit), the 333 * driver increases the 'head' in BUs rather than in bytes, and notifies 334 * the HW of the updated head. For EQ/CQ, the driver uses the 'head' to track 335 * the HW head, and increases the 'head' by 1 for every processed EQE/CQE. 336 * 337 * The 'tail' is the consumer index for SQ/RQ. After the CQE of the SQ/RQ is 338 * processed, the driver increases the 'tail' to indicate that WQEs have 339 * been consumed by the HW, so the driver can post new WQEs into the SQ/RQ. 340 * 341 * The driver doesn't use the 'tail' for EQ/CQ, because the driver ensures 342 * that the EQ/CQ is big enough so they can't overflow, and the driver uses 343 * the owner bits mechanism to detect if the queue has become empty. 344 */ 345 struct gdma_queue { 346 struct gdma_dev *gdma_dev; 347 348 enum gdma_queue_type type; 349 u32 id; 350 351 struct gdma_mem_info mem_info; 352 353 void *queue_mem_ptr; 354 u32 queue_size; 355 356 bool monitor_avl_buf; 357 358 u32 head; 359 u32 tail; 360 struct list_head entry; 361 362 /* Extra fields specific to EQ/CQ. */ 363 union { 364 struct { 365 bool disable_needed; 366 367 gdma_eq_callback *callback; 368 void *context; 369 370 unsigned int msix_index; 371 unsigned int irq; 372 373 u32 log2_throttle_limit; 374 } eq; 375 376 struct { 377 gdma_cq_callback *callback; 378 void *context; 379 380 struct gdma_queue *parent; /* For CQ/EQ relationship */ 381 } cq; 382 }; 383 }; 384 385 struct gdma_queue_spec { 386 enum gdma_queue_type type; 387 bool monitor_avl_buf; 388 unsigned int queue_size; 389 390 /* Extra fields specific to EQ/CQ. */ 391 union { 392 struct { 393 gdma_eq_callback *callback; 394 void *context; 395 396 unsigned long log2_throttle_limit; 397 unsigned int msix_index; 398 } eq; 399 400 struct { 401 gdma_cq_callback *callback; 402 void *context; 403 404 struct gdma_queue *parent_eq; 405 406 } cq; 407 }; 408 }; 409 410 #define MANA_IRQ_NAME_SZ 32 411 412 struct gdma_irq_context { 413 void (*handler)(void *arg); 414 /* Protect the eq_list */ 415 spinlock_t lock; 416 struct list_head eq_list; 417 char name[MANA_IRQ_NAME_SZ]; 418 unsigned int msi; 419 unsigned int irq; 420 refcount_t refcount; 421 unsigned int bitmap_refs; 422 bool dyn_msix; 423 }; 424 425 enum gdma_context_flags { 426 GC_PROBE_SUCCEEDED = 0, 427 GC_IN_SERVICE = 1, 428 }; 429 430 struct gdma_context; 431 432 /** 433 * struct gdma_bus_ops - transport-specific operations 434 * 435 * Lets the bus-agnostic GDMA core drive PCI and CDX devices without 436 * testing configuration symbols. Each bus driver installs its own 437 * instance in gdma_context.bus_ops at probe time. 438 * 439 * @bus_name: Bus token used to build the per-vector IRQ names. 440 * @adev_prefix: Prefix used for auxiliary-device match names. 441 * @msix_can_alloc_dyn: True if the bus can allocate MSI-X vectors after 442 * probe time. Buses that size their vector pool at probe and cannot 443 * grow it later leave this NULL. 444 * @msix_virq: Return the Linux IRQ number backing an MSI vector, or 445 * -EINVAL if the vector has not been allocated yet. 446 * @msix_alloc_at: Allocate an MSI vector on demand and return its IRQ 447 * number, updating @msi with the index actually assigned. Buses that 448 * allocate their whole pool up front leave this NULL. 449 * @msix_free: Release a vector obtained from @msix_alloc_at. Only needed 450 * by buses that implement @msix_alloc_at. 451 * @msix_vec_count: Return the number of entries in the device MSI-X table, 452 * used to clamp the vector count the core asks for. Buses that cannot 453 * report a table size leave this NULL and the clamp is skipped. 454 * @setup_hwc_irqs: Set up the interrupts the hardware channel needs before 455 * it is created. 456 * @setup_remaining_irqs: Set up the remaining interrupts once the device 457 * resource limits are known. 458 * @remove_irqs: Release the interrupts set up by @setup_hwc_irqs and 459 * @setup_remaining_irqs. 460 * @dev_reset: Reset the device using the bus-level reset mechanism. 461 * @schedule_serv_work: Queue device servicing or recovery. Buses without 462 * a servicing path leave this NULL. 463 * @drv_cap_flags1: Extra capability bits this transport can honour, OR'ed 464 * into GDMA_DRV_CAP_FLAGS1 when the driver version is negotiated. 465 */ 466 struct gdma_bus_ops { 467 const char *bus_name; 468 const char *adev_prefix; 469 bool (*msix_can_alloc_dyn)(struct gdma_context *gc); 470 int (*msix_virq)(struct gdma_context *gc, int msi); 471 int (*msix_alloc_at)(struct gdma_context *gc, int *msi); 472 void (*msix_free)(struct gdma_context *gc, int msi, int irq); 473 int (*msix_vec_count)(struct gdma_context *gc); 474 int (*setup_hwc_irqs)(struct gdma_context *gc); 475 int (*setup_remaining_irqs)(struct gdma_context *gc); 476 void (*remove_irqs)(struct gdma_context *gc); 477 int (*dev_reset)(struct gdma_context *gc); 478 int (*schedule_serv_work)(struct gdma_context *gc, 479 enum gdma_eqe_type type); 480 u64 drv_cap_flags1; 481 }; 482 483 struct gdma_context { 484 struct device *dev; 485 struct dentry *mana_pci_debugfs; 486 487 /* Transport-specific operations, installed by the bus driver */ 488 const struct gdma_bus_ops *bus_ops; 489 490 /* Hardware max number of queues */ 491 unsigned int max_num_queues; 492 /* Per-vPort max number of queues */ 493 unsigned int max_num_queues_vport; 494 /* Number of vPorts reported by the device, capped at 495 * MAX_PORTS_IN_MANA_DEV 496 */ 497 u16 num_ports; 498 unsigned int max_num_msix; 499 unsigned int num_msix_usable; 500 struct xarray irq_contexts; 501 502 /* L2 MTU */ 503 u16 adapter_mtu; 504 505 /* NIC supports CQE x8 coalescing */ 506 bool cqe8_coalescing_sup; 507 508 /* This maps a CQ index to the queue structure. */ 509 unsigned int max_num_cqs; 510 struct gdma_queue **cq_table; 511 512 /* Protect eq_test_event and test_event_eq_id */ 513 struct mutex eq_test_event_mutex; 514 struct completion eq_test_event; 515 u32 test_event_eq_id; 516 517 bool is_pf; 518 bool is_pf2; 519 520 phys_addr_t bar0_pa; 521 void __iomem *bar0_va; 522 resource_size_t bar0_size; 523 void __iomem *shm_base; 524 void __iomem *db_page_base; 525 phys_addr_t phys_db_page_base; 526 u64 db_page_off; 527 u64 db_page_size; 528 int numa_node; 529 530 /* Shared memory chanenl (used to bootstrap HWC) */ 531 struct shm_channel shm_channel; 532 533 /* Hardware communication channel (HWC) */ 534 struct gdma_dev hwc; 535 536 /* Azure network adapter */ 537 struct gdma_dev mana; 538 539 /* Azure RDMA adapter */ 540 struct gdma_dev mana_ib; 541 542 u64 pf_cap_flags1; 543 u64 gdma_protocol_ver; 544 545 struct workqueue_struct *service_wq; 546 547 unsigned long flags; 548 549 /* Protect access to GIC context */ 550 struct mutex gic_mutex; 551 552 /* Indicate if this device is sharing MSI for EQs on MANA */ 553 bool msi_sharing; 554 555 /* Bitmap tracks where MSI is allocated when it is not shared for EQs */ 556 unsigned long *msi_bitmap; 557 }; 558 559 static inline bool mana_gd_is_mana(struct gdma_dev *gd) 560 { 561 return gd->dev_id.type == GDMA_DEVICE_MANA; 562 } 563 564 static inline bool mana_gd_is_hwc(struct gdma_dev *gd) 565 { 566 return gd->dev_id.type == GDMA_DEVICE_HWC; 567 } 568 569 u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset); 570 u32 mana_gd_wq_avail_space(struct gdma_queue *wq); 571 572 int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq); 573 574 int mana_gd_create_hwc_queue(struct gdma_dev *gd, 575 const struct gdma_queue_spec *spec, 576 struct gdma_queue **queue_ptr); 577 578 int mana_gd_create_mana_eq(struct gdma_dev *gd, 579 const struct gdma_queue_spec *spec, 580 struct gdma_queue **queue_ptr); 581 582 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 583 const struct gdma_queue_spec *spec, 584 struct gdma_queue **queue_ptr); 585 586 void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue); 587 588 int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe); 589 590 void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit); 591 592 ssize_t mana_gd_read_ring(struct gdma_queue *q, char __user *buf, 593 size_t count, loff_t *pos); 594 595 int mana_schedule_serv_work(struct gdma_context *gc, enum gdma_eqe_type type); 596 597 int mana_gd_alloc_service_wq(struct gdma_context *gc); 598 599 void mana_gd_free_service_wq(struct gdma_context *gc); 600 601 void mana_gd_ring_dim(struct gdma_queue *cq, u32 mod_usec, bool mod_usec_vld, 602 u32 mod_comps, bool mod_comps_vld); 603 604 struct gdma_wqe { 605 u32 reserved :24; 606 u32 last_vbytes :8; 607 608 union { 609 u32 flags; 610 611 struct { 612 u32 num_sge :8; 613 u32 inline_oob_size_div4:3; 614 u32 client_oob_in_sgl :1; 615 u32 reserved1 :4; 616 u32 client_data_unit :14; 617 u32 reserved2 :2; 618 }; 619 }; 620 }; /* HW DATA */ 621 622 #define INLINE_OOB_SMALL_SIZE 8 623 #define INLINE_OOB_LARGE_SIZE 24 624 #define INLINE_OOB_EXTRA_LARGE_SIZE 32 625 626 #define MANA_MAX_TX_WQE_SGL_ENTRIES 30 627 628 #define MAX_TX_WQE_SIZE 512 629 #define MAX_RX_WQE_SIZE 256 630 631 #define MAX_TX_WQE_SGL_ENTRIES ((GDMA_MAX_SQE_SIZE - \ 632 sizeof(struct gdma_sge) - INLINE_OOB_SMALL_SIZE) / \ 633 sizeof(struct gdma_sge)) 634 635 #define MAX_RX_WQE_SGL_ENTRIES ((GDMA_MAX_RQE_SIZE - \ 636 sizeof(struct gdma_sge)) / sizeof(struct gdma_sge)) 637 638 struct gdma_cqe { 639 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4]; 640 641 union { 642 u32 as_uint32; 643 644 struct { 645 u32 wq_num : 24; 646 u32 is_sq : 1; 647 u32 reserved : 4; 648 u32 owner_bits : 3; 649 }; 650 } cqe_info; 651 }; /* HW DATA */ 652 653 #define GDMA_CQE_OWNER_BITS 3 654 655 #define GDMA_CQE_OWNER_MASK ((1 << GDMA_CQE_OWNER_BITS) - 1) 656 657 #define SET_ARM_BIT 1 658 659 #define GDMA_EQE_OWNER_BITS 3 660 661 union gdma_eqe_info { 662 u32 as_uint32; 663 664 struct { 665 u32 type : 8; 666 u32 reserved1 : 8; 667 u32 client_id : 2; 668 u32 reserved2 : 11; 669 u32 owner_bits : 3; 670 }; 671 }; /* HW DATA */ 672 673 #define GDMA_EQE_OWNER_MASK ((1 << GDMA_EQE_OWNER_BITS) - 1) 674 #define INITIALIZED_OWNER_BIT(log2_num_entries) (1UL << (log2_num_entries)) 675 676 struct gdma_eqe { 677 u32 details[GDMA_EVENT_DATA_SIZE / 4]; 678 u32 eqe_info; 679 }; /* HW DATA */ 680 681 #define GDMA_REG_DB_PAGE_OFFSET 8 682 #define GDMA_REG_DB_PAGE_SIZE 0x10 683 #define GDMA_REG_SHM_OFFSET 0x18 684 685 #define GDMA_PF_REG_DB_PAGE_SIZE 0xD0 686 #define GDMA_PF_REG_DB_PAGE_OFF 0xC8 687 #define GDMA_PF_REG_SHM_OFF 0x70 688 689 #define GDMA_SRIOV_REG_CFG_BASE_OFF 0x108 690 691 #define MANA_PF_DEVICE_ID 0x00B9 692 #define MANA_PF2_DEVICE_ID 0x00C1 693 #define MANA_VF_DEVICE_ID 0x00BA 694 695 #define MANA_CDX_DEVICE_ID 0x00C2 696 697 struct gdma_posted_wqe_info { 698 u32 wqe_size_in_bu; 699 /* Unmasked WQE start offset in GDMA basic units. */ 700 u32 wqe_offset; 701 }; 702 703 /* GDMA_GENERATE_TEST_EQE */ 704 struct gdma_generate_test_event_req { 705 struct gdma_req_hdr hdr; 706 u32 queue_index; 707 }; /* HW DATA */ 708 709 /* GDMA_VERIFY_VF_DRIVER_VERSION */ 710 enum { 711 GDMA_PROTOCOL_V1 = 1, 712 GDMA_PROTOCOL_FIRST = GDMA_PROTOCOL_V1, 713 GDMA_PROTOCOL_LAST = GDMA_PROTOCOL_V1, 714 }; 715 716 #define GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT BIT(0) 717 718 /* Advertise to the NIC firmware: the NAPI work_done variable race is fixed, 719 * so the driver is able to reliably support features like busy_poll. 720 */ 721 #define GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX BIT(2) 722 #define GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG BIT(3) 723 #define GDMA_DRV_CAP_FLAG_1_GDMA_PAGES_4MB_1GB_2GB BIT(4) 724 #define GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT BIT(5) 725 #define GDMA_DRV_CAP_FLAG_1_HW_VPORT_LINK_AWARE BIT(6) 726 727 /* Driver can handle holes (zeros) in the device list */ 728 #define GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP BIT(11) 729 730 /* Driver supports dynamic MSI-X vector allocation */ 731 #define GDMA_DRV_CAP_FLAG_1_DYNAMIC_IRQ_ALLOC_SUPPORT BIT(13) 732 733 /* Driver can self reset on EQE notification */ 734 #define GDMA_DRV_CAP_FLAG_1_SELF_RESET_ON_EQE BIT(14) 735 736 /* Driver can self reset on FPGA Reconfig EQE notification */ 737 #define GDMA_DRV_CAP_FLAG_1_HANDLE_RECONFIG_EQE BIT(17) 738 739 /* Driver detects stalled send queues and recovers them */ 740 #define GDMA_DRV_CAP_FLAG_1_HANDLE_STALL_SQ_RECOVERY BIT(18) 741 742 /* Driver supports separate EQ/MSIs for each vPort */ 743 #define GDMA_DRV_CAP_FLAG_1_EQ_MSI_UNSHARE_MULTI_VPORT BIT(19) 744 745 /* Driver supports linearizing the skb when num_sge exceeds hardware limit */ 746 #define GDMA_DRV_CAP_FLAG_1_SKB_LINEARIZE BIT(20) 747 748 /* Driver can send HWC periodically to query stats */ 749 #define GDMA_DRV_CAP_FLAG_1_PERIODIC_STATS_QUERY BIT(21) 750 751 /* Driver can handle hardware recovery events during probe */ 752 #define GDMA_DRV_CAP_FLAG_1_PROBE_RECOVERY BIT(22) 753 754 /* Driver supports self recovery on Hardware Channel timeouts */ 755 #define GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECOVERY BIT(25) 756 757 /* Driver supports dynamic interrupt moderation - DIM */ 758 #define GDMA_DRV_CAP_FLAG_1_DYN_INTERRUPT_MODERATION BIT(28) 759 760 /* Driver supports non-contiguous queue buffers */ 761 #define GDMA_DRV_CAP_FLAG_1_NON_CONTIGUOUS_BUFFERS BIT(30) 762 763 /* Capabilities in the PCI-only group below rely on dynamic MSI-X allocation 764 * and on the servicing and reset paths reached through 765 * mana_schedule_serv_work(). Transports that provide neither leave 766 * gdma_bus_ops.drv_cap_flags1 unset so the group is not advertised. 767 */ 768 #define GDMA_DRV_CAP_FLAGS1_PCI \ 769 (GDMA_DRV_CAP_FLAG_1_DYNAMIC_IRQ_ALLOC_SUPPORT | \ 770 GDMA_DRV_CAP_FLAG_1_SELF_RESET_ON_EQE | \ 771 GDMA_DRV_CAP_FLAG_1_HANDLE_RECONFIG_EQE | \ 772 GDMA_DRV_CAP_FLAG_1_PROBE_RECOVERY | \ 773 GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECOVERY) 774 775 #define GDMA_DRV_CAP_FLAGS1 \ 776 (GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT | \ 777 GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX | \ 778 GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG | \ 779 GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT | \ 780 GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP | \ 781 GDMA_DRV_CAP_FLAG_1_HW_VPORT_LINK_AWARE | \ 782 GDMA_DRV_CAP_FLAG_1_PERIODIC_STATS_QUERY | \ 783 GDMA_DRV_CAP_FLAG_1_SKB_LINEARIZE | \ 784 GDMA_DRV_CAP_FLAG_1_HANDLE_STALL_SQ_RECOVERY | \ 785 GDMA_DRV_CAP_FLAG_1_EQ_MSI_UNSHARE_MULTI_VPORT | \ 786 GDMA_DRV_CAP_FLAG_1_DYN_INTERRUPT_MODERATION | \ 787 GDMA_DRV_CAP_FLAG_1_NON_CONTIGUOUS_BUFFERS) 788 789 #define GDMA_DRV_CAP_FLAGS2 0 790 791 #define GDMA_DRV_CAP_FLAGS3 0 792 793 #define GDMA_DRV_CAP_FLAGS4 0 794 795 struct gdma_verify_ver_req { 796 struct gdma_req_hdr hdr; 797 798 /* Mandatory fields required for protocol establishment */ 799 u64 protocol_ver_min; 800 u64 protocol_ver_max; 801 802 /* Gdma Driver Capability Flags */ 803 u64 gd_drv_cap_flags1; 804 u64 gd_drv_cap_flags2; 805 u64 gd_drv_cap_flags3; 806 u64 gd_drv_cap_flags4; 807 808 /* Advisory fields */ 809 u64 drv_ver; 810 u32 os_type; /* Linux = 0x10; Windows = 0x20; Other = 0x30 */ 811 u32 reserved; 812 u32 os_ver_major; 813 u32 os_ver_minor; 814 u32 os_ver_build; 815 u32 os_ver_platform; 816 u64 reserved_2; 817 u8 os_ver_str1[128]; 818 u8 os_ver_str2[128]; 819 u8 os_ver_str3[128]; 820 u8 os_ver_str4[128]; 821 }; /* HW DATA */ 822 823 /* HW supports dynamic interrupt moderation - DIM */ 824 #define GDMA_PF_CAP_FLAG_1_DYN_INTERRUPT_MODERATION BIT(15) 825 826 struct gdma_verify_ver_resp { 827 struct gdma_resp_hdr hdr; 828 u64 gdma_protocol_ver; 829 u64 pf_cap_flags1; 830 u64 pf_cap_flags2; 831 u64 pf_cap_flags3; 832 u64 pf_cap_flags4; 833 }; /* HW DATA */ 834 835 /* GDMA_QUERY_MAX_RESOURCES */ 836 struct gdma_query_max_resources_resp { 837 struct gdma_resp_hdr hdr; 838 u32 status; 839 u32 max_sq; 840 u32 max_rq; 841 u32 max_cq; 842 u32 max_eq; 843 u32 max_db; 844 u32 max_mst; 845 u32 max_cq_mod_ctx; 846 u32 max_mod_cq; 847 u32 max_msix; 848 }; /* HW DATA */ 849 850 /* GDMA_LIST_DEVICES */ 851 #define GDMA_DEV_LIST_SIZE 64 852 struct gdma_list_devices_resp { 853 struct gdma_resp_hdr hdr; 854 u32 num_of_devs; 855 u32 reserved; 856 struct gdma_dev_id devs[GDMA_DEV_LIST_SIZE]; 857 }; /* HW DATA */ 858 859 /* GDMA_REGISTER_DEVICE */ 860 struct gdma_register_device_resp { 861 struct gdma_resp_hdr hdr; 862 u32 pdid; 863 u32 gpa_mkey; 864 u32 db_id; 865 }; /* HW DATA */ 866 867 struct gdma_allocate_resource_range_req { 868 struct gdma_req_hdr hdr; 869 u32 resource_type; 870 u32 num_resources; 871 u32 alignment; 872 u32 allocated_resources; 873 }; 874 875 struct gdma_allocate_resource_range_resp { 876 struct gdma_resp_hdr hdr; 877 u32 allocated_resources; 878 }; 879 880 struct gdma_destroy_resource_range_req { 881 struct gdma_req_hdr hdr; 882 u32 resource_type; 883 u32 num_resources; 884 u32 allocated_resources; 885 }; 886 887 /* GDMA_CREATE_QUEUE */ 888 struct gdma_create_queue_req { 889 struct gdma_req_hdr hdr; 890 u32 type; 891 u32 reserved1; 892 u32 pdid; 893 u32 doolbell_id; 894 u64 gdma_region; 895 u32 reserved2; 896 u32 queue_size; 897 u32 log2_throttle_limit; 898 u32 eq_pci_msix_index; 899 u32 cq_mod_ctx_id; 900 u32 cq_parent_eq_id; 901 u8 rq_drop_on_overrun; 902 u8 rq_err_on_wqe_overflow; 903 u8 rq_chain_rec_wqes; 904 u8 sq_hw_db; 905 u32 reserved3; 906 }; /* HW DATA */ 907 908 struct gdma_create_queue_resp { 909 struct gdma_resp_hdr hdr; 910 u32 queue_index; 911 }; /* HW DATA */ 912 913 /* GDMA_DISABLE_QUEUE */ 914 struct gdma_disable_queue_req { 915 struct gdma_req_hdr hdr; 916 u32 type; 917 u32 queue_index; 918 u32 alloc_res_id_on_creation; 919 }; /* HW DATA */ 920 921 /* GDMA_QUERY_HWC_TIMEOUT */ 922 struct gdma_query_hwc_timeout_req { 923 struct gdma_req_hdr hdr; 924 u32 timeout_ms; 925 u32 reserved; 926 }; 927 928 struct gdma_query_hwc_timeout_resp { 929 struct gdma_resp_hdr hdr; 930 u32 timeout_ms; 931 u32 reserved; 932 }; 933 934 enum gdma_mr_access_flags { 935 GDMA_ACCESS_FLAG_LOCAL_READ = BIT_ULL(0), 936 GDMA_ACCESS_FLAG_LOCAL_WRITE = BIT_ULL(1), 937 GDMA_ACCESS_FLAG_REMOTE_READ = BIT_ULL(2), 938 GDMA_ACCESS_FLAG_REMOTE_WRITE = BIT_ULL(3), 939 GDMA_ACCESS_FLAG_REMOTE_ATOMIC = BIT_ULL(4), 940 GDMA_ACCESS_FLAG_BIND_MW = BIT_ULL(5), 941 }; 942 943 /* GDMA_CREATE_DMA_REGION */ 944 struct gdma_create_dma_region_req { 945 struct gdma_req_hdr hdr; 946 947 /* The total size of the DMA region */ 948 u64 length; 949 950 /* The offset in the first page */ 951 u32 offset_in_page; 952 953 /* enum gdma_page_type */ 954 u32 gdma_page_type; 955 956 /* The total number of pages */ 957 u32 page_count; 958 959 /* If page_addr_list_len is smaller than page_count, 960 * the remaining page addresses will be added via the 961 * message GDMA_DMA_REGION_ADD_PAGES. 962 */ 963 u32 page_addr_list_len; 964 u64 page_addr_list[]; 965 }; /* HW DATA */ 966 967 struct gdma_create_dma_region_resp { 968 struct gdma_resp_hdr hdr; 969 u64 dma_region_handle; 970 }; /* HW DATA */ 971 972 /* GDMA_DMA_REGION_ADD_PAGES */ 973 struct gdma_dma_region_add_pages_req { 974 struct gdma_req_hdr hdr; 975 976 u64 dma_region_handle; 977 978 u32 page_addr_list_len; 979 u32 reserved3; 980 981 u64 page_addr_list[]; 982 }; /* HW DATA */ 983 984 /* GDMA_DESTROY_DMA_REGION */ 985 struct gdma_destroy_dma_region_req { 986 struct gdma_req_hdr hdr; 987 988 u64 dma_region_handle; 989 }; /* HW DATA */ 990 991 enum gdma_pd_flags { 992 GDMA_PD_FLAG_ALLOW_GPA_MR = BIT(0), 993 GDMA_PD_FLAG_SHORT_PDN = BIT(2), 994 }; 995 996 struct gdma_create_pd_req { 997 struct gdma_req_hdr hdr; 998 enum gdma_pd_flags flags; 999 u32 reserved; 1000 };/* HW DATA */ 1001 1002 struct gdma_create_pd_resp { 1003 struct gdma_resp_hdr hdr; 1004 u64 pd_handle; 1005 u32 pd_id; 1006 u32 reserved; 1007 };/* HW DATA */ 1008 1009 struct gdma_destroy_pd_req { 1010 struct gdma_req_hdr hdr; 1011 u64 pd_handle; 1012 };/* HW DATA */ 1013 1014 struct gdma_destroy_pd_resp { 1015 struct gdma_resp_hdr hdr; 1016 };/* HW DATA */ 1017 1018 enum gdma_mr_type { 1019 /* 1020 * Guest Physical Address - MRs of this type allow access 1021 * to any DMA-mapped memory using bus-logical address 1022 */ 1023 GDMA_MR_TYPE_GPA = 1, 1024 /* Guest Virtual Address - MRs of this type allow access 1025 * to memory mapped by PTEs associated with this MR using a virtual 1026 * address that is set up in the MST 1027 */ 1028 GDMA_MR_TYPE_GVA = 2, 1029 /* Guest zero-based address MRs */ 1030 GDMA_MR_TYPE_ZBVA = 4, 1031 /* Device address MRs */ 1032 GDMA_MR_TYPE_DM = 5, 1033 /* Memory Window type 1 */ 1034 GDMA_MR_TYPE_MW1 = 6, 1035 /* Memory Window type 2 */ 1036 GDMA_MR_TYPE_MW2 = 7, 1037 }; 1038 1039 struct gdma_create_mr_params { 1040 u64 pd_handle; 1041 enum gdma_mr_type mr_type; 1042 union { 1043 struct { 1044 u64 dma_region_handle; 1045 u64 virtual_address; 1046 enum gdma_mr_access_flags access_flags; 1047 } gva; 1048 struct { 1049 u64 dma_region_handle; 1050 enum gdma_mr_access_flags access_flags; 1051 } zbva; 1052 struct { 1053 u64 dm_handle; 1054 u64 offset; 1055 u64 length; 1056 enum gdma_mr_access_flags access_flags; 1057 } da; 1058 }; 1059 }; 1060 1061 struct gdma_create_mr_request { 1062 struct gdma_req_hdr hdr; 1063 u64 pd_handle; 1064 enum gdma_mr_type mr_type; 1065 u32 reserved_1; 1066 1067 union { 1068 struct { 1069 u64 dma_region_handle; 1070 u64 virtual_address; 1071 enum gdma_mr_access_flags access_flags; 1072 } __packed gva; 1073 struct { 1074 u64 dma_region_handle; 1075 enum gdma_mr_access_flags access_flags; 1076 } __packed zbva; 1077 struct { 1078 u64 dm_handle; 1079 u64 offset; 1080 enum gdma_mr_access_flags access_flags; 1081 } __packed da; 1082 } __packed; 1083 u32 reserved_2; 1084 union { 1085 struct { 1086 u64 length; 1087 } da_ext; 1088 }; 1089 };/* HW DATA */ 1090 1091 struct gdma_create_mr_response { 1092 struct gdma_resp_hdr hdr; 1093 u64 mr_handle; 1094 u32 lkey; 1095 u32 rkey; 1096 };/* HW DATA */ 1097 1098 struct gdma_destroy_mr_request { 1099 struct gdma_req_hdr hdr; 1100 u64 mr_handle; 1101 };/* HW DATA */ 1102 1103 struct gdma_destroy_mr_response { 1104 struct gdma_resp_hdr hdr; 1105 };/* HW DATA */ 1106 1107 struct gdma_alloc_dm_req { 1108 struct gdma_req_hdr hdr; 1109 u64 length; 1110 u32 alignment; 1111 u32 flags; 1112 }; /* HW Data */ 1113 1114 struct gdma_alloc_dm_resp { 1115 struct gdma_resp_hdr hdr; 1116 u64 dm_handle; 1117 }; /* HW Data */ 1118 1119 struct gdma_destroy_dm_req { 1120 struct gdma_req_hdr hdr; 1121 u64 dm_handle; 1122 }; /* HW Data */ 1123 1124 struct gdma_destroy_dm_resp { 1125 struct gdma_resp_hdr hdr; 1126 }; /* HW Data */ 1127 1128 int mana_gd_verify_vf_version(struct gdma_context *gc); 1129 int mana_gd_query_max_resources(struct gdma_context *gc); 1130 int mana_gd_setup(struct gdma_context *gc); 1131 void mana_gd_cleanup(struct gdma_context *gc); 1132 int mana_gd_detect_devices(struct gdma_context *gc); 1133 int mana_gd_init_registers(struct gdma_context *gc); 1134 irqreturn_t mana_gd_intr(int irq, void *arg); 1135 void mana_gd_process_eq_events(void *arg); 1136 1137 static inline u32 mana_gd_r32(struct gdma_context *g, u64 offset) 1138 { 1139 return readl(g->bar0_va + offset); 1140 } 1141 1142 static inline u64 mana_gd_r64(struct gdma_context *g, u64 offset) 1143 { 1144 return readq(g->bar0_va + offset); 1145 } 1146 1147 int mana_gd_register_device(struct gdma_dev *gd); 1148 int mana_gd_deregister_device(struct gdma_dev *gd); 1149 1150 int mana_gd_post_work_request(struct gdma_queue *wq, 1151 const struct gdma_wqe_request *wqe_req, 1152 struct gdma_posted_wqe_info *wqe_info); 1153 1154 int mana_gd_post_and_ring(struct gdma_queue *queue, 1155 const struct gdma_wqe_request *wqe, 1156 struct gdma_posted_wqe_info *wqe_info); 1157 1158 int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r); 1159 void mana_gd_free_res_map(struct gdma_resource *r); 1160 1161 void mana_gd_wq_ring_doorbell(struct gdma_context *gc, 1162 struct gdma_queue *queue); 1163 void mana_gd_wq_ring_doorbell_ext(struct gdma_context *gc, struct gdma_queue *queue, 1164 u32 tail_ptr, u8 wqe_cnt, u8 client_offset); 1165 1166 int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 1167 struct gdma_mem_info *gmi, bool allow_scatter); 1168 1169 void mana_gd_free_memory(struct gdma_mem_info *gmi); 1170 1171 int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req, 1172 u32 resp_len, void *resp); 1173 1174 int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle); 1175 void mana_register_debugfs(void); 1176 void mana_unregister_debugfs(void); 1177 1178 int mana_rdma_service_event(struct gdma_context *gc, enum gdma_service_type event); 1179 1180 1181 bool mana_need_log(struct gdma_context *gc, int err); 1182 1183 struct gdma_irq_context *mana_gd_get_gic(struct gdma_context *gc, 1184 bool use_msi_bitmap, 1185 int *msi_requested); 1186 void mana_gd_put_gic(struct gdma_context *gc, bool use_msi_bitmap, int msi); 1187 int mana_gd_query_device_cfg(struct gdma_context *gc, u32 proto_major_ver, 1188 u32 proto_minor_ver, u32 proto_micro_ver, 1189 u16 *max_num_vports, u8 *bm_hostmode); 1190 int mana_gd_dev_reset(struct gdma_context *gc); 1191 1192 #endif /* _GDMA_H */ 1193