1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #ifndef _GDMA_H 5 #define _GDMA_H 6 7 #include <linux/dma-mapping.h> 8 #include <linux/netdevice.h> 9 10 #include "shm_channel.h" 11 12 #define GDMA_STATUS_MORE_ENTRIES 0x00000105 13 #define GDMA_STATUS_CMD_UNSUPPORTED 0xffffffff 14 15 /* Structures labeled with "HW DATA" are exchanged with the hardware. All of 16 * them are naturally aligned and hence don't need __packed. 17 */ 18 19 enum gdma_request_type { 20 GDMA_VERIFY_VF_DRIVER_VERSION = 1, 21 GDMA_QUERY_MAX_RESOURCES = 2, 22 GDMA_LIST_DEVICES = 3, 23 GDMA_REGISTER_DEVICE = 4, 24 GDMA_DEREGISTER_DEVICE = 5, 25 GDMA_GENERATE_TEST_EQE = 10, 26 GDMA_CREATE_QUEUE = 12, 27 GDMA_DISABLE_QUEUE = 13, 28 GDMA_ALLOCATE_RESOURCE_RANGE = 22, 29 GDMA_DESTROY_RESOURCE_RANGE = 24, 30 GDMA_CREATE_DMA_REGION = 25, 31 GDMA_DMA_REGION_ADD_PAGES = 26, 32 GDMA_DESTROY_DMA_REGION = 27, 33 GDMA_CREATE_PD = 29, 34 GDMA_DESTROY_PD = 30, 35 GDMA_CREATE_MR = 31, 36 GDMA_DESTROY_MR = 32, 37 GDMA_QUERY_HWC_TIMEOUT = 84, /* 0x54 */ 38 GDMA_ALLOC_DM = 96, /* 0x60 */ 39 GDMA_DESTROY_DM = 97, /* 0x61 */ 40 }; 41 42 #define GDMA_RESOURCE_DOORBELL_PAGE 27 43 44 enum gdma_queue_type { 45 GDMA_INVALID_QUEUE, 46 GDMA_SQ, 47 GDMA_RQ, 48 GDMA_CQ, 49 GDMA_EQ, 50 }; 51 52 enum gdma_work_request_flags { 53 GDMA_WR_NONE = 0, 54 GDMA_WR_OOB_IN_SGL = BIT(0), 55 GDMA_WR_PAD_BY_SGE0 = BIT(1), 56 }; 57 58 enum gdma_eqe_type { 59 GDMA_EQE_COMPLETION = 3, 60 GDMA_EQE_TEST_EVENT = 64, 61 GDMA_EQE_HWC_INIT_EQ_ID_DB = 129, 62 GDMA_EQE_HWC_INIT_DATA = 130, 63 GDMA_EQE_HWC_INIT_DONE = 131, 64 GDMA_EQE_HWC_FPGA_RECONFIG = 132, 65 GDMA_EQE_HWC_SOC_RECONFIG_DATA = 133, 66 GDMA_EQE_HWC_SOC_SERVICE = 134, 67 GDMA_EQE_HWC_RESET_REQUEST = 135, 68 GDMA_EQE_RNIC_QP_FATAL = 176, 69 }; 70 71 enum { 72 GDMA_DEVICE_NONE = 0, 73 GDMA_DEVICE_HWC = 1, 74 GDMA_DEVICE_MANA = 2, 75 GDMA_DEVICE_MANA_IB = 3, 76 }; 77 78 enum gdma_service_type { 79 GDMA_SERVICE_TYPE_NONE = 0, 80 GDMA_SERVICE_TYPE_RDMA_SUSPEND = 1, 81 GDMA_SERVICE_TYPE_RDMA_RESUME = 2, 82 }; 83 84 struct mana_service_work { 85 struct work_struct work; 86 struct gdma_dev *gdma_dev; 87 enum gdma_service_type event; 88 }; 89 90 struct gdma_resource { 91 /* Protect the bitmap */ 92 spinlock_t lock; 93 94 /* The bitmap size in bits. */ 95 u32 size; 96 97 /* The bitmap tracks the resources. */ 98 unsigned long *map; 99 }; 100 101 union gdma_doorbell_entry { 102 u64 as_uint64; 103 104 struct { 105 u64 id : 24; 106 u64 reserved : 8; 107 u64 tail_ptr : 31; 108 u64 arm : 1; 109 } cq; 110 111 struct { 112 u64 id : 24; 113 u64 wqe_cnt : 8; 114 u64 tail_ptr : 32; 115 } rq; 116 117 struct { 118 u64 id : 24; 119 u64 reserved : 8; 120 u64 tail_ptr : 32; 121 } sq; 122 123 struct { 124 u64 id : 16; 125 u64 reserved : 16; 126 u64 tail_ptr : 31; 127 u64 arm : 1; 128 } eq; 129 }; /* HW DATA */ 130 131 struct gdma_msg_hdr { 132 u32 hdr_type; 133 u32 msg_type; 134 u16 msg_version; 135 u16 hwc_msg_id; 136 u32 msg_size; 137 }; /* HW DATA */ 138 139 struct gdma_dev_id { 140 union { 141 struct { 142 u16 type; 143 u16 instance; 144 }; 145 146 u32 as_uint32; 147 }; 148 }; /* HW DATA */ 149 150 struct gdma_req_hdr { 151 struct gdma_msg_hdr req; 152 struct gdma_msg_hdr resp; /* The expected response */ 153 struct gdma_dev_id dev_id; 154 u32 activity_id; 155 }; /* HW DATA */ 156 157 struct gdma_resp_hdr { 158 struct gdma_msg_hdr response; 159 struct gdma_dev_id dev_id; 160 u32 activity_id; 161 u32 status; 162 u32 reserved; 163 }; /* HW DATA */ 164 165 struct gdma_general_req { 166 struct gdma_req_hdr hdr; 167 }; /* HW DATA */ 168 169 #define GDMA_MESSAGE_V1 1 170 #define GDMA_MESSAGE_V2 2 171 #define GDMA_MESSAGE_V3 3 172 #define GDMA_MESSAGE_V4 4 173 174 struct gdma_general_resp { 175 struct gdma_resp_hdr hdr; 176 }; /* HW DATA */ 177 178 #define GDMA_STANDARD_HEADER_TYPE 0 179 180 static inline void mana_gd_init_req_hdr(struct gdma_req_hdr *hdr, u32 code, 181 u32 req_size, u32 resp_size) 182 { 183 hdr->req.hdr_type = GDMA_STANDARD_HEADER_TYPE; 184 hdr->req.msg_type = code; 185 hdr->req.msg_version = GDMA_MESSAGE_V1; 186 hdr->req.msg_size = req_size; 187 188 hdr->resp.hdr_type = GDMA_STANDARD_HEADER_TYPE; 189 hdr->resp.msg_type = code; 190 hdr->resp.msg_version = GDMA_MESSAGE_V1; 191 hdr->resp.msg_size = resp_size; 192 } 193 194 /* The 16-byte struct is part of the GDMA work queue entry (WQE). */ 195 struct gdma_sge { 196 u64 address; 197 u32 mem_key; 198 u32 size; 199 }; /* HW DATA */ 200 201 struct gdma_wqe_request { 202 struct gdma_sge *sgl; 203 u32 num_sge; 204 205 u32 inline_oob_size; 206 const void *inline_oob_data; 207 208 u32 flags; 209 u32 client_data_unit; 210 }; 211 212 enum gdma_page_type { 213 GDMA_PAGE_TYPE_4K, 214 }; 215 216 #define GDMA_INVALID_DMA_REGION 0 217 218 struct mana_serv_work { 219 struct work_struct serv_work; 220 struct pci_dev *pdev; 221 enum gdma_eqe_type type; 222 }; 223 224 struct gdma_mem_info { 225 struct device *dev; 226 227 dma_addr_t dma_handle; 228 void *virt_addr; 229 u64 length; 230 231 /* Allocated by the PF driver */ 232 u64 dma_region_handle; 233 }; 234 235 #define REGISTER_ATB_MST_MKEY_LOWER_SIZE 8 236 237 struct gdma_dev { 238 struct gdma_context *gdma_context; 239 240 struct gdma_dev_id dev_id; 241 242 u32 pdid; 243 u32 doorbell; 244 u32 gpa_mkey; 245 246 /* GDMA driver specific pointer */ 247 void *driver_data; 248 249 struct auxiliary_device *adev; 250 bool is_suspended; 251 bool rdma_teardown; 252 }; 253 254 /* MANA_PAGE_SIZE is the DMA unit */ 255 #define MANA_PAGE_SHIFT 12 256 #define MANA_PAGE_SIZE BIT(MANA_PAGE_SHIFT) 257 #define MANA_PAGE_ALIGN(x) ALIGN((x), MANA_PAGE_SIZE) 258 #define MANA_PAGE_ALIGNED(addr) IS_ALIGNED((unsigned long)(addr), MANA_PAGE_SIZE) 259 #define MANA_PFN(a) ((a) >> MANA_PAGE_SHIFT) 260 261 /* Required by HW */ 262 #define MANA_MIN_QSIZE MANA_PAGE_SIZE 263 264 #define GDMA_CQE_SIZE 64 265 #define GDMA_EQE_SIZE 16 266 #define GDMA_MAX_SQE_SIZE 512 267 #define GDMA_MAX_RQE_SIZE 256 268 269 #define GDMA_COMP_DATA_SIZE 0x3C 270 271 #define GDMA_EVENT_DATA_SIZE 0xC 272 273 /* The WQE size must be a multiple of the Basic Unit, which is 32 bytes. */ 274 #define GDMA_WQE_BU_SIZE 32 275 276 #define INVALID_PDID UINT_MAX 277 #define INVALID_DOORBELL UINT_MAX 278 #define INVALID_MEM_KEY UINT_MAX 279 #define INVALID_QUEUE_ID UINT_MAX 280 #define INVALID_PCI_MSIX_INDEX UINT_MAX 281 282 struct gdma_comp { 283 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4]; 284 u32 wq_num; 285 bool is_sq; 286 }; 287 288 struct gdma_event { 289 u32 details[GDMA_EVENT_DATA_SIZE / 4]; 290 u8 type; 291 }; 292 293 struct gdma_queue; 294 295 struct mana_eq { 296 struct gdma_queue *eq; 297 struct dentry *mana_eq_debugfs; 298 }; 299 300 typedef void gdma_eq_callback(void *context, struct gdma_queue *q, 301 struct gdma_event *e); 302 303 typedef void gdma_cq_callback(void *context, struct gdma_queue *q); 304 305 /* The 'head' is the producer index. For SQ/RQ, when the driver posts a WQE 306 * (Note: the WQE size must be a multiple of the 32-byte Basic Unit), the 307 * driver increases the 'head' in BUs rather than in bytes, and notifies 308 * the HW of the updated head. For EQ/CQ, the driver uses the 'head' to track 309 * the HW head, and increases the 'head' by 1 for every processed EQE/CQE. 310 * 311 * The 'tail' is the consumer index for SQ/RQ. After the CQE of the SQ/RQ is 312 * processed, the driver increases the 'tail' to indicate that WQEs have 313 * been consumed by the HW, so the driver can post new WQEs into the SQ/RQ. 314 * 315 * The driver doesn't use the 'tail' for EQ/CQ, because the driver ensures 316 * that the EQ/CQ is big enough so they can't overflow, and the driver uses 317 * the owner bits mechanism to detect if the queue has become empty. 318 */ 319 struct gdma_queue { 320 struct gdma_dev *gdma_dev; 321 322 enum gdma_queue_type type; 323 u32 id; 324 325 struct gdma_mem_info mem_info; 326 327 void *queue_mem_ptr; 328 u32 queue_size; 329 330 bool monitor_avl_buf; 331 332 u32 head; 333 u32 tail; 334 struct list_head entry; 335 336 /* Extra fields specific to EQ/CQ. */ 337 union { 338 struct { 339 bool disable_needed; 340 341 gdma_eq_callback *callback; 342 void *context; 343 344 unsigned int msix_index; 345 unsigned int irq; 346 347 u32 log2_throttle_limit; 348 } eq; 349 350 struct { 351 gdma_cq_callback *callback; 352 void *context; 353 354 struct gdma_queue *parent; /* For CQ/EQ relationship */ 355 } cq; 356 }; 357 }; 358 359 struct gdma_queue_spec { 360 enum gdma_queue_type type; 361 bool monitor_avl_buf; 362 unsigned int queue_size; 363 364 /* Extra fields specific to EQ/CQ. */ 365 union { 366 struct { 367 gdma_eq_callback *callback; 368 void *context; 369 370 unsigned long log2_throttle_limit; 371 unsigned int msix_index; 372 } eq; 373 374 struct { 375 gdma_cq_callback *callback; 376 void *context; 377 378 struct gdma_queue *parent_eq; 379 380 } cq; 381 }; 382 }; 383 384 #define MANA_IRQ_NAME_SZ 32 385 386 struct gdma_irq_context { 387 void (*handler)(void *arg); 388 /* Protect the eq_list */ 389 spinlock_t lock; 390 struct list_head eq_list; 391 char name[MANA_IRQ_NAME_SZ]; 392 unsigned int msi; 393 unsigned int irq; 394 refcount_t refcount; 395 unsigned int bitmap_refs; 396 bool dyn_msix; 397 }; 398 399 enum gdma_context_flags { 400 GC_PROBE_SUCCEEDED = 0, 401 GC_IN_SERVICE = 1, 402 }; 403 404 struct gdma_context { 405 struct device *dev; 406 struct dentry *mana_pci_debugfs; 407 408 /* Hardware max number of queues */ 409 unsigned int max_num_queues; 410 /* Per-vPort max number of queues */ 411 unsigned int max_num_queues_vport; 412 unsigned int max_num_msix; 413 unsigned int num_msix_usable; 414 struct xarray irq_contexts; 415 416 /* L2 MTU */ 417 u16 adapter_mtu; 418 419 /* This maps a CQ index to the queue structure. */ 420 unsigned int max_num_cqs; 421 struct gdma_queue **cq_table; 422 423 /* Protect eq_test_event and test_event_eq_id */ 424 struct mutex eq_test_event_mutex; 425 struct completion eq_test_event; 426 u32 test_event_eq_id; 427 428 bool is_pf; 429 bool is_pf2; 430 431 phys_addr_t bar0_pa; 432 void __iomem *bar0_va; 433 resource_size_t bar0_size; 434 void __iomem *shm_base; 435 void __iomem *db_page_base; 436 phys_addr_t phys_db_page_base; 437 u64 db_page_off; 438 u64 db_page_size; 439 int numa_node; 440 441 /* Shared memory chanenl (used to bootstrap HWC) */ 442 struct shm_channel shm_channel; 443 444 /* Hardware communication channel (HWC) */ 445 struct gdma_dev hwc; 446 447 /* Azure network adapter */ 448 struct gdma_dev mana; 449 450 /* Azure RDMA adapter */ 451 struct gdma_dev mana_ib; 452 453 u64 pf_cap_flags1; 454 u64 gdma_protocol_ver; 455 456 struct workqueue_struct *service_wq; 457 458 unsigned long flags; 459 460 /* Protect access to GIC context */ 461 struct mutex gic_mutex; 462 463 /* Indicate if this device is sharing MSI for EQs on MANA */ 464 bool msi_sharing; 465 466 /* Bitmap tracks where MSI is allocated when it is not shared for EQs */ 467 unsigned long *msi_bitmap; 468 }; 469 470 static inline bool mana_gd_is_mana(struct gdma_dev *gd) 471 { 472 return gd->dev_id.type == GDMA_DEVICE_MANA; 473 } 474 475 static inline bool mana_gd_is_hwc(struct gdma_dev *gd) 476 { 477 return gd->dev_id.type == GDMA_DEVICE_HWC; 478 } 479 480 u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset); 481 u32 mana_gd_wq_avail_space(struct gdma_queue *wq); 482 483 int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq); 484 485 int mana_gd_create_hwc_queue(struct gdma_dev *gd, 486 const struct gdma_queue_spec *spec, 487 struct gdma_queue **queue_ptr); 488 489 int mana_gd_create_mana_eq(struct gdma_dev *gd, 490 const struct gdma_queue_spec *spec, 491 struct gdma_queue **queue_ptr); 492 493 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 494 const struct gdma_queue_spec *spec, 495 struct gdma_queue **queue_ptr); 496 497 void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue); 498 499 int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe); 500 501 void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit); 502 503 int mana_schedule_serv_work(struct gdma_context *gc, enum gdma_eqe_type type); 504 505 struct gdma_wqe { 506 u32 reserved :24; 507 u32 last_vbytes :8; 508 509 union { 510 u32 flags; 511 512 struct { 513 u32 num_sge :8; 514 u32 inline_oob_size_div4:3; 515 u32 client_oob_in_sgl :1; 516 u32 reserved1 :4; 517 u32 client_data_unit :14; 518 u32 reserved2 :2; 519 }; 520 }; 521 }; /* HW DATA */ 522 523 #define INLINE_OOB_SMALL_SIZE 8 524 #define INLINE_OOB_LARGE_SIZE 24 525 526 #define MANA_MAX_TX_WQE_SGL_ENTRIES 30 527 528 #define MAX_TX_WQE_SIZE 512 529 #define MAX_RX_WQE_SIZE 256 530 531 #define MAX_TX_WQE_SGL_ENTRIES ((GDMA_MAX_SQE_SIZE - \ 532 sizeof(struct gdma_sge) - INLINE_OOB_SMALL_SIZE) / \ 533 sizeof(struct gdma_sge)) 534 535 #define MAX_RX_WQE_SGL_ENTRIES ((GDMA_MAX_RQE_SIZE - \ 536 sizeof(struct gdma_sge)) / sizeof(struct gdma_sge)) 537 538 struct gdma_cqe { 539 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4]; 540 541 union { 542 u32 as_uint32; 543 544 struct { 545 u32 wq_num : 24; 546 u32 is_sq : 1; 547 u32 reserved : 4; 548 u32 owner_bits : 3; 549 }; 550 } cqe_info; 551 }; /* HW DATA */ 552 553 #define GDMA_CQE_OWNER_BITS 3 554 555 #define GDMA_CQE_OWNER_MASK ((1 << GDMA_CQE_OWNER_BITS) - 1) 556 557 #define SET_ARM_BIT 1 558 559 #define GDMA_EQE_OWNER_BITS 3 560 561 union gdma_eqe_info { 562 u32 as_uint32; 563 564 struct { 565 u32 type : 8; 566 u32 reserved1 : 8; 567 u32 client_id : 2; 568 u32 reserved2 : 11; 569 u32 owner_bits : 3; 570 }; 571 }; /* HW DATA */ 572 573 #define GDMA_EQE_OWNER_MASK ((1 << GDMA_EQE_OWNER_BITS) - 1) 574 #define INITIALIZED_OWNER_BIT(log2_num_entries) (1UL << (log2_num_entries)) 575 576 struct gdma_eqe { 577 u32 details[GDMA_EVENT_DATA_SIZE / 4]; 578 u32 eqe_info; 579 }; /* HW DATA */ 580 581 #define GDMA_REG_DB_PAGE_OFFSET 8 582 #define GDMA_REG_DB_PAGE_SIZE 0x10 583 #define GDMA_REG_SHM_OFFSET 0x18 584 585 #define GDMA_PF_REG_DB_PAGE_SIZE 0xD0 586 #define GDMA_PF_REG_DB_PAGE_OFF 0xC8 587 #define GDMA_PF_REG_SHM_OFF 0x70 588 589 #define GDMA_SRIOV_REG_CFG_BASE_OFF 0x108 590 591 #define MANA_PF_DEVICE_ID 0x00B9 592 #define MANA_PF2_DEVICE_ID 0x00C1 593 #define MANA_VF_DEVICE_ID 0x00BA 594 595 struct gdma_posted_wqe_info { 596 u32 wqe_size_in_bu; 597 }; 598 599 /* GDMA_GENERATE_TEST_EQE */ 600 struct gdma_generate_test_event_req { 601 struct gdma_req_hdr hdr; 602 u32 queue_index; 603 }; /* HW DATA */ 604 605 /* GDMA_VERIFY_VF_DRIVER_VERSION */ 606 enum { 607 GDMA_PROTOCOL_V1 = 1, 608 GDMA_PROTOCOL_FIRST = GDMA_PROTOCOL_V1, 609 GDMA_PROTOCOL_LAST = GDMA_PROTOCOL_V1, 610 }; 611 612 #define GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT BIT(0) 613 614 /* Advertise to the NIC firmware: the NAPI work_done variable race is fixed, 615 * so the driver is able to reliably support features like busy_poll. 616 */ 617 #define GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX BIT(2) 618 #define GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG BIT(3) 619 #define GDMA_DRV_CAP_FLAG_1_GDMA_PAGES_4MB_1GB_2GB BIT(4) 620 #define GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT BIT(5) 621 #define GDMA_DRV_CAP_FLAG_1_HW_VPORT_LINK_AWARE BIT(6) 622 623 /* Driver can handle holes (zeros) in the device list */ 624 #define GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP BIT(11) 625 626 /* Driver supports dynamic MSI-X vector allocation */ 627 #define GDMA_DRV_CAP_FLAG_1_DYNAMIC_IRQ_ALLOC_SUPPORT BIT(13) 628 629 /* Driver can self reset on EQE notification */ 630 #define GDMA_DRV_CAP_FLAG_1_SELF_RESET_ON_EQE BIT(14) 631 632 /* Driver can self reset on FPGA Reconfig EQE notification */ 633 #define GDMA_DRV_CAP_FLAG_1_HANDLE_RECONFIG_EQE BIT(17) 634 635 /* Driver detects stalled send queues and recovers them */ 636 #define GDMA_DRV_CAP_FLAG_1_HANDLE_STALL_SQ_RECOVERY BIT(18) 637 638 /* Driver supports separate EQ/MSIs for each vPort */ 639 #define GDMA_DRV_CAP_FLAG_1_EQ_MSI_UNSHARE_MULTI_VPORT BIT(19) 640 641 /* Driver supports linearizing the skb when num_sge exceeds hardware limit */ 642 #define GDMA_DRV_CAP_FLAG_1_SKB_LINEARIZE BIT(20) 643 644 /* Driver can send HWC periodically to query stats */ 645 #define GDMA_DRV_CAP_FLAG_1_PERIODIC_STATS_QUERY BIT(21) 646 647 /* Driver can handle hardware recovery events during probe */ 648 #define GDMA_DRV_CAP_FLAG_1_PROBE_RECOVERY BIT(22) 649 650 /* Driver supports self recovery on Hardware Channel timeouts */ 651 #define GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECOVERY BIT(25) 652 653 #define GDMA_DRV_CAP_FLAGS1 \ 654 (GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT | \ 655 GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX | \ 656 GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG | \ 657 GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT | \ 658 GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP | \ 659 GDMA_DRV_CAP_FLAG_1_DYNAMIC_IRQ_ALLOC_SUPPORT | \ 660 GDMA_DRV_CAP_FLAG_1_SELF_RESET_ON_EQE | \ 661 GDMA_DRV_CAP_FLAG_1_HANDLE_RECONFIG_EQE | \ 662 GDMA_DRV_CAP_FLAG_1_HW_VPORT_LINK_AWARE | \ 663 GDMA_DRV_CAP_FLAG_1_PERIODIC_STATS_QUERY | \ 664 GDMA_DRV_CAP_FLAG_1_SKB_LINEARIZE | \ 665 GDMA_DRV_CAP_FLAG_1_PROBE_RECOVERY | \ 666 GDMA_DRV_CAP_FLAG_1_HANDLE_STALL_SQ_RECOVERY | \ 667 GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECOVERY | \ 668 GDMA_DRV_CAP_FLAG_1_EQ_MSI_UNSHARE_MULTI_VPORT) 669 670 #define GDMA_DRV_CAP_FLAGS2 0 671 672 #define GDMA_DRV_CAP_FLAGS3 0 673 674 #define GDMA_DRV_CAP_FLAGS4 0 675 676 struct gdma_verify_ver_req { 677 struct gdma_req_hdr hdr; 678 679 /* Mandatory fields required for protocol establishment */ 680 u64 protocol_ver_min; 681 u64 protocol_ver_max; 682 683 /* Gdma Driver Capability Flags */ 684 u64 gd_drv_cap_flags1; 685 u64 gd_drv_cap_flags2; 686 u64 gd_drv_cap_flags3; 687 u64 gd_drv_cap_flags4; 688 689 /* Advisory fields */ 690 u64 drv_ver; 691 u32 os_type; /* Linux = 0x10; Windows = 0x20; Other = 0x30 */ 692 u32 reserved; 693 u32 os_ver_major; 694 u32 os_ver_minor; 695 u32 os_ver_build; 696 u32 os_ver_platform; 697 u64 reserved_2; 698 u8 os_ver_str1[128]; 699 u8 os_ver_str2[128]; 700 u8 os_ver_str3[128]; 701 u8 os_ver_str4[128]; 702 }; /* HW DATA */ 703 704 struct gdma_verify_ver_resp { 705 struct gdma_resp_hdr hdr; 706 u64 gdma_protocol_ver; 707 u64 pf_cap_flags1; 708 u64 pf_cap_flags2; 709 u64 pf_cap_flags3; 710 u64 pf_cap_flags4; 711 }; /* HW DATA */ 712 713 /* GDMA_QUERY_MAX_RESOURCES */ 714 struct gdma_query_max_resources_resp { 715 struct gdma_resp_hdr hdr; 716 u32 status; 717 u32 max_sq; 718 u32 max_rq; 719 u32 max_cq; 720 u32 max_eq; 721 u32 max_db; 722 u32 max_mst; 723 u32 max_cq_mod_ctx; 724 u32 max_mod_cq; 725 u32 max_msix; 726 }; /* HW DATA */ 727 728 /* GDMA_LIST_DEVICES */ 729 #define GDMA_DEV_LIST_SIZE 64 730 struct gdma_list_devices_resp { 731 struct gdma_resp_hdr hdr; 732 u32 num_of_devs; 733 u32 reserved; 734 struct gdma_dev_id devs[GDMA_DEV_LIST_SIZE]; 735 }; /* HW DATA */ 736 737 /* GDMA_REGISTER_DEVICE */ 738 struct gdma_register_device_resp { 739 struct gdma_resp_hdr hdr; 740 u32 pdid; 741 u32 gpa_mkey; 742 u32 db_id; 743 }; /* HW DATA */ 744 745 struct gdma_allocate_resource_range_req { 746 struct gdma_req_hdr hdr; 747 u32 resource_type; 748 u32 num_resources; 749 u32 alignment; 750 u32 allocated_resources; 751 }; 752 753 struct gdma_allocate_resource_range_resp { 754 struct gdma_resp_hdr hdr; 755 u32 allocated_resources; 756 }; 757 758 struct gdma_destroy_resource_range_req { 759 struct gdma_req_hdr hdr; 760 u32 resource_type; 761 u32 num_resources; 762 u32 allocated_resources; 763 }; 764 765 /* GDMA_CREATE_QUEUE */ 766 struct gdma_create_queue_req { 767 struct gdma_req_hdr hdr; 768 u32 type; 769 u32 reserved1; 770 u32 pdid; 771 u32 doolbell_id; 772 u64 gdma_region; 773 u32 reserved2; 774 u32 queue_size; 775 u32 log2_throttle_limit; 776 u32 eq_pci_msix_index; 777 u32 cq_mod_ctx_id; 778 u32 cq_parent_eq_id; 779 u8 rq_drop_on_overrun; 780 u8 rq_err_on_wqe_overflow; 781 u8 rq_chain_rec_wqes; 782 u8 sq_hw_db; 783 u32 reserved3; 784 }; /* HW DATA */ 785 786 struct gdma_create_queue_resp { 787 struct gdma_resp_hdr hdr; 788 u32 queue_index; 789 }; /* HW DATA */ 790 791 /* GDMA_DISABLE_QUEUE */ 792 struct gdma_disable_queue_req { 793 struct gdma_req_hdr hdr; 794 u32 type; 795 u32 queue_index; 796 u32 alloc_res_id_on_creation; 797 }; /* HW DATA */ 798 799 /* GDMA_QUERY_HWC_TIMEOUT */ 800 struct gdma_query_hwc_timeout_req { 801 struct gdma_req_hdr hdr; 802 u32 timeout_ms; 803 u32 reserved; 804 }; 805 806 struct gdma_query_hwc_timeout_resp { 807 struct gdma_resp_hdr hdr; 808 u32 timeout_ms; 809 u32 reserved; 810 }; 811 812 enum gdma_mr_access_flags { 813 GDMA_ACCESS_FLAG_LOCAL_READ = BIT_ULL(0), 814 GDMA_ACCESS_FLAG_LOCAL_WRITE = BIT_ULL(1), 815 GDMA_ACCESS_FLAG_REMOTE_READ = BIT_ULL(2), 816 GDMA_ACCESS_FLAG_REMOTE_WRITE = BIT_ULL(3), 817 GDMA_ACCESS_FLAG_REMOTE_ATOMIC = BIT_ULL(4), 818 GDMA_ACCESS_FLAG_BIND_MW = BIT_ULL(5), 819 }; 820 821 /* GDMA_CREATE_DMA_REGION */ 822 struct gdma_create_dma_region_req { 823 struct gdma_req_hdr hdr; 824 825 /* The total size of the DMA region */ 826 u64 length; 827 828 /* The offset in the first page */ 829 u32 offset_in_page; 830 831 /* enum gdma_page_type */ 832 u32 gdma_page_type; 833 834 /* The total number of pages */ 835 u32 page_count; 836 837 /* If page_addr_list_len is smaller than page_count, 838 * the remaining page addresses will be added via the 839 * message GDMA_DMA_REGION_ADD_PAGES. 840 */ 841 u32 page_addr_list_len; 842 u64 page_addr_list[]; 843 }; /* HW DATA */ 844 845 struct gdma_create_dma_region_resp { 846 struct gdma_resp_hdr hdr; 847 u64 dma_region_handle; 848 }; /* HW DATA */ 849 850 /* GDMA_DMA_REGION_ADD_PAGES */ 851 struct gdma_dma_region_add_pages_req { 852 struct gdma_req_hdr hdr; 853 854 u64 dma_region_handle; 855 856 u32 page_addr_list_len; 857 u32 reserved3; 858 859 u64 page_addr_list[]; 860 }; /* HW DATA */ 861 862 /* GDMA_DESTROY_DMA_REGION */ 863 struct gdma_destroy_dma_region_req { 864 struct gdma_req_hdr hdr; 865 866 u64 dma_region_handle; 867 }; /* HW DATA */ 868 869 enum gdma_pd_flags { 870 GDMA_PD_FLAG_INVALID = 0, 871 GDMA_PD_FLAG_ALLOW_GPA_MR = 1, 872 }; 873 874 struct gdma_create_pd_req { 875 struct gdma_req_hdr hdr; 876 enum gdma_pd_flags flags; 877 u32 reserved; 878 };/* HW DATA */ 879 880 struct gdma_create_pd_resp { 881 struct gdma_resp_hdr hdr; 882 u64 pd_handle; 883 u32 pd_id; 884 u32 reserved; 885 };/* HW DATA */ 886 887 struct gdma_destroy_pd_req { 888 struct gdma_req_hdr hdr; 889 u64 pd_handle; 890 };/* HW DATA */ 891 892 struct gdma_destory_pd_resp { 893 struct gdma_resp_hdr hdr; 894 };/* HW DATA */ 895 896 enum gdma_mr_type { 897 /* 898 * Guest Physical Address - MRs of this type allow access 899 * to any DMA-mapped memory using bus-logical address 900 */ 901 GDMA_MR_TYPE_GPA = 1, 902 /* Guest Virtual Address - MRs of this type allow access 903 * to memory mapped by PTEs associated with this MR using a virtual 904 * address that is set up in the MST 905 */ 906 GDMA_MR_TYPE_GVA = 2, 907 /* Guest zero-based address MRs */ 908 GDMA_MR_TYPE_ZBVA = 4, 909 /* Device address MRs */ 910 GDMA_MR_TYPE_DM = 5, 911 /* Memory Window type 1 */ 912 GDMA_MR_TYPE_MW1 = 6, 913 /* Memory Window type 2 */ 914 GDMA_MR_TYPE_MW2 = 7, 915 }; 916 917 struct gdma_create_mr_params { 918 u64 pd_handle; 919 enum gdma_mr_type mr_type; 920 union { 921 struct { 922 u64 dma_region_handle; 923 u64 virtual_address; 924 enum gdma_mr_access_flags access_flags; 925 } gva; 926 struct { 927 u64 dma_region_handle; 928 enum gdma_mr_access_flags access_flags; 929 } zbva; 930 struct { 931 u64 dm_handle; 932 u64 offset; 933 u64 length; 934 enum gdma_mr_access_flags access_flags; 935 } da; 936 }; 937 }; 938 939 struct gdma_create_mr_request { 940 struct gdma_req_hdr hdr; 941 u64 pd_handle; 942 enum gdma_mr_type mr_type; 943 u32 reserved_1; 944 945 union { 946 struct { 947 u64 dma_region_handle; 948 u64 virtual_address; 949 enum gdma_mr_access_flags access_flags; 950 } __packed gva; 951 struct { 952 u64 dma_region_handle; 953 enum gdma_mr_access_flags access_flags; 954 } __packed zbva; 955 struct { 956 u64 dm_handle; 957 u64 offset; 958 enum gdma_mr_access_flags access_flags; 959 } __packed da; 960 } __packed; 961 u32 reserved_2; 962 union { 963 struct { 964 u64 length; 965 } da_ext; 966 }; 967 };/* HW DATA */ 968 969 struct gdma_create_mr_response { 970 struct gdma_resp_hdr hdr; 971 u64 mr_handle; 972 u32 lkey; 973 u32 rkey; 974 };/* HW DATA */ 975 976 struct gdma_destroy_mr_request { 977 struct gdma_req_hdr hdr; 978 u64 mr_handle; 979 };/* HW DATA */ 980 981 struct gdma_destroy_mr_response { 982 struct gdma_resp_hdr hdr; 983 };/* HW DATA */ 984 985 struct gdma_alloc_dm_req { 986 struct gdma_req_hdr hdr; 987 u64 length; 988 u32 alignment; 989 u32 flags; 990 }; /* HW Data */ 991 992 struct gdma_alloc_dm_resp { 993 struct gdma_resp_hdr hdr; 994 u64 dm_handle; 995 }; /* HW Data */ 996 997 struct gdma_destroy_dm_req { 998 struct gdma_req_hdr hdr; 999 u64 dm_handle; 1000 }; /* HW Data */ 1001 1002 struct gdma_destroy_dm_resp { 1003 struct gdma_resp_hdr hdr; 1004 }; /* HW Data */ 1005 1006 int mana_gd_verify_vf_version(struct pci_dev *pdev); 1007 1008 int mana_gd_register_device(struct gdma_dev *gd); 1009 int mana_gd_deregister_device(struct gdma_dev *gd); 1010 1011 int mana_gd_post_work_request(struct gdma_queue *wq, 1012 const struct gdma_wqe_request *wqe_req, 1013 struct gdma_posted_wqe_info *wqe_info); 1014 1015 int mana_gd_post_and_ring(struct gdma_queue *queue, 1016 const struct gdma_wqe_request *wqe, 1017 struct gdma_posted_wqe_info *wqe_info); 1018 1019 int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r); 1020 void mana_gd_free_res_map(struct gdma_resource *r); 1021 1022 void mana_gd_wq_ring_doorbell(struct gdma_context *gc, 1023 struct gdma_queue *queue); 1024 1025 int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 1026 struct gdma_mem_info *gmi); 1027 1028 void mana_gd_free_memory(struct gdma_mem_info *gmi); 1029 1030 int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req, 1031 u32 resp_len, void *resp); 1032 1033 int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle); 1034 void mana_register_debugfs(void); 1035 void mana_unregister_debugfs(void); 1036 1037 int mana_rdma_service_event(struct gdma_context *gc, enum gdma_service_type event); 1038 1039 int mana_gd_suspend(struct pci_dev *pdev, pm_message_t state); 1040 int mana_gd_resume(struct pci_dev *pdev); 1041 1042 bool mana_need_log(struct gdma_context *gc, int err); 1043 1044 struct gdma_irq_context *mana_gd_get_gic(struct gdma_context *gc, 1045 bool use_msi_bitmap, 1046 int *msi_requested); 1047 void mana_gd_put_gic(struct gdma_context *gc, bool use_msi_bitmap, int msi); 1048 int mana_gd_query_device_cfg(struct gdma_context *gc, u32 proto_major_ver, 1049 u32 proto_minor_ver, u32 proto_micro_ver, 1050 u16 *max_num_vports, u8 *bm_hostmode); 1051 #endif /* _GDMA_H */ 1052