1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #ifndef _GDMA_H 5 #define _GDMA_H 6 7 #include <linux/dma-mapping.h> 8 #include <linux/netdevice.h> 9 10 #include "shm_channel.h" 11 12 #define GDMA_STATUS_MORE_ENTRIES 0x00000105 13 #define GDMA_STATUS_CMD_UNSUPPORTED 0xffffffff 14 15 /* Structures labeled with "HW DATA" are exchanged with the hardware. All of 16 * them are naturally aligned and hence don't need __packed. 17 */ 18 19 enum gdma_request_type { 20 GDMA_VERIFY_VF_DRIVER_VERSION = 1, 21 GDMA_QUERY_MAX_RESOURCES = 2, 22 GDMA_LIST_DEVICES = 3, 23 GDMA_REGISTER_DEVICE = 4, 24 GDMA_DEREGISTER_DEVICE = 5, 25 GDMA_GENERATE_TEST_EQE = 10, 26 GDMA_CREATE_QUEUE = 12, 27 GDMA_DISABLE_QUEUE = 13, 28 GDMA_ALLOCATE_RESOURCE_RANGE = 22, 29 GDMA_DESTROY_RESOURCE_RANGE = 24, 30 GDMA_CREATE_DMA_REGION = 25, 31 GDMA_DMA_REGION_ADD_PAGES = 26, 32 GDMA_DESTROY_DMA_REGION = 27, 33 GDMA_CREATE_PD = 29, 34 GDMA_DESTROY_PD = 30, 35 GDMA_CREATE_MR = 31, 36 GDMA_DESTROY_MR = 32, 37 GDMA_QUERY_HWC_TIMEOUT = 84, /* 0x54 */ 38 GDMA_ALLOC_DM = 96, /* 0x60 */ 39 GDMA_DESTROY_DM = 97, /* 0x61 */ 40 }; 41 42 #define GDMA_RESOURCE_DOORBELL_PAGE 27 43 44 enum gdma_queue_type { 45 GDMA_INVALID_QUEUE, 46 GDMA_SQ, 47 GDMA_RQ, 48 GDMA_CQ, 49 GDMA_EQ, 50 GDMA_DIM, 51 }; 52 53 enum gdma_work_request_flags { 54 GDMA_WR_NONE = 0, 55 GDMA_WR_OOB_IN_SGL = BIT(0), 56 GDMA_WR_PAD_BY_SGE0 = BIT(1), 57 }; 58 59 enum gdma_eqe_type { 60 GDMA_EQE_COMPLETION = 3, 61 GDMA_EQE_TEST_EVENT = 64, 62 GDMA_EQE_HWC_INIT_EQ_ID_DB = 129, 63 GDMA_EQE_HWC_INIT_DATA = 130, 64 GDMA_EQE_HWC_INIT_DONE = 131, 65 GDMA_EQE_HWC_FPGA_RECONFIG = 132, 66 GDMA_EQE_HWC_SOC_RECONFIG_DATA = 133, 67 GDMA_EQE_HWC_SOC_SERVICE = 134, 68 GDMA_EQE_HWC_RESET_REQUEST = 135, 69 GDMA_EQE_RNIC_QP_FATAL = 176, 70 }; 71 72 enum { 73 GDMA_DEVICE_NONE = 0, 74 GDMA_DEVICE_HWC = 1, 75 GDMA_DEVICE_MANA = 2, 76 GDMA_DEVICE_MANA_IB = 3, 77 }; 78 79 enum gdma_service_type { 80 GDMA_SERVICE_TYPE_NONE = 0, 81 GDMA_SERVICE_TYPE_RDMA_SUSPEND = 1, 82 GDMA_SERVICE_TYPE_RDMA_RESUME = 2, 83 }; 84 85 struct mana_service_work { 86 struct work_struct work; 87 struct gdma_dev *gdma_dev; 88 enum gdma_service_type event; 89 }; 90 91 struct gdma_resource { 92 /* Protect the bitmap */ 93 spinlock_t lock; 94 95 /* The bitmap size in bits. */ 96 u32 size; 97 98 /* The bitmap tracks the resources. */ 99 unsigned long *map; 100 }; 101 102 union gdma_doorbell_entry { 103 u64 as_uint64; 104 105 struct { 106 u64 id : 24; 107 u64 reserved : 8; 108 u64 tail_ptr : 31; 109 u64 arm : 1; 110 } cq; 111 112 struct { 113 u64 id : 24; 114 u64 wqe_cnt : 8; 115 u64 tail_ptr : 32; 116 } rq; 117 118 struct { 119 u64 id : 24; 120 u64 reserved : 8; 121 u64 tail_ptr : 32; 122 } sq; 123 124 struct { 125 u64 id : 16; 126 u64 reserved : 16; 127 u64 tail_ptr : 31; 128 u64 arm : 1; 129 } eq; 130 131 struct { 132 u64 id : 24; 133 u64 reserved : 8; 134 u64 mod_usec : 10; 135 u64 reserve1 : 5; 136 u64 mod_usec_vld : 1; 137 u64 mod_comps : 8; 138 u64 reserve2 : 7; 139 u64 mod_comps_vld: 1; 140 } dim; 141 }; /* HW DATA */ 142 143 struct gdma_msg_hdr { 144 u32 hdr_type; 145 u32 msg_type; 146 u16 msg_version; 147 u16 hwc_msg_id; 148 u32 msg_size; 149 }; /* HW DATA */ 150 151 struct gdma_dev_id { 152 union { 153 struct { 154 u16 type; 155 u16 instance; 156 }; 157 158 u32 as_uint32; 159 }; 160 }; /* HW DATA */ 161 162 struct gdma_req_hdr { 163 struct gdma_msg_hdr req; 164 struct gdma_msg_hdr resp; /* The expected response */ 165 struct gdma_dev_id dev_id; 166 u32 activity_id; 167 }; /* HW DATA */ 168 169 struct gdma_resp_hdr { 170 struct gdma_msg_hdr response; 171 struct gdma_dev_id dev_id; 172 u32 activity_id; 173 u32 status; 174 u32 reserved; 175 }; /* HW DATA */ 176 177 struct gdma_general_req { 178 struct gdma_req_hdr hdr; 179 }; /* HW DATA */ 180 181 #define GDMA_MESSAGE_V1 1 182 #define GDMA_MESSAGE_V2 2 183 #define GDMA_MESSAGE_V3 3 184 #define GDMA_MESSAGE_V4 4 185 #define GDMA_MESSAGE_V5 5 186 187 struct gdma_general_resp { 188 struct gdma_resp_hdr hdr; 189 }; /* HW DATA */ 190 191 #define GDMA_STANDARD_HEADER_TYPE 0 192 193 static inline void mana_gd_init_req_hdr(struct gdma_req_hdr *hdr, u32 code, 194 u32 req_size, u32 resp_size) 195 { 196 hdr->req.hdr_type = GDMA_STANDARD_HEADER_TYPE; 197 hdr->req.msg_type = code; 198 hdr->req.msg_version = GDMA_MESSAGE_V1; 199 hdr->req.msg_size = req_size; 200 201 hdr->resp.hdr_type = GDMA_STANDARD_HEADER_TYPE; 202 hdr->resp.msg_type = code; 203 hdr->resp.msg_version = GDMA_MESSAGE_V1; 204 hdr->resp.msg_size = resp_size; 205 } 206 207 /* The 16-byte struct is part of the GDMA work queue entry (WQE). */ 208 struct gdma_sge { 209 u64 address; 210 u32 mem_key; 211 u32 size; 212 }; /* HW DATA */ 213 214 struct gdma_wqe_request { 215 struct gdma_sge *sgl; 216 u32 num_sge; 217 218 u32 inline_oob_size; 219 const void *inline_oob_data; 220 221 u32 flags; 222 u32 client_data_unit; 223 }; 224 225 enum gdma_page_type { 226 GDMA_PAGE_TYPE_4K, 227 }; 228 229 #define GDMA_INVALID_DMA_REGION 0 230 231 struct mana_serv_work { 232 struct work_struct serv_work; 233 struct pci_dev *pdev; 234 enum gdma_eqe_type type; 235 }; 236 237 struct gdma_mem_info { 238 struct device *dev; 239 240 dma_addr_t dma_handle; 241 void *virt_addr; 242 u64 length; 243 244 /* Allocated by the PF driver */ 245 u64 dma_region_handle; 246 }; 247 248 #define REGISTER_ATB_MST_MKEY_LOWER_SIZE 8 249 250 struct gdma_dev { 251 struct gdma_context *gdma_context; 252 253 struct gdma_dev_id dev_id; 254 255 u32 pdid; 256 u32 doorbell; 257 u32 gpa_mkey; 258 259 /* GDMA driver specific pointer */ 260 void *driver_data; 261 262 struct auxiliary_device *adev; 263 bool is_suspended; 264 bool rdma_teardown; 265 }; 266 267 /* MANA_PAGE_SIZE is the DMA unit */ 268 #define MANA_PAGE_SHIFT 12 269 #define MANA_PAGE_SIZE BIT(MANA_PAGE_SHIFT) 270 #define MANA_PAGE_ALIGN(x) ALIGN((x), MANA_PAGE_SIZE) 271 #define MANA_PAGE_ALIGNED(addr) IS_ALIGNED((unsigned long)(addr), MANA_PAGE_SIZE) 272 #define MANA_PFN(a) ((a) >> MANA_PAGE_SHIFT) 273 274 /* Required by HW */ 275 #define MANA_MIN_QSIZE MANA_PAGE_SIZE 276 277 #define GDMA_CQE_SIZE 64 278 #define GDMA_EQE_SIZE 16 279 #define GDMA_MAX_SQE_SIZE 512 280 #define GDMA_MAX_RQE_SIZE 256 281 282 #define GDMA_COMP_DATA_SIZE 0x3C 283 284 #define GDMA_EVENT_DATA_SIZE 0xC 285 286 /* The WQE size must be a multiple of the Basic Unit, which is 32 bytes. */ 287 #define GDMA_WQE_BU_SIZE 32 288 289 #define INVALID_PDID UINT_MAX 290 #define INVALID_DOORBELL UINT_MAX 291 #define INVALID_MEM_KEY UINT_MAX 292 #define INVALID_QUEUE_ID UINT_MAX 293 #define INVALID_PCI_MSIX_INDEX UINT_MAX 294 295 struct gdma_comp { 296 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4]; 297 u32 wq_num; 298 bool is_sq; 299 }; 300 301 struct gdma_event { 302 u32 details[GDMA_EVENT_DATA_SIZE / 4]; 303 u8 type; 304 }; 305 306 struct gdma_queue; 307 308 struct mana_eq { 309 struct gdma_queue *eq; 310 struct dentry *mana_eq_debugfs; 311 }; 312 313 typedef void gdma_eq_callback(void *context, struct gdma_queue *q, 314 struct gdma_event *e); 315 316 typedef void gdma_cq_callback(void *context, struct gdma_queue *q); 317 318 /* The 'head' is the producer index. For SQ/RQ, when the driver posts a WQE 319 * (Note: the WQE size must be a multiple of the 32-byte Basic Unit), the 320 * driver increases the 'head' in BUs rather than in bytes, and notifies 321 * the HW of the updated head. For EQ/CQ, the driver uses the 'head' to track 322 * the HW head, and increases the 'head' by 1 for every processed EQE/CQE. 323 * 324 * The 'tail' is the consumer index for SQ/RQ. After the CQE of the SQ/RQ is 325 * processed, the driver increases the 'tail' to indicate that WQEs have 326 * been consumed by the HW, so the driver can post new WQEs into the SQ/RQ. 327 * 328 * The driver doesn't use the 'tail' for EQ/CQ, because the driver ensures 329 * that the EQ/CQ is big enough so they can't overflow, and the driver uses 330 * the owner bits mechanism to detect if the queue has become empty. 331 */ 332 struct gdma_queue { 333 struct gdma_dev *gdma_dev; 334 335 enum gdma_queue_type type; 336 u32 id; 337 338 struct gdma_mem_info mem_info; 339 340 void *queue_mem_ptr; 341 u32 queue_size; 342 343 bool monitor_avl_buf; 344 345 u32 head; 346 u32 tail; 347 struct list_head entry; 348 349 /* Extra fields specific to EQ/CQ. */ 350 union { 351 struct { 352 bool disable_needed; 353 354 gdma_eq_callback *callback; 355 void *context; 356 357 unsigned int msix_index; 358 unsigned int irq; 359 360 u32 log2_throttle_limit; 361 } eq; 362 363 struct { 364 gdma_cq_callback *callback; 365 void *context; 366 367 struct gdma_queue *parent; /* For CQ/EQ relationship */ 368 } cq; 369 }; 370 }; 371 372 struct gdma_queue_spec { 373 enum gdma_queue_type type; 374 bool monitor_avl_buf; 375 unsigned int queue_size; 376 377 /* Extra fields specific to EQ/CQ. */ 378 union { 379 struct { 380 gdma_eq_callback *callback; 381 void *context; 382 383 unsigned long log2_throttle_limit; 384 unsigned int msix_index; 385 } eq; 386 387 struct { 388 gdma_cq_callback *callback; 389 void *context; 390 391 struct gdma_queue *parent_eq; 392 393 } cq; 394 }; 395 }; 396 397 #define MANA_IRQ_NAME_SZ 32 398 399 struct gdma_irq_context { 400 void (*handler)(void *arg); 401 /* Protect the eq_list */ 402 spinlock_t lock; 403 struct list_head eq_list; 404 char name[MANA_IRQ_NAME_SZ]; 405 unsigned int msi; 406 unsigned int irq; 407 refcount_t refcount; 408 unsigned int bitmap_refs; 409 bool dyn_msix; 410 }; 411 412 enum gdma_context_flags { 413 GC_PROBE_SUCCEEDED = 0, 414 GC_IN_SERVICE = 1, 415 }; 416 417 struct gdma_context { 418 struct device *dev; 419 struct dentry *mana_pci_debugfs; 420 421 /* Hardware max number of queues */ 422 unsigned int max_num_queues; 423 /* Per-vPort max number of queues */ 424 unsigned int max_num_queues_vport; 425 unsigned int max_num_msix; 426 unsigned int num_msix_usable; 427 struct xarray irq_contexts; 428 429 /* L2 MTU */ 430 u16 adapter_mtu; 431 432 /* NIC supports CQE x8 coalescing */ 433 bool cqe8_coalescing_sup; 434 435 /* This maps a CQ index to the queue structure. */ 436 unsigned int max_num_cqs; 437 struct gdma_queue **cq_table; 438 439 /* Protect eq_test_event and test_event_eq_id */ 440 struct mutex eq_test_event_mutex; 441 struct completion eq_test_event; 442 u32 test_event_eq_id; 443 444 bool is_pf; 445 bool is_pf2; 446 447 phys_addr_t bar0_pa; 448 void __iomem *bar0_va; 449 resource_size_t bar0_size; 450 void __iomem *shm_base; 451 void __iomem *db_page_base; 452 phys_addr_t phys_db_page_base; 453 u64 db_page_off; 454 u64 db_page_size; 455 int numa_node; 456 457 /* Shared memory chanenl (used to bootstrap HWC) */ 458 struct shm_channel shm_channel; 459 460 /* Hardware communication channel (HWC) */ 461 struct gdma_dev hwc; 462 463 /* Azure network adapter */ 464 struct gdma_dev mana; 465 466 /* Azure RDMA adapter */ 467 struct gdma_dev mana_ib; 468 469 u64 pf_cap_flags1; 470 u64 gdma_protocol_ver; 471 472 struct workqueue_struct *service_wq; 473 474 unsigned long flags; 475 476 /* Protect access to GIC context */ 477 struct mutex gic_mutex; 478 479 /* Indicate if this device is sharing MSI for EQs on MANA */ 480 bool msi_sharing; 481 482 /* Bitmap tracks where MSI is allocated when it is not shared for EQs */ 483 unsigned long *msi_bitmap; 484 }; 485 486 static inline bool mana_gd_is_mana(struct gdma_dev *gd) 487 { 488 return gd->dev_id.type == GDMA_DEVICE_MANA; 489 } 490 491 static inline bool mana_gd_is_hwc(struct gdma_dev *gd) 492 { 493 return gd->dev_id.type == GDMA_DEVICE_HWC; 494 } 495 496 u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset); 497 u32 mana_gd_wq_avail_space(struct gdma_queue *wq); 498 499 int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq); 500 501 int mana_gd_create_hwc_queue(struct gdma_dev *gd, 502 const struct gdma_queue_spec *spec, 503 struct gdma_queue **queue_ptr); 504 505 int mana_gd_create_mana_eq(struct gdma_dev *gd, 506 const struct gdma_queue_spec *spec, 507 struct gdma_queue **queue_ptr); 508 509 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 510 const struct gdma_queue_spec *spec, 511 struct gdma_queue **queue_ptr); 512 513 void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue); 514 515 int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe); 516 517 void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit); 518 519 int mana_schedule_serv_work(struct gdma_context *gc, enum gdma_eqe_type type); 520 521 void mana_gd_ring_dim(struct gdma_queue *cq, u32 mod_usec, bool mod_usec_vld, 522 u32 mod_comps, bool mod_comps_vld); 523 524 struct gdma_wqe { 525 u32 reserved :24; 526 u32 last_vbytes :8; 527 528 union { 529 u32 flags; 530 531 struct { 532 u32 num_sge :8; 533 u32 inline_oob_size_div4:3; 534 u32 client_oob_in_sgl :1; 535 u32 reserved1 :4; 536 u32 client_data_unit :14; 537 u32 reserved2 :2; 538 }; 539 }; 540 }; /* HW DATA */ 541 542 #define INLINE_OOB_SMALL_SIZE 8 543 #define INLINE_OOB_LARGE_SIZE 24 544 545 #define MANA_MAX_TX_WQE_SGL_ENTRIES 30 546 547 #define MAX_TX_WQE_SIZE 512 548 #define MAX_RX_WQE_SIZE 256 549 550 #define MAX_TX_WQE_SGL_ENTRIES ((GDMA_MAX_SQE_SIZE - \ 551 sizeof(struct gdma_sge) - INLINE_OOB_SMALL_SIZE) / \ 552 sizeof(struct gdma_sge)) 553 554 #define MAX_RX_WQE_SGL_ENTRIES ((GDMA_MAX_RQE_SIZE - \ 555 sizeof(struct gdma_sge)) / sizeof(struct gdma_sge)) 556 557 struct gdma_cqe { 558 u32 cqe_data[GDMA_COMP_DATA_SIZE / 4]; 559 560 union { 561 u32 as_uint32; 562 563 struct { 564 u32 wq_num : 24; 565 u32 is_sq : 1; 566 u32 reserved : 4; 567 u32 owner_bits : 3; 568 }; 569 } cqe_info; 570 }; /* HW DATA */ 571 572 #define GDMA_CQE_OWNER_BITS 3 573 574 #define GDMA_CQE_OWNER_MASK ((1 << GDMA_CQE_OWNER_BITS) - 1) 575 576 #define SET_ARM_BIT 1 577 578 #define GDMA_EQE_OWNER_BITS 3 579 580 union gdma_eqe_info { 581 u32 as_uint32; 582 583 struct { 584 u32 type : 8; 585 u32 reserved1 : 8; 586 u32 client_id : 2; 587 u32 reserved2 : 11; 588 u32 owner_bits : 3; 589 }; 590 }; /* HW DATA */ 591 592 #define GDMA_EQE_OWNER_MASK ((1 << GDMA_EQE_OWNER_BITS) - 1) 593 #define INITIALIZED_OWNER_BIT(log2_num_entries) (1UL << (log2_num_entries)) 594 595 struct gdma_eqe { 596 u32 details[GDMA_EVENT_DATA_SIZE / 4]; 597 u32 eqe_info; 598 }; /* HW DATA */ 599 600 #define GDMA_REG_DB_PAGE_OFFSET 8 601 #define GDMA_REG_DB_PAGE_SIZE 0x10 602 #define GDMA_REG_SHM_OFFSET 0x18 603 604 #define GDMA_PF_REG_DB_PAGE_SIZE 0xD0 605 #define GDMA_PF_REG_DB_PAGE_OFF 0xC8 606 #define GDMA_PF_REG_SHM_OFF 0x70 607 608 #define GDMA_SRIOV_REG_CFG_BASE_OFF 0x108 609 610 #define MANA_PF_DEVICE_ID 0x00B9 611 #define MANA_PF2_DEVICE_ID 0x00C1 612 #define MANA_VF_DEVICE_ID 0x00BA 613 614 struct gdma_posted_wqe_info { 615 u32 wqe_size_in_bu; 616 }; 617 618 /* GDMA_GENERATE_TEST_EQE */ 619 struct gdma_generate_test_event_req { 620 struct gdma_req_hdr hdr; 621 u32 queue_index; 622 }; /* HW DATA */ 623 624 /* GDMA_VERIFY_VF_DRIVER_VERSION */ 625 enum { 626 GDMA_PROTOCOL_V1 = 1, 627 GDMA_PROTOCOL_FIRST = GDMA_PROTOCOL_V1, 628 GDMA_PROTOCOL_LAST = GDMA_PROTOCOL_V1, 629 }; 630 631 #define GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT BIT(0) 632 633 /* Advertise to the NIC firmware: the NAPI work_done variable race is fixed, 634 * so the driver is able to reliably support features like busy_poll. 635 */ 636 #define GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX BIT(2) 637 #define GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG BIT(3) 638 #define GDMA_DRV_CAP_FLAG_1_GDMA_PAGES_4MB_1GB_2GB BIT(4) 639 #define GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT BIT(5) 640 #define GDMA_DRV_CAP_FLAG_1_HW_VPORT_LINK_AWARE BIT(6) 641 642 /* Driver can handle holes (zeros) in the device list */ 643 #define GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP BIT(11) 644 645 /* Driver supports dynamic MSI-X vector allocation */ 646 #define GDMA_DRV_CAP_FLAG_1_DYNAMIC_IRQ_ALLOC_SUPPORT BIT(13) 647 648 /* Driver can self reset on EQE notification */ 649 #define GDMA_DRV_CAP_FLAG_1_SELF_RESET_ON_EQE BIT(14) 650 651 /* Driver can self reset on FPGA Reconfig EQE notification */ 652 #define GDMA_DRV_CAP_FLAG_1_HANDLE_RECONFIG_EQE BIT(17) 653 654 /* Driver detects stalled send queues and recovers them */ 655 #define GDMA_DRV_CAP_FLAG_1_HANDLE_STALL_SQ_RECOVERY BIT(18) 656 657 /* Driver supports separate EQ/MSIs for each vPort */ 658 #define GDMA_DRV_CAP_FLAG_1_EQ_MSI_UNSHARE_MULTI_VPORT BIT(19) 659 660 /* Driver supports linearizing the skb when num_sge exceeds hardware limit */ 661 #define GDMA_DRV_CAP_FLAG_1_SKB_LINEARIZE BIT(20) 662 663 /* Driver can send HWC periodically to query stats */ 664 #define GDMA_DRV_CAP_FLAG_1_PERIODIC_STATS_QUERY BIT(21) 665 666 /* Driver can handle hardware recovery events during probe */ 667 #define GDMA_DRV_CAP_FLAG_1_PROBE_RECOVERY BIT(22) 668 669 /* Driver supports self recovery on Hardware Channel timeouts */ 670 #define GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECOVERY BIT(25) 671 672 /* Driver supports dynamic interrupt moderation - DIM */ 673 #define GDMA_DRV_CAP_FLAG_1_DYN_INTERRUPT_MODERATION BIT(28) 674 675 #define GDMA_DRV_CAP_FLAGS1 \ 676 (GDMA_DRV_CAP_FLAG_1_EQ_SHARING_MULTI_VPORT | \ 677 GDMA_DRV_CAP_FLAG_1_NAPI_WKDONE_FIX | \ 678 GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG | \ 679 GDMA_DRV_CAP_FLAG_1_VARIABLE_INDIRECTION_TABLE_SUPPORT | \ 680 GDMA_DRV_CAP_FLAG_1_DEV_LIST_HOLES_SUP | \ 681 GDMA_DRV_CAP_FLAG_1_DYNAMIC_IRQ_ALLOC_SUPPORT | \ 682 GDMA_DRV_CAP_FLAG_1_SELF_RESET_ON_EQE | \ 683 GDMA_DRV_CAP_FLAG_1_HANDLE_RECONFIG_EQE | \ 684 GDMA_DRV_CAP_FLAG_1_HW_VPORT_LINK_AWARE | \ 685 GDMA_DRV_CAP_FLAG_1_PERIODIC_STATS_QUERY | \ 686 GDMA_DRV_CAP_FLAG_1_SKB_LINEARIZE | \ 687 GDMA_DRV_CAP_FLAG_1_PROBE_RECOVERY | \ 688 GDMA_DRV_CAP_FLAG_1_HANDLE_STALL_SQ_RECOVERY | \ 689 GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECOVERY | \ 690 GDMA_DRV_CAP_FLAG_1_EQ_MSI_UNSHARE_MULTI_VPORT | \ 691 GDMA_DRV_CAP_FLAG_1_DYN_INTERRUPT_MODERATION) 692 693 #define GDMA_DRV_CAP_FLAGS2 0 694 695 #define GDMA_DRV_CAP_FLAGS3 0 696 697 #define GDMA_DRV_CAP_FLAGS4 0 698 699 struct gdma_verify_ver_req { 700 struct gdma_req_hdr hdr; 701 702 /* Mandatory fields required for protocol establishment */ 703 u64 protocol_ver_min; 704 u64 protocol_ver_max; 705 706 /* Gdma Driver Capability Flags */ 707 u64 gd_drv_cap_flags1; 708 u64 gd_drv_cap_flags2; 709 u64 gd_drv_cap_flags3; 710 u64 gd_drv_cap_flags4; 711 712 /* Advisory fields */ 713 u64 drv_ver; 714 u32 os_type; /* Linux = 0x10; Windows = 0x20; Other = 0x30 */ 715 u32 reserved; 716 u32 os_ver_major; 717 u32 os_ver_minor; 718 u32 os_ver_build; 719 u32 os_ver_platform; 720 u64 reserved_2; 721 u8 os_ver_str1[128]; 722 u8 os_ver_str2[128]; 723 u8 os_ver_str3[128]; 724 u8 os_ver_str4[128]; 725 }; /* HW DATA */ 726 727 /* HW supports dynamic interrupt moderation - DIM */ 728 #define GDMA_PF_CAP_FLAG_1_DYN_INTERRUPT_MODERATION BIT(15) 729 730 struct gdma_verify_ver_resp { 731 struct gdma_resp_hdr hdr; 732 u64 gdma_protocol_ver; 733 u64 pf_cap_flags1; 734 u64 pf_cap_flags2; 735 u64 pf_cap_flags3; 736 u64 pf_cap_flags4; 737 }; /* HW DATA */ 738 739 /* GDMA_QUERY_MAX_RESOURCES */ 740 struct gdma_query_max_resources_resp { 741 struct gdma_resp_hdr hdr; 742 u32 status; 743 u32 max_sq; 744 u32 max_rq; 745 u32 max_cq; 746 u32 max_eq; 747 u32 max_db; 748 u32 max_mst; 749 u32 max_cq_mod_ctx; 750 u32 max_mod_cq; 751 u32 max_msix; 752 }; /* HW DATA */ 753 754 /* GDMA_LIST_DEVICES */ 755 #define GDMA_DEV_LIST_SIZE 64 756 struct gdma_list_devices_resp { 757 struct gdma_resp_hdr hdr; 758 u32 num_of_devs; 759 u32 reserved; 760 struct gdma_dev_id devs[GDMA_DEV_LIST_SIZE]; 761 }; /* HW DATA */ 762 763 /* GDMA_REGISTER_DEVICE */ 764 struct gdma_register_device_resp { 765 struct gdma_resp_hdr hdr; 766 u32 pdid; 767 u32 gpa_mkey; 768 u32 db_id; 769 }; /* HW DATA */ 770 771 struct gdma_allocate_resource_range_req { 772 struct gdma_req_hdr hdr; 773 u32 resource_type; 774 u32 num_resources; 775 u32 alignment; 776 u32 allocated_resources; 777 }; 778 779 struct gdma_allocate_resource_range_resp { 780 struct gdma_resp_hdr hdr; 781 u32 allocated_resources; 782 }; 783 784 struct gdma_destroy_resource_range_req { 785 struct gdma_req_hdr hdr; 786 u32 resource_type; 787 u32 num_resources; 788 u32 allocated_resources; 789 }; 790 791 /* GDMA_CREATE_QUEUE */ 792 struct gdma_create_queue_req { 793 struct gdma_req_hdr hdr; 794 u32 type; 795 u32 reserved1; 796 u32 pdid; 797 u32 doolbell_id; 798 u64 gdma_region; 799 u32 reserved2; 800 u32 queue_size; 801 u32 log2_throttle_limit; 802 u32 eq_pci_msix_index; 803 u32 cq_mod_ctx_id; 804 u32 cq_parent_eq_id; 805 u8 rq_drop_on_overrun; 806 u8 rq_err_on_wqe_overflow; 807 u8 rq_chain_rec_wqes; 808 u8 sq_hw_db; 809 u32 reserved3; 810 }; /* HW DATA */ 811 812 struct gdma_create_queue_resp { 813 struct gdma_resp_hdr hdr; 814 u32 queue_index; 815 }; /* HW DATA */ 816 817 /* GDMA_DISABLE_QUEUE */ 818 struct gdma_disable_queue_req { 819 struct gdma_req_hdr hdr; 820 u32 type; 821 u32 queue_index; 822 u32 alloc_res_id_on_creation; 823 }; /* HW DATA */ 824 825 /* GDMA_QUERY_HWC_TIMEOUT */ 826 struct gdma_query_hwc_timeout_req { 827 struct gdma_req_hdr hdr; 828 u32 timeout_ms; 829 u32 reserved; 830 }; 831 832 struct gdma_query_hwc_timeout_resp { 833 struct gdma_resp_hdr hdr; 834 u32 timeout_ms; 835 u32 reserved; 836 }; 837 838 enum gdma_mr_access_flags { 839 GDMA_ACCESS_FLAG_LOCAL_READ = BIT_ULL(0), 840 GDMA_ACCESS_FLAG_LOCAL_WRITE = BIT_ULL(1), 841 GDMA_ACCESS_FLAG_REMOTE_READ = BIT_ULL(2), 842 GDMA_ACCESS_FLAG_REMOTE_WRITE = BIT_ULL(3), 843 GDMA_ACCESS_FLAG_REMOTE_ATOMIC = BIT_ULL(4), 844 GDMA_ACCESS_FLAG_BIND_MW = BIT_ULL(5), 845 }; 846 847 /* GDMA_CREATE_DMA_REGION */ 848 struct gdma_create_dma_region_req { 849 struct gdma_req_hdr hdr; 850 851 /* The total size of the DMA region */ 852 u64 length; 853 854 /* The offset in the first page */ 855 u32 offset_in_page; 856 857 /* enum gdma_page_type */ 858 u32 gdma_page_type; 859 860 /* The total number of pages */ 861 u32 page_count; 862 863 /* If page_addr_list_len is smaller than page_count, 864 * the remaining page addresses will be added via the 865 * message GDMA_DMA_REGION_ADD_PAGES. 866 */ 867 u32 page_addr_list_len; 868 u64 page_addr_list[]; 869 }; /* HW DATA */ 870 871 struct gdma_create_dma_region_resp { 872 struct gdma_resp_hdr hdr; 873 u64 dma_region_handle; 874 }; /* HW DATA */ 875 876 /* GDMA_DMA_REGION_ADD_PAGES */ 877 struct gdma_dma_region_add_pages_req { 878 struct gdma_req_hdr hdr; 879 880 u64 dma_region_handle; 881 882 u32 page_addr_list_len; 883 u32 reserved3; 884 885 u64 page_addr_list[]; 886 }; /* HW DATA */ 887 888 /* GDMA_DESTROY_DMA_REGION */ 889 struct gdma_destroy_dma_region_req { 890 struct gdma_req_hdr hdr; 891 892 u64 dma_region_handle; 893 }; /* HW DATA */ 894 895 enum gdma_pd_flags { 896 GDMA_PD_FLAG_INVALID = 0, 897 GDMA_PD_FLAG_ALLOW_GPA_MR = 1, 898 }; 899 900 struct gdma_create_pd_req { 901 struct gdma_req_hdr hdr; 902 enum gdma_pd_flags flags; 903 u32 reserved; 904 };/* HW DATA */ 905 906 struct gdma_create_pd_resp { 907 struct gdma_resp_hdr hdr; 908 u64 pd_handle; 909 u32 pd_id; 910 u32 reserved; 911 };/* HW DATA */ 912 913 struct gdma_destroy_pd_req { 914 struct gdma_req_hdr hdr; 915 u64 pd_handle; 916 };/* HW DATA */ 917 918 struct gdma_destory_pd_resp { 919 struct gdma_resp_hdr hdr; 920 };/* HW DATA */ 921 922 enum gdma_mr_type { 923 /* 924 * Guest Physical Address - MRs of this type allow access 925 * to any DMA-mapped memory using bus-logical address 926 */ 927 GDMA_MR_TYPE_GPA = 1, 928 /* Guest Virtual Address - MRs of this type allow access 929 * to memory mapped by PTEs associated with this MR using a virtual 930 * address that is set up in the MST 931 */ 932 GDMA_MR_TYPE_GVA = 2, 933 /* Guest zero-based address MRs */ 934 GDMA_MR_TYPE_ZBVA = 4, 935 /* Device address MRs */ 936 GDMA_MR_TYPE_DM = 5, 937 /* Memory Window type 1 */ 938 GDMA_MR_TYPE_MW1 = 6, 939 /* Memory Window type 2 */ 940 GDMA_MR_TYPE_MW2 = 7, 941 }; 942 943 struct gdma_create_mr_params { 944 u64 pd_handle; 945 enum gdma_mr_type mr_type; 946 union { 947 struct { 948 u64 dma_region_handle; 949 u64 virtual_address; 950 enum gdma_mr_access_flags access_flags; 951 } gva; 952 struct { 953 u64 dma_region_handle; 954 enum gdma_mr_access_flags access_flags; 955 } zbva; 956 struct { 957 u64 dm_handle; 958 u64 offset; 959 u64 length; 960 enum gdma_mr_access_flags access_flags; 961 } da; 962 }; 963 }; 964 965 struct gdma_create_mr_request { 966 struct gdma_req_hdr hdr; 967 u64 pd_handle; 968 enum gdma_mr_type mr_type; 969 u32 reserved_1; 970 971 union { 972 struct { 973 u64 dma_region_handle; 974 u64 virtual_address; 975 enum gdma_mr_access_flags access_flags; 976 } __packed gva; 977 struct { 978 u64 dma_region_handle; 979 enum gdma_mr_access_flags access_flags; 980 } __packed zbva; 981 struct { 982 u64 dm_handle; 983 u64 offset; 984 enum gdma_mr_access_flags access_flags; 985 } __packed da; 986 } __packed; 987 u32 reserved_2; 988 union { 989 struct { 990 u64 length; 991 } da_ext; 992 }; 993 };/* HW DATA */ 994 995 struct gdma_create_mr_response { 996 struct gdma_resp_hdr hdr; 997 u64 mr_handle; 998 u32 lkey; 999 u32 rkey; 1000 };/* HW DATA */ 1001 1002 struct gdma_destroy_mr_request { 1003 struct gdma_req_hdr hdr; 1004 u64 mr_handle; 1005 };/* HW DATA */ 1006 1007 struct gdma_destroy_mr_response { 1008 struct gdma_resp_hdr hdr; 1009 };/* HW DATA */ 1010 1011 struct gdma_alloc_dm_req { 1012 struct gdma_req_hdr hdr; 1013 u64 length; 1014 u32 alignment; 1015 u32 flags; 1016 }; /* HW Data */ 1017 1018 struct gdma_alloc_dm_resp { 1019 struct gdma_resp_hdr hdr; 1020 u64 dm_handle; 1021 }; /* HW Data */ 1022 1023 struct gdma_destroy_dm_req { 1024 struct gdma_req_hdr hdr; 1025 u64 dm_handle; 1026 }; /* HW Data */ 1027 1028 struct gdma_destroy_dm_resp { 1029 struct gdma_resp_hdr hdr; 1030 }; /* HW Data */ 1031 1032 int mana_gd_verify_vf_version(struct pci_dev *pdev); 1033 1034 int mana_gd_register_device(struct gdma_dev *gd); 1035 int mana_gd_deregister_device(struct gdma_dev *gd); 1036 1037 int mana_gd_post_work_request(struct gdma_queue *wq, 1038 const struct gdma_wqe_request *wqe_req, 1039 struct gdma_posted_wqe_info *wqe_info); 1040 1041 int mana_gd_post_and_ring(struct gdma_queue *queue, 1042 const struct gdma_wqe_request *wqe, 1043 struct gdma_posted_wqe_info *wqe_info); 1044 1045 int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r); 1046 void mana_gd_free_res_map(struct gdma_resource *r); 1047 1048 void mana_gd_wq_ring_doorbell(struct gdma_context *gc, 1049 struct gdma_queue *queue); 1050 1051 int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 1052 struct gdma_mem_info *gmi); 1053 1054 void mana_gd_free_memory(struct gdma_mem_info *gmi); 1055 1056 int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req, 1057 u32 resp_len, void *resp); 1058 1059 int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle); 1060 void mana_register_debugfs(void); 1061 void mana_unregister_debugfs(void); 1062 1063 int mana_rdma_service_event(struct gdma_context *gc, enum gdma_service_type event); 1064 1065 int mana_gd_suspend(struct pci_dev *pdev, pm_message_t state); 1066 int mana_gd_resume(struct pci_dev *pdev); 1067 1068 bool mana_need_log(struct gdma_context *gc, int err); 1069 1070 struct gdma_irq_context *mana_gd_get_gic(struct gdma_context *gc, 1071 bool use_msi_bitmap, 1072 int *msi_requested); 1073 void mana_gd_put_gic(struct gdma_context *gc, bool use_msi_bitmap, int msi); 1074 int mana_gd_query_device_cfg(struct gdma_context *gc, u32 proto_major_ver, 1075 u32 proto_minor_ver, u32 proto_micro_ver, 1076 u16 *max_num_vports, u8 *bm_hostmode); 1077 #endif /* _GDMA_H */ 1078