1*9ac0038dSTim Harvey /* SPDX-License-Identifier: GPL-2.0 */ 2*9ac0038dSTim Harvey /* 3*9ac0038dSTim Harvey * tda1997x - NXP HDMI receiver 4*9ac0038dSTim Harvey * 5*9ac0038dSTim Harvey * Copyright 2017 Tim Harvey <tharvey@gateworks.com> 6*9ac0038dSTim Harvey * 7*9ac0038dSTim Harvey */ 8*9ac0038dSTim Harvey 9*9ac0038dSTim Harvey #ifndef _TDA1997X_ 10*9ac0038dSTim Harvey #define _TDA1997X_ 11*9ac0038dSTim Harvey 12*9ac0038dSTim Harvey /* Platform Data */ 13*9ac0038dSTim Harvey struct tda1997x_platform_data { 14*9ac0038dSTim Harvey enum v4l2_mbus_type vidout_bus_type; 15*9ac0038dSTim Harvey u32 vidout_bus_width; 16*9ac0038dSTim Harvey u8 vidout_port_cfg[9]; 17*9ac0038dSTim Harvey /* pin polarity (1=invert) */ 18*9ac0038dSTim Harvey bool vidout_inv_de; 19*9ac0038dSTim Harvey bool vidout_inv_hs; 20*9ac0038dSTim Harvey bool vidout_inv_vs; 21*9ac0038dSTim Harvey bool vidout_inv_pclk; 22*9ac0038dSTim Harvey /* clock delays (0=-8, 1=-7 ... 15=+7 pixels) */ 23*9ac0038dSTim Harvey u8 vidout_delay_hs; 24*9ac0038dSTim Harvey u8 vidout_delay_vs; 25*9ac0038dSTim Harvey u8 vidout_delay_de; 26*9ac0038dSTim Harvey u8 vidout_delay_pclk; 27*9ac0038dSTim Harvey /* sync selections (controls how sync pins are derived) */ 28*9ac0038dSTim Harvey u8 vidout_sel_hs; 29*9ac0038dSTim Harvey u8 vidout_sel_vs; 30*9ac0038dSTim Harvey u8 vidout_sel_de; 31*9ac0038dSTim Harvey 32*9ac0038dSTim Harvey /* Audio Port Output */ 33*9ac0038dSTim Harvey int audout_format; 34*9ac0038dSTim Harvey u32 audout_mclk_fs; /* clock multiplier */ 35*9ac0038dSTim Harvey u32 audout_width; /* 13 or 32 bit */ 36*9ac0038dSTim Harvey u32 audout_layout; /* layout0=AP0 layout1=AP0,AP1,AP2,AP3 */ 37*9ac0038dSTim Harvey bool audout_layoutauto; /* audio layout dictated by pkt header */ 38*9ac0038dSTim Harvey bool audout_invert_clk; /* data valid on rising edge of BCLK */ 39*9ac0038dSTim Harvey bool audio_auto_mute; /* enable hardware audio auto-mute */ 40*9ac0038dSTim Harvey }; 41*9ac0038dSTim Harvey 42*9ac0038dSTim Harvey #endif 43