xref: /linux/include/linux/ssb/ssb.h (revision d0b73b488c55df905ea8faaad079f8535629ed26)
1 #ifndef LINUX_SSB_H_
2 #define LINUX_SSB_H_
3 
4 #include <linux/device.h>
5 #include <linux/list.h>
6 #include <linux/types.h>
7 #include <linux/spinlock.h>
8 #include <linux/pci.h>
9 #include <linux/gpio.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/platform_device.h>
13 
14 #include <linux/ssb/ssb_regs.h>
15 
16 
17 struct pcmcia_device;
18 struct ssb_bus;
19 struct ssb_driver;
20 
21 struct ssb_sprom_core_pwr_info {
22 	u8 itssi_2g, itssi_5g;
23 	u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
24 	u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
25 };
26 
27 struct ssb_sprom {
28 	u8 revision;
29 	u8 il0mac[6];		/* MAC address for 802.11b/g */
30 	u8 et0mac[6];		/* MAC address for Ethernet */
31 	u8 et1mac[6];		/* MAC address for 802.11a */
32 	u8 et0phyaddr;		/* MII address for enet0 */
33 	u8 et1phyaddr;		/* MII address for enet1 */
34 	u8 et0mdcport;		/* MDIO for enet0 */
35 	u8 et1mdcport;		/* MDIO for enet1 */
36 	u16 board_rev;		/* Board revision number from SPROM. */
37 	u16 board_num;		/* Board number from SPROM. */
38 	u16 board_type;		/* Board type from SPROM. */
39 	u8 country_code;	/* Country Code */
40 	char alpha2[2];		/* Country Code as two chars like EU or US */
41 	u8 leddc_on_time;	/* LED Powersave Duty Cycle On Count */
42 	u8 leddc_off_time;	/* LED Powersave Duty Cycle Off Count */
43 	u8 ant_available_a;	/* 2GHz antenna available bits (up to 4) */
44 	u8 ant_available_bg;	/* 5GHz antenna available bits (up to 4) */
45 	u16 pa0b0;
46 	u16 pa0b1;
47 	u16 pa0b2;
48 	u16 pa1b0;
49 	u16 pa1b1;
50 	u16 pa1b2;
51 	u16 pa1lob0;
52 	u16 pa1lob1;
53 	u16 pa1lob2;
54 	u16 pa1hib0;
55 	u16 pa1hib1;
56 	u16 pa1hib2;
57 	u8 gpio0;		/* GPIO pin 0 */
58 	u8 gpio1;		/* GPIO pin 1 */
59 	u8 gpio2;		/* GPIO pin 2 */
60 	u8 gpio3;		/* GPIO pin 3 */
61 	u8 maxpwr_bg;		/* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
62 	u8 maxpwr_al;		/* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
63 	u8 maxpwr_a;		/* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
64 	u8 maxpwr_ah;		/* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
65 	u8 itssi_a;		/* Idle TSSI Target for A-PHY */
66 	u8 itssi_bg;		/* Idle TSSI Target for B/G-PHY */
67 	u8 tri2g;		/* 2.4GHz TX isolation */
68 	u8 tri5gl;		/* 5.2GHz TX isolation */
69 	u8 tri5g;		/* 5.3GHz TX isolation */
70 	u8 tri5gh;		/* 5.8GHz TX isolation */
71 	u8 txpid2g[4];		/* 2GHz TX power index */
72 	u8 txpid5gl[4];		/* 4.9 - 5.1GHz TX power index */
73 	u8 txpid5g[4];		/* 5.1 - 5.5GHz TX power index */
74 	u8 txpid5gh[4];		/* 5.5 - ...GHz TX power index */
75 	s8 rxpo2g;		/* 2GHz RX power offset */
76 	s8 rxpo5g;		/* 5GHz RX power offset */
77 	u8 rssisav2g;		/* 2GHz RSSI params */
78 	u8 rssismc2g;
79 	u8 rssismf2g;
80 	u8 bxa2g;		/* 2GHz BX arch */
81 	u8 rssisav5g;		/* 5GHz RSSI params */
82 	u8 rssismc5g;
83 	u8 rssismf5g;
84 	u8 bxa5g;		/* 5GHz BX arch */
85 	u16 cck2gpo;		/* CCK power offset */
86 	u32 ofdm2gpo;		/* 2.4GHz OFDM power offset */
87 	u32 ofdm5glpo;		/* 5.2GHz OFDM power offset */
88 	u32 ofdm5gpo;		/* 5.3GHz OFDM power offset */
89 	u32 ofdm5ghpo;		/* 5.8GHz OFDM power offset */
90 	u16 boardflags_lo;	/* Board flags (bits 0-15) */
91 	u16 boardflags_hi;	/* Board flags (bits 16-31) */
92 	u16 boardflags2_lo;	/* Board flags (bits 32-47) */
93 	u16 boardflags2_hi;	/* Board flags (bits 48-63) */
94 	/* TODO store board flags in a single u64 */
95 
96 	struct ssb_sprom_core_pwr_info core_pwr_info[4];
97 
98 	/* Antenna gain values for up to 4 antennas
99 	 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
100 	 * loss in the connectors is bigger than the gain. */
101 	struct {
102 		s8 a0, a1, a2, a3;
103 	} antenna_gain;
104 
105 	struct {
106 		struct {
107 			u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
108 		} ghz2;
109 		struct {
110 			u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
111 		} ghz5;
112 	} fem;
113 
114 	u16 mcs2gpo[8];
115 	u16 mcs5gpo[8];
116 	u16 mcs5glpo[8];
117 	u16 mcs5ghpo[8];
118 	u8 opo;
119 
120 	u8 rxgainerr2ga[3];
121 	u8 rxgainerr5gla[3];
122 	u8 rxgainerr5gma[3];
123 	u8 rxgainerr5gha[3];
124 	u8 rxgainerr5gua[3];
125 
126 	u8 noiselvl2ga[3];
127 	u8 noiselvl5gla[3];
128 	u8 noiselvl5gma[3];
129 	u8 noiselvl5gha[3];
130 	u8 noiselvl5gua[3];
131 
132 	u8 regrev;
133 	u8 txchain;
134 	u8 rxchain;
135 	u8 antswitch;
136 	u16 cddpo;
137 	u16 stbcpo;
138 	u16 bw40po;
139 	u16 bwduppo;
140 
141 	u8 tempthresh;
142 	u8 tempoffset;
143 	u16 rawtempsense;
144 	u8 measpower;
145 	u8 tempsense_slope;
146 	u8 tempcorrx;
147 	u8 tempsense_option;
148 	u8 freqoffset_corr;
149 	u8 iqcal_swp_dis;
150 	u8 hw_iqcal_en;
151 	u8 elna2g;
152 	u8 elna5g;
153 	u8 phycal_tempdelta;
154 	u8 temps_period;
155 	u8 temps_hysteresis;
156 	u8 measpower1;
157 	u8 measpower2;
158 	u8 pcieingress_war;
159 
160 	/* power per rate from sromrev 9 */
161 	u16 cckbw202gpo;
162 	u16 cckbw20ul2gpo;
163 	u32 legofdmbw202gpo;
164 	u32 legofdmbw20ul2gpo;
165 	u32 legofdmbw205glpo;
166 	u32 legofdmbw20ul5glpo;
167 	u32 legofdmbw205gmpo;
168 	u32 legofdmbw20ul5gmpo;
169 	u32 legofdmbw205ghpo;
170 	u32 legofdmbw20ul5ghpo;
171 	u32 mcsbw202gpo;
172 	u32 mcsbw20ul2gpo;
173 	u32 mcsbw402gpo;
174 	u32 mcsbw205glpo;
175 	u32 mcsbw20ul5glpo;
176 	u32 mcsbw405glpo;
177 	u32 mcsbw205gmpo;
178 	u32 mcsbw20ul5gmpo;
179 	u32 mcsbw405gmpo;
180 	u32 mcsbw205ghpo;
181 	u32 mcsbw20ul5ghpo;
182 	u32 mcsbw405ghpo;
183 	u16 mcs32po;
184 	u16 legofdm40duppo;
185 	u8 sar2g;
186 	u8 sar5g;
187 };
188 
189 /* Information about the PCB the circuitry is soldered on. */
190 struct ssb_boardinfo {
191 	u16 vendor;
192 	u16 type;
193 };
194 
195 
196 struct ssb_device;
197 /* Lowlevel read/write operations on the device MMIO.
198  * Internal, don't use that outside of ssb. */
199 struct ssb_bus_ops {
200 	u8 (*read8)(struct ssb_device *dev, u16 offset);
201 	u16 (*read16)(struct ssb_device *dev, u16 offset);
202 	u32 (*read32)(struct ssb_device *dev, u16 offset);
203 	void (*write8)(struct ssb_device *dev, u16 offset, u8 value);
204 	void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
205 	void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
206 #ifdef CONFIG_SSB_BLOCKIO
207 	void (*block_read)(struct ssb_device *dev, void *buffer,
208 			   size_t count, u16 offset, u8 reg_width);
209 	void (*block_write)(struct ssb_device *dev, const void *buffer,
210 			    size_t count, u16 offset, u8 reg_width);
211 #endif
212 };
213 
214 
215 /* Core-ID values. */
216 #define SSB_DEV_CHIPCOMMON	0x800
217 #define SSB_DEV_ILINE20		0x801
218 #define SSB_DEV_SDRAM		0x803
219 #define SSB_DEV_PCI		0x804
220 #define SSB_DEV_MIPS		0x805
221 #define SSB_DEV_ETHERNET	0x806
222 #define SSB_DEV_V90		0x807
223 #define SSB_DEV_USB11_HOSTDEV	0x808
224 #define SSB_DEV_ADSL		0x809
225 #define SSB_DEV_ILINE100	0x80A
226 #define SSB_DEV_IPSEC		0x80B
227 #define SSB_DEV_PCMCIA		0x80D
228 #define SSB_DEV_INTERNAL_MEM	0x80E
229 #define SSB_DEV_MEMC_SDRAM	0x80F
230 #define SSB_DEV_EXTIF		0x811
231 #define SSB_DEV_80211		0x812
232 #define SSB_DEV_MIPS_3302	0x816
233 #define SSB_DEV_USB11_HOST	0x817
234 #define SSB_DEV_USB11_DEV	0x818
235 #define SSB_DEV_USB20_HOST	0x819
236 #define SSB_DEV_USB20_DEV	0x81A
237 #define SSB_DEV_SDIO_HOST	0x81B
238 #define SSB_DEV_ROBOSWITCH	0x81C
239 #define SSB_DEV_PARA_ATA	0x81D
240 #define SSB_DEV_SATA_XORDMA	0x81E
241 #define SSB_DEV_ETHERNET_GBIT	0x81F
242 #define SSB_DEV_PCIE		0x820
243 #define SSB_DEV_MIMO_PHY	0x821
244 #define SSB_DEV_SRAM_CTRLR	0x822
245 #define SSB_DEV_MINI_MACPHY	0x823
246 #define SSB_DEV_ARM_1176	0x824
247 #define SSB_DEV_ARM_7TDMI	0x825
248 #define SSB_DEV_ARM_CM3		0x82A
249 
250 /* Vendor-ID values */
251 #define SSB_VENDOR_BROADCOM	0x4243
252 
253 /* Some kernel subsystems poke with dev->drvdata, so we must use the
254  * following ugly workaround to get from struct device to struct ssb_device */
255 struct __ssb_dev_wrapper {
256 	struct device dev;
257 	struct ssb_device *sdev;
258 };
259 
260 struct ssb_device {
261 	/* Having a copy of the ops pointer in each dev struct
262 	 * is an optimization. */
263 	const struct ssb_bus_ops *ops;
264 
265 	struct device *dev, *dma_dev;
266 
267 	struct ssb_bus *bus;
268 	struct ssb_device_id id;
269 
270 	u8 core_index;
271 	unsigned int irq;
272 
273 	/* Internal-only stuff follows. */
274 	void *drvdata;		/* Per-device data */
275 	void *devtypedata;	/* Per-devicetype (eg 802.11) data */
276 };
277 
278 /* Go from struct device to struct ssb_device. */
279 static inline
280 struct ssb_device * dev_to_ssb_dev(struct device *dev)
281 {
282 	struct __ssb_dev_wrapper *wrap;
283 	wrap = container_of(dev, struct __ssb_dev_wrapper, dev);
284 	return wrap->sdev;
285 }
286 
287 /* Device specific user data */
288 static inline
289 void ssb_set_drvdata(struct ssb_device *dev, void *data)
290 {
291 	dev->drvdata = data;
292 }
293 static inline
294 void * ssb_get_drvdata(struct ssb_device *dev)
295 {
296 	return dev->drvdata;
297 }
298 
299 /* Devicetype specific user data. This is per device-type (not per device) */
300 void ssb_set_devtypedata(struct ssb_device *dev, void *data);
301 static inline
302 void * ssb_get_devtypedata(struct ssb_device *dev)
303 {
304 	return dev->devtypedata;
305 }
306 
307 
308 struct ssb_driver {
309 	const char *name;
310 	const struct ssb_device_id *id_table;
311 
312 	int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id);
313 	void (*remove)(struct ssb_device *dev);
314 	int (*suspend)(struct ssb_device *dev, pm_message_t state);
315 	int (*resume)(struct ssb_device *dev);
316 	void (*shutdown)(struct ssb_device *dev);
317 
318 	struct device_driver drv;
319 };
320 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
321 
322 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
323 #define ssb_driver_register(drv) \
324 	__ssb_driver_register(drv, THIS_MODULE)
325 
326 extern void ssb_driver_unregister(struct ssb_driver *drv);
327 
328 
329 
330 
331 enum ssb_bustype {
332 	SSB_BUSTYPE_SSB,	/* This SSB bus is the system bus */
333 	SSB_BUSTYPE_PCI,	/* SSB is connected to PCI bus */
334 	SSB_BUSTYPE_PCMCIA,	/* SSB is connected to PCMCIA bus */
335 	SSB_BUSTYPE_SDIO,	/* SSB is connected to SDIO bus */
336 };
337 
338 /* board_vendor */
339 #define SSB_BOARDVENDOR_BCM	0x14E4	/* Broadcom */
340 #define SSB_BOARDVENDOR_DELL	0x1028	/* Dell */
341 #define SSB_BOARDVENDOR_HP	0x0E11	/* HP */
342 /* board_type */
343 #define SSB_BOARD_BCM94306MP	0x0418
344 #define SSB_BOARD_BCM4309G	0x0421
345 #define SSB_BOARD_BCM4306CB	0x0417
346 #define SSB_BOARD_BCM4309MP	0x040C
347 #define SSB_BOARD_MP4318	0x044A
348 #define SSB_BOARD_BU4306	0x0416
349 #define SSB_BOARD_BU4309	0x040A
350 /* chip_package */
351 #define SSB_CHIPPACK_BCM4712S	1	/* Small 200pin 4712 */
352 #define SSB_CHIPPACK_BCM4712M	2	/* Medium 225pin 4712 */
353 #define SSB_CHIPPACK_BCM4712L	0	/* Large 340pin 4712 */
354 
355 #include <linux/ssb/ssb_driver_chipcommon.h>
356 #include <linux/ssb/ssb_driver_mips.h>
357 #include <linux/ssb/ssb_driver_extif.h>
358 #include <linux/ssb/ssb_driver_pci.h>
359 
360 struct ssb_bus {
361 	/* The MMIO area. */
362 	void __iomem *mmio;
363 
364 	const struct ssb_bus_ops *ops;
365 
366 	/* The core currently mapped into the MMIO window.
367 	 * Not valid on all host-buses. So don't use outside of SSB. */
368 	struct ssb_device *mapped_device;
369 	union {
370 		/* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
371 		u8 mapped_pcmcia_seg;
372 		/* Current SSB base address window for SDIO. */
373 		u32 sdio_sbaddr;
374 	};
375 	/* Lock for core and segment switching.
376 	 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
377 	spinlock_t bar_lock;
378 
379 	/* The host-bus this backplane is running on. */
380 	enum ssb_bustype bustype;
381 	/* Pointers to the host-bus. Check bustype before using any of these pointers. */
382 	union {
383 		/* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
384 		struct pci_dev *host_pci;
385 		/* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
386 		struct pcmcia_device *host_pcmcia;
387 		/* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
388 		struct sdio_func *host_sdio;
389 	};
390 
391 	/* See enum ssb_quirks */
392 	unsigned int quirks;
393 
394 #ifdef CONFIG_SSB_SPROM
395 	/* Mutex to protect the SPROM writing. */
396 	struct mutex sprom_mutex;
397 #endif
398 
399 	/* ID information about the Chip. */
400 	u16 chip_id;
401 	u8 chip_rev;
402 	u16 sprom_offset;
403 	u16 sprom_size;		/* number of words in sprom */
404 	u8 chip_package;
405 
406 	/* List of devices (cores) on the backplane. */
407 	struct ssb_device devices[SSB_MAX_NR_CORES];
408 	u8 nr_devices;
409 
410 	/* Software ID number for this bus. */
411 	unsigned int busnumber;
412 
413 	/* The ChipCommon device (if available). */
414 	struct ssb_chipcommon chipco;
415 	/* The PCI-core device (if available). */
416 	struct ssb_pcicore pcicore;
417 	/* The MIPS-core device (if available). */
418 	struct ssb_mipscore mipscore;
419 	/* The EXTif-core device (if available). */
420 	struct ssb_extif extif;
421 
422 	/* The following structure elements are not available in early
423 	 * SSB initialization. Though, they are available for regular
424 	 * registered drivers at any stage. So be careful when
425 	 * using them in the ssb core code. */
426 
427 	/* ID information about the PCB. */
428 	struct ssb_boardinfo boardinfo;
429 	/* Contents of the SPROM. */
430 	struct ssb_sprom sprom;
431 	/* If the board has a cardbus slot, this is set to true. */
432 	bool has_cardbus_slot;
433 
434 #ifdef CONFIG_SSB_EMBEDDED
435 	/* Lock for GPIO register access. */
436 	spinlock_t gpio_lock;
437 	struct platform_device *watchdog;
438 #endif /* EMBEDDED */
439 #ifdef CONFIG_SSB_DRIVER_GPIO
440 	struct gpio_chip gpio;
441 #endif /* DRIVER_GPIO */
442 
443 	/* Internal-only stuff follows. Do not touch. */
444 	struct list_head list;
445 #ifdef CONFIG_SSB_DEBUG
446 	/* Is the bus already powered up? */
447 	bool powered_up;
448 	int power_warn_count;
449 #endif /* DEBUG */
450 };
451 
452 enum ssb_quirks {
453 	/* SDIO connected card requires performing a read after writing a 32-bit value */
454 	SSB_QUIRK_SDIO_READ_AFTER_WRITE32	= (1 << 0),
455 };
456 
457 /* The initialization-invariants. */
458 struct ssb_init_invariants {
459 	/* Versioning information about the PCB. */
460 	struct ssb_boardinfo boardinfo;
461 	/* The SPROM information. That's either stored in an
462 	 * EEPROM or NVRAM on the board. */
463 	struct ssb_sprom sprom;
464 	/* If the board has a cardbus slot, this is set to true. */
465 	bool has_cardbus_slot;
466 };
467 /* Type of function to fetch the invariants. */
468 typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
469 				     struct ssb_init_invariants *iv);
470 
471 /* Register a SSB system bus. get_invariants() is called after the
472  * basic system devices are initialized.
473  * The invariants are usually fetched from some NVRAM.
474  * Put the invariants into the struct pointed to by iv. */
475 extern int ssb_bus_ssbbus_register(struct ssb_bus *bus,
476 				   unsigned long baseaddr,
477 				   ssb_invariants_func_t get_invariants);
478 #ifdef CONFIG_SSB_PCIHOST
479 extern int ssb_bus_pcibus_register(struct ssb_bus *bus,
480 				   struct pci_dev *host_pci);
481 #endif /* CONFIG_SSB_PCIHOST */
482 #ifdef CONFIG_SSB_PCMCIAHOST
483 extern int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
484 				      struct pcmcia_device *pcmcia_dev,
485 				      unsigned long baseaddr);
486 #endif /* CONFIG_SSB_PCMCIAHOST */
487 #ifdef CONFIG_SSB_SDIOHOST
488 extern int ssb_bus_sdiobus_register(struct ssb_bus *bus,
489 				    struct sdio_func *sdio_func,
490 				    unsigned int quirks);
491 #endif /* CONFIG_SSB_SDIOHOST */
492 
493 
494 extern void ssb_bus_unregister(struct ssb_bus *bus);
495 
496 /* Does the device have an SPROM? */
497 extern bool ssb_is_sprom_available(struct ssb_bus *bus);
498 
499 /* Set a fallback SPROM.
500  * See kdoc at the function definition for complete documentation. */
501 extern int ssb_arch_register_fallback_sprom(
502 		int (*sprom_callback)(struct ssb_bus *bus,
503 		struct ssb_sprom *out));
504 
505 /* Suspend a SSB bus.
506  * Call this from the parent bus suspend routine. */
507 extern int ssb_bus_suspend(struct ssb_bus *bus);
508 /* Resume a SSB bus.
509  * Call this from the parent bus resume routine. */
510 extern int ssb_bus_resume(struct ssb_bus *bus);
511 
512 extern u32 ssb_clockspeed(struct ssb_bus *bus);
513 
514 /* Is the device enabled in hardware? */
515 int ssb_device_is_enabled(struct ssb_device *dev);
516 /* Enable a device and pass device-specific SSB_TMSLOW flags.
517  * If no device-specific flags are available, use 0. */
518 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags);
519 /* Disable a device in hardware and pass SSB_TMSLOW flags (if any). */
520 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags);
521 
522 
523 /* Device MMIO register read/write functions. */
524 static inline u8 ssb_read8(struct ssb_device *dev, u16 offset)
525 {
526 	return dev->ops->read8(dev, offset);
527 }
528 static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
529 {
530 	return dev->ops->read16(dev, offset);
531 }
532 static inline u32 ssb_read32(struct ssb_device *dev, u16 offset)
533 {
534 	return dev->ops->read32(dev, offset);
535 }
536 static inline void ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
537 {
538 	dev->ops->write8(dev, offset, value);
539 }
540 static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
541 {
542 	dev->ops->write16(dev, offset, value);
543 }
544 static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
545 {
546 	dev->ops->write32(dev, offset, value);
547 }
548 #ifdef CONFIG_SSB_BLOCKIO
549 static inline void ssb_block_read(struct ssb_device *dev, void *buffer,
550 				  size_t count, u16 offset, u8 reg_width)
551 {
552 	dev->ops->block_read(dev, buffer, count, offset, reg_width);
553 }
554 
555 static inline void ssb_block_write(struct ssb_device *dev, const void *buffer,
556 				   size_t count, u16 offset, u8 reg_width)
557 {
558 	dev->ops->block_write(dev, buffer, count, offset, reg_width);
559 }
560 #endif /* CONFIG_SSB_BLOCKIO */
561 
562 
563 /* The SSB DMA API. Use this API for any DMA operation on the device.
564  * This API basically is a wrapper that calls the correct DMA API for
565  * the host device type the SSB device is attached to. */
566 
567 /* Translation (routing) bits that need to be ORed to DMA
568  * addresses before they are given to a device. */
569 extern u32 ssb_dma_translation(struct ssb_device *dev);
570 #define SSB_DMA_TRANSLATION_MASK	0xC0000000
571 #define SSB_DMA_TRANSLATION_SHIFT	30
572 
573 static inline void __cold __ssb_dma_not_implemented(struct ssb_device *dev)
574 {
575 #ifdef CONFIG_SSB_DEBUG
576 	printk(KERN_ERR "SSB: BUG! Calling DMA API for "
577 	       "unsupported bustype %d\n", dev->bus->bustype);
578 #endif /* DEBUG */
579 }
580 
581 #ifdef CONFIG_SSB_PCIHOST
582 /* PCI-host wrapper driver */
583 extern int ssb_pcihost_register(struct pci_driver *driver);
584 static inline void ssb_pcihost_unregister(struct pci_driver *driver)
585 {
586 	pci_unregister_driver(driver);
587 }
588 
589 static inline
590 void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
591 {
592 	if (sdev->bus->bustype == SSB_BUSTYPE_PCI)
593 		pci_set_power_state(sdev->bus->host_pci, state);
594 }
595 #else
596 static inline void ssb_pcihost_unregister(struct pci_driver *driver)
597 {
598 }
599 
600 static inline
601 void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
602 {
603 }
604 #endif /* CONFIG_SSB_PCIHOST */
605 
606 
607 /* If a driver is shutdown or suspended, call this to signal
608  * that the bus may be completely powered down. SSB will decide,
609  * if it's really time to power down the bus, based on if there
610  * are other devices that want to run. */
611 extern int ssb_bus_may_powerdown(struct ssb_bus *bus);
612 /* Before initializing and enabling a device, call this to power-up the bus.
613  * If you want to allow use of dynamic-power-control, pass the flag.
614  * Otherwise static always-on powercontrol will be used. */
615 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
616 
617 extern void ssb_commit_settings(struct ssb_bus *bus);
618 
619 /* Various helper functions */
620 extern u32 ssb_admatch_base(u32 adm);
621 extern u32 ssb_admatch_size(u32 adm);
622 
623 /* PCI device mapping and fixup routines.
624  * Called from the architecture pcibios init code.
625  * These are only available on SSB_EMBEDDED configurations. */
626 #ifdef CONFIG_SSB_EMBEDDED
627 int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
628 int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
629 #endif /* CONFIG_SSB_EMBEDDED */
630 
631 #endif /* LINUX_SSB_H_ */
632