1 /* 2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com 4 * 5 * EXYNOS - Power management unit definition 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * 12 * Notice: 13 * This is not a list of all Exynos Power Management Unit SFRs. 14 * There are too many of them, not mentioning subtle differences 15 * between SoCs. For now, put here only the used registers. 16 */ 17 18 #ifndef __LINUX_SOC_EXYNOS_REGS_PMU_H 19 #define __LINUX_SOC_EXYNOS_REGS_PMU_H __FILE__ 20 21 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200 22 23 #define S5P_CENTRAL_LOWPWR_CFG (1 << 16) 24 25 #define S5P_CENTRAL_SEQ_OPTION 0x0208 26 27 #define S5P_USE_STANDBY_WFI0 (1 << 16) 28 #define S5P_USE_STANDBY_WFI1 (1 << 17) 29 #define S5P_USE_STANDBY_WFI2 (1 << 19) 30 #define S5P_USE_STANDBY_WFI3 (1 << 20) 31 #define S5P_USE_STANDBY_WFE0 (1 << 24) 32 #define S5P_USE_STANDBY_WFE1 (1 << 25) 33 #define S5P_USE_STANDBY_WFE2 (1 << 27) 34 #define S5P_USE_STANDBY_WFE3 (1 << 28) 35 36 #define S5P_USE_STANDBY_WFI_ALL \ 37 (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFI1 | \ 38 S5P_USE_STANDBY_WFI2 | S5P_USE_STANDBY_WFI3 | \ 39 S5P_USE_STANDBY_WFE0 | S5P_USE_STANDBY_WFE1 | \ 40 S5P_USE_STANDBY_WFE2 | S5P_USE_STANDBY_WFE3) 41 42 #define S5P_USE_DELAYED_RESET_ASSERTION BIT(12) 43 44 #define EXYNOS_CORE_PO_RESET(n) ((1 << 4) << n) 45 #define EXYNOS_WAKEUP_FROM_LOWPWR (1 << 28) 46 #define EXYNOS_SWRESET 0x0400 47 48 #define S5P_WAKEUP_STAT 0x0600 49 #define S5P_EINT_WAKEUP_MASK 0x0604 50 #define S5P_WAKEUP_MASK 0x0608 51 #define S5P_WAKEUP_MASK2 0x0614 52 53 #define S5P_INFORM0 0x0800 54 #define S5P_INFORM1 0x0804 55 #define S5P_INFORM5 0x0814 56 #define S5P_INFORM6 0x0818 57 #define S5P_INFORM7 0x081C 58 #define S5P_PMU_SPARE2 0x0908 59 #define S5P_PMU_SPARE3 0x090C 60 61 #define EXYNOS_IROM_DATA2 0x0988 62 #define S5P_ARM_CORE0_LOWPWR 0x1000 63 #define S5P_DIS_IRQ_CORE0 0x1004 64 #define S5P_DIS_IRQ_CENTRAL0 0x1008 65 #define S5P_ARM_CORE1_LOWPWR 0x1010 66 #define S5P_DIS_IRQ_CORE1 0x1014 67 #define S5P_DIS_IRQ_CENTRAL1 0x1018 68 #define S5P_ARM_COMMON_LOWPWR 0x1080 69 #define S5P_L2_0_LOWPWR 0x10C0 70 #define S5P_L2_1_LOWPWR 0x10C4 71 #define S5P_CMU_ACLKSTOP_LOWPWR 0x1100 72 #define S5P_CMU_SCLKSTOP_LOWPWR 0x1104 73 #define S5P_CMU_RESET_LOWPWR 0x110C 74 #define S5P_APLL_SYSCLK_LOWPWR 0x1120 75 #define S5P_MPLL_SYSCLK_LOWPWR 0x1124 76 #define S5P_VPLL_SYSCLK_LOWPWR 0x1128 77 #define S5P_EPLL_SYSCLK_LOWPWR 0x112C 78 #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 0x1138 79 #define S5P_CMU_RESET_GPSALIVE_LOWPWR 0x113C 80 #define S5P_CMU_CLKSTOP_CAM_LOWPWR 0x1140 81 #define S5P_CMU_CLKSTOP_TV_LOWPWR 0x1144 82 #define S5P_CMU_CLKSTOP_MFC_LOWPWR 0x1148 83 #define S5P_CMU_CLKSTOP_G3D_LOWPWR 0x114C 84 #define S5P_CMU_CLKSTOP_LCD0_LOWPWR 0x1150 85 #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 0x1158 86 #define S5P_CMU_CLKSTOP_GPS_LOWPWR 0x115C 87 #define S5P_CMU_RESET_CAM_LOWPWR 0x1160 88 #define S5P_CMU_RESET_TV_LOWPWR 0x1164 89 #define S5P_CMU_RESET_MFC_LOWPWR 0x1168 90 #define S5P_CMU_RESET_G3D_LOWPWR 0x116C 91 #define S5P_CMU_RESET_LCD0_LOWPWR 0x1170 92 #define S5P_CMU_RESET_MAUDIO_LOWPWR 0x1178 93 #define S5P_CMU_RESET_GPS_LOWPWR 0x117C 94 #define S5P_TOP_BUS_LOWPWR 0x1180 95 #define S5P_TOP_RETENTION_LOWPWR 0x1184 96 #define S5P_TOP_PWR_LOWPWR 0x1188 97 #define S5P_LOGIC_RESET_LOWPWR 0x11A0 98 #define S5P_ONENAND_MEM_LOWPWR 0x11C0 99 #define S5P_G2D_ACP_MEM_LOWPWR 0x11C8 100 #define S5P_USBOTG_MEM_LOWPWR 0x11CC 101 #define S5P_HSMMC_MEM_LOWPWR 0x11D0 102 #define S5P_CSSYS_MEM_LOWPWR 0x11D4 103 #define S5P_SECSS_MEM_LOWPWR 0x11D8 104 #define S5P_PAD_RETENTION_DRAM_LOWPWR 0x1200 105 #define S5P_PAD_RETENTION_MAUDIO_LOWPWR 0x1204 106 #define S5P_PAD_RETENTION_GPIO_LOWPWR 0x1220 107 #define S5P_PAD_RETENTION_UART_LOWPWR 0x1224 108 #define S5P_PAD_RETENTION_MMCA_LOWPWR 0x1228 109 #define S5P_PAD_RETENTION_MMCB_LOWPWR 0x122C 110 #define S5P_PAD_RETENTION_EBIA_LOWPWR 0x1230 111 #define S5P_PAD_RETENTION_EBIB_LOWPWR 0x1234 112 #define S5P_PAD_RETENTION_ISOLATION_LOWPWR 0x1240 113 #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 0x1260 114 #define S5P_XUSBXTI_LOWPWR 0x1280 115 #define S5P_XXTI_LOWPWR 0x1284 116 #define S5P_EXT_REGULATOR_LOWPWR 0x12C0 117 #define S5P_GPIO_MODE_LOWPWR 0x1300 118 #define S5P_GPIO_MODE_MAUDIO_LOWPWR 0x1340 119 #define S5P_CAM_LOWPWR 0x1380 120 #define S5P_TV_LOWPWR 0x1384 121 #define S5P_MFC_LOWPWR 0x1388 122 #define S5P_G3D_LOWPWR 0x138C 123 #define S5P_LCD0_LOWPWR 0x1390 124 #define S5P_MAUDIO_LOWPWR 0x1398 125 #define S5P_GPS_LOWPWR 0x139C 126 #define S5P_GPS_ALIVE_LOWPWR 0x13A0 127 128 #define EXYNOS_ARM_CORE0_CONFIGURATION 0x2000 129 #define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \ 130 (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr))) 131 #define EXYNOS_ARM_CORE_STATUS(_nr) \ 132 (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4) 133 #define EXYNOS_ARM_CORE_OPTION(_nr) \ 134 (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x8) 135 136 #define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500 137 #define EXYNOS_COMMON_CONFIGURATION(_nr) \ 138 (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr))) 139 #define EXYNOS_COMMON_STATUS(_nr) \ 140 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4) 141 #define EXYNOS_COMMON_OPTION(_nr) \ 142 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8) 143 144 #define EXYNOS_ARM_L2_CONFIGURATION 0x2600 145 #define EXYNOS_L2_CONFIGURATION(_nr) \ 146 (EXYNOS_ARM_L2_CONFIGURATION + ((_nr) * 0x80)) 147 #define EXYNOS_L2_STATUS(_nr) \ 148 (EXYNOS_L2_CONFIGURATION(_nr) + 0x4) 149 #define EXYNOS_L2_OPTION(_nr) \ 150 (EXYNOS_L2_CONFIGURATION(_nr) + 0x8) 151 152 #define EXYNOS_L2_USE_RETENTION BIT(4) 153 154 #define S5P_PAD_RET_MAUDIO_OPTION 0x3028 155 #define S5P_PAD_RET_MMC2_OPTION 0x30c8 156 #define S5P_PAD_RET_GPIO_OPTION 0x3108 157 #define S5P_PAD_RET_UART_OPTION 0x3128 158 #define S5P_PAD_RET_MMCA_OPTION 0x3148 159 #define S5P_PAD_RET_MMCB_OPTION 0x3168 160 #define S5P_PAD_RET_EBIA_OPTION 0x3188 161 #define S5P_PAD_RET_EBIB_OPTION 0x31A8 162 #define S5P_PAD_RET_SPI_OPTION 0x31c8 163 164 #define S5P_PS_HOLD_CONTROL 0x330C 165 #define S5P_PS_HOLD_EN (1 << 31) 166 #define S5P_PS_HOLD_OUTPUT_HIGH (3 << 8) 167 168 #define S5P_CAM_OPTION 0x3C08 169 #define S5P_MFC_OPTION 0x3C48 170 #define S5P_G3D_OPTION 0x3C68 171 #define S5P_LCD0_OPTION 0x3C88 172 #define S5P_LCD1_OPTION 0x3CA8 173 #define S5P_ISP_OPTION S5P_LCD1_OPTION 174 175 #define S5P_CORE_LOCAL_PWR_EN 0x3 176 #define S5P_CORE_WAKEUP_FROM_LOCAL_CFG (0x3 << 8) 177 #define S5P_CORE_AUTOWAKEUP_EN (1 << 31) 178 179 /* Only for EXYNOS4210 */ 180 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154 181 #define S5P_CMU_RESET_LCD1_LOWPWR 0x1174 182 #define S5P_MODIMIF_MEM_LOWPWR 0x11C4 183 #define S5P_PCIE_MEM_LOWPWR 0x11E0 184 #define S5P_SATA_MEM_LOWPWR 0x11E4 185 #define S5P_LCD1_LOWPWR 0x1394 186 187 /* Only for EXYNOS4x12 */ 188 #define S5P_ISP_ARM_LOWPWR 0x1050 189 #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 0x1054 190 #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 0x1058 191 #define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 0x1110 192 #define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 0x1114 193 #define S5P_CMU_RESET_COREBLK_LOWPWR 0x111C 194 #define S5P_MPLLUSER_SYSCLK_LOWPWR 0x1130 195 #define S5P_CMU_CLKSTOP_ISP_LOWPWR 0x1154 196 #define S5P_CMU_RESET_ISP_LOWPWR 0x1174 197 #define S5P_TOP_BUS_COREBLK_LOWPWR 0x1190 198 #define S5P_TOP_RETENTION_COREBLK_LOWPWR 0x1194 199 #define S5P_TOP_PWR_COREBLK_LOWPWR 0x1198 200 #define S5P_OSCCLK_GATE_LOWPWR 0x11A4 201 #define S5P_LOGIC_RESET_COREBLK_LOWPWR 0x11B0 202 #define S5P_OSCCLK_GATE_COREBLK_LOWPWR 0x11B4 203 #define S5P_HSI_MEM_LOWPWR 0x11C4 204 #define S5P_ROTATOR_MEM_LOWPWR 0x11DC 205 #define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 0x123C 206 #define S5P_PAD_ISOLATION_COREBLK_LOWPWR 0x1250 207 #define S5P_GPIO_MODE_COREBLK_LOWPWR 0x1320 208 #define S5P_TOP_ASB_RESET_LOWPWR 0x1344 209 #define S5P_TOP_ASB_ISOLATION_LOWPWR 0x1348 210 #define S5P_ISP_LOWPWR 0x1394 211 #define S5P_DRAM_FREQ_DOWN_LOWPWR 0x13B0 212 #define S5P_DDRPHY_DLLOFF_LOWPWR 0x13B4 213 #define S5P_CMU_SYSCLK_ISP_LOWPWR 0x13B8 214 #define S5P_CMU_SYSCLK_GPS_LOWPWR 0x13BC 215 #define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 0x13C0 216 217 #define S5P_ARM_L2_0_OPTION 0x2608 218 #define S5P_ARM_L2_1_OPTION 0x2628 219 #define S5P_ONENAND_MEM_OPTION 0x2E08 220 #define S5P_HSI_MEM_OPTION 0x2E28 221 #define S5P_G2D_ACP_MEM_OPTION 0x2E48 222 #define S5P_USBOTG_MEM_OPTION 0x2E68 223 #define S5P_HSMMC_MEM_OPTION 0x2E88 224 #define S5P_CSSYS_MEM_OPTION 0x2EA8 225 #define S5P_SECSS_MEM_OPTION 0x2EC8 226 #define S5P_ROTATOR_MEM_OPTION 0x2F48 227 228 /* Only for EXYNOS4412 */ 229 #define S5P_ARM_CORE2_LOWPWR 0x1020 230 #define S5P_DIS_IRQ_CORE2 0x1024 231 #define S5P_DIS_IRQ_CENTRAL2 0x1028 232 #define S5P_ARM_CORE3_LOWPWR 0x1030 233 #define S5P_DIS_IRQ_CORE3 0x1034 234 #define S5P_DIS_IRQ_CENTRAL3 0x1038 235 236 /* Only for EXYNOS3XXX */ 237 #define EXYNOS3_ARM_CORE0_SYS_PWR_REG 0x1000 238 #define EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004 239 #define EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008 240 #define EXYNOS3_ARM_CORE1_SYS_PWR_REG 0x1010 241 #define EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014 242 #define EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018 243 #define EXYNOS3_ISP_ARM_SYS_PWR_REG 0x1050 244 #define EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054 245 #define EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058 246 #define EXYNOS3_ARM_COMMON_SYS_PWR_REG 0x1080 247 #define EXYNOS3_ARM_L2_SYS_PWR_REG 0x10C0 248 #define EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG 0x1100 249 #define EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG 0x1104 250 #define EXYNOS3_CMU_RESET_SYS_PWR_REG 0x110C 251 #define EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG 0x1110 252 #define EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG 0x1114 253 #define EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG 0x111C 254 #define EXYNOS3_APLL_SYSCLK_SYS_PWR_REG 0x1120 255 #define EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG 0x1124 256 #define EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG 0x1128 257 #define EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG 0x112C 258 #define EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1130 259 #define EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1134 260 #define EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG 0x1138 261 #define EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG 0x1140 262 #define EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1148 263 #define EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x114C 264 #define EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG 0x1150 265 #define EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1154 266 #define EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG 0x1158 267 #define EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG 0x1160 268 #define EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG 0x1168 269 #define EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG 0x116C 270 #define EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG 0x1170 271 #define EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG 0x1174 272 #define EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG 0x1178 273 #define EXYNOS3_TOP_BUS_SYS_PWR_REG 0x1180 274 #define EXYNOS3_TOP_RETENTION_SYS_PWR_REG 0x1184 275 #define EXYNOS3_TOP_PWR_SYS_PWR_REG 0x1188 276 #define EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG 0x1190 277 #define EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG 0x1194 278 #define EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG 0x1198 279 #define EXYNOS3_LOGIC_RESET_SYS_PWR_REG 0x11A0 280 #define EXYNOS3_OSCCLK_GATE_SYS_PWR_REG 0x11A4 281 #define EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG 0x11B0 282 #define EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG 0x11B4 283 #define EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200 284 #define EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG 0x1204 285 #define EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG 0x1208 286 #define EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1218 287 #define EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220 288 #define EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG 0x1224 289 #define EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1228 290 #define EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG 0x122C 291 #define EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230 292 #define EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234 293 #define EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1238 294 #define EXYNOS3_PAD_ISOLATION_SYS_PWR_REG 0x1240 295 #define EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG 0x1260 296 #define EXYNOS3_XUSBXTI_SYS_PWR_REG 0x1280 297 #define EXYNOS3_XXTI_SYS_PWR_REG 0x1284 298 #define EXYNOS3_EXT_REGULATOR_SYS_PWR_REG 0x12C0 299 #define EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG 0x12C4 300 #define EXYNOS3_GPIO_MODE_SYS_PWR_REG 0x1300 301 #define EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG 0x1340 302 #define EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG 0x1344 303 #define EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348 304 #define EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG 0x1350 305 #define EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG 0x1354 306 #define EXYNOS3_CAM_SYS_PWR_REG 0x1380 307 #define EXYNOS3_MFC_SYS_PWR_REG 0x1388 308 #define EXYNOS3_G3D_SYS_PWR_REG 0x138C 309 #define EXYNOS3_LCD0_SYS_PWR_REG 0x1390 310 #define EXYNOS3_ISP_SYS_PWR_REG 0x1394 311 #define EXYNOS3_MAUDIO_SYS_PWR_REG 0x1398 312 #define EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG 0x13B0 313 #define EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG 0x13B4 314 #define EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG 0x13B8 315 #define EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG 0x13C0 316 #define EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG 0x13C4 317 #define EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG 0x13C8 318 319 #define EXYNOS3_ARM_CORE0_OPTION 0x2008 320 #define EXYNOS3_ARM_CORE_OPTION(_nr) \ 321 (EXYNOS3_ARM_CORE0_OPTION + ((_nr) * 0x80)) 322 323 #define EXYNOS3_ARM_COMMON_OPTION 0x2408 324 #define EXYNOS3_ARM_L2_OPTION 0x2608 325 #define EXYNOS3_TOP_PWR_OPTION 0x2C48 326 #define EXYNOS3_CORE_TOP_PWR_OPTION 0x2CA8 327 #define EXYNOS3_XUSBXTI_DURATION 0x341C 328 #define EXYNOS3_XXTI_DURATION 0x343C 329 #define EXYNOS3_EXT_REGULATOR_DURATION 0x361C 330 #define EXYNOS3_EXT_REGULATOR_COREBLK_DURATION 0x363C 331 #define XUSBXTI_DURATION 0x00000BB8 332 #define XXTI_DURATION XUSBXTI_DURATION 333 #define EXT_REGULATOR_DURATION 0x00001D4C 334 #define EXT_REGULATOR_COREBLK_DURATION EXT_REGULATOR_DURATION 335 336 /* for XXX_OPTION */ 337 #define EXYNOS3_OPTION_USE_SC_COUNTER (1 << 0) 338 #define EXYNOS3_OPTION_USE_SC_FEEDBACK (1 << 1) 339 #define EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7) 340 341 /* For EXYNOS5 */ 342 343 #define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408 344 #define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C 345 346 #define EXYNOS5_USE_RETENTION BIT(4) 347 #define EXYNOS5_SYS_WDTRESET (1 << 20) 348 349 #define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000 350 #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004 351 #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008 352 #define EXYNOS5_ARM_CORE1_SYS_PWR_REG 0x1010 353 #define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014 354 #define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018 355 #define EXYNOS5_FSYS_ARM_SYS_PWR_REG 0x1040 356 #define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG 0x1048 357 #define EXYNOS5_ISP_ARM_SYS_PWR_REG 0x1050 358 #define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054 359 #define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058 360 #define EXYNOS5_ARM_COMMON_SYS_PWR_REG 0x1080 361 #define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0 362 #define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 0x1100 363 #define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 0x1104 364 #define EXYNOS5_CMU_RESET_SYS_PWR_REG 0x110C 365 #define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG 0x1120 366 #define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG 0x1124 367 #define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 0x112C 368 #define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 0x1130 369 #define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 0x1134 370 #define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 0x1138 371 #define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 0x1140 372 #define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 0x1144 373 #define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 0x1148 374 #define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 0x114C 375 #define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 0x1150 376 #define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 0x1154 377 #define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1164 378 #define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1170 379 #define EXYNOS5_TOP_BUS_SYS_PWR_REG 0x1180 380 #define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 0x1184 381 #define EXYNOS5_TOP_PWR_SYS_PWR_REG 0x1188 382 #define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 0x1190 383 #define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG 0x1194 384 #define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 0x1198 385 #define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 0x11A0 386 #define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4 387 #define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 0x11B0 388 #define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4 389 #define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 0x11C0 390 #define EXYNOS5_G2D_MEM_SYS_PWR_REG 0x11C8 391 #define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 0x11CC 392 #define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 0x11D0 393 #define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 0x11D4 394 #define EXYNOS5_SECSS_MEM_SYS_PWR_REG 0x11D8 395 #define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 0x11DC 396 #define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 0x11E0 397 #define EXYNOS5_INTROM_MEM_SYS_PWR_REG 0x11E4 398 #define EXYNOS5_JPEG_MEM_SYS_PWR_REG 0x11E8 399 #define EXYNOS5_HSI_MEM_SYS_PWR_REG 0x11EC 400 #define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 0x11F4 401 #define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC 402 #define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200 403 #define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204 404 #define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220 405 #define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224 406 #define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228 407 #define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C 408 #define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230 409 #define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234 410 #define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238 411 #define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG 0x123C 412 #define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 0x1240 413 #define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG 0x1250 414 #define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260 415 #define EXYNOS5_XUSBXTI_SYS_PWR_REG 0x1280 416 #define EXYNOS5_XXTI_SYS_PWR_REG 0x1284 417 #define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 0x12C0 418 #define EXYNOS5_GPIO_MODE_SYS_PWR_REG 0x1300 419 #define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 0x1320 420 #define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 0x1340 421 #define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 0x1344 422 #define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348 423 #define EXYNOS5_GSCL_SYS_PWR_REG 0x1400 424 #define EXYNOS5_ISP_SYS_PWR_REG 0x1404 425 #define EXYNOS5_MFC_SYS_PWR_REG 0x1408 426 #define EXYNOS5_G3D_SYS_PWR_REG 0x140C 427 #define EXYNOS5_DISP1_SYS_PWR_REG 0x1414 428 #define EXYNOS5_MAU_SYS_PWR_REG 0x1418 429 #define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 0x1480 430 #define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1484 431 #define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1488 432 #define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x148C 433 #define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1494 434 #define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1498 435 #define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0 436 #define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 0x14C4 437 #define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 0x14C8 438 #define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 0x14CC 439 #define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D4 440 #define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D8 441 #define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 0x1580 442 #define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 0x1584 443 #define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 0x1588 444 #define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 0x158C 445 #define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 0x1594 446 #define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 0x1598 447 448 #define EXYNOS5_ARM_CORE0_OPTION 0x2008 449 #define EXYNOS5_ARM_CORE1_OPTION 0x2088 450 #define EXYNOS5_FSYS_ARM_OPTION 0x2208 451 #define EXYNOS5_ISP_ARM_OPTION 0x2288 452 #define EXYNOS5_ARM_COMMON_OPTION 0x2408 453 #define EXYNOS5_ARM_L2_OPTION 0x2608 454 #define EXYNOS5_TOP_PWR_OPTION 0x2C48 455 #define EXYNOS5_TOP_PWR_SYSMEM_OPTION 0x2CC8 456 #define EXYNOS5_JPEG_MEM_OPTION 0x2F48 457 #define EXYNOS5_GSCL_OPTION 0x4008 458 #define EXYNOS5_ISP_OPTION 0x4028 459 #define EXYNOS5_MFC_OPTION 0x4048 460 #define EXYNOS5_G3D_OPTION 0x4068 461 #define EXYNOS5_DISP1_OPTION 0x40A8 462 #define EXYNOS5_MAU_OPTION 0x40C8 463 464 #define EXYNOS5_USE_SC_FEEDBACK (1 << 1) 465 #define EXYNOS5_USE_SC_COUNTER (1 << 0) 466 467 #define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7) 468 469 #define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24) 470 #define EXYNOS5_OPTION_USE_STANDBYWFI (1 << 16) 471 472 #define EXYNOS5_OPTION_USE_RETENTION (1 << 4) 473 474 #define EXYNOS5420_SWRESET_KFC_SEL 0x3 475 476 /* Only for EXYNOS5420 */ 477 #define EXYNOS5420_L2RSTDISABLE_VALUE BIT(3) 478 479 #define EXYNOS5420_LPI_MASK 0x0004 480 #define EXYNOS5420_LPI_MASK1 0x0008 481 #define EXYNOS5420_UFS BIT(8) 482 #define EXYNOS5420_ATB_KFC BIT(13) 483 #define EXYNOS5420_ATB_ISP_ARM BIT(19) 484 #define EXYNOS5420_EMULATION BIT(31) 485 486 #define EXYNOS5420_ARM_INTR_SPREAD_ENABLE 0x0100 487 #define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI 0x0104 488 #define EXYNOS5420_UP_SCHEDULER 0x0120 489 #define SPREAD_ENABLE 0xF 490 #define SPREAD_USE_STANDWFI 0xF 491 492 #define EXYNOS5420_KFC_CORE_RESET0 BIT(8) 493 #define EXYNOS5420_KFC_ETM_RESET0 BIT(20) 494 495 #define EXYNOS5420_KFC_CORE_RESET(_nr) \ 496 ((EXYNOS5420_KFC_CORE_RESET0 | EXYNOS5420_KFC_ETM_RESET0) << (_nr)) 497 498 #define EXYNOS5420_ARM_CORE2_SYS_PWR_REG 0x1020 499 #define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG 0x1024 500 #define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG 0x1028 501 #define EXYNOS5420_ARM_CORE3_SYS_PWR_REG 0x1030 502 #define EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG 0x1034 503 #define EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG 0x1038 504 #define EXYNOS5420_KFC_CORE0_SYS_PWR_REG 0x1040 505 #define EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG 0x1044 506 #define EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG 0x1048 507 #define EXYNOS5420_KFC_CORE1_SYS_PWR_REG 0x1050 508 #define EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG 0x1054 509 #define EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG 0x1058 510 #define EXYNOS5420_KFC_CORE2_SYS_PWR_REG 0x1060 511 #define EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG 0x1064 512 #define EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG 0x1068 513 #define EXYNOS5420_KFC_CORE3_SYS_PWR_REG 0x1070 514 #define EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG 0x1074 515 #define EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG 0x1078 516 #define EXYNOS5420_ISP_ARM_SYS_PWR_REG 0x1090 517 #define EXYNOS5420_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1094 518 #define EXYNOS5420_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1098 519 #define EXYNOS5420_ARM_COMMON_SYS_PWR_REG 0x10A0 520 #define EXYNOS5420_KFC_COMMON_SYS_PWR_REG 0x10B0 521 #define EXYNOS5420_KFC_L2_SYS_PWR_REG 0x10D0 522 #define EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG 0x1158 523 #define EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG 0x115C 524 #define EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG 0x1160 525 #define EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG 0x1174 526 #define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG 0x1178 527 #define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG 0x11B8 528 #define EXYNOS5420_INTROM_MEM_SYS_PWR_REG 0x11BC 529 #define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1208 530 #define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1210 531 #define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG 0x1214 532 #define EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1218 533 #define EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG 0x121C 534 #define EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1220 535 #define EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG 0x1224 536 #define EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1228 537 #define EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG 0x122C 538 #define EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG 0x1230 539 #define EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG 0x1234 540 #define EXYNOS5420_DISP1_SYS_PWR_REG 0x1410 541 #define EXYNOS5420_MAU_SYS_PWR_REG 0x1414 542 #define EXYNOS5420_G2D_SYS_PWR_REG 0x1418 543 #define EXYNOS5420_MSC_SYS_PWR_REG 0x141C 544 #define EXYNOS5420_FSYS_SYS_PWR_REG 0x1420 545 #define EXYNOS5420_FSYS2_SYS_PWR_REG 0x1424 546 #define EXYNOS5420_PSGEN_SYS_PWR_REG 0x1428 547 #define EXYNOS5420_PERIC_SYS_PWR_REG 0x142C 548 #define EXYNOS5420_WCORE_SYS_PWR_REG 0x1430 549 #define EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1490 550 #define EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1494 551 #define EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG 0x1498 552 #define EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG 0x149C 553 #define EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG 0x14A0 554 #define EXYNOS5420_CMU_CLKSTOP_FSYS2_SYS_PWR_REG 0x14A4 555 #define EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG 0x14A8 556 #define EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG 0x14AC 557 #define EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG 0x14B0 558 #define EXYNOS5420_CMU_SYSCLK_TOPPWR_SYS_PWR_REG 0x14BC 559 #define EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D0 560 #define EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D4 561 #define EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG 0x14D8 562 #define EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG 0x14DC 563 #define EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG 0x14E0 564 #define EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG 0x14E4 565 #define EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG 0x14E8 566 #define EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG 0x14EC 567 #define EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG 0x14F0 568 #define EXYNOS5420_CMU_SYSCLK_SYSMEM_TOPPWR_SYS_PWR_REG 0x14F4 569 #define EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG 0x1570 570 #define EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG 0x1574 571 #define EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG 0x1578 572 #define EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG 0x157C 573 #define EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG 0x1590 574 #define EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG 0x1594 575 #define EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG 0x1598 576 #define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG 0x159C 577 #define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG 0x15A0 578 #define EXYNOS5420_SFR_AXI_CGDIS1 0x15E4 579 #define EXYNOS5420_ARM_COMMON_OPTION 0x2508 580 #define EXYNOS5420_KFC_COMMON_OPTION 0x2588 581 #define EXYNOS5420_LOGIC_RESET_DURATION3 0x2D1C 582 583 #define EXYNOS5420_PAD_RET_GPIO_OPTION 0x30C8 584 #define EXYNOS5420_PAD_RET_UART_OPTION 0x30E8 585 #define EXYNOS5420_PAD_RET_MMCA_OPTION 0x3108 586 #define EXYNOS5420_PAD_RET_MMCB_OPTION 0x3128 587 #define EXYNOS5420_PAD_RET_MMCC_OPTION 0x3148 588 #define EXYNOS5420_PAD_RET_HSI_OPTION 0x3168 589 #define EXYNOS5420_PAD_RET_SPI_OPTION 0x31C8 590 #define EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION 0x31E8 591 #define EXYNOS_PAD_RET_DRAM_OPTION 0x3008 592 #define EXYNOS_PAD_RET_MAUDIO_OPTION 0x3028 593 #define EXYNOS_PAD_RET_JTAG_OPTION 0x3048 594 #define EXYNOS_PAD_RET_EBIA_OPTION 0x3188 595 #define EXYNOS_PAD_RET_EBIB_OPTION 0x31A8 596 597 #define EXYNOS5420_FSYS2_OPTION 0x4168 598 #define EXYNOS5420_PSGEN_OPTION 0x4188 599 600 /* For EXYNOS_CENTRAL_SEQ_OPTION */ 601 #define EXYNOS5_USE_STANDBYWFI_ARM_CORE0 BIT(16) 602 #define EXYNOS5_USE_STANDBYWFI_ARM_CORE1 BUT(17) 603 #define EXYNOS5_USE_STANDBYWFE_ARM_CORE0 BIT(24) 604 #define EXYNOS5_USE_STANDBYWFE_ARM_CORE1 BIT(25) 605 606 #define EXYNOS5420_ARM_USE_STANDBY_WFI0 BIT(4) 607 #define EXYNOS5420_ARM_USE_STANDBY_WFI1 BIT(5) 608 #define EXYNOS5420_ARM_USE_STANDBY_WFI2 BIT(6) 609 #define EXYNOS5420_ARM_USE_STANDBY_WFI3 BIT(7) 610 #define EXYNOS5420_KFC_USE_STANDBY_WFI0 BIT(8) 611 #define EXYNOS5420_KFC_USE_STANDBY_WFI1 BIT(9) 612 #define EXYNOS5420_KFC_USE_STANDBY_WFI2 BIT(10) 613 #define EXYNOS5420_KFC_USE_STANDBY_WFI3 BIT(11) 614 #define EXYNOS5420_ARM_USE_STANDBY_WFE0 BIT(16) 615 #define EXYNOS5420_ARM_USE_STANDBY_WFE1 BIT(17) 616 #define EXYNOS5420_ARM_USE_STANDBY_WFE2 BIT(18) 617 #define EXYNOS5420_ARM_USE_STANDBY_WFE3 BIT(19) 618 #define EXYNOS5420_KFC_USE_STANDBY_WFE0 BIT(20) 619 #define EXYNOS5420_KFC_USE_STANDBY_WFE1 BIT(21) 620 #define EXYNOS5420_KFC_USE_STANDBY_WFE2 BIT(22) 621 #define EXYNOS5420_KFC_USE_STANDBY_WFE3 BIT(23) 622 623 #define DUR_WAIT_RESET 0xF 624 625 #define EXYNOS5420_USE_STANDBY_WFI_ALL (EXYNOS5420_ARM_USE_STANDBY_WFI0 \ 626 | EXYNOS5420_ARM_USE_STANDBY_WFI1 \ 627 | EXYNOS5420_ARM_USE_STANDBY_WFI2 \ 628 | EXYNOS5420_ARM_USE_STANDBY_WFI3 \ 629 | EXYNOS5420_KFC_USE_STANDBY_WFI0 \ 630 | EXYNOS5420_KFC_USE_STANDBY_WFI1 \ 631 | EXYNOS5420_KFC_USE_STANDBY_WFI2 \ 632 | EXYNOS5420_KFC_USE_STANDBY_WFI3) 633 634 /* For EXYNOS5433 */ 635 #define EXYNOS5433_PAD_RETENTION_AUD_OPTION (0x3028) 636 #define EXYNOS5433_PAD_RETENTION_MMC2_OPTION (0x30C8) 637 #define EXYNOS5433_PAD_RETENTION_TOP_OPTION (0x3108) 638 #define EXYNOS5433_PAD_RETENTION_UART_OPTION (0x3128) 639 #define EXYNOS5433_PAD_RETENTION_MMC0_OPTION (0x3148) 640 #define EXYNOS5433_PAD_RETENTION_MMC1_OPTION (0x3168) 641 #define EXYNOS5433_PAD_RETENTION_EBIA_OPTION (0x3188) 642 #define EXYNOS5433_PAD_RETENTION_EBIB_OPTION (0x31A8) 643 #define EXYNOS5433_PAD_RETENTION_SPI_OPTION (0x31C8) 644 #define EXYNOS5433_PAD_RETENTION_MIF_OPTION (0x31E8) 645 #define EXYNOS5433_PAD_RETENTION_USBXTI_OPTION (0x3228) 646 #define EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION (0x3248) 647 #define EXYNOS5433_PAD_RETENTION_UFS_OPTION (0x3268) 648 #define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION (0x32A8) 649 650 #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */ 651