1*16216333SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 20c570674SLaxman Dewangan /* 30c570674SLaxman Dewangan * tps51632-regulator.h -- TPS51632 regulator 40c570674SLaxman Dewangan * 50c570674SLaxman Dewangan * Interface for regulator driver for TPS51632 3-2-1 Phase D-Cap Step Down 60c570674SLaxman Dewangan * Driverless Controller with serial VID control and DVFS. 70c570674SLaxman Dewangan * 80c570674SLaxman Dewangan * Copyright (C) 2012 NVIDIA Corporation 90c570674SLaxman Dewangan 100c570674SLaxman Dewangan * Author: Laxman Dewangan <ldewangan@nvidia.com> 110c570674SLaxman Dewangan */ 120c570674SLaxman Dewangan 130c570674SLaxman Dewangan #ifndef __LINUX_REGULATOR_TPS51632_H 140c570674SLaxman Dewangan #define __LINUX_REGULATOR_TPS51632_H 150c570674SLaxman Dewangan 160c570674SLaxman Dewangan /* 170c570674SLaxman Dewangan * struct tps51632_regulator_platform_data - tps51632 regulator platform data. 180c570674SLaxman Dewangan * 190c570674SLaxman Dewangan * @reg_init_data: The regulator init data. 200c570674SLaxman Dewangan * @enable_pwm_dvfs: Enable PWM DVFS or not. 210c570674SLaxman Dewangan * @dvfs_step_20mV: Step for DVFS is 20mV or 10mV. 220c570674SLaxman Dewangan * @max_voltage_uV: Maximum possible voltage in PWM-DVFS mode. 230c570674SLaxman Dewangan * @base_voltage_uV: Base voltage when PWM-DVFS enabled. 240c570674SLaxman Dewangan */ 250c570674SLaxman Dewangan struct tps51632_regulator_platform_data { 260c570674SLaxman Dewangan struct regulator_init_data *reg_init_data; 270c570674SLaxman Dewangan bool enable_pwm_dvfs; 280c570674SLaxman Dewangan bool dvfs_step_20mV; 290c570674SLaxman Dewangan int max_voltage_uV; 300c570674SLaxman Dewangan int base_voltage_uV; 310c570674SLaxman Dewangan }; 320c570674SLaxman Dewangan 330c570674SLaxman Dewangan #endif /* __LINUX_REGULATOR_TPS51632_H */ 34