1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _QED_IF_H 34 #define _QED_IF_H 35 36 #include <linux/types.h> 37 #include <linux/interrupt.h> 38 #include <linux/netdevice.h> 39 #include <linux/pci.h> 40 #include <linux/skbuff.h> 41 #include <linux/types.h> 42 #include <asm/byteorder.h> 43 #include <linux/io.h> 44 #include <linux/compiler.h> 45 #include <linux/kernel.h> 46 #include <linux/list.h> 47 #include <linux/slab.h> 48 #include <linux/qed/common_hsi.h> 49 #include <linux/qed/qed_chain.h> 50 51 enum dcbx_protocol_type { 52 DCBX_PROTOCOL_ISCSI, 53 DCBX_PROTOCOL_FCOE, 54 DCBX_PROTOCOL_ROCE, 55 DCBX_PROTOCOL_ROCE_V2, 56 DCBX_PROTOCOL_ETH, 57 DCBX_MAX_PROTOCOL_TYPE 58 }; 59 60 #define QED_ROCE_PROTOCOL_INDEX (3) 61 62 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4 63 #define QED_LLDP_PORT_ID_STAT_LEN 4 64 #define QED_DCBX_MAX_APP_PROTOCOL 32 65 #define QED_MAX_PFC_PRIORITIES 8 66 #define QED_DCBX_DSCP_SIZE 64 67 68 struct qed_dcbx_lldp_remote { 69 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 70 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 71 bool enable_rx; 72 bool enable_tx; 73 u32 tx_interval; 74 u32 max_credit; 75 }; 76 77 struct qed_dcbx_lldp_local { 78 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 79 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 80 }; 81 82 struct qed_dcbx_app_prio { 83 u8 roce; 84 u8 roce_v2; 85 u8 fcoe; 86 u8 iscsi; 87 u8 eth; 88 }; 89 90 struct qed_dbcx_pfc_params { 91 bool willing; 92 bool enabled; 93 u8 prio[QED_MAX_PFC_PRIORITIES]; 94 u8 max_tc; 95 }; 96 97 enum qed_dcbx_sf_ieee_type { 98 QED_DCBX_SF_IEEE_ETHTYPE, 99 QED_DCBX_SF_IEEE_TCP_PORT, 100 QED_DCBX_SF_IEEE_UDP_PORT, 101 QED_DCBX_SF_IEEE_TCP_UDP_PORT 102 }; 103 104 struct qed_app_entry { 105 bool ethtype; 106 enum qed_dcbx_sf_ieee_type sf_ieee; 107 bool enabled; 108 u8 prio; 109 u16 proto_id; 110 enum dcbx_protocol_type proto_type; 111 }; 112 113 struct qed_dcbx_params { 114 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL]; 115 u16 num_app_entries; 116 bool app_willing; 117 bool app_valid; 118 bool app_error; 119 bool ets_willing; 120 bool ets_enabled; 121 bool ets_cbs; 122 bool valid; 123 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES]; 124 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES]; 125 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES]; 126 struct qed_dbcx_pfc_params pfc; 127 u8 max_ets_tc; 128 }; 129 130 struct qed_dcbx_admin_params { 131 struct qed_dcbx_params params; 132 bool valid; 133 }; 134 135 struct qed_dcbx_remote_params { 136 struct qed_dcbx_params params; 137 bool valid; 138 }; 139 140 struct qed_dcbx_operational_params { 141 struct qed_dcbx_app_prio app_prio; 142 struct qed_dcbx_params params; 143 bool valid; 144 bool enabled; 145 bool ieee; 146 bool cee; 147 bool local; 148 u32 err; 149 }; 150 151 struct qed_dcbx_get { 152 struct qed_dcbx_operational_params operational; 153 struct qed_dcbx_lldp_remote lldp_remote; 154 struct qed_dcbx_lldp_local lldp_local; 155 struct qed_dcbx_remote_params remote; 156 struct qed_dcbx_admin_params local; 157 }; 158 159 enum qed_nvm_images { 160 QED_NVM_IMAGE_ISCSI_CFG, 161 QED_NVM_IMAGE_FCOE_CFG, 162 QED_NVM_IMAGE_NVM_CFG1, 163 QED_NVM_IMAGE_DEFAULT_CFG, 164 QED_NVM_IMAGE_NVM_META, 165 }; 166 167 struct qed_link_eee_params { 168 u32 tx_lpi_timer; 169 #define QED_EEE_1G_ADV BIT(0) 170 #define QED_EEE_10G_ADV BIT(1) 171 172 /* Capabilities are represented using QED_EEE_*_ADV values */ 173 u8 adv_caps; 174 u8 lp_adv_caps; 175 bool enable; 176 bool tx_lpi_enable; 177 }; 178 179 enum qed_led_mode { 180 QED_LED_MODE_OFF, 181 QED_LED_MODE_ON, 182 QED_LED_MODE_RESTORE 183 }; 184 185 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \ 186 (void __iomem *)(reg_addr)) 187 188 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr)) 189 190 #define QED_COALESCE_MAX 0x1FF 191 #define QED_DEFAULT_RX_USECS 12 192 #define QED_DEFAULT_TX_USECS 48 193 194 /* forward */ 195 struct qed_dev; 196 197 struct qed_eth_pf_params { 198 /* The following parameters are used during HW-init 199 * and these parameters need to be passed as arguments 200 * to update_pf_params routine invoked before slowpath start 201 */ 202 u16 num_cons; 203 204 /* per-VF number of CIDs */ 205 u8 num_vf_cons; 206 #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32) 207 208 /* To enable arfs, previous to HW-init a positive number needs to be 209 * set [as filters require allocated searcher ILT memory]. 210 * This will set the maximal number of configured steering-filters. 211 */ 212 u32 num_arfs_filters; 213 }; 214 215 struct qed_fcoe_pf_params { 216 /* The following parameters are used during protocol-init */ 217 u64 glbl_q_params_addr; 218 u64 bdq_pbl_base_addr[2]; 219 220 /* The following parameters are used during HW-init 221 * and these parameters need to be passed as arguments 222 * to update_pf_params routine invoked before slowpath start 223 */ 224 u16 num_cons; 225 u16 num_tasks; 226 227 /* The following parameters are used during protocol-init */ 228 u16 sq_num_pbl_pages; 229 230 u16 cq_num_entries; 231 u16 cmdq_num_entries; 232 u16 rq_buffer_log_size; 233 u16 mtu; 234 u16 dummy_icid; 235 u16 bdq_xoff_threshold[2]; 236 u16 bdq_xon_threshold[2]; 237 u16 rq_buffer_size; 238 u8 num_cqs; /* num of global CQs */ 239 u8 log_page_size; 240 u8 gl_rq_pi; 241 u8 gl_cmd_pi; 242 u8 debug_mode; 243 u8 is_target; 244 u8 bdq_pbl_num_entries[2]; 245 }; 246 247 /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */ 248 struct qed_iscsi_pf_params { 249 u64 glbl_q_params_addr; 250 u64 bdq_pbl_base_addr[3]; 251 u16 cq_num_entries; 252 u16 cmdq_num_entries; 253 u32 two_msl_timer; 254 u16 tx_sws_timer; 255 256 /* The following parameters are used during HW-init 257 * and these parameters need to be passed as arguments 258 * to update_pf_params routine invoked before slowpath start 259 */ 260 u16 num_cons; 261 u16 num_tasks; 262 263 /* The following parameters are used during protocol-init */ 264 u16 half_way_close_timeout; 265 u16 bdq_xoff_threshold[3]; 266 u16 bdq_xon_threshold[3]; 267 u16 cmdq_xoff_threshold; 268 u16 cmdq_xon_threshold; 269 u16 rq_buffer_size; 270 271 u8 num_sq_pages_in_ring; 272 u8 num_r2tq_pages_in_ring; 273 u8 num_uhq_pages_in_ring; 274 u8 num_queues; 275 u8 log_page_size; 276 u8 rqe_log_size; 277 u8 max_fin_rt; 278 u8 gl_rq_pi; 279 u8 gl_cmd_pi; 280 u8 debug_mode; 281 u8 ll2_ooo_queue_id; 282 283 u8 is_target; 284 u8 is_soc_en; 285 u8 soc_num_of_blocks_log; 286 u8 bdq_pbl_num_entries[3]; 287 }; 288 289 struct qed_rdma_pf_params { 290 /* Supplied to QED during resource allocation (may affect the ILT and 291 * the doorbell BAR). 292 */ 293 u32 min_dpis; /* number of requested DPIs */ 294 u32 num_qps; /* number of requested Queue Pairs */ 295 u32 num_srqs; /* number of requested SRQ */ 296 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */ 297 u8 gl_pi; /* protocol index */ 298 299 /* Will allocate rate limiters to be used with QPs */ 300 u8 enable_dcqcn; 301 }; 302 303 struct qed_pf_params { 304 struct qed_eth_pf_params eth_pf_params; 305 struct qed_fcoe_pf_params fcoe_pf_params; 306 struct qed_iscsi_pf_params iscsi_pf_params; 307 struct qed_rdma_pf_params rdma_pf_params; 308 }; 309 310 enum qed_int_mode { 311 QED_INT_MODE_INTA, 312 QED_INT_MODE_MSIX, 313 QED_INT_MODE_MSI, 314 QED_INT_MODE_POLL, 315 }; 316 317 struct qed_sb_info { 318 struct status_block_e4 *sb_virt; 319 dma_addr_t sb_phys; 320 u32 sb_ack; /* Last given ack */ 321 u16 igu_sb_id; 322 void __iomem *igu_addr; 323 u8 flags; 324 #define QED_SB_INFO_INIT 0x1 325 #define QED_SB_INFO_SETUP 0x2 326 327 struct qed_dev *cdev; 328 }; 329 330 enum qed_dev_type { 331 QED_DEV_TYPE_BB, 332 QED_DEV_TYPE_AH, 333 }; 334 335 struct qed_dev_info { 336 unsigned long pci_mem_start; 337 unsigned long pci_mem_end; 338 unsigned int pci_irq; 339 u8 num_hwfns; 340 341 u8 hw_mac[ETH_ALEN]; 342 bool is_mf_default; 343 344 /* FW version */ 345 u16 fw_major; 346 u16 fw_minor; 347 u16 fw_rev; 348 u16 fw_eng; 349 350 /* MFW version */ 351 u32 mfw_rev; 352 #define QED_MFW_VERSION_0_MASK 0x000000FF 353 #define QED_MFW_VERSION_0_OFFSET 0 354 #define QED_MFW_VERSION_1_MASK 0x0000FF00 355 #define QED_MFW_VERSION_1_OFFSET 8 356 #define QED_MFW_VERSION_2_MASK 0x00FF0000 357 #define QED_MFW_VERSION_2_OFFSET 16 358 #define QED_MFW_VERSION_3_MASK 0xFF000000 359 #define QED_MFW_VERSION_3_OFFSET 24 360 361 u32 flash_size; 362 u8 mf_mode; 363 bool tx_switching; 364 bool rdma_supported; 365 u16 mtu; 366 367 bool wol_support; 368 369 /* MBI version */ 370 u32 mbi_version; 371 #define QED_MBI_VERSION_0_MASK 0x000000FF 372 #define QED_MBI_VERSION_0_OFFSET 0 373 #define QED_MBI_VERSION_1_MASK 0x0000FF00 374 #define QED_MBI_VERSION_1_OFFSET 8 375 #define QED_MBI_VERSION_2_MASK 0x00FF0000 376 #define QED_MBI_VERSION_2_OFFSET 16 377 378 enum qed_dev_type dev_type; 379 380 /* Output parameters for qede */ 381 bool vxlan_enable; 382 bool gre_enable; 383 bool geneve_enable; 384 385 u8 abs_pf_id; 386 }; 387 388 enum qed_sb_type { 389 QED_SB_TYPE_L2_QUEUE, 390 QED_SB_TYPE_CNQ, 391 QED_SB_TYPE_STORAGE, 392 }; 393 394 enum qed_protocol { 395 QED_PROTOCOL_ETH, 396 QED_PROTOCOL_ISCSI, 397 QED_PROTOCOL_FCOE, 398 }; 399 400 enum qed_link_mode_bits { 401 QED_LM_FIBRE_BIT = BIT(0), 402 QED_LM_Autoneg_BIT = BIT(1), 403 QED_LM_Asym_Pause_BIT = BIT(2), 404 QED_LM_Pause_BIT = BIT(3), 405 QED_LM_1000baseT_Half_BIT = BIT(4), 406 QED_LM_1000baseT_Full_BIT = BIT(5), 407 QED_LM_10000baseKR_Full_BIT = BIT(6), 408 QED_LM_25000baseKR_Full_BIT = BIT(7), 409 QED_LM_40000baseLR4_Full_BIT = BIT(8), 410 QED_LM_50000baseKR2_Full_BIT = BIT(9), 411 QED_LM_100000baseKR4_Full_BIT = BIT(10), 412 QED_LM_COUNT = 11 413 }; 414 415 struct qed_link_params { 416 bool link_up; 417 418 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0) 419 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1) 420 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2) 421 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3) 422 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4) 423 #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5) 424 u32 override_flags; 425 bool autoneg; 426 u32 adv_speeds; 427 u32 forced_speed; 428 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0) 429 #define QED_LINK_PAUSE_RX_ENABLE BIT(1) 430 #define QED_LINK_PAUSE_TX_ENABLE BIT(2) 431 u32 pause_config; 432 #define QED_LINK_LOOPBACK_NONE BIT(0) 433 #define QED_LINK_LOOPBACK_INT_PHY BIT(1) 434 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2) 435 #define QED_LINK_LOOPBACK_EXT BIT(3) 436 #define QED_LINK_LOOPBACK_MAC BIT(4) 437 u32 loopback_mode; 438 struct qed_link_eee_params eee; 439 }; 440 441 struct qed_link_output { 442 bool link_up; 443 444 /* In QED_LM_* defs */ 445 u32 supported_caps; 446 u32 advertised_caps; 447 u32 lp_caps; 448 449 u32 speed; /* In Mb/s */ 450 u8 duplex; /* In DUPLEX defs */ 451 u8 port; /* In PORT defs */ 452 bool autoneg; 453 u32 pause_config; 454 455 /* EEE - capability & param */ 456 bool eee_supported; 457 bool eee_active; 458 u8 sup_caps; 459 struct qed_link_eee_params eee; 460 }; 461 462 struct qed_probe_params { 463 enum qed_protocol protocol; 464 u32 dp_module; 465 u8 dp_level; 466 bool is_vf; 467 }; 468 469 #define QED_DRV_VER_STR_SIZE 12 470 struct qed_slowpath_params { 471 u32 int_mode; 472 u8 drv_major; 473 u8 drv_minor; 474 u8 drv_rev; 475 u8 drv_eng; 476 u8 name[QED_DRV_VER_STR_SIZE]; 477 }; 478 479 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */ 480 481 struct qed_int_info { 482 struct msix_entry *msix; 483 u8 msix_cnt; 484 485 /* This should be updated by the protocol driver */ 486 u8 used_cnt; 487 }; 488 489 #define QED_NVM_SIGNATURE 0x12435687 490 491 enum qed_nvm_flash_cmd { 492 QED_NVM_FLASH_CMD_FILE_DATA = 0x2, 493 QED_NVM_FLASH_CMD_FILE_START = 0x3, 494 QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4, 495 QED_NVM_FLASH_CMD_NVM_MAX, 496 }; 497 498 struct qed_common_cb_ops { 499 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc); 500 void (*link_update)(void *dev, 501 struct qed_link_output *link); 502 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type); 503 }; 504 505 struct qed_selftest_ops { 506 /** 507 * @brief selftest_interrupt - Perform interrupt test 508 * 509 * @param cdev 510 * 511 * @return 0 on success, error otherwise. 512 */ 513 int (*selftest_interrupt)(struct qed_dev *cdev); 514 515 /** 516 * @brief selftest_memory - Perform memory test 517 * 518 * @param cdev 519 * 520 * @return 0 on success, error otherwise. 521 */ 522 int (*selftest_memory)(struct qed_dev *cdev); 523 524 /** 525 * @brief selftest_register - Perform register test 526 * 527 * @param cdev 528 * 529 * @return 0 on success, error otherwise. 530 */ 531 int (*selftest_register)(struct qed_dev *cdev); 532 533 /** 534 * @brief selftest_clock - Perform clock test 535 * 536 * @param cdev 537 * 538 * @return 0 on success, error otherwise. 539 */ 540 int (*selftest_clock)(struct qed_dev *cdev); 541 542 /** 543 * @brief selftest_nvram - Perform nvram test 544 * 545 * @param cdev 546 * 547 * @return 0 on success, error otherwise. 548 */ 549 int (*selftest_nvram) (struct qed_dev *cdev); 550 }; 551 552 struct qed_common_ops { 553 struct qed_selftest_ops *selftest; 554 555 struct qed_dev* (*probe)(struct pci_dev *dev, 556 struct qed_probe_params *params); 557 558 void (*remove)(struct qed_dev *cdev); 559 560 int (*set_power_state)(struct qed_dev *cdev, 561 pci_power_t state); 562 563 void (*set_name) (struct qed_dev *cdev, char name[]); 564 565 /* Client drivers need to make this call before slowpath_start. 566 * PF params required for the call before slowpath_start is 567 * documented within the qed_pf_params structure definition. 568 */ 569 void (*update_pf_params)(struct qed_dev *cdev, 570 struct qed_pf_params *params); 571 int (*slowpath_start)(struct qed_dev *cdev, 572 struct qed_slowpath_params *params); 573 574 int (*slowpath_stop)(struct qed_dev *cdev); 575 576 /* Requests to use `cnt' interrupts for fastpath. 577 * upon success, returns number of interrupts allocated for fastpath. 578 */ 579 int (*set_fp_int)(struct qed_dev *cdev, 580 u16 cnt); 581 582 /* Fills `info' with pointers required for utilizing interrupts */ 583 int (*get_fp_int)(struct qed_dev *cdev, 584 struct qed_int_info *info); 585 586 u32 (*sb_init)(struct qed_dev *cdev, 587 struct qed_sb_info *sb_info, 588 void *sb_virt_addr, 589 dma_addr_t sb_phy_addr, 590 u16 sb_id, 591 enum qed_sb_type type); 592 593 u32 (*sb_release)(struct qed_dev *cdev, 594 struct qed_sb_info *sb_info, 595 u16 sb_id); 596 597 void (*simd_handler_config)(struct qed_dev *cdev, 598 void *token, 599 int index, 600 void (*handler)(void *)); 601 602 void (*simd_handler_clean)(struct qed_dev *cdev, 603 int index); 604 int (*dbg_grc)(struct qed_dev *cdev, 605 void *buffer, u32 *num_dumped_bytes); 606 607 int (*dbg_grc_size)(struct qed_dev *cdev); 608 609 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer); 610 611 int (*dbg_all_data_size) (struct qed_dev *cdev); 612 613 /** 614 * @brief can_link_change - can the instance change the link or not 615 * 616 * @param cdev 617 * 618 * @return true if link-change is allowed, false otherwise. 619 */ 620 bool (*can_link_change)(struct qed_dev *cdev); 621 622 /** 623 * @brief set_link - set links according to params 624 * 625 * @param cdev 626 * @param params - values used to override the default link configuration 627 * 628 * @return 0 on success, error otherwise. 629 */ 630 int (*set_link)(struct qed_dev *cdev, 631 struct qed_link_params *params); 632 633 /** 634 * @brief get_link - returns the current link state. 635 * 636 * @param cdev 637 * @param if_link - structure to be filled with current link configuration. 638 */ 639 void (*get_link)(struct qed_dev *cdev, 640 struct qed_link_output *if_link); 641 642 /** 643 * @brief - drains chip in case Tx completions fail to arrive due to pause. 644 * 645 * @param cdev 646 */ 647 int (*drain)(struct qed_dev *cdev); 648 649 /** 650 * @brief update_msglvl - update module debug level 651 * 652 * @param cdev 653 * @param dp_module 654 * @param dp_level 655 */ 656 void (*update_msglvl)(struct qed_dev *cdev, 657 u32 dp_module, 658 u8 dp_level); 659 660 int (*chain_alloc)(struct qed_dev *cdev, 661 enum qed_chain_use_mode intended_use, 662 enum qed_chain_mode mode, 663 enum qed_chain_cnt_type cnt_type, 664 u32 num_elems, 665 size_t elem_size, 666 struct qed_chain *p_chain, 667 struct qed_chain_ext_pbl *ext_pbl); 668 669 void (*chain_free)(struct qed_dev *cdev, 670 struct qed_chain *p_chain); 671 672 /** 673 * @brief nvm_flash - Flash nvm data. 674 * 675 * @param cdev 676 * @param name - file containing the data 677 * 678 * @return 0 on success, error otherwise. 679 */ 680 int (*nvm_flash)(struct qed_dev *cdev, const char *name); 681 682 /** 683 * @brief nvm_get_image - reads an entire image from nvram 684 * 685 * @param cdev 686 * @param type - type of the request nvram image 687 * @param buf - preallocated buffer to fill with the image 688 * @param len - length of the allocated buffer 689 * 690 * @return 0 on success, error otherwise 691 */ 692 int (*nvm_get_image)(struct qed_dev *cdev, 693 enum qed_nvm_images type, u8 *buf, u16 len); 694 695 /** 696 * @brief set_coalesce - Configure Rx coalesce value in usec 697 * 698 * @param cdev 699 * @param rx_coal - Rx coalesce value in usec 700 * @param tx_coal - Tx coalesce value in usec 701 * @param qid - Queue index 702 * @param sb_id - Status Block Id 703 * 704 * @return 0 on success, error otherwise. 705 */ 706 int (*set_coalesce)(struct qed_dev *cdev, 707 u16 rx_coal, u16 tx_coal, void *handle); 708 709 /** 710 * @brief set_led - Configure LED mode 711 * 712 * @param cdev 713 * @param mode - LED mode 714 * 715 * @return 0 on success, error otherwise. 716 */ 717 int (*set_led)(struct qed_dev *cdev, 718 enum qed_led_mode mode); 719 720 /** 721 * @brief update_drv_state - API to inform the change in the driver state. 722 * 723 * @param cdev 724 * @param active 725 * 726 */ 727 int (*update_drv_state)(struct qed_dev *cdev, bool active); 728 729 /** 730 * @brief update_mac - API to inform the change in the mac address 731 * 732 * @param cdev 733 * @param mac 734 * 735 */ 736 int (*update_mac)(struct qed_dev *cdev, u8 *mac); 737 738 /** 739 * @brief update_mtu - API to inform the change in the mtu 740 * 741 * @param cdev 742 * @param mtu 743 * 744 */ 745 int (*update_mtu)(struct qed_dev *cdev, u16 mtu); 746 747 /** 748 * @brief update_wol - update of changes in the WoL configuration 749 * 750 * @param cdev 751 * @param enabled - true iff WoL should be enabled. 752 */ 753 int (*update_wol) (struct qed_dev *cdev, bool enabled); 754 }; 755 756 #define MASK_FIELD(_name, _value) \ 757 ((_value) &= (_name ## _MASK)) 758 759 #define FIELD_VALUE(_name, _value) \ 760 ((_value & _name ## _MASK) << _name ## _SHIFT) 761 762 #define SET_FIELD(value, name, flag) \ 763 do { \ 764 (value) &= ~(name ## _MASK << name ## _SHIFT); \ 765 (value) |= (((u64)flag) << (name ## _SHIFT)); \ 766 } while (0) 767 768 #define GET_FIELD(value, name) \ 769 (((value) >> (name ## _SHIFT)) & name ## _MASK) 770 771 /* Debug print definitions */ 772 #define DP_ERR(cdev, fmt, ...) \ 773 do { \ 774 pr_err("[%s:%d(%s)]" fmt, \ 775 __func__, __LINE__, \ 776 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 777 ## __VA_ARGS__); \ 778 } while (0) 779 780 #define DP_NOTICE(cdev, fmt, ...) \ 781 do { \ 782 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \ 783 pr_notice("[%s:%d(%s)]" fmt, \ 784 __func__, __LINE__, \ 785 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 786 ## __VA_ARGS__); \ 787 \ 788 } \ 789 } while (0) 790 791 #define DP_INFO(cdev, fmt, ...) \ 792 do { \ 793 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \ 794 pr_notice("[%s:%d(%s)]" fmt, \ 795 __func__, __LINE__, \ 796 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 797 ## __VA_ARGS__); \ 798 } \ 799 } while (0) 800 801 #define DP_VERBOSE(cdev, module, fmt, ...) \ 802 do { \ 803 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \ 804 ((cdev)->dp_module & module))) { \ 805 pr_notice("[%s:%d(%s)]" fmt, \ 806 __func__, __LINE__, \ 807 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 808 ## __VA_ARGS__); \ 809 } \ 810 } while (0) 811 812 enum DP_LEVEL { 813 QED_LEVEL_VERBOSE = 0x0, 814 QED_LEVEL_INFO = 0x1, 815 QED_LEVEL_NOTICE = 0x2, 816 QED_LEVEL_ERR = 0x3, 817 }; 818 819 #define QED_LOG_LEVEL_SHIFT (30) 820 #define QED_LOG_VERBOSE_MASK (0x3fffffff) 821 #define QED_LOG_INFO_MASK (0x40000000) 822 #define QED_LOG_NOTICE_MASK (0x80000000) 823 824 enum DP_MODULE { 825 QED_MSG_SPQ = 0x10000, 826 QED_MSG_STATS = 0x20000, 827 QED_MSG_DCB = 0x40000, 828 QED_MSG_IOV = 0x80000, 829 QED_MSG_SP = 0x100000, 830 QED_MSG_STORAGE = 0x200000, 831 QED_MSG_CXT = 0x800000, 832 QED_MSG_LL2 = 0x1000000, 833 QED_MSG_ILT = 0x2000000, 834 QED_MSG_RDMA = 0x4000000, 835 QED_MSG_DEBUG = 0x8000000, 836 /* to be added...up to 0x8000000 */ 837 }; 838 839 enum qed_mf_mode { 840 QED_MF_DEFAULT, 841 QED_MF_OVLAN, 842 QED_MF_NPAR, 843 }; 844 845 struct qed_eth_stats_common { 846 u64 no_buff_discards; 847 u64 packet_too_big_discard; 848 u64 ttl0_discard; 849 u64 rx_ucast_bytes; 850 u64 rx_mcast_bytes; 851 u64 rx_bcast_bytes; 852 u64 rx_ucast_pkts; 853 u64 rx_mcast_pkts; 854 u64 rx_bcast_pkts; 855 u64 mftag_filter_discards; 856 u64 mac_filter_discards; 857 u64 tx_ucast_bytes; 858 u64 tx_mcast_bytes; 859 u64 tx_bcast_bytes; 860 u64 tx_ucast_pkts; 861 u64 tx_mcast_pkts; 862 u64 tx_bcast_pkts; 863 u64 tx_err_drop_pkts; 864 u64 tpa_coalesced_pkts; 865 u64 tpa_coalesced_events; 866 u64 tpa_aborts_num; 867 u64 tpa_not_coalesced_pkts; 868 u64 tpa_coalesced_bytes; 869 870 /* port */ 871 u64 rx_64_byte_packets; 872 u64 rx_65_to_127_byte_packets; 873 u64 rx_128_to_255_byte_packets; 874 u64 rx_256_to_511_byte_packets; 875 u64 rx_512_to_1023_byte_packets; 876 u64 rx_1024_to_1518_byte_packets; 877 u64 rx_crc_errors; 878 u64 rx_mac_crtl_frames; 879 u64 rx_pause_frames; 880 u64 rx_pfc_frames; 881 u64 rx_align_errors; 882 u64 rx_carrier_errors; 883 u64 rx_oversize_packets; 884 u64 rx_jabbers; 885 u64 rx_undersize_packets; 886 u64 rx_fragments; 887 u64 tx_64_byte_packets; 888 u64 tx_65_to_127_byte_packets; 889 u64 tx_128_to_255_byte_packets; 890 u64 tx_256_to_511_byte_packets; 891 u64 tx_512_to_1023_byte_packets; 892 u64 tx_1024_to_1518_byte_packets; 893 u64 tx_pause_frames; 894 u64 tx_pfc_frames; 895 u64 brb_truncates; 896 u64 brb_discards; 897 u64 rx_mac_bytes; 898 u64 rx_mac_uc_packets; 899 u64 rx_mac_mc_packets; 900 u64 rx_mac_bc_packets; 901 u64 rx_mac_frames_ok; 902 u64 tx_mac_bytes; 903 u64 tx_mac_uc_packets; 904 u64 tx_mac_mc_packets; 905 u64 tx_mac_bc_packets; 906 u64 tx_mac_ctrl_frames; 907 }; 908 909 struct qed_eth_stats_bb { 910 u64 rx_1519_to_1522_byte_packets; 911 u64 rx_1519_to_2047_byte_packets; 912 u64 rx_2048_to_4095_byte_packets; 913 u64 rx_4096_to_9216_byte_packets; 914 u64 rx_9217_to_16383_byte_packets; 915 u64 tx_1519_to_2047_byte_packets; 916 u64 tx_2048_to_4095_byte_packets; 917 u64 tx_4096_to_9216_byte_packets; 918 u64 tx_9217_to_16383_byte_packets; 919 u64 tx_lpi_entry_count; 920 u64 tx_total_collisions; 921 }; 922 923 struct qed_eth_stats_ah { 924 u64 rx_1519_to_max_byte_packets; 925 u64 tx_1519_to_max_byte_packets; 926 }; 927 928 struct qed_eth_stats { 929 struct qed_eth_stats_common common; 930 931 union { 932 struct qed_eth_stats_bb bb; 933 struct qed_eth_stats_ah ah; 934 }; 935 }; 936 937 #define QED_SB_IDX 0x0002 938 939 #define RX_PI 0 940 #define TX_PI(tc) (RX_PI + 1 + tc) 941 942 struct qed_sb_cnt_info { 943 /* Original, current, and free SBs for PF */ 944 int orig; 945 int cnt; 946 int free_cnt; 947 948 /* Original, current and free SBS for child VFs */ 949 int iov_orig; 950 int iov_cnt; 951 int free_cnt_iov; 952 }; 953 954 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info) 955 { 956 u32 prod = 0; 957 u16 rc = 0; 958 959 prod = le32_to_cpu(sb_info->sb_virt->prod_index) & 960 STATUS_BLOCK_E4_PROD_INDEX_MASK; 961 if (sb_info->sb_ack != prod) { 962 sb_info->sb_ack = prod; 963 rc |= QED_SB_IDX; 964 } 965 966 /* Let SB update */ 967 mmiowb(); 968 return rc; 969 } 970 971 /** 972 * 973 * @brief This function creates an update command for interrupts that is 974 * written to the IGU. 975 * 976 * @param sb_info - This is the structure allocated and 977 * initialized per status block. Assumption is 978 * that it was initialized using qed_sb_init 979 * @param int_cmd - Enable/Disable/Nop 980 * @param upd_flg - whether igu consumer should be 981 * updated. 982 * 983 * @return inline void 984 */ 985 static inline void qed_sb_ack(struct qed_sb_info *sb_info, 986 enum igu_int_cmd int_cmd, 987 u8 upd_flg) 988 { 989 struct igu_prod_cons_update igu_ack = { 0 }; 990 991 igu_ack.sb_id_and_flags = 992 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 993 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 994 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 995 (IGU_SEG_ACCESS_REG << 996 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 997 998 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags); 999 1000 /* Both segments (interrupts & acks) are written to same place address; 1001 * Need to guarantee all commands will be received (in-order) by HW. 1002 */ 1003 mmiowb(); 1004 barrier(); 1005 } 1006 1007 static inline void __internal_ram_wr(void *p_hwfn, 1008 void __iomem *addr, 1009 int size, 1010 u32 *data) 1011 1012 { 1013 unsigned int i; 1014 1015 for (i = 0; i < size / sizeof(*data); i++) 1016 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]); 1017 } 1018 1019 static inline void internal_ram_wr(void __iomem *addr, 1020 int size, 1021 u32 *data) 1022 { 1023 __internal_ram_wr(NULL, addr, size, data); 1024 } 1025 1026 enum qed_rss_caps { 1027 QED_RSS_IPV4 = 0x1, 1028 QED_RSS_IPV6 = 0x2, 1029 QED_RSS_IPV4_TCP = 0x4, 1030 QED_RSS_IPV6_TCP = 0x8, 1031 QED_RSS_IPV4_UDP = 0x10, 1032 QED_RSS_IPV6_UDP = 0x20, 1033 }; 1034 1035 #define QED_RSS_IND_TABLE_SIZE 128 1036 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */ 1037 #endif 1038