1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _QED_IF_H 34 #define _QED_IF_H 35 36 #include <linux/types.h> 37 #include <linux/interrupt.h> 38 #include <linux/netdevice.h> 39 #include <linux/pci.h> 40 #include <linux/skbuff.h> 41 #include <linux/types.h> 42 #include <asm/byteorder.h> 43 #include <linux/io.h> 44 #include <linux/compiler.h> 45 #include <linux/kernel.h> 46 #include <linux/list.h> 47 #include <linux/slab.h> 48 #include <linux/qed/common_hsi.h> 49 #include <linux/qed/qed_chain.h> 50 51 enum dcbx_protocol_type { 52 DCBX_PROTOCOL_ISCSI, 53 DCBX_PROTOCOL_FCOE, 54 DCBX_PROTOCOL_ROCE, 55 DCBX_PROTOCOL_ROCE_V2, 56 DCBX_PROTOCOL_ETH, 57 DCBX_MAX_PROTOCOL_TYPE 58 }; 59 60 #define QED_ROCE_PROTOCOL_INDEX (3) 61 62 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4 63 #define QED_LLDP_PORT_ID_STAT_LEN 4 64 #define QED_DCBX_MAX_APP_PROTOCOL 32 65 #define QED_MAX_PFC_PRIORITIES 8 66 #define QED_DCBX_DSCP_SIZE 64 67 68 struct qed_dcbx_lldp_remote { 69 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 70 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 71 bool enable_rx; 72 bool enable_tx; 73 u32 tx_interval; 74 u32 max_credit; 75 }; 76 77 struct qed_dcbx_lldp_local { 78 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 79 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 80 }; 81 82 struct qed_dcbx_app_prio { 83 u8 roce; 84 u8 roce_v2; 85 u8 fcoe; 86 u8 iscsi; 87 u8 eth; 88 }; 89 90 struct qed_dbcx_pfc_params { 91 bool willing; 92 bool enabled; 93 u8 prio[QED_MAX_PFC_PRIORITIES]; 94 u8 max_tc; 95 }; 96 97 enum qed_dcbx_sf_ieee_type { 98 QED_DCBX_SF_IEEE_ETHTYPE, 99 QED_DCBX_SF_IEEE_TCP_PORT, 100 QED_DCBX_SF_IEEE_UDP_PORT, 101 QED_DCBX_SF_IEEE_TCP_UDP_PORT 102 }; 103 104 struct qed_app_entry { 105 bool ethtype; 106 enum qed_dcbx_sf_ieee_type sf_ieee; 107 bool enabled; 108 u8 prio; 109 u16 proto_id; 110 enum dcbx_protocol_type proto_type; 111 }; 112 113 struct qed_dcbx_params { 114 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL]; 115 u16 num_app_entries; 116 bool app_willing; 117 bool app_valid; 118 bool app_error; 119 bool ets_willing; 120 bool ets_enabled; 121 bool ets_cbs; 122 bool valid; 123 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES]; 124 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES]; 125 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES]; 126 struct qed_dbcx_pfc_params pfc; 127 u8 max_ets_tc; 128 }; 129 130 struct qed_dcbx_admin_params { 131 struct qed_dcbx_params params; 132 bool valid; 133 }; 134 135 struct qed_dcbx_remote_params { 136 struct qed_dcbx_params params; 137 bool valid; 138 }; 139 140 struct qed_dcbx_operational_params { 141 struct qed_dcbx_app_prio app_prio; 142 struct qed_dcbx_params params; 143 bool valid; 144 bool enabled; 145 bool ieee; 146 bool cee; 147 bool local; 148 u32 err; 149 }; 150 151 struct qed_dcbx_get { 152 struct qed_dcbx_operational_params operational; 153 struct qed_dcbx_lldp_remote lldp_remote; 154 struct qed_dcbx_lldp_local lldp_local; 155 struct qed_dcbx_remote_params remote; 156 struct qed_dcbx_admin_params local; 157 }; 158 159 enum qed_led_mode { 160 QED_LED_MODE_OFF, 161 QED_LED_MODE_ON, 162 QED_LED_MODE_RESTORE 163 }; 164 165 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \ 166 (void __iomem *)(reg_addr)) 167 168 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr)) 169 170 #define QED_COALESCE_MAX 0xFF 171 #define QED_DEFAULT_RX_USECS 12 172 173 /* forward */ 174 struct qed_dev; 175 176 struct qed_eth_pf_params { 177 /* The following parameters are used during HW-init 178 * and these parameters need to be passed as arguments 179 * to update_pf_params routine invoked before slowpath start 180 */ 181 u16 num_cons; 182 183 /* To enable arfs, previous to HW-init a positive number needs to be 184 * set [as filters require allocated searcher ILT memory]. 185 * This will set the maximal number of configured steering-filters. 186 */ 187 u32 num_arfs_filters; 188 }; 189 190 struct qed_fcoe_pf_params { 191 /* The following parameters are used during protocol-init */ 192 u64 glbl_q_params_addr; 193 u64 bdq_pbl_base_addr[2]; 194 195 /* The following parameters are used during HW-init 196 * and these parameters need to be passed as arguments 197 * to update_pf_params routine invoked before slowpath start 198 */ 199 u16 num_cons; 200 u16 num_tasks; 201 202 /* The following parameters are used during protocol-init */ 203 u16 sq_num_pbl_pages; 204 205 u16 cq_num_entries; 206 u16 cmdq_num_entries; 207 u16 rq_buffer_log_size; 208 u16 mtu; 209 u16 dummy_icid; 210 u16 bdq_xoff_threshold[2]; 211 u16 bdq_xon_threshold[2]; 212 u16 rq_buffer_size; 213 u8 num_cqs; /* num of global CQs */ 214 u8 log_page_size; 215 u8 gl_rq_pi; 216 u8 gl_cmd_pi; 217 u8 debug_mode; 218 u8 is_target; 219 u8 bdq_pbl_num_entries[2]; 220 }; 221 222 /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */ 223 struct qed_iscsi_pf_params { 224 u64 glbl_q_params_addr; 225 u64 bdq_pbl_base_addr[2]; 226 u32 max_cwnd; 227 u16 cq_num_entries; 228 u16 cmdq_num_entries; 229 u32 two_msl_timer; 230 u16 dup_ack_threshold; 231 u16 tx_sws_timer; 232 u16 min_rto; 233 u16 min_rto_rt; 234 u16 max_rto; 235 236 /* The following parameters are used during HW-init 237 * and these parameters need to be passed as arguments 238 * to update_pf_params routine invoked before slowpath start 239 */ 240 u16 num_cons; 241 u16 num_tasks; 242 243 /* The following parameters are used during protocol-init */ 244 u16 half_way_close_timeout; 245 u16 bdq_xoff_threshold[2]; 246 u16 bdq_xon_threshold[2]; 247 u16 cmdq_xoff_threshold; 248 u16 cmdq_xon_threshold; 249 u16 rq_buffer_size; 250 251 u8 num_sq_pages_in_ring; 252 u8 num_r2tq_pages_in_ring; 253 u8 num_uhq_pages_in_ring; 254 u8 num_queues; 255 u8 log_page_size; 256 u8 rqe_log_size; 257 u8 max_fin_rt; 258 u8 gl_rq_pi; 259 u8 gl_cmd_pi; 260 u8 debug_mode; 261 u8 ll2_ooo_queue_id; 262 u8 ooo_enable; 263 264 u8 is_target; 265 u8 bdq_pbl_num_entries[2]; 266 }; 267 268 struct qed_rdma_pf_params { 269 /* Supplied to QED during resource allocation (may affect the ILT and 270 * the doorbell BAR). 271 */ 272 u32 min_dpis; /* number of requested DPIs */ 273 u32 num_qps; /* number of requested Queue Pairs */ 274 u32 num_srqs; /* number of requested SRQ */ 275 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */ 276 u8 gl_pi; /* protocol index */ 277 278 /* Will allocate rate limiters to be used with QPs */ 279 u8 enable_dcqcn; 280 }; 281 282 struct qed_pf_params { 283 struct qed_eth_pf_params eth_pf_params; 284 struct qed_fcoe_pf_params fcoe_pf_params; 285 struct qed_iscsi_pf_params iscsi_pf_params; 286 struct qed_rdma_pf_params rdma_pf_params; 287 }; 288 289 enum qed_int_mode { 290 QED_INT_MODE_INTA, 291 QED_INT_MODE_MSIX, 292 QED_INT_MODE_MSI, 293 QED_INT_MODE_POLL, 294 }; 295 296 struct qed_sb_info { 297 struct status_block *sb_virt; 298 dma_addr_t sb_phys; 299 u32 sb_ack; /* Last given ack */ 300 u16 igu_sb_id; 301 void __iomem *igu_addr; 302 u8 flags; 303 #define QED_SB_INFO_INIT 0x1 304 #define QED_SB_INFO_SETUP 0x2 305 306 struct qed_dev *cdev; 307 }; 308 309 enum qed_dev_type { 310 QED_DEV_TYPE_BB, 311 QED_DEV_TYPE_AH, 312 }; 313 314 struct qed_dev_info { 315 unsigned long pci_mem_start; 316 unsigned long pci_mem_end; 317 unsigned int pci_irq; 318 u8 num_hwfns; 319 320 u8 hw_mac[ETH_ALEN]; 321 bool is_mf_default; 322 323 /* FW version */ 324 u16 fw_major; 325 u16 fw_minor; 326 u16 fw_rev; 327 u16 fw_eng; 328 329 /* MFW version */ 330 u32 mfw_rev; 331 332 u32 flash_size; 333 u8 mf_mode; 334 bool tx_switching; 335 bool rdma_supported; 336 u16 mtu; 337 338 bool wol_support; 339 340 enum qed_dev_type dev_type; 341 342 /* Output parameters for qede */ 343 bool vxlan_enable; 344 bool gre_enable; 345 bool geneve_enable; 346 }; 347 348 enum qed_sb_type { 349 QED_SB_TYPE_L2_QUEUE, 350 QED_SB_TYPE_CNQ, 351 QED_SB_TYPE_STORAGE, 352 }; 353 354 enum qed_protocol { 355 QED_PROTOCOL_ETH, 356 QED_PROTOCOL_ISCSI, 357 QED_PROTOCOL_FCOE, 358 }; 359 360 enum qed_link_mode_bits { 361 QED_LM_FIBRE_BIT = BIT(0), 362 QED_LM_Autoneg_BIT = BIT(1), 363 QED_LM_Asym_Pause_BIT = BIT(2), 364 QED_LM_Pause_BIT = BIT(3), 365 QED_LM_1000baseT_Half_BIT = BIT(4), 366 QED_LM_1000baseT_Full_BIT = BIT(5), 367 QED_LM_10000baseKR_Full_BIT = BIT(6), 368 QED_LM_25000baseKR_Full_BIT = BIT(7), 369 QED_LM_40000baseLR4_Full_BIT = BIT(8), 370 QED_LM_50000baseKR2_Full_BIT = BIT(9), 371 QED_LM_100000baseKR4_Full_BIT = BIT(10), 372 QED_LM_COUNT = 11 373 }; 374 375 struct qed_link_params { 376 bool link_up; 377 378 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0) 379 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1) 380 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2) 381 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3) 382 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4) 383 u32 override_flags; 384 bool autoneg; 385 u32 adv_speeds; 386 u32 forced_speed; 387 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0) 388 #define QED_LINK_PAUSE_RX_ENABLE BIT(1) 389 #define QED_LINK_PAUSE_TX_ENABLE BIT(2) 390 u32 pause_config; 391 #define QED_LINK_LOOPBACK_NONE BIT(0) 392 #define QED_LINK_LOOPBACK_INT_PHY BIT(1) 393 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2) 394 #define QED_LINK_LOOPBACK_EXT BIT(3) 395 #define QED_LINK_LOOPBACK_MAC BIT(4) 396 u32 loopback_mode; 397 }; 398 399 struct qed_link_output { 400 bool link_up; 401 402 /* In QED_LM_* defs */ 403 u32 supported_caps; 404 u32 advertised_caps; 405 u32 lp_caps; 406 407 u32 speed; /* In Mb/s */ 408 u8 duplex; /* In DUPLEX defs */ 409 u8 port; /* In PORT defs */ 410 bool autoneg; 411 u32 pause_config; 412 }; 413 414 struct qed_probe_params { 415 enum qed_protocol protocol; 416 u32 dp_module; 417 u8 dp_level; 418 bool is_vf; 419 }; 420 421 #define QED_DRV_VER_STR_SIZE 12 422 struct qed_slowpath_params { 423 u32 int_mode; 424 u8 drv_major; 425 u8 drv_minor; 426 u8 drv_rev; 427 u8 drv_eng; 428 u8 name[QED_DRV_VER_STR_SIZE]; 429 }; 430 431 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */ 432 433 struct qed_int_info { 434 struct msix_entry *msix; 435 u8 msix_cnt; 436 437 /* This should be updated by the protocol driver */ 438 u8 used_cnt; 439 }; 440 441 struct qed_common_cb_ops { 442 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc); 443 void (*link_update)(void *dev, 444 struct qed_link_output *link); 445 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type); 446 }; 447 448 struct qed_selftest_ops { 449 /** 450 * @brief selftest_interrupt - Perform interrupt test 451 * 452 * @param cdev 453 * 454 * @return 0 on success, error otherwise. 455 */ 456 int (*selftest_interrupt)(struct qed_dev *cdev); 457 458 /** 459 * @brief selftest_memory - Perform memory test 460 * 461 * @param cdev 462 * 463 * @return 0 on success, error otherwise. 464 */ 465 int (*selftest_memory)(struct qed_dev *cdev); 466 467 /** 468 * @brief selftest_register - Perform register test 469 * 470 * @param cdev 471 * 472 * @return 0 on success, error otherwise. 473 */ 474 int (*selftest_register)(struct qed_dev *cdev); 475 476 /** 477 * @brief selftest_clock - Perform clock test 478 * 479 * @param cdev 480 * 481 * @return 0 on success, error otherwise. 482 */ 483 int (*selftest_clock)(struct qed_dev *cdev); 484 485 /** 486 * @brief selftest_nvram - Perform nvram test 487 * 488 * @param cdev 489 * 490 * @return 0 on success, error otherwise. 491 */ 492 int (*selftest_nvram) (struct qed_dev *cdev); 493 }; 494 495 struct qed_common_ops { 496 struct qed_selftest_ops *selftest; 497 498 struct qed_dev* (*probe)(struct pci_dev *dev, 499 struct qed_probe_params *params); 500 501 void (*remove)(struct qed_dev *cdev); 502 503 int (*set_power_state)(struct qed_dev *cdev, 504 pci_power_t state); 505 506 void (*set_id)(struct qed_dev *cdev, 507 char name[], 508 char ver_str[]); 509 510 /* Client drivers need to make this call before slowpath_start. 511 * PF params required for the call before slowpath_start is 512 * documented within the qed_pf_params structure definition. 513 */ 514 void (*update_pf_params)(struct qed_dev *cdev, 515 struct qed_pf_params *params); 516 int (*slowpath_start)(struct qed_dev *cdev, 517 struct qed_slowpath_params *params); 518 519 int (*slowpath_stop)(struct qed_dev *cdev); 520 521 /* Requests to use `cnt' interrupts for fastpath. 522 * upon success, returns number of interrupts allocated for fastpath. 523 */ 524 int (*set_fp_int)(struct qed_dev *cdev, 525 u16 cnt); 526 527 /* Fills `info' with pointers required for utilizing interrupts */ 528 int (*get_fp_int)(struct qed_dev *cdev, 529 struct qed_int_info *info); 530 531 u32 (*sb_init)(struct qed_dev *cdev, 532 struct qed_sb_info *sb_info, 533 void *sb_virt_addr, 534 dma_addr_t sb_phy_addr, 535 u16 sb_id, 536 enum qed_sb_type type); 537 538 u32 (*sb_release)(struct qed_dev *cdev, 539 struct qed_sb_info *sb_info, 540 u16 sb_id); 541 542 void (*simd_handler_config)(struct qed_dev *cdev, 543 void *token, 544 int index, 545 void (*handler)(void *)); 546 547 void (*simd_handler_clean)(struct qed_dev *cdev, 548 int index); 549 int (*dbg_grc)(struct qed_dev *cdev, 550 void *buffer, u32 *num_dumped_bytes); 551 552 int (*dbg_grc_size)(struct qed_dev *cdev); 553 554 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer); 555 556 int (*dbg_all_data_size) (struct qed_dev *cdev); 557 558 /** 559 * @brief can_link_change - can the instance change the link or not 560 * 561 * @param cdev 562 * 563 * @return true if link-change is allowed, false otherwise. 564 */ 565 bool (*can_link_change)(struct qed_dev *cdev); 566 567 /** 568 * @brief set_link - set links according to params 569 * 570 * @param cdev 571 * @param params - values used to override the default link configuration 572 * 573 * @return 0 on success, error otherwise. 574 */ 575 int (*set_link)(struct qed_dev *cdev, 576 struct qed_link_params *params); 577 578 /** 579 * @brief get_link - returns the current link state. 580 * 581 * @param cdev 582 * @param if_link - structure to be filled with current link configuration. 583 */ 584 void (*get_link)(struct qed_dev *cdev, 585 struct qed_link_output *if_link); 586 587 /** 588 * @brief - drains chip in case Tx completions fail to arrive due to pause. 589 * 590 * @param cdev 591 */ 592 int (*drain)(struct qed_dev *cdev); 593 594 /** 595 * @brief update_msglvl - update module debug level 596 * 597 * @param cdev 598 * @param dp_module 599 * @param dp_level 600 */ 601 void (*update_msglvl)(struct qed_dev *cdev, 602 u32 dp_module, 603 u8 dp_level); 604 605 int (*chain_alloc)(struct qed_dev *cdev, 606 enum qed_chain_use_mode intended_use, 607 enum qed_chain_mode mode, 608 enum qed_chain_cnt_type cnt_type, 609 u32 num_elems, 610 size_t elem_size, 611 struct qed_chain *p_chain); 612 613 void (*chain_free)(struct qed_dev *cdev, 614 struct qed_chain *p_chain); 615 616 /** 617 * @brief get_coalesce - Get coalesce parameters in usec 618 * 619 * @param cdev 620 * @param rx_coal - Rx coalesce value in usec 621 * @param tx_coal - Tx coalesce value in usec 622 * 623 */ 624 void (*get_coalesce)(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal); 625 626 /** 627 * @brief set_coalesce - Configure Rx coalesce value in usec 628 * 629 * @param cdev 630 * @param rx_coal - Rx coalesce value in usec 631 * @param tx_coal - Tx coalesce value in usec 632 * @param qid - Queue index 633 * @param sb_id - Status Block Id 634 * 635 * @return 0 on success, error otherwise. 636 */ 637 int (*set_coalesce)(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, 638 u16 qid, u16 sb_id); 639 640 /** 641 * @brief set_led - Configure LED mode 642 * 643 * @param cdev 644 * @param mode - LED mode 645 * 646 * @return 0 on success, error otherwise. 647 */ 648 int (*set_led)(struct qed_dev *cdev, 649 enum qed_led_mode mode); 650 651 /** 652 * @brief update_drv_state - API to inform the change in the driver state. 653 * 654 * @param cdev 655 * @param active 656 * 657 */ 658 int (*update_drv_state)(struct qed_dev *cdev, bool active); 659 660 /** 661 * @brief update_mac - API to inform the change in the mac address 662 * 663 * @param cdev 664 * @param mac 665 * 666 */ 667 int (*update_mac)(struct qed_dev *cdev, u8 *mac); 668 669 /** 670 * @brief update_mtu - API to inform the change in the mtu 671 * 672 * @param cdev 673 * @param mtu 674 * 675 */ 676 int (*update_mtu)(struct qed_dev *cdev, u16 mtu); 677 678 /** 679 * @brief update_wol - update of changes in the WoL configuration 680 * 681 * @param cdev 682 * @param enabled - true iff WoL should be enabled. 683 */ 684 int (*update_wol) (struct qed_dev *cdev, bool enabled); 685 }; 686 687 #define MASK_FIELD(_name, _value) \ 688 ((_value) &= (_name ## _MASK)) 689 690 #define FIELD_VALUE(_name, _value) \ 691 ((_value & _name ## _MASK) << _name ## _SHIFT) 692 693 #define SET_FIELD(value, name, flag) \ 694 do { \ 695 (value) &= ~(name ## _MASK << name ## _SHIFT); \ 696 (value) |= (((u64)flag) << (name ## _SHIFT)); \ 697 } while (0) 698 699 #define GET_FIELD(value, name) \ 700 (((value) >> (name ## _SHIFT)) & name ## _MASK) 701 702 /* Debug print definitions */ 703 #define DP_ERR(cdev, fmt, ...) \ 704 pr_err("[%s:%d(%s)]" fmt, \ 705 __func__, __LINE__, \ 706 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 707 ## __VA_ARGS__) \ 708 709 #define DP_NOTICE(cdev, fmt, ...) \ 710 do { \ 711 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \ 712 pr_notice("[%s:%d(%s)]" fmt, \ 713 __func__, __LINE__, \ 714 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 715 ## __VA_ARGS__); \ 716 \ 717 } \ 718 } while (0) 719 720 #define DP_INFO(cdev, fmt, ...) \ 721 do { \ 722 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \ 723 pr_notice("[%s:%d(%s)]" fmt, \ 724 __func__, __LINE__, \ 725 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 726 ## __VA_ARGS__); \ 727 } \ 728 } while (0) 729 730 #define DP_VERBOSE(cdev, module, fmt, ...) \ 731 do { \ 732 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \ 733 ((cdev)->dp_module & module))) { \ 734 pr_notice("[%s:%d(%s)]" fmt, \ 735 __func__, __LINE__, \ 736 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 737 ## __VA_ARGS__); \ 738 } \ 739 } while (0) 740 741 enum DP_LEVEL { 742 QED_LEVEL_VERBOSE = 0x0, 743 QED_LEVEL_INFO = 0x1, 744 QED_LEVEL_NOTICE = 0x2, 745 QED_LEVEL_ERR = 0x3, 746 }; 747 748 #define QED_LOG_LEVEL_SHIFT (30) 749 #define QED_LOG_VERBOSE_MASK (0x3fffffff) 750 #define QED_LOG_INFO_MASK (0x40000000) 751 #define QED_LOG_NOTICE_MASK (0x80000000) 752 753 enum DP_MODULE { 754 QED_MSG_SPQ = 0x10000, 755 QED_MSG_STATS = 0x20000, 756 QED_MSG_DCB = 0x40000, 757 QED_MSG_IOV = 0x80000, 758 QED_MSG_SP = 0x100000, 759 QED_MSG_STORAGE = 0x200000, 760 QED_MSG_CXT = 0x800000, 761 QED_MSG_LL2 = 0x1000000, 762 QED_MSG_ILT = 0x2000000, 763 QED_MSG_RDMA = 0x4000000, 764 QED_MSG_DEBUG = 0x8000000, 765 /* to be added...up to 0x8000000 */ 766 }; 767 768 enum qed_mf_mode { 769 QED_MF_DEFAULT, 770 QED_MF_OVLAN, 771 QED_MF_NPAR, 772 }; 773 774 struct qed_eth_stats_common { 775 u64 no_buff_discards; 776 u64 packet_too_big_discard; 777 u64 ttl0_discard; 778 u64 rx_ucast_bytes; 779 u64 rx_mcast_bytes; 780 u64 rx_bcast_bytes; 781 u64 rx_ucast_pkts; 782 u64 rx_mcast_pkts; 783 u64 rx_bcast_pkts; 784 u64 mftag_filter_discards; 785 u64 mac_filter_discards; 786 u64 tx_ucast_bytes; 787 u64 tx_mcast_bytes; 788 u64 tx_bcast_bytes; 789 u64 tx_ucast_pkts; 790 u64 tx_mcast_pkts; 791 u64 tx_bcast_pkts; 792 u64 tx_err_drop_pkts; 793 u64 tpa_coalesced_pkts; 794 u64 tpa_coalesced_events; 795 u64 tpa_aborts_num; 796 u64 tpa_not_coalesced_pkts; 797 u64 tpa_coalesced_bytes; 798 799 /* port */ 800 u64 rx_64_byte_packets; 801 u64 rx_65_to_127_byte_packets; 802 u64 rx_128_to_255_byte_packets; 803 u64 rx_256_to_511_byte_packets; 804 u64 rx_512_to_1023_byte_packets; 805 u64 rx_1024_to_1518_byte_packets; 806 u64 rx_crc_errors; 807 u64 rx_mac_crtl_frames; 808 u64 rx_pause_frames; 809 u64 rx_pfc_frames; 810 u64 rx_align_errors; 811 u64 rx_carrier_errors; 812 u64 rx_oversize_packets; 813 u64 rx_jabbers; 814 u64 rx_undersize_packets; 815 u64 rx_fragments; 816 u64 tx_64_byte_packets; 817 u64 tx_65_to_127_byte_packets; 818 u64 tx_128_to_255_byte_packets; 819 u64 tx_256_to_511_byte_packets; 820 u64 tx_512_to_1023_byte_packets; 821 u64 tx_1024_to_1518_byte_packets; 822 u64 tx_pause_frames; 823 u64 tx_pfc_frames; 824 u64 brb_truncates; 825 u64 brb_discards; 826 u64 rx_mac_bytes; 827 u64 rx_mac_uc_packets; 828 u64 rx_mac_mc_packets; 829 u64 rx_mac_bc_packets; 830 u64 rx_mac_frames_ok; 831 u64 tx_mac_bytes; 832 u64 tx_mac_uc_packets; 833 u64 tx_mac_mc_packets; 834 u64 tx_mac_bc_packets; 835 u64 tx_mac_ctrl_frames; 836 }; 837 838 struct qed_eth_stats_bb { 839 u64 rx_1519_to_1522_byte_packets; 840 u64 rx_1519_to_2047_byte_packets; 841 u64 rx_2048_to_4095_byte_packets; 842 u64 rx_4096_to_9216_byte_packets; 843 u64 rx_9217_to_16383_byte_packets; 844 u64 tx_1519_to_2047_byte_packets; 845 u64 tx_2048_to_4095_byte_packets; 846 u64 tx_4096_to_9216_byte_packets; 847 u64 tx_9217_to_16383_byte_packets; 848 u64 tx_lpi_entry_count; 849 u64 tx_total_collisions; 850 }; 851 852 struct qed_eth_stats_ah { 853 u64 rx_1519_to_max_byte_packets; 854 u64 tx_1519_to_max_byte_packets; 855 }; 856 857 struct qed_eth_stats { 858 struct qed_eth_stats_common common; 859 860 union { 861 struct qed_eth_stats_bb bb; 862 struct qed_eth_stats_ah ah; 863 }; 864 }; 865 866 #define QED_SB_IDX 0x0002 867 868 #define RX_PI 0 869 #define TX_PI(tc) (RX_PI + 1 + tc) 870 871 struct qed_sb_cnt_info { 872 int sb_cnt; 873 int sb_iov_cnt; 874 int sb_free_blk; 875 }; 876 877 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info) 878 { 879 u32 prod = 0; 880 u16 rc = 0; 881 882 prod = le32_to_cpu(sb_info->sb_virt->prod_index) & 883 STATUS_BLOCK_PROD_INDEX_MASK; 884 if (sb_info->sb_ack != prod) { 885 sb_info->sb_ack = prod; 886 rc |= QED_SB_IDX; 887 } 888 889 /* Let SB update */ 890 mmiowb(); 891 return rc; 892 } 893 894 /** 895 * 896 * @brief This function creates an update command for interrupts that is 897 * written to the IGU. 898 * 899 * @param sb_info - This is the structure allocated and 900 * initialized per status block. Assumption is 901 * that it was initialized using qed_sb_init 902 * @param int_cmd - Enable/Disable/Nop 903 * @param upd_flg - whether igu consumer should be 904 * updated. 905 * 906 * @return inline void 907 */ 908 static inline void qed_sb_ack(struct qed_sb_info *sb_info, 909 enum igu_int_cmd int_cmd, 910 u8 upd_flg) 911 { 912 struct igu_prod_cons_update igu_ack = { 0 }; 913 914 igu_ack.sb_id_and_flags = 915 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 916 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 917 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 918 (IGU_SEG_ACCESS_REG << 919 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 920 921 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags); 922 923 /* Both segments (interrupts & acks) are written to same place address; 924 * Need to guarantee all commands will be received (in-order) by HW. 925 */ 926 mmiowb(); 927 barrier(); 928 } 929 930 static inline void __internal_ram_wr(void *p_hwfn, 931 void __iomem *addr, 932 int size, 933 u32 *data) 934 935 { 936 unsigned int i; 937 938 for (i = 0; i < size / sizeof(*data); i++) 939 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]); 940 } 941 942 static inline void internal_ram_wr(void __iomem *addr, 943 int size, 944 u32 *data) 945 { 946 __internal_ram_wr(NULL, addr, size, data); 947 } 948 949 enum qed_rss_caps { 950 QED_RSS_IPV4 = 0x1, 951 QED_RSS_IPV6 = 0x2, 952 QED_RSS_IPV4_TCP = 0x4, 953 QED_RSS_IPV6_TCP = 0x8, 954 QED_RSS_IPV4_UDP = 0x10, 955 QED_RSS_IPV6_UDP = 0x20, 956 }; 957 958 #define QED_RSS_IND_TABLE_SIZE 128 959 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */ 960 #endif 961