1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _QED_IF_H 34 #define _QED_IF_H 35 36 #include <linux/types.h> 37 #include <linux/interrupt.h> 38 #include <linux/netdevice.h> 39 #include <linux/pci.h> 40 #include <linux/skbuff.h> 41 #include <linux/types.h> 42 #include <asm/byteorder.h> 43 #include <linux/io.h> 44 #include <linux/compiler.h> 45 #include <linux/kernel.h> 46 #include <linux/list.h> 47 #include <linux/slab.h> 48 #include <linux/qed/common_hsi.h> 49 #include <linux/qed/qed_chain.h> 50 51 enum dcbx_protocol_type { 52 DCBX_PROTOCOL_ISCSI, 53 DCBX_PROTOCOL_FCOE, 54 DCBX_PROTOCOL_ROCE, 55 DCBX_PROTOCOL_ROCE_V2, 56 DCBX_PROTOCOL_ETH, 57 DCBX_MAX_PROTOCOL_TYPE 58 }; 59 60 #define QED_ROCE_PROTOCOL_INDEX (3) 61 62 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4 63 #define QED_LLDP_PORT_ID_STAT_LEN 4 64 #define QED_DCBX_MAX_APP_PROTOCOL 32 65 #define QED_MAX_PFC_PRIORITIES 8 66 #define QED_DCBX_DSCP_SIZE 64 67 68 struct qed_dcbx_lldp_remote { 69 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 70 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 71 bool enable_rx; 72 bool enable_tx; 73 u32 tx_interval; 74 u32 max_credit; 75 }; 76 77 struct qed_dcbx_lldp_local { 78 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 79 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 80 }; 81 82 struct qed_dcbx_app_prio { 83 u8 roce; 84 u8 roce_v2; 85 u8 fcoe; 86 u8 iscsi; 87 u8 eth; 88 }; 89 90 struct qed_dbcx_pfc_params { 91 bool willing; 92 bool enabled; 93 u8 prio[QED_MAX_PFC_PRIORITIES]; 94 u8 max_tc; 95 }; 96 97 enum qed_dcbx_sf_ieee_type { 98 QED_DCBX_SF_IEEE_ETHTYPE, 99 QED_DCBX_SF_IEEE_TCP_PORT, 100 QED_DCBX_SF_IEEE_UDP_PORT, 101 QED_DCBX_SF_IEEE_TCP_UDP_PORT 102 }; 103 104 struct qed_app_entry { 105 bool ethtype; 106 enum qed_dcbx_sf_ieee_type sf_ieee; 107 bool enabled; 108 u8 prio; 109 u16 proto_id; 110 enum dcbx_protocol_type proto_type; 111 }; 112 113 struct qed_dcbx_params { 114 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL]; 115 u16 num_app_entries; 116 bool app_willing; 117 bool app_valid; 118 bool app_error; 119 bool ets_willing; 120 bool ets_enabled; 121 bool ets_cbs; 122 bool valid; 123 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES]; 124 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES]; 125 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES]; 126 struct qed_dbcx_pfc_params pfc; 127 u8 max_ets_tc; 128 }; 129 130 struct qed_dcbx_admin_params { 131 struct qed_dcbx_params params; 132 bool valid; 133 }; 134 135 struct qed_dcbx_remote_params { 136 struct qed_dcbx_params params; 137 bool valid; 138 }; 139 140 struct qed_dcbx_operational_params { 141 struct qed_dcbx_app_prio app_prio; 142 struct qed_dcbx_params params; 143 bool valid; 144 bool enabled; 145 bool ieee; 146 bool cee; 147 bool local; 148 u32 err; 149 }; 150 151 struct qed_dcbx_get { 152 struct qed_dcbx_operational_params operational; 153 struct qed_dcbx_lldp_remote lldp_remote; 154 struct qed_dcbx_lldp_local lldp_local; 155 struct qed_dcbx_remote_params remote; 156 struct qed_dcbx_admin_params local; 157 }; 158 159 enum qed_nvm_images { 160 QED_NVM_IMAGE_ISCSI_CFG, 161 QED_NVM_IMAGE_FCOE_CFG, 162 QED_NVM_IMAGE_NVM_CFG1, 163 QED_NVM_IMAGE_DEFAULT_CFG, 164 QED_NVM_IMAGE_NVM_META, 165 }; 166 167 struct qed_link_eee_params { 168 u32 tx_lpi_timer; 169 #define QED_EEE_1G_ADV BIT(0) 170 #define QED_EEE_10G_ADV BIT(1) 171 172 /* Capabilities are represented using QED_EEE_*_ADV values */ 173 u8 adv_caps; 174 u8 lp_adv_caps; 175 bool enable; 176 bool tx_lpi_enable; 177 }; 178 179 enum qed_led_mode { 180 QED_LED_MODE_OFF, 181 QED_LED_MODE_ON, 182 QED_LED_MODE_RESTORE 183 }; 184 185 struct qed_mfw_tlv_eth { 186 u16 lso_maxoff_size; 187 bool lso_maxoff_size_set; 188 u16 lso_minseg_size; 189 bool lso_minseg_size_set; 190 u8 prom_mode; 191 bool prom_mode_set; 192 u16 tx_descr_size; 193 bool tx_descr_size_set; 194 u16 rx_descr_size; 195 bool rx_descr_size_set; 196 u16 netq_count; 197 bool netq_count_set; 198 u32 tcp4_offloads; 199 bool tcp4_offloads_set; 200 u32 tcp6_offloads; 201 bool tcp6_offloads_set; 202 u16 tx_descr_qdepth; 203 bool tx_descr_qdepth_set; 204 u16 rx_descr_qdepth; 205 bool rx_descr_qdepth_set; 206 u8 iov_offload; 207 #define QED_MFW_TLV_IOV_OFFLOAD_NONE (0) 208 #define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE (1) 209 #define QED_MFW_TLV_IOV_OFFLOAD_VEB (2) 210 #define QED_MFW_TLV_IOV_OFFLOAD_VEPA (3) 211 bool iov_offload_set; 212 u8 txqs_empty; 213 bool txqs_empty_set; 214 u8 rxqs_empty; 215 bool rxqs_empty_set; 216 u8 num_txqs_full; 217 bool num_txqs_full_set; 218 u8 num_rxqs_full; 219 bool num_rxqs_full_set; 220 }; 221 222 #define QED_MFW_TLV_TIME_SIZE 14 223 struct qed_mfw_tlv_time { 224 bool b_set; 225 u8 month; 226 u8 day; 227 u8 hour; 228 u8 min; 229 u16 msec; 230 u16 usec; 231 }; 232 233 struct qed_mfw_tlv_fcoe { 234 u8 scsi_timeout; 235 bool scsi_timeout_set; 236 u32 rt_tov; 237 bool rt_tov_set; 238 u32 ra_tov; 239 bool ra_tov_set; 240 u32 ed_tov; 241 bool ed_tov_set; 242 u32 cr_tov; 243 bool cr_tov_set; 244 u8 boot_type; 245 bool boot_type_set; 246 u8 npiv_state; 247 bool npiv_state_set; 248 u32 num_npiv_ids; 249 bool num_npiv_ids_set; 250 u8 switch_name[8]; 251 bool switch_name_set; 252 u16 switch_portnum; 253 bool switch_portnum_set; 254 u8 switch_portid[3]; 255 bool switch_portid_set; 256 u8 vendor_name[8]; 257 bool vendor_name_set; 258 u8 switch_model[8]; 259 bool switch_model_set; 260 u8 switch_fw_version[8]; 261 bool switch_fw_version_set; 262 u8 qos_pri; 263 bool qos_pri_set; 264 u8 port_alias[3]; 265 bool port_alias_set; 266 u8 port_state; 267 #define QED_MFW_TLV_PORT_STATE_OFFLINE (0) 268 #define QED_MFW_TLV_PORT_STATE_LOOP (1) 269 #define QED_MFW_TLV_PORT_STATE_P2P (2) 270 #define QED_MFW_TLV_PORT_STATE_FABRIC (3) 271 bool port_state_set; 272 u16 fip_tx_descr_size; 273 bool fip_tx_descr_size_set; 274 u16 fip_rx_descr_size; 275 bool fip_rx_descr_size_set; 276 u16 link_failures; 277 bool link_failures_set; 278 u8 fcoe_boot_progress; 279 bool fcoe_boot_progress_set; 280 u64 rx_bcast; 281 bool rx_bcast_set; 282 u64 tx_bcast; 283 bool tx_bcast_set; 284 u16 fcoe_txq_depth; 285 bool fcoe_txq_depth_set; 286 u16 fcoe_rxq_depth; 287 bool fcoe_rxq_depth_set; 288 u64 fcoe_rx_frames; 289 bool fcoe_rx_frames_set; 290 u64 fcoe_rx_bytes; 291 bool fcoe_rx_bytes_set; 292 u64 fcoe_tx_frames; 293 bool fcoe_tx_frames_set; 294 u64 fcoe_tx_bytes; 295 bool fcoe_tx_bytes_set; 296 u16 crc_count; 297 bool crc_count_set; 298 u32 crc_err_src_fcid[5]; 299 bool crc_err_src_fcid_set[5]; 300 struct qed_mfw_tlv_time crc_err[5]; 301 u16 losync_err; 302 bool losync_err_set; 303 u16 losig_err; 304 bool losig_err_set; 305 u16 primtive_err; 306 bool primtive_err_set; 307 u16 disparity_err; 308 bool disparity_err_set; 309 u16 code_violation_err; 310 bool code_violation_err_set; 311 u32 flogi_param[4]; 312 bool flogi_param_set[4]; 313 struct qed_mfw_tlv_time flogi_tstamp; 314 u32 flogi_acc_param[4]; 315 bool flogi_acc_param_set[4]; 316 struct qed_mfw_tlv_time flogi_acc_tstamp; 317 u32 flogi_rjt; 318 bool flogi_rjt_set; 319 struct qed_mfw_tlv_time flogi_rjt_tstamp; 320 u32 fdiscs; 321 bool fdiscs_set; 322 u8 fdisc_acc; 323 bool fdisc_acc_set; 324 u8 fdisc_rjt; 325 bool fdisc_rjt_set; 326 u8 plogi; 327 bool plogi_set; 328 u8 plogi_acc; 329 bool plogi_acc_set; 330 u8 plogi_rjt; 331 bool plogi_rjt_set; 332 u32 plogi_dst_fcid[5]; 333 bool plogi_dst_fcid_set[5]; 334 struct qed_mfw_tlv_time plogi_tstamp[5]; 335 u32 plogi_acc_src_fcid[5]; 336 bool plogi_acc_src_fcid_set[5]; 337 struct qed_mfw_tlv_time plogi_acc_tstamp[5]; 338 u8 tx_plogos; 339 bool tx_plogos_set; 340 u8 plogo_acc; 341 bool plogo_acc_set; 342 u8 plogo_rjt; 343 bool plogo_rjt_set; 344 u32 plogo_src_fcid[5]; 345 bool plogo_src_fcid_set[5]; 346 struct qed_mfw_tlv_time plogo_tstamp[5]; 347 u8 rx_logos; 348 bool rx_logos_set; 349 u8 tx_accs; 350 bool tx_accs_set; 351 u8 tx_prlis; 352 bool tx_prlis_set; 353 u8 rx_accs; 354 bool rx_accs_set; 355 u8 tx_abts; 356 bool tx_abts_set; 357 u8 rx_abts_acc; 358 bool rx_abts_acc_set; 359 u8 rx_abts_rjt; 360 bool rx_abts_rjt_set; 361 u32 abts_dst_fcid[5]; 362 bool abts_dst_fcid_set[5]; 363 struct qed_mfw_tlv_time abts_tstamp[5]; 364 u8 rx_rscn; 365 bool rx_rscn_set; 366 u32 rx_rscn_nport[4]; 367 bool rx_rscn_nport_set[4]; 368 u8 tx_lun_rst; 369 bool tx_lun_rst_set; 370 u8 abort_task_sets; 371 bool abort_task_sets_set; 372 u8 tx_tprlos; 373 bool tx_tprlos_set; 374 u8 tx_nos; 375 bool tx_nos_set; 376 u8 rx_nos; 377 bool rx_nos_set; 378 u8 ols; 379 bool ols_set; 380 u8 lr; 381 bool lr_set; 382 u8 lrr; 383 bool lrr_set; 384 u8 tx_lip; 385 bool tx_lip_set; 386 u8 rx_lip; 387 bool rx_lip_set; 388 u8 eofa; 389 bool eofa_set; 390 u8 eofni; 391 bool eofni_set; 392 u8 scsi_chks; 393 bool scsi_chks_set; 394 u8 scsi_cond_met; 395 bool scsi_cond_met_set; 396 u8 scsi_busy; 397 bool scsi_busy_set; 398 u8 scsi_inter; 399 bool scsi_inter_set; 400 u8 scsi_inter_cond_met; 401 bool scsi_inter_cond_met_set; 402 u8 scsi_rsv_conflicts; 403 bool scsi_rsv_conflicts_set; 404 u8 scsi_tsk_full; 405 bool scsi_tsk_full_set; 406 u8 scsi_aca_active; 407 bool scsi_aca_active_set; 408 u8 scsi_tsk_abort; 409 bool scsi_tsk_abort_set; 410 u32 scsi_rx_chk[5]; 411 bool scsi_rx_chk_set[5]; 412 struct qed_mfw_tlv_time scsi_chk_tstamp[5]; 413 }; 414 415 struct qed_mfw_tlv_iscsi { 416 u8 target_llmnr; 417 bool target_llmnr_set; 418 u8 header_digest; 419 bool header_digest_set; 420 u8 data_digest; 421 bool data_digest_set; 422 u8 auth_method; 423 #define QED_MFW_TLV_AUTH_METHOD_NONE (1) 424 #define QED_MFW_TLV_AUTH_METHOD_CHAP (2) 425 #define QED_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP (3) 426 bool auth_method_set; 427 u16 boot_taget_portal; 428 bool boot_taget_portal_set; 429 u16 frame_size; 430 bool frame_size_set; 431 u16 tx_desc_size; 432 bool tx_desc_size_set; 433 u16 rx_desc_size; 434 bool rx_desc_size_set; 435 u8 boot_progress; 436 bool boot_progress_set; 437 u16 tx_desc_qdepth; 438 bool tx_desc_qdepth_set; 439 u16 rx_desc_qdepth; 440 bool rx_desc_qdepth_set; 441 u64 rx_frames; 442 bool rx_frames_set; 443 u64 rx_bytes; 444 bool rx_bytes_set; 445 u64 tx_frames; 446 bool tx_frames_set; 447 u64 tx_bytes; 448 bool tx_bytes_set; 449 }; 450 451 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \ 452 (void __iomem *)(reg_addr)) 453 454 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr)) 455 456 #define QED_COALESCE_MAX 0x1FF 457 #define QED_DEFAULT_RX_USECS 12 458 #define QED_DEFAULT_TX_USECS 48 459 460 /* forward */ 461 struct qed_dev; 462 463 struct qed_eth_pf_params { 464 /* The following parameters are used during HW-init 465 * and these parameters need to be passed as arguments 466 * to update_pf_params routine invoked before slowpath start 467 */ 468 u16 num_cons; 469 470 /* per-VF number of CIDs */ 471 u8 num_vf_cons; 472 #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32) 473 474 /* To enable arfs, previous to HW-init a positive number needs to be 475 * set [as filters require allocated searcher ILT memory]. 476 * This will set the maximal number of configured steering-filters. 477 */ 478 u32 num_arfs_filters; 479 }; 480 481 struct qed_fcoe_pf_params { 482 /* The following parameters are used during protocol-init */ 483 u64 glbl_q_params_addr; 484 u64 bdq_pbl_base_addr[2]; 485 486 /* The following parameters are used during HW-init 487 * and these parameters need to be passed as arguments 488 * to update_pf_params routine invoked before slowpath start 489 */ 490 u16 num_cons; 491 u16 num_tasks; 492 493 /* The following parameters are used during protocol-init */ 494 u16 sq_num_pbl_pages; 495 496 u16 cq_num_entries; 497 u16 cmdq_num_entries; 498 u16 rq_buffer_log_size; 499 u16 mtu; 500 u16 dummy_icid; 501 u16 bdq_xoff_threshold[2]; 502 u16 bdq_xon_threshold[2]; 503 u16 rq_buffer_size; 504 u8 num_cqs; /* num of global CQs */ 505 u8 log_page_size; 506 u8 gl_rq_pi; 507 u8 gl_cmd_pi; 508 u8 debug_mode; 509 u8 is_target; 510 u8 bdq_pbl_num_entries[2]; 511 }; 512 513 /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */ 514 struct qed_iscsi_pf_params { 515 u64 glbl_q_params_addr; 516 u64 bdq_pbl_base_addr[3]; 517 u16 cq_num_entries; 518 u16 cmdq_num_entries; 519 u32 two_msl_timer; 520 u16 tx_sws_timer; 521 522 /* The following parameters are used during HW-init 523 * and these parameters need to be passed as arguments 524 * to update_pf_params routine invoked before slowpath start 525 */ 526 u16 num_cons; 527 u16 num_tasks; 528 529 /* The following parameters are used during protocol-init */ 530 u16 half_way_close_timeout; 531 u16 bdq_xoff_threshold[3]; 532 u16 bdq_xon_threshold[3]; 533 u16 cmdq_xoff_threshold; 534 u16 cmdq_xon_threshold; 535 u16 rq_buffer_size; 536 537 u8 num_sq_pages_in_ring; 538 u8 num_r2tq_pages_in_ring; 539 u8 num_uhq_pages_in_ring; 540 u8 num_queues; 541 u8 log_page_size; 542 u8 rqe_log_size; 543 u8 max_fin_rt; 544 u8 gl_rq_pi; 545 u8 gl_cmd_pi; 546 u8 debug_mode; 547 u8 ll2_ooo_queue_id; 548 549 u8 is_target; 550 u8 is_soc_en; 551 u8 soc_num_of_blocks_log; 552 u8 bdq_pbl_num_entries[3]; 553 }; 554 555 struct qed_rdma_pf_params { 556 /* Supplied to QED during resource allocation (may affect the ILT and 557 * the doorbell BAR). 558 */ 559 u32 min_dpis; /* number of requested DPIs */ 560 u32 num_qps; /* number of requested Queue Pairs */ 561 u32 num_srqs; /* number of requested SRQ */ 562 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */ 563 u8 gl_pi; /* protocol index */ 564 565 /* Will allocate rate limiters to be used with QPs */ 566 u8 enable_dcqcn; 567 }; 568 569 struct qed_pf_params { 570 struct qed_eth_pf_params eth_pf_params; 571 struct qed_fcoe_pf_params fcoe_pf_params; 572 struct qed_iscsi_pf_params iscsi_pf_params; 573 struct qed_rdma_pf_params rdma_pf_params; 574 }; 575 576 enum qed_int_mode { 577 QED_INT_MODE_INTA, 578 QED_INT_MODE_MSIX, 579 QED_INT_MODE_MSI, 580 QED_INT_MODE_POLL, 581 }; 582 583 struct qed_sb_info { 584 struct status_block_e4 *sb_virt; 585 dma_addr_t sb_phys; 586 u32 sb_ack; /* Last given ack */ 587 u16 igu_sb_id; 588 void __iomem *igu_addr; 589 u8 flags; 590 #define QED_SB_INFO_INIT 0x1 591 #define QED_SB_INFO_SETUP 0x2 592 593 struct qed_dev *cdev; 594 }; 595 596 enum qed_dev_type { 597 QED_DEV_TYPE_BB, 598 QED_DEV_TYPE_AH, 599 }; 600 601 struct qed_dev_info { 602 unsigned long pci_mem_start; 603 unsigned long pci_mem_end; 604 unsigned int pci_irq; 605 u8 num_hwfns; 606 607 u8 hw_mac[ETH_ALEN]; 608 609 /* FW version */ 610 u16 fw_major; 611 u16 fw_minor; 612 u16 fw_rev; 613 u16 fw_eng; 614 615 /* MFW version */ 616 u32 mfw_rev; 617 #define QED_MFW_VERSION_0_MASK 0x000000FF 618 #define QED_MFW_VERSION_0_OFFSET 0 619 #define QED_MFW_VERSION_1_MASK 0x0000FF00 620 #define QED_MFW_VERSION_1_OFFSET 8 621 #define QED_MFW_VERSION_2_MASK 0x00FF0000 622 #define QED_MFW_VERSION_2_OFFSET 16 623 #define QED_MFW_VERSION_3_MASK 0xFF000000 624 #define QED_MFW_VERSION_3_OFFSET 24 625 626 u32 flash_size; 627 bool b_inter_pf_switch; 628 bool tx_switching; 629 bool rdma_supported; 630 u16 mtu; 631 632 bool wol_support; 633 634 /* MBI version */ 635 u32 mbi_version; 636 #define QED_MBI_VERSION_0_MASK 0x000000FF 637 #define QED_MBI_VERSION_0_OFFSET 0 638 #define QED_MBI_VERSION_1_MASK 0x0000FF00 639 #define QED_MBI_VERSION_1_OFFSET 8 640 #define QED_MBI_VERSION_2_MASK 0x00FF0000 641 #define QED_MBI_VERSION_2_OFFSET 16 642 643 enum qed_dev_type dev_type; 644 645 /* Output parameters for qede */ 646 bool vxlan_enable; 647 bool gre_enable; 648 bool geneve_enable; 649 650 u8 abs_pf_id; 651 }; 652 653 enum qed_sb_type { 654 QED_SB_TYPE_L2_QUEUE, 655 QED_SB_TYPE_CNQ, 656 QED_SB_TYPE_STORAGE, 657 }; 658 659 enum qed_protocol { 660 QED_PROTOCOL_ETH, 661 QED_PROTOCOL_ISCSI, 662 QED_PROTOCOL_FCOE, 663 }; 664 665 enum qed_link_mode_bits { 666 QED_LM_FIBRE_BIT = BIT(0), 667 QED_LM_Autoneg_BIT = BIT(1), 668 QED_LM_Asym_Pause_BIT = BIT(2), 669 QED_LM_Pause_BIT = BIT(3), 670 QED_LM_1000baseT_Full_BIT = BIT(4), 671 QED_LM_10000baseT_Full_BIT = BIT(5), 672 QED_LM_10000baseKR_Full_BIT = BIT(6), 673 QED_LM_20000baseKR2_Full_BIT = BIT(7), 674 QED_LM_25000baseKR_Full_BIT = BIT(8), 675 QED_LM_40000baseLR4_Full_BIT = BIT(9), 676 QED_LM_50000baseKR2_Full_BIT = BIT(10), 677 QED_LM_100000baseKR4_Full_BIT = BIT(11), 678 QED_LM_2500baseX_Full_BIT = BIT(12), 679 QED_LM_Backplane_BIT = BIT(13), 680 QED_LM_1000baseKX_Full_BIT = BIT(14), 681 QED_LM_10000baseKX4_Full_BIT = BIT(15), 682 QED_LM_10000baseR_FEC_BIT = BIT(16), 683 QED_LM_40000baseKR4_Full_BIT = BIT(17), 684 QED_LM_40000baseCR4_Full_BIT = BIT(18), 685 QED_LM_40000baseSR4_Full_BIT = BIT(19), 686 QED_LM_25000baseCR_Full_BIT = BIT(20), 687 QED_LM_25000baseSR_Full_BIT = BIT(21), 688 QED_LM_50000baseCR2_Full_BIT = BIT(22), 689 QED_LM_100000baseSR4_Full_BIT = BIT(23), 690 QED_LM_100000baseCR4_Full_BIT = BIT(24), 691 QED_LM_100000baseLR4_ER4_Full_BIT = BIT(25), 692 QED_LM_50000baseSR2_Full_BIT = BIT(26), 693 QED_LM_1000baseX_Full_BIT = BIT(27), 694 QED_LM_10000baseCR_Full_BIT = BIT(28), 695 QED_LM_10000baseSR_Full_BIT = BIT(29), 696 QED_LM_10000baseLR_Full_BIT = BIT(30), 697 QED_LM_10000baseLRM_Full_BIT = BIT(31), 698 QED_LM_COUNT = 32 699 }; 700 701 struct qed_link_params { 702 bool link_up; 703 704 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0) 705 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1) 706 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2) 707 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3) 708 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4) 709 #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5) 710 u32 override_flags; 711 bool autoneg; 712 u32 adv_speeds; 713 u32 forced_speed; 714 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0) 715 #define QED_LINK_PAUSE_RX_ENABLE BIT(1) 716 #define QED_LINK_PAUSE_TX_ENABLE BIT(2) 717 u32 pause_config; 718 #define QED_LINK_LOOPBACK_NONE BIT(0) 719 #define QED_LINK_LOOPBACK_INT_PHY BIT(1) 720 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2) 721 #define QED_LINK_LOOPBACK_EXT BIT(3) 722 #define QED_LINK_LOOPBACK_MAC BIT(4) 723 u32 loopback_mode; 724 struct qed_link_eee_params eee; 725 }; 726 727 struct qed_link_output { 728 bool link_up; 729 730 /* In QED_LM_* defs */ 731 u32 supported_caps; 732 u32 advertised_caps; 733 u32 lp_caps; 734 735 u32 speed; /* In Mb/s */ 736 u8 duplex; /* In DUPLEX defs */ 737 u8 port; /* In PORT defs */ 738 bool autoneg; 739 u32 pause_config; 740 741 /* EEE - capability & param */ 742 bool eee_supported; 743 bool eee_active; 744 u8 sup_caps; 745 struct qed_link_eee_params eee; 746 }; 747 748 struct qed_probe_params { 749 enum qed_protocol protocol; 750 u32 dp_module; 751 u8 dp_level; 752 bool is_vf; 753 }; 754 755 #define QED_DRV_VER_STR_SIZE 12 756 struct qed_slowpath_params { 757 u32 int_mode; 758 u8 drv_major; 759 u8 drv_minor; 760 u8 drv_rev; 761 u8 drv_eng; 762 u8 name[QED_DRV_VER_STR_SIZE]; 763 }; 764 765 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */ 766 767 struct qed_int_info { 768 struct msix_entry *msix; 769 u8 msix_cnt; 770 771 /* This should be updated by the protocol driver */ 772 u8 used_cnt; 773 }; 774 775 struct qed_generic_tlvs { 776 #define QED_TLV_IP_CSUM BIT(0) 777 #define QED_TLV_LSO BIT(1) 778 u16 feat_flags; 779 #define QED_TLV_MAC_COUNT 3 780 u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN]; 781 }; 782 783 #define QED_I2C_DEV_ADDR_A0 0xA0 784 #define QED_I2C_DEV_ADDR_A2 0xA2 785 786 #define QED_NVM_SIGNATURE 0x12435687 787 788 enum qed_nvm_flash_cmd { 789 QED_NVM_FLASH_CMD_FILE_DATA = 0x2, 790 QED_NVM_FLASH_CMD_FILE_START = 0x3, 791 QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4, 792 QED_NVM_FLASH_CMD_NVM_MAX, 793 }; 794 795 struct qed_common_cb_ops { 796 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc); 797 void (*link_update)(void *dev, 798 struct qed_link_output *link); 799 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type); 800 void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data); 801 void (*get_protocol_tlv_data)(void *dev, void *data); 802 }; 803 804 struct qed_selftest_ops { 805 /** 806 * @brief selftest_interrupt - Perform interrupt test 807 * 808 * @param cdev 809 * 810 * @return 0 on success, error otherwise. 811 */ 812 int (*selftest_interrupt)(struct qed_dev *cdev); 813 814 /** 815 * @brief selftest_memory - Perform memory test 816 * 817 * @param cdev 818 * 819 * @return 0 on success, error otherwise. 820 */ 821 int (*selftest_memory)(struct qed_dev *cdev); 822 823 /** 824 * @brief selftest_register - Perform register test 825 * 826 * @param cdev 827 * 828 * @return 0 on success, error otherwise. 829 */ 830 int (*selftest_register)(struct qed_dev *cdev); 831 832 /** 833 * @brief selftest_clock - Perform clock test 834 * 835 * @param cdev 836 * 837 * @return 0 on success, error otherwise. 838 */ 839 int (*selftest_clock)(struct qed_dev *cdev); 840 841 /** 842 * @brief selftest_nvram - Perform nvram test 843 * 844 * @param cdev 845 * 846 * @return 0 on success, error otherwise. 847 */ 848 int (*selftest_nvram) (struct qed_dev *cdev); 849 }; 850 851 struct qed_common_ops { 852 struct qed_selftest_ops *selftest; 853 854 struct qed_dev* (*probe)(struct pci_dev *dev, 855 struct qed_probe_params *params); 856 857 void (*remove)(struct qed_dev *cdev); 858 859 int (*set_power_state)(struct qed_dev *cdev, 860 pci_power_t state); 861 862 void (*set_name) (struct qed_dev *cdev, char name[]); 863 864 /* Client drivers need to make this call before slowpath_start. 865 * PF params required for the call before slowpath_start is 866 * documented within the qed_pf_params structure definition. 867 */ 868 void (*update_pf_params)(struct qed_dev *cdev, 869 struct qed_pf_params *params); 870 int (*slowpath_start)(struct qed_dev *cdev, 871 struct qed_slowpath_params *params); 872 873 int (*slowpath_stop)(struct qed_dev *cdev); 874 875 /* Requests to use `cnt' interrupts for fastpath. 876 * upon success, returns number of interrupts allocated for fastpath. 877 */ 878 int (*set_fp_int)(struct qed_dev *cdev, 879 u16 cnt); 880 881 /* Fills `info' with pointers required for utilizing interrupts */ 882 int (*get_fp_int)(struct qed_dev *cdev, 883 struct qed_int_info *info); 884 885 u32 (*sb_init)(struct qed_dev *cdev, 886 struct qed_sb_info *sb_info, 887 void *sb_virt_addr, 888 dma_addr_t sb_phy_addr, 889 u16 sb_id, 890 enum qed_sb_type type); 891 892 u32 (*sb_release)(struct qed_dev *cdev, 893 struct qed_sb_info *sb_info, 894 u16 sb_id); 895 896 void (*simd_handler_config)(struct qed_dev *cdev, 897 void *token, 898 int index, 899 void (*handler)(void *)); 900 901 void (*simd_handler_clean)(struct qed_dev *cdev, 902 int index); 903 int (*dbg_grc)(struct qed_dev *cdev, 904 void *buffer, u32 *num_dumped_bytes); 905 906 int (*dbg_grc_size)(struct qed_dev *cdev); 907 908 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer); 909 910 int (*dbg_all_data_size) (struct qed_dev *cdev); 911 912 /** 913 * @brief can_link_change - can the instance change the link or not 914 * 915 * @param cdev 916 * 917 * @return true if link-change is allowed, false otherwise. 918 */ 919 bool (*can_link_change)(struct qed_dev *cdev); 920 921 /** 922 * @brief set_link - set links according to params 923 * 924 * @param cdev 925 * @param params - values used to override the default link configuration 926 * 927 * @return 0 on success, error otherwise. 928 */ 929 int (*set_link)(struct qed_dev *cdev, 930 struct qed_link_params *params); 931 932 /** 933 * @brief get_link - returns the current link state. 934 * 935 * @param cdev 936 * @param if_link - structure to be filled with current link configuration. 937 */ 938 void (*get_link)(struct qed_dev *cdev, 939 struct qed_link_output *if_link); 940 941 /** 942 * @brief - drains chip in case Tx completions fail to arrive due to pause. 943 * 944 * @param cdev 945 */ 946 int (*drain)(struct qed_dev *cdev); 947 948 /** 949 * @brief update_msglvl - update module debug level 950 * 951 * @param cdev 952 * @param dp_module 953 * @param dp_level 954 */ 955 void (*update_msglvl)(struct qed_dev *cdev, 956 u32 dp_module, 957 u8 dp_level); 958 959 int (*chain_alloc)(struct qed_dev *cdev, 960 enum qed_chain_use_mode intended_use, 961 enum qed_chain_mode mode, 962 enum qed_chain_cnt_type cnt_type, 963 u32 num_elems, 964 size_t elem_size, 965 struct qed_chain *p_chain, 966 struct qed_chain_ext_pbl *ext_pbl); 967 968 void (*chain_free)(struct qed_dev *cdev, 969 struct qed_chain *p_chain); 970 971 /** 972 * @brief nvm_flash - Flash nvm data. 973 * 974 * @param cdev 975 * @param name - file containing the data 976 * 977 * @return 0 on success, error otherwise. 978 */ 979 int (*nvm_flash)(struct qed_dev *cdev, const char *name); 980 981 /** 982 * @brief nvm_get_image - reads an entire image from nvram 983 * 984 * @param cdev 985 * @param type - type of the request nvram image 986 * @param buf - preallocated buffer to fill with the image 987 * @param len - length of the allocated buffer 988 * 989 * @return 0 on success, error otherwise 990 */ 991 int (*nvm_get_image)(struct qed_dev *cdev, 992 enum qed_nvm_images type, u8 *buf, u16 len); 993 994 /** 995 * @brief set_coalesce - Configure Rx coalesce value in usec 996 * 997 * @param cdev 998 * @param rx_coal - Rx coalesce value in usec 999 * @param tx_coal - Tx coalesce value in usec 1000 * @param qid - Queue index 1001 * @param sb_id - Status Block Id 1002 * 1003 * @return 0 on success, error otherwise. 1004 */ 1005 int (*set_coalesce)(struct qed_dev *cdev, 1006 u16 rx_coal, u16 tx_coal, void *handle); 1007 1008 /** 1009 * @brief set_led - Configure LED mode 1010 * 1011 * @param cdev 1012 * @param mode - LED mode 1013 * 1014 * @return 0 on success, error otherwise. 1015 */ 1016 int (*set_led)(struct qed_dev *cdev, 1017 enum qed_led_mode mode); 1018 1019 /** 1020 * @brief update_drv_state - API to inform the change in the driver state. 1021 * 1022 * @param cdev 1023 * @param active 1024 * 1025 */ 1026 int (*update_drv_state)(struct qed_dev *cdev, bool active); 1027 1028 /** 1029 * @brief update_mac - API to inform the change in the mac address 1030 * 1031 * @param cdev 1032 * @param mac 1033 * 1034 */ 1035 int (*update_mac)(struct qed_dev *cdev, u8 *mac); 1036 1037 /** 1038 * @brief update_mtu - API to inform the change in the mtu 1039 * 1040 * @param cdev 1041 * @param mtu 1042 * 1043 */ 1044 int (*update_mtu)(struct qed_dev *cdev, u16 mtu); 1045 1046 /** 1047 * @brief update_wol - update of changes in the WoL configuration 1048 * 1049 * @param cdev 1050 * @param enabled - true iff WoL should be enabled. 1051 */ 1052 int (*update_wol) (struct qed_dev *cdev, bool enabled); 1053 1054 /** 1055 * @brief read_module_eeprom 1056 * 1057 * @param cdev 1058 * @param buf - buffer 1059 * @param dev_addr - PHY device memory region 1060 * @param offset - offset into eeprom contents to be read 1061 * @param len - buffer length, i.e., max bytes to be read 1062 */ 1063 int (*read_module_eeprom)(struct qed_dev *cdev, 1064 char *buf, u8 dev_addr, u32 offset, u32 len); 1065 }; 1066 1067 #define MASK_FIELD(_name, _value) \ 1068 ((_value) &= (_name ## _MASK)) 1069 1070 #define FIELD_VALUE(_name, _value) \ 1071 ((_value & _name ## _MASK) << _name ## _SHIFT) 1072 1073 #define SET_FIELD(value, name, flag) \ 1074 do { \ 1075 (value) &= ~(name ## _MASK << name ## _SHIFT); \ 1076 (value) |= (((u64)flag) << (name ## _SHIFT)); \ 1077 } while (0) 1078 1079 #define GET_FIELD(value, name) \ 1080 (((value) >> (name ## _SHIFT)) & name ## _MASK) 1081 1082 /* Debug print definitions */ 1083 #define DP_ERR(cdev, fmt, ...) \ 1084 do { \ 1085 pr_err("[%s:%d(%s)]" fmt, \ 1086 __func__, __LINE__, \ 1087 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 1088 ## __VA_ARGS__); \ 1089 } while (0) 1090 1091 #define DP_NOTICE(cdev, fmt, ...) \ 1092 do { \ 1093 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \ 1094 pr_notice("[%s:%d(%s)]" fmt, \ 1095 __func__, __LINE__, \ 1096 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 1097 ## __VA_ARGS__); \ 1098 \ 1099 } \ 1100 } while (0) 1101 1102 #define DP_INFO(cdev, fmt, ...) \ 1103 do { \ 1104 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \ 1105 pr_notice("[%s:%d(%s)]" fmt, \ 1106 __func__, __LINE__, \ 1107 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 1108 ## __VA_ARGS__); \ 1109 } \ 1110 } while (0) 1111 1112 #define DP_VERBOSE(cdev, module, fmt, ...) \ 1113 do { \ 1114 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \ 1115 ((cdev)->dp_module & module))) { \ 1116 pr_notice("[%s:%d(%s)]" fmt, \ 1117 __func__, __LINE__, \ 1118 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 1119 ## __VA_ARGS__); \ 1120 } \ 1121 } while (0) 1122 1123 enum DP_LEVEL { 1124 QED_LEVEL_VERBOSE = 0x0, 1125 QED_LEVEL_INFO = 0x1, 1126 QED_LEVEL_NOTICE = 0x2, 1127 QED_LEVEL_ERR = 0x3, 1128 }; 1129 1130 #define QED_LOG_LEVEL_SHIFT (30) 1131 #define QED_LOG_VERBOSE_MASK (0x3fffffff) 1132 #define QED_LOG_INFO_MASK (0x40000000) 1133 #define QED_LOG_NOTICE_MASK (0x80000000) 1134 1135 enum DP_MODULE { 1136 QED_MSG_SPQ = 0x10000, 1137 QED_MSG_STATS = 0x20000, 1138 QED_MSG_DCB = 0x40000, 1139 QED_MSG_IOV = 0x80000, 1140 QED_MSG_SP = 0x100000, 1141 QED_MSG_STORAGE = 0x200000, 1142 QED_MSG_CXT = 0x800000, 1143 QED_MSG_LL2 = 0x1000000, 1144 QED_MSG_ILT = 0x2000000, 1145 QED_MSG_RDMA = 0x4000000, 1146 QED_MSG_DEBUG = 0x8000000, 1147 /* to be added...up to 0x8000000 */ 1148 }; 1149 1150 enum qed_mf_mode { 1151 QED_MF_DEFAULT, 1152 QED_MF_OVLAN, 1153 QED_MF_NPAR, 1154 }; 1155 1156 struct qed_eth_stats_common { 1157 u64 no_buff_discards; 1158 u64 packet_too_big_discard; 1159 u64 ttl0_discard; 1160 u64 rx_ucast_bytes; 1161 u64 rx_mcast_bytes; 1162 u64 rx_bcast_bytes; 1163 u64 rx_ucast_pkts; 1164 u64 rx_mcast_pkts; 1165 u64 rx_bcast_pkts; 1166 u64 mftag_filter_discards; 1167 u64 mac_filter_discards; 1168 u64 gft_filter_drop; 1169 u64 tx_ucast_bytes; 1170 u64 tx_mcast_bytes; 1171 u64 tx_bcast_bytes; 1172 u64 tx_ucast_pkts; 1173 u64 tx_mcast_pkts; 1174 u64 tx_bcast_pkts; 1175 u64 tx_err_drop_pkts; 1176 u64 tpa_coalesced_pkts; 1177 u64 tpa_coalesced_events; 1178 u64 tpa_aborts_num; 1179 u64 tpa_not_coalesced_pkts; 1180 u64 tpa_coalesced_bytes; 1181 1182 /* port */ 1183 u64 rx_64_byte_packets; 1184 u64 rx_65_to_127_byte_packets; 1185 u64 rx_128_to_255_byte_packets; 1186 u64 rx_256_to_511_byte_packets; 1187 u64 rx_512_to_1023_byte_packets; 1188 u64 rx_1024_to_1518_byte_packets; 1189 u64 rx_crc_errors; 1190 u64 rx_mac_crtl_frames; 1191 u64 rx_pause_frames; 1192 u64 rx_pfc_frames; 1193 u64 rx_align_errors; 1194 u64 rx_carrier_errors; 1195 u64 rx_oversize_packets; 1196 u64 rx_jabbers; 1197 u64 rx_undersize_packets; 1198 u64 rx_fragments; 1199 u64 tx_64_byte_packets; 1200 u64 tx_65_to_127_byte_packets; 1201 u64 tx_128_to_255_byte_packets; 1202 u64 tx_256_to_511_byte_packets; 1203 u64 tx_512_to_1023_byte_packets; 1204 u64 tx_1024_to_1518_byte_packets; 1205 u64 tx_pause_frames; 1206 u64 tx_pfc_frames; 1207 u64 brb_truncates; 1208 u64 brb_discards; 1209 u64 rx_mac_bytes; 1210 u64 rx_mac_uc_packets; 1211 u64 rx_mac_mc_packets; 1212 u64 rx_mac_bc_packets; 1213 u64 rx_mac_frames_ok; 1214 u64 tx_mac_bytes; 1215 u64 tx_mac_uc_packets; 1216 u64 tx_mac_mc_packets; 1217 u64 tx_mac_bc_packets; 1218 u64 tx_mac_ctrl_frames; 1219 u64 link_change_count; 1220 }; 1221 1222 struct qed_eth_stats_bb { 1223 u64 rx_1519_to_1522_byte_packets; 1224 u64 rx_1519_to_2047_byte_packets; 1225 u64 rx_2048_to_4095_byte_packets; 1226 u64 rx_4096_to_9216_byte_packets; 1227 u64 rx_9217_to_16383_byte_packets; 1228 u64 tx_1519_to_2047_byte_packets; 1229 u64 tx_2048_to_4095_byte_packets; 1230 u64 tx_4096_to_9216_byte_packets; 1231 u64 tx_9217_to_16383_byte_packets; 1232 u64 tx_lpi_entry_count; 1233 u64 tx_total_collisions; 1234 }; 1235 1236 struct qed_eth_stats_ah { 1237 u64 rx_1519_to_max_byte_packets; 1238 u64 tx_1519_to_max_byte_packets; 1239 }; 1240 1241 struct qed_eth_stats { 1242 struct qed_eth_stats_common common; 1243 1244 union { 1245 struct qed_eth_stats_bb bb; 1246 struct qed_eth_stats_ah ah; 1247 }; 1248 }; 1249 1250 #define QED_SB_IDX 0x0002 1251 1252 #define RX_PI 0 1253 #define TX_PI(tc) (RX_PI + 1 + tc) 1254 1255 struct qed_sb_cnt_info { 1256 /* Original, current, and free SBs for PF */ 1257 int orig; 1258 int cnt; 1259 int free_cnt; 1260 1261 /* Original, current and free SBS for child VFs */ 1262 int iov_orig; 1263 int iov_cnt; 1264 int free_cnt_iov; 1265 }; 1266 1267 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info) 1268 { 1269 u32 prod = 0; 1270 u16 rc = 0; 1271 1272 prod = le32_to_cpu(sb_info->sb_virt->prod_index) & 1273 STATUS_BLOCK_E4_PROD_INDEX_MASK; 1274 if (sb_info->sb_ack != prod) { 1275 sb_info->sb_ack = prod; 1276 rc |= QED_SB_IDX; 1277 } 1278 1279 /* Let SB update */ 1280 mmiowb(); 1281 return rc; 1282 } 1283 1284 /** 1285 * 1286 * @brief This function creates an update command for interrupts that is 1287 * written to the IGU. 1288 * 1289 * @param sb_info - This is the structure allocated and 1290 * initialized per status block. Assumption is 1291 * that it was initialized using qed_sb_init 1292 * @param int_cmd - Enable/Disable/Nop 1293 * @param upd_flg - whether igu consumer should be 1294 * updated. 1295 * 1296 * @return inline void 1297 */ 1298 static inline void qed_sb_ack(struct qed_sb_info *sb_info, 1299 enum igu_int_cmd int_cmd, 1300 u8 upd_flg) 1301 { 1302 struct igu_prod_cons_update igu_ack = { 0 }; 1303 1304 igu_ack.sb_id_and_flags = 1305 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 1306 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 1307 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 1308 (IGU_SEG_ACCESS_REG << 1309 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 1310 1311 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags); 1312 1313 /* Both segments (interrupts & acks) are written to same place address; 1314 * Need to guarantee all commands will be received (in-order) by HW. 1315 */ 1316 mmiowb(); 1317 barrier(); 1318 } 1319 1320 static inline void __internal_ram_wr(void *p_hwfn, 1321 void __iomem *addr, 1322 int size, 1323 u32 *data) 1324 1325 { 1326 unsigned int i; 1327 1328 for (i = 0; i < size / sizeof(*data); i++) 1329 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]); 1330 } 1331 1332 static inline void internal_ram_wr(void __iomem *addr, 1333 int size, 1334 u32 *data) 1335 { 1336 __internal_ram_wr(NULL, addr, size, data); 1337 } 1338 1339 enum qed_rss_caps { 1340 QED_RSS_IPV4 = 0x1, 1341 QED_RSS_IPV6 = 0x2, 1342 QED_RSS_IPV4_TCP = 0x4, 1343 QED_RSS_IPV6_TCP = 0x8, 1344 QED_RSS_IPV4_UDP = 0x10, 1345 QED_RSS_IPV6_UDP = 0x20, 1346 }; 1347 1348 #define QED_RSS_IND_TABLE_SIZE 128 1349 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */ 1350 #endif 1351