1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _QED_IF_H 34 #define _QED_IF_H 35 36 #include <linux/types.h> 37 #include <linux/interrupt.h> 38 #include <linux/netdevice.h> 39 #include <linux/pci.h> 40 #include <linux/skbuff.h> 41 #include <linux/types.h> 42 #include <asm/byteorder.h> 43 #include <linux/io.h> 44 #include <linux/compiler.h> 45 #include <linux/kernel.h> 46 #include <linux/list.h> 47 #include <linux/slab.h> 48 #include <linux/qed/common_hsi.h> 49 #include <linux/qed/qed_chain.h> 50 51 enum dcbx_protocol_type { 52 DCBX_PROTOCOL_ISCSI, 53 DCBX_PROTOCOL_FCOE, 54 DCBX_PROTOCOL_ROCE, 55 DCBX_PROTOCOL_ROCE_V2, 56 DCBX_PROTOCOL_ETH, 57 DCBX_MAX_PROTOCOL_TYPE 58 }; 59 60 #define QED_ROCE_PROTOCOL_INDEX (3) 61 62 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4 63 #define QED_LLDP_PORT_ID_STAT_LEN 4 64 #define QED_DCBX_MAX_APP_PROTOCOL 32 65 #define QED_MAX_PFC_PRIORITIES 8 66 #define QED_DCBX_DSCP_SIZE 64 67 68 struct qed_dcbx_lldp_remote { 69 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 70 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 71 bool enable_rx; 72 bool enable_tx; 73 u32 tx_interval; 74 u32 max_credit; 75 }; 76 77 struct qed_dcbx_lldp_local { 78 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 79 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 80 }; 81 82 struct qed_dcbx_app_prio { 83 u8 roce; 84 u8 roce_v2; 85 u8 fcoe; 86 u8 iscsi; 87 u8 eth; 88 }; 89 90 struct qed_dbcx_pfc_params { 91 bool willing; 92 bool enabled; 93 u8 prio[QED_MAX_PFC_PRIORITIES]; 94 u8 max_tc; 95 }; 96 97 enum qed_dcbx_sf_ieee_type { 98 QED_DCBX_SF_IEEE_ETHTYPE, 99 QED_DCBX_SF_IEEE_TCP_PORT, 100 QED_DCBX_SF_IEEE_UDP_PORT, 101 QED_DCBX_SF_IEEE_TCP_UDP_PORT 102 }; 103 104 struct qed_app_entry { 105 bool ethtype; 106 enum qed_dcbx_sf_ieee_type sf_ieee; 107 bool enabled; 108 u8 prio; 109 u16 proto_id; 110 enum dcbx_protocol_type proto_type; 111 }; 112 113 struct qed_dcbx_params { 114 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL]; 115 u16 num_app_entries; 116 bool app_willing; 117 bool app_valid; 118 bool app_error; 119 bool ets_willing; 120 bool ets_enabled; 121 bool ets_cbs; 122 bool valid; 123 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES]; 124 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES]; 125 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES]; 126 struct qed_dbcx_pfc_params pfc; 127 u8 max_ets_tc; 128 }; 129 130 struct qed_dcbx_admin_params { 131 struct qed_dcbx_params params; 132 bool valid; 133 }; 134 135 struct qed_dcbx_remote_params { 136 struct qed_dcbx_params params; 137 bool valid; 138 }; 139 140 struct qed_dcbx_operational_params { 141 struct qed_dcbx_app_prio app_prio; 142 struct qed_dcbx_params params; 143 bool valid; 144 bool enabled; 145 bool ieee; 146 bool cee; 147 bool local; 148 u32 err; 149 }; 150 151 struct qed_dcbx_get { 152 struct qed_dcbx_operational_params operational; 153 struct qed_dcbx_lldp_remote lldp_remote; 154 struct qed_dcbx_lldp_local lldp_local; 155 struct qed_dcbx_remote_params remote; 156 struct qed_dcbx_admin_params local; 157 }; 158 159 enum qed_nvm_images { 160 QED_NVM_IMAGE_ISCSI_CFG, 161 QED_NVM_IMAGE_FCOE_CFG, 162 QED_NVM_IMAGE_NVM_CFG1, 163 QED_NVM_IMAGE_DEFAULT_CFG, 164 QED_NVM_IMAGE_NVM_META, 165 }; 166 167 struct qed_link_eee_params { 168 u32 tx_lpi_timer; 169 #define QED_EEE_1G_ADV BIT(0) 170 #define QED_EEE_10G_ADV BIT(1) 171 172 /* Capabilities are represented using QED_EEE_*_ADV values */ 173 u8 adv_caps; 174 u8 lp_adv_caps; 175 bool enable; 176 bool tx_lpi_enable; 177 }; 178 179 enum qed_led_mode { 180 QED_LED_MODE_OFF, 181 QED_LED_MODE_ON, 182 QED_LED_MODE_RESTORE 183 }; 184 185 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \ 186 (void __iomem *)(reg_addr)) 187 188 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr)) 189 190 #define QED_COALESCE_MAX 0x1FF 191 #define QED_DEFAULT_RX_USECS 12 192 #define QED_DEFAULT_TX_USECS 48 193 194 /* forward */ 195 struct qed_dev; 196 197 struct qed_eth_pf_params { 198 /* The following parameters are used during HW-init 199 * and these parameters need to be passed as arguments 200 * to update_pf_params routine invoked before slowpath start 201 */ 202 u16 num_cons; 203 204 /* per-VF number of CIDs */ 205 u8 num_vf_cons; 206 #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32) 207 208 /* To enable arfs, previous to HW-init a positive number needs to be 209 * set [as filters require allocated searcher ILT memory]. 210 * This will set the maximal number of configured steering-filters. 211 */ 212 u32 num_arfs_filters; 213 }; 214 215 struct qed_fcoe_pf_params { 216 /* The following parameters are used during protocol-init */ 217 u64 glbl_q_params_addr; 218 u64 bdq_pbl_base_addr[2]; 219 220 /* The following parameters are used during HW-init 221 * and these parameters need to be passed as arguments 222 * to update_pf_params routine invoked before slowpath start 223 */ 224 u16 num_cons; 225 u16 num_tasks; 226 227 /* The following parameters are used during protocol-init */ 228 u16 sq_num_pbl_pages; 229 230 u16 cq_num_entries; 231 u16 cmdq_num_entries; 232 u16 rq_buffer_log_size; 233 u16 mtu; 234 u16 dummy_icid; 235 u16 bdq_xoff_threshold[2]; 236 u16 bdq_xon_threshold[2]; 237 u16 rq_buffer_size; 238 u8 num_cqs; /* num of global CQs */ 239 u8 log_page_size; 240 u8 gl_rq_pi; 241 u8 gl_cmd_pi; 242 u8 debug_mode; 243 u8 is_target; 244 u8 bdq_pbl_num_entries[2]; 245 }; 246 247 /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */ 248 struct qed_iscsi_pf_params { 249 u64 glbl_q_params_addr; 250 u64 bdq_pbl_base_addr[3]; 251 u16 cq_num_entries; 252 u16 cmdq_num_entries; 253 u32 two_msl_timer; 254 u16 tx_sws_timer; 255 256 /* The following parameters are used during HW-init 257 * and these parameters need to be passed as arguments 258 * to update_pf_params routine invoked before slowpath start 259 */ 260 u16 num_cons; 261 u16 num_tasks; 262 263 /* The following parameters are used during protocol-init */ 264 u16 half_way_close_timeout; 265 u16 bdq_xoff_threshold[3]; 266 u16 bdq_xon_threshold[3]; 267 u16 cmdq_xoff_threshold; 268 u16 cmdq_xon_threshold; 269 u16 rq_buffer_size; 270 271 u8 num_sq_pages_in_ring; 272 u8 num_r2tq_pages_in_ring; 273 u8 num_uhq_pages_in_ring; 274 u8 num_queues; 275 u8 log_page_size; 276 u8 rqe_log_size; 277 u8 max_fin_rt; 278 u8 gl_rq_pi; 279 u8 gl_cmd_pi; 280 u8 debug_mode; 281 u8 ll2_ooo_queue_id; 282 283 u8 is_target; 284 u8 is_soc_en; 285 u8 soc_num_of_blocks_log; 286 u8 bdq_pbl_num_entries[3]; 287 }; 288 289 struct qed_rdma_pf_params { 290 /* Supplied to QED during resource allocation (may affect the ILT and 291 * the doorbell BAR). 292 */ 293 u32 min_dpis; /* number of requested DPIs */ 294 u32 num_qps; /* number of requested Queue Pairs */ 295 u32 num_srqs; /* number of requested SRQ */ 296 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */ 297 u8 gl_pi; /* protocol index */ 298 299 /* Will allocate rate limiters to be used with QPs */ 300 u8 enable_dcqcn; 301 }; 302 303 struct qed_pf_params { 304 struct qed_eth_pf_params eth_pf_params; 305 struct qed_fcoe_pf_params fcoe_pf_params; 306 struct qed_iscsi_pf_params iscsi_pf_params; 307 struct qed_rdma_pf_params rdma_pf_params; 308 }; 309 310 enum qed_int_mode { 311 QED_INT_MODE_INTA, 312 QED_INT_MODE_MSIX, 313 QED_INT_MODE_MSI, 314 QED_INT_MODE_POLL, 315 }; 316 317 struct qed_sb_info { 318 struct status_block_e4 *sb_virt; 319 dma_addr_t sb_phys; 320 u32 sb_ack; /* Last given ack */ 321 u16 igu_sb_id; 322 void __iomem *igu_addr; 323 u8 flags; 324 #define QED_SB_INFO_INIT 0x1 325 #define QED_SB_INFO_SETUP 0x2 326 327 struct qed_dev *cdev; 328 }; 329 330 enum qed_dev_type { 331 QED_DEV_TYPE_BB, 332 QED_DEV_TYPE_AH, 333 }; 334 335 struct qed_dev_info { 336 unsigned long pci_mem_start; 337 unsigned long pci_mem_end; 338 unsigned int pci_irq; 339 u8 num_hwfns; 340 341 u8 hw_mac[ETH_ALEN]; 342 343 /* FW version */ 344 u16 fw_major; 345 u16 fw_minor; 346 u16 fw_rev; 347 u16 fw_eng; 348 349 /* MFW version */ 350 u32 mfw_rev; 351 #define QED_MFW_VERSION_0_MASK 0x000000FF 352 #define QED_MFW_VERSION_0_OFFSET 0 353 #define QED_MFW_VERSION_1_MASK 0x0000FF00 354 #define QED_MFW_VERSION_1_OFFSET 8 355 #define QED_MFW_VERSION_2_MASK 0x00FF0000 356 #define QED_MFW_VERSION_2_OFFSET 16 357 #define QED_MFW_VERSION_3_MASK 0xFF000000 358 #define QED_MFW_VERSION_3_OFFSET 24 359 360 u32 flash_size; 361 bool b_inter_pf_switch; 362 bool tx_switching; 363 bool rdma_supported; 364 u16 mtu; 365 366 bool wol_support; 367 368 /* MBI version */ 369 u32 mbi_version; 370 #define QED_MBI_VERSION_0_MASK 0x000000FF 371 #define QED_MBI_VERSION_0_OFFSET 0 372 #define QED_MBI_VERSION_1_MASK 0x0000FF00 373 #define QED_MBI_VERSION_1_OFFSET 8 374 #define QED_MBI_VERSION_2_MASK 0x00FF0000 375 #define QED_MBI_VERSION_2_OFFSET 16 376 377 enum qed_dev_type dev_type; 378 379 /* Output parameters for qede */ 380 bool vxlan_enable; 381 bool gre_enable; 382 bool geneve_enable; 383 384 u8 abs_pf_id; 385 }; 386 387 enum qed_sb_type { 388 QED_SB_TYPE_L2_QUEUE, 389 QED_SB_TYPE_CNQ, 390 QED_SB_TYPE_STORAGE, 391 }; 392 393 enum qed_protocol { 394 QED_PROTOCOL_ETH, 395 QED_PROTOCOL_ISCSI, 396 QED_PROTOCOL_FCOE, 397 }; 398 399 enum qed_link_mode_bits { 400 QED_LM_FIBRE_BIT = BIT(0), 401 QED_LM_Autoneg_BIT = BIT(1), 402 QED_LM_Asym_Pause_BIT = BIT(2), 403 QED_LM_Pause_BIT = BIT(3), 404 QED_LM_1000baseT_Half_BIT = BIT(4), 405 QED_LM_1000baseT_Full_BIT = BIT(5), 406 QED_LM_10000baseKR_Full_BIT = BIT(6), 407 QED_LM_25000baseKR_Full_BIT = BIT(7), 408 QED_LM_40000baseLR4_Full_BIT = BIT(8), 409 QED_LM_50000baseKR2_Full_BIT = BIT(9), 410 QED_LM_100000baseKR4_Full_BIT = BIT(10), 411 QED_LM_COUNT = 11 412 }; 413 414 struct qed_link_params { 415 bool link_up; 416 417 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0) 418 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1) 419 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2) 420 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3) 421 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4) 422 #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5) 423 u32 override_flags; 424 bool autoneg; 425 u32 adv_speeds; 426 u32 forced_speed; 427 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0) 428 #define QED_LINK_PAUSE_RX_ENABLE BIT(1) 429 #define QED_LINK_PAUSE_TX_ENABLE BIT(2) 430 u32 pause_config; 431 #define QED_LINK_LOOPBACK_NONE BIT(0) 432 #define QED_LINK_LOOPBACK_INT_PHY BIT(1) 433 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2) 434 #define QED_LINK_LOOPBACK_EXT BIT(3) 435 #define QED_LINK_LOOPBACK_MAC BIT(4) 436 u32 loopback_mode; 437 struct qed_link_eee_params eee; 438 }; 439 440 struct qed_link_output { 441 bool link_up; 442 443 /* In QED_LM_* defs */ 444 u32 supported_caps; 445 u32 advertised_caps; 446 u32 lp_caps; 447 448 u32 speed; /* In Mb/s */ 449 u8 duplex; /* In DUPLEX defs */ 450 u8 port; /* In PORT defs */ 451 bool autoneg; 452 u32 pause_config; 453 454 /* EEE - capability & param */ 455 bool eee_supported; 456 bool eee_active; 457 u8 sup_caps; 458 struct qed_link_eee_params eee; 459 }; 460 461 struct qed_probe_params { 462 enum qed_protocol protocol; 463 u32 dp_module; 464 u8 dp_level; 465 bool is_vf; 466 }; 467 468 #define QED_DRV_VER_STR_SIZE 12 469 struct qed_slowpath_params { 470 u32 int_mode; 471 u8 drv_major; 472 u8 drv_minor; 473 u8 drv_rev; 474 u8 drv_eng; 475 u8 name[QED_DRV_VER_STR_SIZE]; 476 }; 477 478 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */ 479 480 struct qed_int_info { 481 struct msix_entry *msix; 482 u8 msix_cnt; 483 484 /* This should be updated by the protocol driver */ 485 u8 used_cnt; 486 }; 487 488 #define QED_NVM_SIGNATURE 0x12435687 489 490 enum qed_nvm_flash_cmd { 491 QED_NVM_FLASH_CMD_FILE_DATA = 0x2, 492 QED_NVM_FLASH_CMD_FILE_START = 0x3, 493 QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4, 494 QED_NVM_FLASH_CMD_NVM_MAX, 495 }; 496 497 struct qed_common_cb_ops { 498 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc); 499 void (*link_update)(void *dev, 500 struct qed_link_output *link); 501 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type); 502 }; 503 504 struct qed_selftest_ops { 505 /** 506 * @brief selftest_interrupt - Perform interrupt test 507 * 508 * @param cdev 509 * 510 * @return 0 on success, error otherwise. 511 */ 512 int (*selftest_interrupt)(struct qed_dev *cdev); 513 514 /** 515 * @brief selftest_memory - Perform memory test 516 * 517 * @param cdev 518 * 519 * @return 0 on success, error otherwise. 520 */ 521 int (*selftest_memory)(struct qed_dev *cdev); 522 523 /** 524 * @brief selftest_register - Perform register test 525 * 526 * @param cdev 527 * 528 * @return 0 on success, error otherwise. 529 */ 530 int (*selftest_register)(struct qed_dev *cdev); 531 532 /** 533 * @brief selftest_clock - Perform clock test 534 * 535 * @param cdev 536 * 537 * @return 0 on success, error otherwise. 538 */ 539 int (*selftest_clock)(struct qed_dev *cdev); 540 541 /** 542 * @brief selftest_nvram - Perform nvram test 543 * 544 * @param cdev 545 * 546 * @return 0 on success, error otherwise. 547 */ 548 int (*selftest_nvram) (struct qed_dev *cdev); 549 }; 550 551 struct qed_common_ops { 552 struct qed_selftest_ops *selftest; 553 554 struct qed_dev* (*probe)(struct pci_dev *dev, 555 struct qed_probe_params *params); 556 557 void (*remove)(struct qed_dev *cdev); 558 559 int (*set_power_state)(struct qed_dev *cdev, 560 pci_power_t state); 561 562 void (*set_name) (struct qed_dev *cdev, char name[]); 563 564 /* Client drivers need to make this call before slowpath_start. 565 * PF params required for the call before slowpath_start is 566 * documented within the qed_pf_params structure definition. 567 */ 568 void (*update_pf_params)(struct qed_dev *cdev, 569 struct qed_pf_params *params); 570 int (*slowpath_start)(struct qed_dev *cdev, 571 struct qed_slowpath_params *params); 572 573 int (*slowpath_stop)(struct qed_dev *cdev); 574 575 /* Requests to use `cnt' interrupts for fastpath. 576 * upon success, returns number of interrupts allocated for fastpath. 577 */ 578 int (*set_fp_int)(struct qed_dev *cdev, 579 u16 cnt); 580 581 /* Fills `info' with pointers required for utilizing interrupts */ 582 int (*get_fp_int)(struct qed_dev *cdev, 583 struct qed_int_info *info); 584 585 u32 (*sb_init)(struct qed_dev *cdev, 586 struct qed_sb_info *sb_info, 587 void *sb_virt_addr, 588 dma_addr_t sb_phy_addr, 589 u16 sb_id, 590 enum qed_sb_type type); 591 592 u32 (*sb_release)(struct qed_dev *cdev, 593 struct qed_sb_info *sb_info, 594 u16 sb_id); 595 596 void (*simd_handler_config)(struct qed_dev *cdev, 597 void *token, 598 int index, 599 void (*handler)(void *)); 600 601 void (*simd_handler_clean)(struct qed_dev *cdev, 602 int index); 603 int (*dbg_grc)(struct qed_dev *cdev, 604 void *buffer, u32 *num_dumped_bytes); 605 606 int (*dbg_grc_size)(struct qed_dev *cdev); 607 608 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer); 609 610 int (*dbg_all_data_size) (struct qed_dev *cdev); 611 612 /** 613 * @brief can_link_change - can the instance change the link or not 614 * 615 * @param cdev 616 * 617 * @return true if link-change is allowed, false otherwise. 618 */ 619 bool (*can_link_change)(struct qed_dev *cdev); 620 621 /** 622 * @brief set_link - set links according to params 623 * 624 * @param cdev 625 * @param params - values used to override the default link configuration 626 * 627 * @return 0 on success, error otherwise. 628 */ 629 int (*set_link)(struct qed_dev *cdev, 630 struct qed_link_params *params); 631 632 /** 633 * @brief get_link - returns the current link state. 634 * 635 * @param cdev 636 * @param if_link - structure to be filled with current link configuration. 637 */ 638 void (*get_link)(struct qed_dev *cdev, 639 struct qed_link_output *if_link); 640 641 /** 642 * @brief - drains chip in case Tx completions fail to arrive due to pause. 643 * 644 * @param cdev 645 */ 646 int (*drain)(struct qed_dev *cdev); 647 648 /** 649 * @brief update_msglvl - update module debug level 650 * 651 * @param cdev 652 * @param dp_module 653 * @param dp_level 654 */ 655 void (*update_msglvl)(struct qed_dev *cdev, 656 u32 dp_module, 657 u8 dp_level); 658 659 int (*chain_alloc)(struct qed_dev *cdev, 660 enum qed_chain_use_mode intended_use, 661 enum qed_chain_mode mode, 662 enum qed_chain_cnt_type cnt_type, 663 u32 num_elems, 664 size_t elem_size, 665 struct qed_chain *p_chain, 666 struct qed_chain_ext_pbl *ext_pbl); 667 668 void (*chain_free)(struct qed_dev *cdev, 669 struct qed_chain *p_chain); 670 671 /** 672 * @brief nvm_flash - Flash nvm data. 673 * 674 * @param cdev 675 * @param name - file containing the data 676 * 677 * @return 0 on success, error otherwise. 678 */ 679 int (*nvm_flash)(struct qed_dev *cdev, const char *name); 680 681 /** 682 * @brief nvm_get_image - reads an entire image from nvram 683 * 684 * @param cdev 685 * @param type - type of the request nvram image 686 * @param buf - preallocated buffer to fill with the image 687 * @param len - length of the allocated buffer 688 * 689 * @return 0 on success, error otherwise 690 */ 691 int (*nvm_get_image)(struct qed_dev *cdev, 692 enum qed_nvm_images type, u8 *buf, u16 len); 693 694 /** 695 * @brief set_coalesce - Configure Rx coalesce value in usec 696 * 697 * @param cdev 698 * @param rx_coal - Rx coalesce value in usec 699 * @param tx_coal - Tx coalesce value in usec 700 * @param qid - Queue index 701 * @param sb_id - Status Block Id 702 * 703 * @return 0 on success, error otherwise. 704 */ 705 int (*set_coalesce)(struct qed_dev *cdev, 706 u16 rx_coal, u16 tx_coal, void *handle); 707 708 /** 709 * @brief set_led - Configure LED mode 710 * 711 * @param cdev 712 * @param mode - LED mode 713 * 714 * @return 0 on success, error otherwise. 715 */ 716 int (*set_led)(struct qed_dev *cdev, 717 enum qed_led_mode mode); 718 719 /** 720 * @brief update_drv_state - API to inform the change in the driver state. 721 * 722 * @param cdev 723 * @param active 724 * 725 */ 726 int (*update_drv_state)(struct qed_dev *cdev, bool active); 727 728 /** 729 * @brief update_mac - API to inform the change in the mac address 730 * 731 * @param cdev 732 * @param mac 733 * 734 */ 735 int (*update_mac)(struct qed_dev *cdev, u8 *mac); 736 737 /** 738 * @brief update_mtu - API to inform the change in the mtu 739 * 740 * @param cdev 741 * @param mtu 742 * 743 */ 744 int (*update_mtu)(struct qed_dev *cdev, u16 mtu); 745 746 /** 747 * @brief update_wol - update of changes in the WoL configuration 748 * 749 * @param cdev 750 * @param enabled - true iff WoL should be enabled. 751 */ 752 int (*update_wol) (struct qed_dev *cdev, bool enabled); 753 }; 754 755 #define MASK_FIELD(_name, _value) \ 756 ((_value) &= (_name ## _MASK)) 757 758 #define FIELD_VALUE(_name, _value) \ 759 ((_value & _name ## _MASK) << _name ## _SHIFT) 760 761 #define SET_FIELD(value, name, flag) \ 762 do { \ 763 (value) &= ~(name ## _MASK << name ## _SHIFT); \ 764 (value) |= (((u64)flag) << (name ## _SHIFT)); \ 765 } while (0) 766 767 #define GET_FIELD(value, name) \ 768 (((value) >> (name ## _SHIFT)) & name ## _MASK) 769 770 /* Debug print definitions */ 771 #define DP_ERR(cdev, fmt, ...) \ 772 do { \ 773 pr_err("[%s:%d(%s)]" fmt, \ 774 __func__, __LINE__, \ 775 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 776 ## __VA_ARGS__); \ 777 } while (0) 778 779 #define DP_NOTICE(cdev, fmt, ...) \ 780 do { \ 781 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \ 782 pr_notice("[%s:%d(%s)]" fmt, \ 783 __func__, __LINE__, \ 784 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 785 ## __VA_ARGS__); \ 786 \ 787 } \ 788 } while (0) 789 790 #define DP_INFO(cdev, fmt, ...) \ 791 do { \ 792 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \ 793 pr_notice("[%s:%d(%s)]" fmt, \ 794 __func__, __LINE__, \ 795 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 796 ## __VA_ARGS__); \ 797 } \ 798 } while (0) 799 800 #define DP_VERBOSE(cdev, module, fmt, ...) \ 801 do { \ 802 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \ 803 ((cdev)->dp_module & module))) { \ 804 pr_notice("[%s:%d(%s)]" fmt, \ 805 __func__, __LINE__, \ 806 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 807 ## __VA_ARGS__); \ 808 } \ 809 } while (0) 810 811 enum DP_LEVEL { 812 QED_LEVEL_VERBOSE = 0x0, 813 QED_LEVEL_INFO = 0x1, 814 QED_LEVEL_NOTICE = 0x2, 815 QED_LEVEL_ERR = 0x3, 816 }; 817 818 #define QED_LOG_LEVEL_SHIFT (30) 819 #define QED_LOG_VERBOSE_MASK (0x3fffffff) 820 #define QED_LOG_INFO_MASK (0x40000000) 821 #define QED_LOG_NOTICE_MASK (0x80000000) 822 823 enum DP_MODULE { 824 QED_MSG_SPQ = 0x10000, 825 QED_MSG_STATS = 0x20000, 826 QED_MSG_DCB = 0x40000, 827 QED_MSG_IOV = 0x80000, 828 QED_MSG_SP = 0x100000, 829 QED_MSG_STORAGE = 0x200000, 830 QED_MSG_CXT = 0x800000, 831 QED_MSG_LL2 = 0x1000000, 832 QED_MSG_ILT = 0x2000000, 833 QED_MSG_RDMA = 0x4000000, 834 QED_MSG_DEBUG = 0x8000000, 835 /* to be added...up to 0x8000000 */ 836 }; 837 838 enum qed_mf_mode { 839 QED_MF_DEFAULT, 840 QED_MF_OVLAN, 841 QED_MF_NPAR, 842 }; 843 844 struct qed_eth_stats_common { 845 u64 no_buff_discards; 846 u64 packet_too_big_discard; 847 u64 ttl0_discard; 848 u64 rx_ucast_bytes; 849 u64 rx_mcast_bytes; 850 u64 rx_bcast_bytes; 851 u64 rx_ucast_pkts; 852 u64 rx_mcast_pkts; 853 u64 rx_bcast_pkts; 854 u64 mftag_filter_discards; 855 u64 mac_filter_discards; 856 u64 tx_ucast_bytes; 857 u64 tx_mcast_bytes; 858 u64 tx_bcast_bytes; 859 u64 tx_ucast_pkts; 860 u64 tx_mcast_pkts; 861 u64 tx_bcast_pkts; 862 u64 tx_err_drop_pkts; 863 u64 tpa_coalesced_pkts; 864 u64 tpa_coalesced_events; 865 u64 tpa_aborts_num; 866 u64 tpa_not_coalesced_pkts; 867 u64 tpa_coalesced_bytes; 868 869 /* port */ 870 u64 rx_64_byte_packets; 871 u64 rx_65_to_127_byte_packets; 872 u64 rx_128_to_255_byte_packets; 873 u64 rx_256_to_511_byte_packets; 874 u64 rx_512_to_1023_byte_packets; 875 u64 rx_1024_to_1518_byte_packets; 876 u64 rx_crc_errors; 877 u64 rx_mac_crtl_frames; 878 u64 rx_pause_frames; 879 u64 rx_pfc_frames; 880 u64 rx_align_errors; 881 u64 rx_carrier_errors; 882 u64 rx_oversize_packets; 883 u64 rx_jabbers; 884 u64 rx_undersize_packets; 885 u64 rx_fragments; 886 u64 tx_64_byte_packets; 887 u64 tx_65_to_127_byte_packets; 888 u64 tx_128_to_255_byte_packets; 889 u64 tx_256_to_511_byte_packets; 890 u64 tx_512_to_1023_byte_packets; 891 u64 tx_1024_to_1518_byte_packets; 892 u64 tx_pause_frames; 893 u64 tx_pfc_frames; 894 u64 brb_truncates; 895 u64 brb_discards; 896 u64 rx_mac_bytes; 897 u64 rx_mac_uc_packets; 898 u64 rx_mac_mc_packets; 899 u64 rx_mac_bc_packets; 900 u64 rx_mac_frames_ok; 901 u64 tx_mac_bytes; 902 u64 tx_mac_uc_packets; 903 u64 tx_mac_mc_packets; 904 u64 tx_mac_bc_packets; 905 u64 tx_mac_ctrl_frames; 906 }; 907 908 struct qed_eth_stats_bb { 909 u64 rx_1519_to_1522_byte_packets; 910 u64 rx_1519_to_2047_byte_packets; 911 u64 rx_2048_to_4095_byte_packets; 912 u64 rx_4096_to_9216_byte_packets; 913 u64 rx_9217_to_16383_byte_packets; 914 u64 tx_1519_to_2047_byte_packets; 915 u64 tx_2048_to_4095_byte_packets; 916 u64 tx_4096_to_9216_byte_packets; 917 u64 tx_9217_to_16383_byte_packets; 918 u64 tx_lpi_entry_count; 919 u64 tx_total_collisions; 920 }; 921 922 struct qed_eth_stats_ah { 923 u64 rx_1519_to_max_byte_packets; 924 u64 tx_1519_to_max_byte_packets; 925 }; 926 927 struct qed_eth_stats { 928 struct qed_eth_stats_common common; 929 930 union { 931 struct qed_eth_stats_bb bb; 932 struct qed_eth_stats_ah ah; 933 }; 934 }; 935 936 #define QED_SB_IDX 0x0002 937 938 #define RX_PI 0 939 #define TX_PI(tc) (RX_PI + 1 + tc) 940 941 struct qed_sb_cnt_info { 942 /* Original, current, and free SBs for PF */ 943 int orig; 944 int cnt; 945 int free_cnt; 946 947 /* Original, current and free SBS for child VFs */ 948 int iov_orig; 949 int iov_cnt; 950 int free_cnt_iov; 951 }; 952 953 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info) 954 { 955 u32 prod = 0; 956 u16 rc = 0; 957 958 prod = le32_to_cpu(sb_info->sb_virt->prod_index) & 959 STATUS_BLOCK_E4_PROD_INDEX_MASK; 960 if (sb_info->sb_ack != prod) { 961 sb_info->sb_ack = prod; 962 rc |= QED_SB_IDX; 963 } 964 965 /* Let SB update */ 966 mmiowb(); 967 return rc; 968 } 969 970 /** 971 * 972 * @brief This function creates an update command for interrupts that is 973 * written to the IGU. 974 * 975 * @param sb_info - This is the structure allocated and 976 * initialized per status block. Assumption is 977 * that it was initialized using qed_sb_init 978 * @param int_cmd - Enable/Disable/Nop 979 * @param upd_flg - whether igu consumer should be 980 * updated. 981 * 982 * @return inline void 983 */ 984 static inline void qed_sb_ack(struct qed_sb_info *sb_info, 985 enum igu_int_cmd int_cmd, 986 u8 upd_flg) 987 { 988 struct igu_prod_cons_update igu_ack = { 0 }; 989 990 igu_ack.sb_id_and_flags = 991 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 992 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 993 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 994 (IGU_SEG_ACCESS_REG << 995 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 996 997 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags); 998 999 /* Both segments (interrupts & acks) are written to same place address; 1000 * Need to guarantee all commands will be received (in-order) by HW. 1001 */ 1002 mmiowb(); 1003 barrier(); 1004 } 1005 1006 static inline void __internal_ram_wr(void *p_hwfn, 1007 void __iomem *addr, 1008 int size, 1009 u32 *data) 1010 1011 { 1012 unsigned int i; 1013 1014 for (i = 0; i < size / sizeof(*data); i++) 1015 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]); 1016 } 1017 1018 static inline void internal_ram_wr(void __iomem *addr, 1019 int size, 1020 u32 *data) 1021 { 1022 __internal_ram_wr(NULL, addr, size, data); 1023 } 1024 1025 enum qed_rss_caps { 1026 QED_RSS_IPV4 = 0x1, 1027 QED_RSS_IPV6 = 0x2, 1028 QED_RSS_IPV4_TCP = 0x4, 1029 QED_RSS_IPV6_TCP = 0x8, 1030 QED_RSS_IPV4_UDP = 0x10, 1031 QED_RSS_IPV6_UDP = 0x20, 1032 }; 1033 1034 #define QED_RSS_IND_TABLE_SIZE 128 1035 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */ 1036 #endif 1037