1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _QED_IF_H 34 #define _QED_IF_H 35 36 #include <linux/types.h> 37 #include <linux/interrupt.h> 38 #include <linux/netdevice.h> 39 #include <linux/pci.h> 40 #include <linux/skbuff.h> 41 #include <linux/types.h> 42 #include <asm/byteorder.h> 43 #include <linux/io.h> 44 #include <linux/compiler.h> 45 #include <linux/kernel.h> 46 #include <linux/list.h> 47 #include <linux/slab.h> 48 #include <linux/qed/common_hsi.h> 49 #include <linux/qed/qed_chain.h> 50 51 enum dcbx_protocol_type { 52 DCBX_PROTOCOL_ISCSI, 53 DCBX_PROTOCOL_FCOE, 54 DCBX_PROTOCOL_ROCE, 55 DCBX_PROTOCOL_ROCE_V2, 56 DCBX_PROTOCOL_ETH, 57 DCBX_MAX_PROTOCOL_TYPE 58 }; 59 60 #define QED_ROCE_PROTOCOL_INDEX (3) 61 62 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4 63 #define QED_LLDP_PORT_ID_STAT_LEN 4 64 #define QED_DCBX_MAX_APP_PROTOCOL 32 65 #define QED_MAX_PFC_PRIORITIES 8 66 #define QED_DCBX_DSCP_SIZE 64 67 68 struct qed_dcbx_lldp_remote { 69 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 70 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 71 bool enable_rx; 72 bool enable_tx; 73 u32 tx_interval; 74 u32 max_credit; 75 }; 76 77 struct qed_dcbx_lldp_local { 78 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 79 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 80 }; 81 82 struct qed_dcbx_app_prio { 83 u8 roce; 84 u8 roce_v2; 85 u8 fcoe; 86 u8 iscsi; 87 u8 eth; 88 }; 89 90 struct qed_dbcx_pfc_params { 91 bool willing; 92 bool enabled; 93 u8 prio[QED_MAX_PFC_PRIORITIES]; 94 u8 max_tc; 95 }; 96 97 enum qed_dcbx_sf_ieee_type { 98 QED_DCBX_SF_IEEE_ETHTYPE, 99 QED_DCBX_SF_IEEE_TCP_PORT, 100 QED_DCBX_SF_IEEE_UDP_PORT, 101 QED_DCBX_SF_IEEE_TCP_UDP_PORT 102 }; 103 104 struct qed_app_entry { 105 bool ethtype; 106 enum qed_dcbx_sf_ieee_type sf_ieee; 107 bool enabled; 108 u8 prio; 109 u16 proto_id; 110 enum dcbx_protocol_type proto_type; 111 }; 112 113 struct qed_dcbx_params { 114 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL]; 115 u16 num_app_entries; 116 bool app_willing; 117 bool app_valid; 118 bool app_error; 119 bool ets_willing; 120 bool ets_enabled; 121 bool ets_cbs; 122 bool valid; 123 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES]; 124 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES]; 125 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES]; 126 struct qed_dbcx_pfc_params pfc; 127 u8 max_ets_tc; 128 }; 129 130 struct qed_dcbx_admin_params { 131 struct qed_dcbx_params params; 132 bool valid; 133 }; 134 135 struct qed_dcbx_remote_params { 136 struct qed_dcbx_params params; 137 bool valid; 138 }; 139 140 struct qed_dcbx_operational_params { 141 struct qed_dcbx_app_prio app_prio; 142 struct qed_dcbx_params params; 143 bool valid; 144 bool enabled; 145 bool ieee; 146 bool cee; 147 u32 err; 148 }; 149 150 struct qed_dcbx_get { 151 struct qed_dcbx_operational_params operational; 152 struct qed_dcbx_lldp_remote lldp_remote; 153 struct qed_dcbx_lldp_local lldp_local; 154 struct qed_dcbx_remote_params remote; 155 struct qed_dcbx_admin_params local; 156 }; 157 158 enum qed_led_mode { 159 QED_LED_MODE_OFF, 160 QED_LED_MODE_ON, 161 QED_LED_MODE_RESTORE 162 }; 163 164 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \ 165 (void __iomem *)(reg_addr)) 166 167 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr)) 168 169 #define QED_COALESCE_MAX 0xFF 170 #define QED_DEFAULT_RX_USECS 12 171 172 /* forward */ 173 struct qed_dev; 174 175 struct qed_eth_pf_params { 176 /* The following parameters are used during HW-init 177 * and these parameters need to be passed as arguments 178 * to update_pf_params routine invoked before slowpath start 179 */ 180 u16 num_cons; 181 }; 182 183 struct qed_fcoe_pf_params { 184 /* The following parameters are used during protocol-init */ 185 u64 glbl_q_params_addr; 186 u64 bdq_pbl_base_addr[2]; 187 188 /* The following parameters are used during HW-init 189 * and these parameters need to be passed as arguments 190 * to update_pf_params routine invoked before slowpath start 191 */ 192 u16 num_cons; 193 u16 num_tasks; 194 195 /* The following parameters are used during protocol-init */ 196 u16 sq_num_pbl_pages; 197 198 u16 cq_num_entries; 199 u16 cmdq_num_entries; 200 u16 rq_buffer_log_size; 201 u16 mtu; 202 u16 dummy_icid; 203 u16 bdq_xoff_threshold[2]; 204 u16 bdq_xon_threshold[2]; 205 u16 rq_buffer_size; 206 u8 num_cqs; /* num of global CQs */ 207 u8 log_page_size; 208 u8 gl_rq_pi; 209 u8 gl_cmd_pi; 210 u8 debug_mode; 211 u8 is_target; 212 u8 bdq_pbl_num_entries[2]; 213 }; 214 215 /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */ 216 struct qed_iscsi_pf_params { 217 u64 glbl_q_params_addr; 218 u64 bdq_pbl_base_addr[2]; 219 u32 max_cwnd; 220 u16 cq_num_entries; 221 u16 cmdq_num_entries; 222 u32 two_msl_timer; 223 u16 dup_ack_threshold; 224 u16 tx_sws_timer; 225 u16 min_rto; 226 u16 min_rto_rt; 227 u16 max_rto; 228 229 /* The following parameters are used during HW-init 230 * and these parameters need to be passed as arguments 231 * to update_pf_params routine invoked before slowpath start 232 */ 233 u16 num_cons; 234 u16 num_tasks; 235 236 /* The following parameters are used during protocol-init */ 237 u16 half_way_close_timeout; 238 u16 bdq_xoff_threshold[2]; 239 u16 bdq_xon_threshold[2]; 240 u16 cmdq_xoff_threshold; 241 u16 cmdq_xon_threshold; 242 u16 rq_buffer_size; 243 244 u8 num_sq_pages_in_ring; 245 u8 num_r2tq_pages_in_ring; 246 u8 num_uhq_pages_in_ring; 247 u8 num_queues; 248 u8 log_page_size; 249 u8 rqe_log_size; 250 u8 max_fin_rt; 251 u8 gl_rq_pi; 252 u8 gl_cmd_pi; 253 u8 debug_mode; 254 u8 ll2_ooo_queue_id; 255 u8 ooo_enable; 256 257 u8 is_target; 258 u8 bdq_pbl_num_entries[2]; 259 }; 260 261 struct qed_rdma_pf_params { 262 /* Supplied to QED during resource allocation (may affect the ILT and 263 * the doorbell BAR). 264 */ 265 u32 min_dpis; /* number of requested DPIs */ 266 u32 num_mrs; /* number of requested memory regions */ 267 u32 num_qps; /* number of requested Queue Pairs */ 268 u32 num_srqs; /* number of requested SRQ */ 269 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */ 270 u8 gl_pi; /* protocol index */ 271 272 /* Will allocate rate limiters to be used with QPs */ 273 u8 enable_dcqcn; 274 }; 275 276 struct qed_pf_params { 277 struct qed_eth_pf_params eth_pf_params; 278 struct qed_fcoe_pf_params fcoe_pf_params; 279 struct qed_iscsi_pf_params iscsi_pf_params; 280 struct qed_rdma_pf_params rdma_pf_params; 281 }; 282 283 enum qed_int_mode { 284 QED_INT_MODE_INTA, 285 QED_INT_MODE_MSIX, 286 QED_INT_MODE_MSI, 287 QED_INT_MODE_POLL, 288 }; 289 290 struct qed_sb_info { 291 struct status_block *sb_virt; 292 dma_addr_t sb_phys; 293 u32 sb_ack; /* Last given ack */ 294 u16 igu_sb_id; 295 void __iomem *igu_addr; 296 u8 flags; 297 #define QED_SB_INFO_INIT 0x1 298 #define QED_SB_INFO_SETUP 0x2 299 300 struct qed_dev *cdev; 301 }; 302 303 struct qed_dev_info { 304 unsigned long pci_mem_start; 305 unsigned long pci_mem_end; 306 unsigned int pci_irq; 307 u8 num_hwfns; 308 309 u8 hw_mac[ETH_ALEN]; 310 bool is_mf_default; 311 312 /* FW version */ 313 u16 fw_major; 314 u16 fw_minor; 315 u16 fw_rev; 316 u16 fw_eng; 317 318 /* MFW version */ 319 u32 mfw_rev; 320 321 u32 flash_size; 322 u8 mf_mode; 323 bool tx_switching; 324 bool rdma_supported; 325 u16 mtu; 326 327 bool wol_support; 328 }; 329 330 enum qed_sb_type { 331 QED_SB_TYPE_L2_QUEUE, 332 QED_SB_TYPE_CNQ, 333 QED_SB_TYPE_STORAGE, 334 }; 335 336 enum qed_protocol { 337 QED_PROTOCOL_ETH, 338 QED_PROTOCOL_ISCSI, 339 QED_PROTOCOL_FCOE, 340 }; 341 342 enum qed_link_mode_bits { 343 QED_LM_FIBRE_BIT = BIT(0), 344 QED_LM_Autoneg_BIT = BIT(1), 345 QED_LM_Asym_Pause_BIT = BIT(2), 346 QED_LM_Pause_BIT = BIT(3), 347 QED_LM_1000baseT_Half_BIT = BIT(4), 348 QED_LM_1000baseT_Full_BIT = BIT(5), 349 QED_LM_10000baseKR_Full_BIT = BIT(6), 350 QED_LM_25000baseKR_Full_BIT = BIT(7), 351 QED_LM_40000baseLR4_Full_BIT = BIT(8), 352 QED_LM_50000baseKR2_Full_BIT = BIT(9), 353 QED_LM_100000baseKR4_Full_BIT = BIT(10), 354 QED_LM_COUNT = 11 355 }; 356 357 struct qed_link_params { 358 bool link_up; 359 360 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0) 361 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1) 362 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2) 363 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3) 364 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4) 365 u32 override_flags; 366 bool autoneg; 367 u32 adv_speeds; 368 u32 forced_speed; 369 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0) 370 #define QED_LINK_PAUSE_RX_ENABLE BIT(1) 371 #define QED_LINK_PAUSE_TX_ENABLE BIT(2) 372 u32 pause_config; 373 #define QED_LINK_LOOPBACK_NONE BIT(0) 374 #define QED_LINK_LOOPBACK_INT_PHY BIT(1) 375 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2) 376 #define QED_LINK_LOOPBACK_EXT BIT(3) 377 #define QED_LINK_LOOPBACK_MAC BIT(4) 378 u32 loopback_mode; 379 }; 380 381 struct qed_link_output { 382 bool link_up; 383 384 /* In QED_LM_* defs */ 385 u32 supported_caps; 386 u32 advertised_caps; 387 u32 lp_caps; 388 389 u32 speed; /* In Mb/s */ 390 u8 duplex; /* In DUPLEX defs */ 391 u8 port; /* In PORT defs */ 392 bool autoneg; 393 u32 pause_config; 394 }; 395 396 struct qed_probe_params { 397 enum qed_protocol protocol; 398 u32 dp_module; 399 u8 dp_level; 400 bool is_vf; 401 }; 402 403 #define QED_DRV_VER_STR_SIZE 12 404 struct qed_slowpath_params { 405 u32 int_mode; 406 u8 drv_major; 407 u8 drv_minor; 408 u8 drv_rev; 409 u8 drv_eng; 410 u8 name[QED_DRV_VER_STR_SIZE]; 411 }; 412 413 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */ 414 415 struct qed_int_info { 416 struct msix_entry *msix; 417 u8 msix_cnt; 418 419 /* This should be updated by the protocol driver */ 420 u8 used_cnt; 421 }; 422 423 struct qed_common_cb_ops { 424 void (*link_update)(void *dev, 425 struct qed_link_output *link); 426 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type); 427 }; 428 429 struct qed_selftest_ops { 430 /** 431 * @brief selftest_interrupt - Perform interrupt test 432 * 433 * @param cdev 434 * 435 * @return 0 on success, error otherwise. 436 */ 437 int (*selftest_interrupt)(struct qed_dev *cdev); 438 439 /** 440 * @brief selftest_memory - Perform memory test 441 * 442 * @param cdev 443 * 444 * @return 0 on success, error otherwise. 445 */ 446 int (*selftest_memory)(struct qed_dev *cdev); 447 448 /** 449 * @brief selftest_register - Perform register test 450 * 451 * @param cdev 452 * 453 * @return 0 on success, error otherwise. 454 */ 455 int (*selftest_register)(struct qed_dev *cdev); 456 457 /** 458 * @brief selftest_clock - Perform clock test 459 * 460 * @param cdev 461 * 462 * @return 0 on success, error otherwise. 463 */ 464 int (*selftest_clock)(struct qed_dev *cdev); 465 466 /** 467 * @brief selftest_nvram - Perform nvram test 468 * 469 * @param cdev 470 * 471 * @return 0 on success, error otherwise. 472 */ 473 int (*selftest_nvram) (struct qed_dev *cdev); 474 }; 475 476 struct qed_common_ops { 477 struct qed_selftest_ops *selftest; 478 479 struct qed_dev* (*probe)(struct pci_dev *dev, 480 struct qed_probe_params *params); 481 482 void (*remove)(struct qed_dev *cdev); 483 484 int (*set_power_state)(struct qed_dev *cdev, 485 pci_power_t state); 486 487 void (*set_id)(struct qed_dev *cdev, 488 char name[], 489 char ver_str[]); 490 491 /* Client drivers need to make this call before slowpath_start. 492 * PF params required for the call before slowpath_start is 493 * documented within the qed_pf_params structure definition. 494 */ 495 void (*update_pf_params)(struct qed_dev *cdev, 496 struct qed_pf_params *params); 497 int (*slowpath_start)(struct qed_dev *cdev, 498 struct qed_slowpath_params *params); 499 500 int (*slowpath_stop)(struct qed_dev *cdev); 501 502 /* Requests to use `cnt' interrupts for fastpath. 503 * upon success, returns number of interrupts allocated for fastpath. 504 */ 505 int (*set_fp_int)(struct qed_dev *cdev, 506 u16 cnt); 507 508 /* Fills `info' with pointers required for utilizing interrupts */ 509 int (*get_fp_int)(struct qed_dev *cdev, 510 struct qed_int_info *info); 511 512 u32 (*sb_init)(struct qed_dev *cdev, 513 struct qed_sb_info *sb_info, 514 void *sb_virt_addr, 515 dma_addr_t sb_phy_addr, 516 u16 sb_id, 517 enum qed_sb_type type); 518 519 u32 (*sb_release)(struct qed_dev *cdev, 520 struct qed_sb_info *sb_info, 521 u16 sb_id); 522 523 void (*simd_handler_config)(struct qed_dev *cdev, 524 void *token, 525 int index, 526 void (*handler)(void *)); 527 528 void (*simd_handler_clean)(struct qed_dev *cdev, 529 int index); 530 int (*dbg_grc)(struct qed_dev *cdev, 531 void *buffer, u32 *num_dumped_bytes); 532 533 int (*dbg_grc_size)(struct qed_dev *cdev); 534 535 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer); 536 537 int (*dbg_all_data_size) (struct qed_dev *cdev); 538 539 /** 540 * @brief can_link_change - can the instance change the link or not 541 * 542 * @param cdev 543 * 544 * @return true if link-change is allowed, false otherwise. 545 */ 546 bool (*can_link_change)(struct qed_dev *cdev); 547 548 /** 549 * @brief set_link - set links according to params 550 * 551 * @param cdev 552 * @param params - values used to override the default link configuration 553 * 554 * @return 0 on success, error otherwise. 555 */ 556 int (*set_link)(struct qed_dev *cdev, 557 struct qed_link_params *params); 558 559 /** 560 * @brief get_link - returns the current link state. 561 * 562 * @param cdev 563 * @param if_link - structure to be filled with current link configuration. 564 */ 565 void (*get_link)(struct qed_dev *cdev, 566 struct qed_link_output *if_link); 567 568 /** 569 * @brief - drains chip in case Tx completions fail to arrive due to pause. 570 * 571 * @param cdev 572 */ 573 int (*drain)(struct qed_dev *cdev); 574 575 /** 576 * @brief update_msglvl - update module debug level 577 * 578 * @param cdev 579 * @param dp_module 580 * @param dp_level 581 */ 582 void (*update_msglvl)(struct qed_dev *cdev, 583 u32 dp_module, 584 u8 dp_level); 585 586 int (*chain_alloc)(struct qed_dev *cdev, 587 enum qed_chain_use_mode intended_use, 588 enum qed_chain_mode mode, 589 enum qed_chain_cnt_type cnt_type, 590 u32 num_elems, 591 size_t elem_size, 592 struct qed_chain *p_chain); 593 594 void (*chain_free)(struct qed_dev *cdev, 595 struct qed_chain *p_chain); 596 597 /** 598 * @brief get_coalesce - Get coalesce parameters in usec 599 * 600 * @param cdev 601 * @param rx_coal - Rx coalesce value in usec 602 * @param tx_coal - Tx coalesce value in usec 603 * 604 */ 605 void (*get_coalesce)(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal); 606 607 /** 608 * @brief set_coalesce - Configure Rx coalesce value in usec 609 * 610 * @param cdev 611 * @param rx_coal - Rx coalesce value in usec 612 * @param tx_coal - Tx coalesce value in usec 613 * @param qid - Queue index 614 * @param sb_id - Status Block Id 615 * 616 * @return 0 on success, error otherwise. 617 */ 618 int (*set_coalesce)(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, 619 u8 qid, u16 sb_id); 620 621 /** 622 * @brief set_led - Configure LED mode 623 * 624 * @param cdev 625 * @param mode - LED mode 626 * 627 * @return 0 on success, error otherwise. 628 */ 629 int (*set_led)(struct qed_dev *cdev, 630 enum qed_led_mode mode); 631 632 /** 633 * @brief update_drv_state - API to inform the change in the driver state. 634 * 635 * @param cdev 636 * @param active 637 * 638 */ 639 int (*update_drv_state)(struct qed_dev *cdev, bool active); 640 641 /** 642 * @brief update_mac - API to inform the change in the mac address 643 * 644 * @param cdev 645 * @param mac 646 * 647 */ 648 int (*update_mac)(struct qed_dev *cdev, u8 *mac); 649 650 /** 651 * @brief update_mtu - API to inform the change in the mtu 652 * 653 * @param cdev 654 * @param mtu 655 * 656 */ 657 int (*update_mtu)(struct qed_dev *cdev, u16 mtu); 658 659 /** 660 * @brief update_wol - update of changes in the WoL configuration 661 * 662 * @param cdev 663 * @param enabled - true iff WoL should be enabled. 664 */ 665 int (*update_wol) (struct qed_dev *cdev, bool enabled); 666 }; 667 668 #define MASK_FIELD(_name, _value) \ 669 ((_value) &= (_name ## _MASK)) 670 671 #define FIELD_VALUE(_name, _value) \ 672 ((_value & _name ## _MASK) << _name ## _SHIFT) 673 674 #define SET_FIELD(value, name, flag) \ 675 do { \ 676 (value) &= ~(name ## _MASK << name ## _SHIFT); \ 677 (value) |= (((u64)flag) << (name ## _SHIFT)); \ 678 } while (0) 679 680 #define GET_FIELD(value, name) \ 681 (((value) >> (name ## _SHIFT)) & name ## _MASK) 682 683 /* Debug print definitions */ 684 #define DP_ERR(cdev, fmt, ...) \ 685 pr_err("[%s:%d(%s)]" fmt, \ 686 __func__, __LINE__, \ 687 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 688 ## __VA_ARGS__) \ 689 690 #define DP_NOTICE(cdev, fmt, ...) \ 691 do { \ 692 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \ 693 pr_notice("[%s:%d(%s)]" fmt, \ 694 __func__, __LINE__, \ 695 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 696 ## __VA_ARGS__); \ 697 \ 698 } \ 699 } while (0) 700 701 #define DP_INFO(cdev, fmt, ...) \ 702 do { \ 703 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \ 704 pr_notice("[%s:%d(%s)]" fmt, \ 705 __func__, __LINE__, \ 706 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 707 ## __VA_ARGS__); \ 708 } \ 709 } while (0) 710 711 #define DP_VERBOSE(cdev, module, fmt, ...) \ 712 do { \ 713 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \ 714 ((cdev)->dp_module & module))) { \ 715 pr_notice("[%s:%d(%s)]" fmt, \ 716 __func__, __LINE__, \ 717 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 718 ## __VA_ARGS__); \ 719 } \ 720 } while (0) 721 722 enum DP_LEVEL { 723 QED_LEVEL_VERBOSE = 0x0, 724 QED_LEVEL_INFO = 0x1, 725 QED_LEVEL_NOTICE = 0x2, 726 QED_LEVEL_ERR = 0x3, 727 }; 728 729 #define QED_LOG_LEVEL_SHIFT (30) 730 #define QED_LOG_VERBOSE_MASK (0x3fffffff) 731 #define QED_LOG_INFO_MASK (0x40000000) 732 #define QED_LOG_NOTICE_MASK (0x80000000) 733 734 enum DP_MODULE { 735 QED_MSG_SPQ = 0x10000, 736 QED_MSG_STATS = 0x20000, 737 QED_MSG_DCB = 0x40000, 738 QED_MSG_IOV = 0x80000, 739 QED_MSG_SP = 0x100000, 740 QED_MSG_STORAGE = 0x200000, 741 QED_MSG_CXT = 0x800000, 742 QED_MSG_LL2 = 0x1000000, 743 QED_MSG_ILT = 0x2000000, 744 QED_MSG_RDMA = 0x4000000, 745 QED_MSG_DEBUG = 0x8000000, 746 /* to be added...up to 0x8000000 */ 747 }; 748 749 enum qed_mf_mode { 750 QED_MF_DEFAULT, 751 QED_MF_OVLAN, 752 QED_MF_NPAR, 753 }; 754 755 struct qed_eth_stats { 756 u64 no_buff_discards; 757 u64 packet_too_big_discard; 758 u64 ttl0_discard; 759 u64 rx_ucast_bytes; 760 u64 rx_mcast_bytes; 761 u64 rx_bcast_bytes; 762 u64 rx_ucast_pkts; 763 u64 rx_mcast_pkts; 764 u64 rx_bcast_pkts; 765 u64 mftag_filter_discards; 766 u64 mac_filter_discards; 767 u64 tx_ucast_bytes; 768 u64 tx_mcast_bytes; 769 u64 tx_bcast_bytes; 770 u64 tx_ucast_pkts; 771 u64 tx_mcast_pkts; 772 u64 tx_bcast_pkts; 773 u64 tx_err_drop_pkts; 774 u64 tpa_coalesced_pkts; 775 u64 tpa_coalesced_events; 776 u64 tpa_aborts_num; 777 u64 tpa_not_coalesced_pkts; 778 u64 tpa_coalesced_bytes; 779 780 /* port */ 781 u64 rx_64_byte_packets; 782 u64 rx_65_to_127_byte_packets; 783 u64 rx_128_to_255_byte_packets; 784 u64 rx_256_to_511_byte_packets; 785 u64 rx_512_to_1023_byte_packets; 786 u64 rx_1024_to_1518_byte_packets; 787 u64 rx_1519_to_1522_byte_packets; 788 u64 rx_1519_to_2047_byte_packets; 789 u64 rx_2048_to_4095_byte_packets; 790 u64 rx_4096_to_9216_byte_packets; 791 u64 rx_9217_to_16383_byte_packets; 792 u64 rx_crc_errors; 793 u64 rx_mac_crtl_frames; 794 u64 rx_pause_frames; 795 u64 rx_pfc_frames; 796 u64 rx_align_errors; 797 u64 rx_carrier_errors; 798 u64 rx_oversize_packets; 799 u64 rx_jabbers; 800 u64 rx_undersize_packets; 801 u64 rx_fragments; 802 u64 tx_64_byte_packets; 803 u64 tx_65_to_127_byte_packets; 804 u64 tx_128_to_255_byte_packets; 805 u64 tx_256_to_511_byte_packets; 806 u64 tx_512_to_1023_byte_packets; 807 u64 tx_1024_to_1518_byte_packets; 808 u64 tx_1519_to_2047_byte_packets; 809 u64 tx_2048_to_4095_byte_packets; 810 u64 tx_4096_to_9216_byte_packets; 811 u64 tx_9217_to_16383_byte_packets; 812 u64 tx_pause_frames; 813 u64 tx_pfc_frames; 814 u64 tx_lpi_entry_count; 815 u64 tx_total_collisions; 816 u64 brb_truncates; 817 u64 brb_discards; 818 u64 rx_mac_bytes; 819 u64 rx_mac_uc_packets; 820 u64 rx_mac_mc_packets; 821 u64 rx_mac_bc_packets; 822 u64 rx_mac_frames_ok; 823 u64 tx_mac_bytes; 824 u64 tx_mac_uc_packets; 825 u64 tx_mac_mc_packets; 826 u64 tx_mac_bc_packets; 827 u64 tx_mac_ctrl_frames; 828 }; 829 830 #define QED_SB_IDX 0x0002 831 832 #define RX_PI 0 833 #define TX_PI(tc) (RX_PI + 1 + tc) 834 835 struct qed_sb_cnt_info { 836 int sb_cnt; 837 int sb_iov_cnt; 838 int sb_free_blk; 839 }; 840 841 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info) 842 { 843 u32 prod = 0; 844 u16 rc = 0; 845 846 prod = le32_to_cpu(sb_info->sb_virt->prod_index) & 847 STATUS_BLOCK_PROD_INDEX_MASK; 848 if (sb_info->sb_ack != prod) { 849 sb_info->sb_ack = prod; 850 rc |= QED_SB_IDX; 851 } 852 853 /* Let SB update */ 854 mmiowb(); 855 return rc; 856 } 857 858 /** 859 * 860 * @brief This function creates an update command for interrupts that is 861 * written to the IGU. 862 * 863 * @param sb_info - This is the structure allocated and 864 * initialized per status block. Assumption is 865 * that it was initialized using qed_sb_init 866 * @param int_cmd - Enable/Disable/Nop 867 * @param upd_flg - whether igu consumer should be 868 * updated. 869 * 870 * @return inline void 871 */ 872 static inline void qed_sb_ack(struct qed_sb_info *sb_info, 873 enum igu_int_cmd int_cmd, 874 u8 upd_flg) 875 { 876 struct igu_prod_cons_update igu_ack = { 0 }; 877 878 igu_ack.sb_id_and_flags = 879 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 880 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 881 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 882 (IGU_SEG_ACCESS_REG << 883 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 884 885 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags); 886 887 /* Both segments (interrupts & acks) are written to same place address; 888 * Need to guarantee all commands will be received (in-order) by HW. 889 */ 890 mmiowb(); 891 barrier(); 892 } 893 894 static inline void __internal_ram_wr(void *p_hwfn, 895 void __iomem *addr, 896 int size, 897 u32 *data) 898 899 { 900 unsigned int i; 901 902 for (i = 0; i < size / sizeof(*data); i++) 903 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]); 904 } 905 906 static inline void internal_ram_wr(void __iomem *addr, 907 int size, 908 u32 *data) 909 { 910 __internal_ram_wr(NULL, addr, size, data); 911 } 912 913 enum qed_rss_caps { 914 QED_RSS_IPV4 = 0x1, 915 QED_RSS_IPV6 = 0x2, 916 QED_RSS_IPV4_TCP = 0x4, 917 QED_RSS_IPV6_TCP = 0x8, 918 QED_RSS_IPV4_UDP = 0x10, 919 QED_RSS_IPV6_UDP = 0x20, 920 }; 921 922 #define QED_RSS_IND_TABLE_SIZE 128 923 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */ 924 #endif 925