1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _QED_IF_H 34 #define _QED_IF_H 35 36 #include <linux/types.h> 37 #include <linux/interrupt.h> 38 #include <linux/netdevice.h> 39 #include <linux/pci.h> 40 #include <linux/skbuff.h> 41 #include <linux/types.h> 42 #include <asm/byteorder.h> 43 #include <linux/io.h> 44 #include <linux/compiler.h> 45 #include <linux/kernel.h> 46 #include <linux/list.h> 47 #include <linux/slab.h> 48 #include <linux/qed/common_hsi.h> 49 #include <linux/qed/qed_chain.h> 50 51 enum dcbx_protocol_type { 52 DCBX_PROTOCOL_ISCSI, 53 DCBX_PROTOCOL_FCOE, 54 DCBX_PROTOCOL_ROCE, 55 DCBX_PROTOCOL_ROCE_V2, 56 DCBX_PROTOCOL_ETH, 57 DCBX_MAX_PROTOCOL_TYPE 58 }; 59 60 #define QED_ROCE_PROTOCOL_INDEX (3) 61 62 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4 63 #define QED_LLDP_PORT_ID_STAT_LEN 4 64 #define QED_DCBX_MAX_APP_PROTOCOL 32 65 #define QED_MAX_PFC_PRIORITIES 8 66 #define QED_DCBX_DSCP_SIZE 64 67 68 struct qed_dcbx_lldp_remote { 69 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 70 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 71 bool enable_rx; 72 bool enable_tx; 73 u32 tx_interval; 74 u32 max_credit; 75 }; 76 77 struct qed_dcbx_lldp_local { 78 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 79 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 80 }; 81 82 struct qed_dcbx_app_prio { 83 u8 roce; 84 u8 roce_v2; 85 u8 fcoe; 86 u8 iscsi; 87 u8 eth; 88 }; 89 90 struct qed_dbcx_pfc_params { 91 bool willing; 92 bool enabled; 93 u8 prio[QED_MAX_PFC_PRIORITIES]; 94 u8 max_tc; 95 }; 96 97 enum qed_dcbx_sf_ieee_type { 98 QED_DCBX_SF_IEEE_ETHTYPE, 99 QED_DCBX_SF_IEEE_TCP_PORT, 100 QED_DCBX_SF_IEEE_UDP_PORT, 101 QED_DCBX_SF_IEEE_TCP_UDP_PORT 102 }; 103 104 struct qed_app_entry { 105 bool ethtype; 106 enum qed_dcbx_sf_ieee_type sf_ieee; 107 bool enabled; 108 u8 prio; 109 u16 proto_id; 110 enum dcbx_protocol_type proto_type; 111 }; 112 113 struct qed_dcbx_params { 114 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL]; 115 u16 num_app_entries; 116 bool app_willing; 117 bool app_valid; 118 bool app_error; 119 bool ets_willing; 120 bool ets_enabled; 121 bool ets_cbs; 122 bool valid; 123 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES]; 124 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES]; 125 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES]; 126 struct qed_dbcx_pfc_params pfc; 127 u8 max_ets_tc; 128 }; 129 130 struct qed_dcbx_admin_params { 131 struct qed_dcbx_params params; 132 bool valid; 133 }; 134 135 struct qed_dcbx_remote_params { 136 struct qed_dcbx_params params; 137 bool valid; 138 }; 139 140 struct qed_dcbx_operational_params { 141 struct qed_dcbx_app_prio app_prio; 142 struct qed_dcbx_params params; 143 bool valid; 144 bool enabled; 145 bool ieee; 146 bool cee; 147 bool local; 148 u32 err; 149 }; 150 151 struct qed_dcbx_get { 152 struct qed_dcbx_operational_params operational; 153 struct qed_dcbx_lldp_remote lldp_remote; 154 struct qed_dcbx_lldp_local lldp_local; 155 struct qed_dcbx_remote_params remote; 156 struct qed_dcbx_admin_params local; 157 }; 158 159 enum qed_nvm_images { 160 QED_NVM_IMAGE_ISCSI_CFG, 161 QED_NVM_IMAGE_FCOE_CFG, 162 }; 163 164 enum qed_led_mode { 165 QED_LED_MODE_OFF, 166 QED_LED_MODE_ON, 167 QED_LED_MODE_RESTORE 168 }; 169 170 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \ 171 (void __iomem *)(reg_addr)) 172 173 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr)) 174 175 #define QED_COALESCE_MAX 0xFF 176 #define QED_DEFAULT_RX_USECS 12 177 178 /* forward */ 179 struct qed_dev; 180 181 struct qed_eth_pf_params { 182 /* The following parameters are used during HW-init 183 * and these parameters need to be passed as arguments 184 * to update_pf_params routine invoked before slowpath start 185 */ 186 u16 num_cons; 187 188 /* per-VF number of CIDs */ 189 u8 num_vf_cons; 190 #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32) 191 192 /* To enable arfs, previous to HW-init a positive number needs to be 193 * set [as filters require allocated searcher ILT memory]. 194 * This will set the maximal number of configured steering-filters. 195 */ 196 u32 num_arfs_filters; 197 }; 198 199 struct qed_fcoe_pf_params { 200 /* The following parameters are used during protocol-init */ 201 u64 glbl_q_params_addr; 202 u64 bdq_pbl_base_addr[2]; 203 204 /* The following parameters are used during HW-init 205 * and these parameters need to be passed as arguments 206 * to update_pf_params routine invoked before slowpath start 207 */ 208 u16 num_cons; 209 u16 num_tasks; 210 211 /* The following parameters are used during protocol-init */ 212 u16 sq_num_pbl_pages; 213 214 u16 cq_num_entries; 215 u16 cmdq_num_entries; 216 u16 rq_buffer_log_size; 217 u16 mtu; 218 u16 dummy_icid; 219 u16 bdq_xoff_threshold[2]; 220 u16 bdq_xon_threshold[2]; 221 u16 rq_buffer_size; 222 u8 num_cqs; /* num of global CQs */ 223 u8 log_page_size; 224 u8 gl_rq_pi; 225 u8 gl_cmd_pi; 226 u8 debug_mode; 227 u8 is_target; 228 u8 bdq_pbl_num_entries[2]; 229 }; 230 231 /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */ 232 struct qed_iscsi_pf_params { 233 u64 glbl_q_params_addr; 234 u64 bdq_pbl_base_addr[2]; 235 u32 max_cwnd; 236 u16 cq_num_entries; 237 u16 cmdq_num_entries; 238 u32 two_msl_timer; 239 u16 dup_ack_threshold; 240 u16 tx_sws_timer; 241 u16 min_rto; 242 u16 min_rto_rt; 243 u16 max_rto; 244 245 /* The following parameters are used during HW-init 246 * and these parameters need to be passed as arguments 247 * to update_pf_params routine invoked before slowpath start 248 */ 249 u16 num_cons; 250 u16 num_tasks; 251 252 /* The following parameters are used during protocol-init */ 253 u16 half_way_close_timeout; 254 u16 bdq_xoff_threshold[2]; 255 u16 bdq_xon_threshold[2]; 256 u16 cmdq_xoff_threshold; 257 u16 cmdq_xon_threshold; 258 u16 rq_buffer_size; 259 260 u8 num_sq_pages_in_ring; 261 u8 num_r2tq_pages_in_ring; 262 u8 num_uhq_pages_in_ring; 263 u8 num_queues; 264 u8 log_page_size; 265 u8 rqe_log_size; 266 u8 max_fin_rt; 267 u8 gl_rq_pi; 268 u8 gl_cmd_pi; 269 u8 debug_mode; 270 u8 ll2_ooo_queue_id; 271 u8 ooo_enable; 272 273 u8 is_target; 274 u8 bdq_pbl_num_entries[2]; 275 }; 276 277 struct qed_rdma_pf_params { 278 /* Supplied to QED during resource allocation (may affect the ILT and 279 * the doorbell BAR). 280 */ 281 u32 min_dpis; /* number of requested DPIs */ 282 u32 num_qps; /* number of requested Queue Pairs */ 283 u32 num_srqs; /* number of requested SRQ */ 284 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */ 285 u8 gl_pi; /* protocol index */ 286 287 /* Will allocate rate limiters to be used with QPs */ 288 u8 enable_dcqcn; 289 }; 290 291 struct qed_pf_params { 292 struct qed_eth_pf_params eth_pf_params; 293 struct qed_fcoe_pf_params fcoe_pf_params; 294 struct qed_iscsi_pf_params iscsi_pf_params; 295 struct qed_rdma_pf_params rdma_pf_params; 296 }; 297 298 enum qed_int_mode { 299 QED_INT_MODE_INTA, 300 QED_INT_MODE_MSIX, 301 QED_INT_MODE_MSI, 302 QED_INT_MODE_POLL, 303 }; 304 305 struct qed_sb_info { 306 struct status_block *sb_virt; 307 dma_addr_t sb_phys; 308 u32 sb_ack; /* Last given ack */ 309 u16 igu_sb_id; 310 void __iomem *igu_addr; 311 u8 flags; 312 #define QED_SB_INFO_INIT 0x1 313 #define QED_SB_INFO_SETUP 0x2 314 315 struct qed_dev *cdev; 316 }; 317 318 enum qed_dev_type { 319 QED_DEV_TYPE_BB, 320 QED_DEV_TYPE_AH, 321 }; 322 323 struct qed_dev_info { 324 unsigned long pci_mem_start; 325 unsigned long pci_mem_end; 326 unsigned int pci_irq; 327 u8 num_hwfns; 328 329 u8 hw_mac[ETH_ALEN]; 330 bool is_mf_default; 331 332 /* FW version */ 333 u16 fw_major; 334 u16 fw_minor; 335 u16 fw_rev; 336 u16 fw_eng; 337 338 /* MFW version */ 339 u32 mfw_rev; 340 #define QED_MFW_VERSION_0_MASK 0x000000FF 341 #define QED_MFW_VERSION_0_OFFSET 0 342 #define QED_MFW_VERSION_1_MASK 0x0000FF00 343 #define QED_MFW_VERSION_1_OFFSET 8 344 #define QED_MFW_VERSION_2_MASK 0x00FF0000 345 #define QED_MFW_VERSION_2_OFFSET 16 346 #define QED_MFW_VERSION_3_MASK 0xFF000000 347 #define QED_MFW_VERSION_3_OFFSET 24 348 349 u32 flash_size; 350 u8 mf_mode; 351 bool tx_switching; 352 bool rdma_supported; 353 u16 mtu; 354 355 bool wol_support; 356 357 /* MBI version */ 358 u32 mbi_version; 359 #define QED_MBI_VERSION_0_MASK 0x000000FF 360 #define QED_MBI_VERSION_0_OFFSET 0 361 #define QED_MBI_VERSION_1_MASK 0x0000FF00 362 #define QED_MBI_VERSION_1_OFFSET 8 363 #define QED_MBI_VERSION_2_MASK 0x00FF0000 364 #define QED_MBI_VERSION_2_OFFSET 16 365 366 enum qed_dev_type dev_type; 367 368 /* Output parameters for qede */ 369 bool vxlan_enable; 370 bool gre_enable; 371 bool geneve_enable; 372 373 u8 abs_pf_id; 374 }; 375 376 enum qed_sb_type { 377 QED_SB_TYPE_L2_QUEUE, 378 QED_SB_TYPE_CNQ, 379 QED_SB_TYPE_STORAGE, 380 }; 381 382 enum qed_protocol { 383 QED_PROTOCOL_ETH, 384 QED_PROTOCOL_ISCSI, 385 QED_PROTOCOL_FCOE, 386 }; 387 388 enum qed_link_mode_bits { 389 QED_LM_FIBRE_BIT = BIT(0), 390 QED_LM_Autoneg_BIT = BIT(1), 391 QED_LM_Asym_Pause_BIT = BIT(2), 392 QED_LM_Pause_BIT = BIT(3), 393 QED_LM_1000baseT_Half_BIT = BIT(4), 394 QED_LM_1000baseT_Full_BIT = BIT(5), 395 QED_LM_10000baseKR_Full_BIT = BIT(6), 396 QED_LM_25000baseKR_Full_BIT = BIT(7), 397 QED_LM_40000baseLR4_Full_BIT = BIT(8), 398 QED_LM_50000baseKR2_Full_BIT = BIT(9), 399 QED_LM_100000baseKR4_Full_BIT = BIT(10), 400 QED_LM_COUNT = 11 401 }; 402 403 struct qed_link_params { 404 bool link_up; 405 406 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0) 407 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1) 408 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2) 409 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3) 410 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4) 411 u32 override_flags; 412 bool autoneg; 413 u32 adv_speeds; 414 u32 forced_speed; 415 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0) 416 #define QED_LINK_PAUSE_RX_ENABLE BIT(1) 417 #define QED_LINK_PAUSE_TX_ENABLE BIT(2) 418 u32 pause_config; 419 #define QED_LINK_LOOPBACK_NONE BIT(0) 420 #define QED_LINK_LOOPBACK_INT_PHY BIT(1) 421 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2) 422 #define QED_LINK_LOOPBACK_EXT BIT(3) 423 #define QED_LINK_LOOPBACK_MAC BIT(4) 424 u32 loopback_mode; 425 }; 426 427 struct qed_link_output { 428 bool link_up; 429 430 /* In QED_LM_* defs */ 431 u32 supported_caps; 432 u32 advertised_caps; 433 u32 lp_caps; 434 435 u32 speed; /* In Mb/s */ 436 u8 duplex; /* In DUPLEX defs */ 437 u8 port; /* In PORT defs */ 438 bool autoneg; 439 u32 pause_config; 440 }; 441 442 struct qed_probe_params { 443 enum qed_protocol protocol; 444 u32 dp_module; 445 u8 dp_level; 446 bool is_vf; 447 }; 448 449 #define QED_DRV_VER_STR_SIZE 12 450 struct qed_slowpath_params { 451 u32 int_mode; 452 u8 drv_major; 453 u8 drv_minor; 454 u8 drv_rev; 455 u8 drv_eng; 456 u8 name[QED_DRV_VER_STR_SIZE]; 457 }; 458 459 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */ 460 461 struct qed_int_info { 462 struct msix_entry *msix; 463 u8 msix_cnt; 464 465 /* This should be updated by the protocol driver */ 466 u8 used_cnt; 467 }; 468 469 struct qed_common_cb_ops { 470 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc); 471 void (*link_update)(void *dev, 472 struct qed_link_output *link); 473 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type); 474 }; 475 476 struct qed_selftest_ops { 477 /** 478 * @brief selftest_interrupt - Perform interrupt test 479 * 480 * @param cdev 481 * 482 * @return 0 on success, error otherwise. 483 */ 484 int (*selftest_interrupt)(struct qed_dev *cdev); 485 486 /** 487 * @brief selftest_memory - Perform memory test 488 * 489 * @param cdev 490 * 491 * @return 0 on success, error otherwise. 492 */ 493 int (*selftest_memory)(struct qed_dev *cdev); 494 495 /** 496 * @brief selftest_register - Perform register test 497 * 498 * @param cdev 499 * 500 * @return 0 on success, error otherwise. 501 */ 502 int (*selftest_register)(struct qed_dev *cdev); 503 504 /** 505 * @brief selftest_clock - Perform clock test 506 * 507 * @param cdev 508 * 509 * @return 0 on success, error otherwise. 510 */ 511 int (*selftest_clock)(struct qed_dev *cdev); 512 513 /** 514 * @brief selftest_nvram - Perform nvram test 515 * 516 * @param cdev 517 * 518 * @return 0 on success, error otherwise. 519 */ 520 int (*selftest_nvram) (struct qed_dev *cdev); 521 }; 522 523 struct qed_common_ops { 524 struct qed_selftest_ops *selftest; 525 526 struct qed_dev* (*probe)(struct pci_dev *dev, 527 struct qed_probe_params *params); 528 529 void (*remove)(struct qed_dev *cdev); 530 531 int (*set_power_state)(struct qed_dev *cdev, 532 pci_power_t state); 533 534 void (*set_name) (struct qed_dev *cdev, char name[]); 535 536 /* Client drivers need to make this call before slowpath_start. 537 * PF params required for the call before slowpath_start is 538 * documented within the qed_pf_params structure definition. 539 */ 540 void (*update_pf_params)(struct qed_dev *cdev, 541 struct qed_pf_params *params); 542 int (*slowpath_start)(struct qed_dev *cdev, 543 struct qed_slowpath_params *params); 544 545 int (*slowpath_stop)(struct qed_dev *cdev); 546 547 /* Requests to use `cnt' interrupts for fastpath. 548 * upon success, returns number of interrupts allocated for fastpath. 549 */ 550 int (*set_fp_int)(struct qed_dev *cdev, 551 u16 cnt); 552 553 /* Fills `info' with pointers required for utilizing interrupts */ 554 int (*get_fp_int)(struct qed_dev *cdev, 555 struct qed_int_info *info); 556 557 u32 (*sb_init)(struct qed_dev *cdev, 558 struct qed_sb_info *sb_info, 559 void *sb_virt_addr, 560 dma_addr_t sb_phy_addr, 561 u16 sb_id, 562 enum qed_sb_type type); 563 564 u32 (*sb_release)(struct qed_dev *cdev, 565 struct qed_sb_info *sb_info, 566 u16 sb_id); 567 568 void (*simd_handler_config)(struct qed_dev *cdev, 569 void *token, 570 int index, 571 void (*handler)(void *)); 572 573 void (*simd_handler_clean)(struct qed_dev *cdev, 574 int index); 575 int (*dbg_grc)(struct qed_dev *cdev, 576 void *buffer, u32 *num_dumped_bytes); 577 578 int (*dbg_grc_size)(struct qed_dev *cdev); 579 580 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer); 581 582 int (*dbg_all_data_size) (struct qed_dev *cdev); 583 584 /** 585 * @brief can_link_change - can the instance change the link or not 586 * 587 * @param cdev 588 * 589 * @return true if link-change is allowed, false otherwise. 590 */ 591 bool (*can_link_change)(struct qed_dev *cdev); 592 593 /** 594 * @brief set_link - set links according to params 595 * 596 * @param cdev 597 * @param params - values used to override the default link configuration 598 * 599 * @return 0 on success, error otherwise. 600 */ 601 int (*set_link)(struct qed_dev *cdev, 602 struct qed_link_params *params); 603 604 /** 605 * @brief get_link - returns the current link state. 606 * 607 * @param cdev 608 * @param if_link - structure to be filled with current link configuration. 609 */ 610 void (*get_link)(struct qed_dev *cdev, 611 struct qed_link_output *if_link); 612 613 /** 614 * @brief - drains chip in case Tx completions fail to arrive due to pause. 615 * 616 * @param cdev 617 */ 618 int (*drain)(struct qed_dev *cdev); 619 620 /** 621 * @brief update_msglvl - update module debug level 622 * 623 * @param cdev 624 * @param dp_module 625 * @param dp_level 626 */ 627 void (*update_msglvl)(struct qed_dev *cdev, 628 u32 dp_module, 629 u8 dp_level); 630 631 int (*chain_alloc)(struct qed_dev *cdev, 632 enum qed_chain_use_mode intended_use, 633 enum qed_chain_mode mode, 634 enum qed_chain_cnt_type cnt_type, 635 u32 num_elems, 636 size_t elem_size, 637 struct qed_chain *p_chain, 638 struct qed_chain_ext_pbl *ext_pbl); 639 640 void (*chain_free)(struct qed_dev *cdev, 641 struct qed_chain *p_chain); 642 643 /** 644 * @brief nvm_get_image - reads an entire image from nvram 645 * 646 * @param cdev 647 * @param type - type of the request nvram image 648 * @param buf - preallocated buffer to fill with the image 649 * @param len - length of the allocated buffer 650 * 651 * @return 0 on success, error otherwise 652 */ 653 int (*nvm_get_image)(struct qed_dev *cdev, 654 enum qed_nvm_images type, u8 *buf, u16 len); 655 656 /** 657 * @brief get_coalesce - Get coalesce parameters in usec 658 * 659 * @param cdev 660 * @param rx_coal - Rx coalesce value in usec 661 * @param tx_coal - Tx coalesce value in usec 662 * 663 */ 664 void (*get_coalesce)(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal); 665 666 /** 667 * @brief set_coalesce - Configure Rx coalesce value in usec 668 * 669 * @param cdev 670 * @param rx_coal - Rx coalesce value in usec 671 * @param tx_coal - Tx coalesce value in usec 672 * @param qid - Queue index 673 * @param sb_id - Status Block Id 674 * 675 * @return 0 on success, error otherwise. 676 */ 677 int (*set_coalesce)(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, 678 u16 qid, u16 sb_id); 679 680 /** 681 * @brief set_led - Configure LED mode 682 * 683 * @param cdev 684 * @param mode - LED mode 685 * 686 * @return 0 on success, error otherwise. 687 */ 688 int (*set_led)(struct qed_dev *cdev, 689 enum qed_led_mode mode); 690 691 /** 692 * @brief update_drv_state - API to inform the change in the driver state. 693 * 694 * @param cdev 695 * @param active 696 * 697 */ 698 int (*update_drv_state)(struct qed_dev *cdev, bool active); 699 700 /** 701 * @brief update_mac - API to inform the change in the mac address 702 * 703 * @param cdev 704 * @param mac 705 * 706 */ 707 int (*update_mac)(struct qed_dev *cdev, u8 *mac); 708 709 /** 710 * @brief update_mtu - API to inform the change in the mtu 711 * 712 * @param cdev 713 * @param mtu 714 * 715 */ 716 int (*update_mtu)(struct qed_dev *cdev, u16 mtu); 717 718 /** 719 * @brief update_wol - update of changes in the WoL configuration 720 * 721 * @param cdev 722 * @param enabled - true iff WoL should be enabled. 723 */ 724 int (*update_wol) (struct qed_dev *cdev, bool enabled); 725 }; 726 727 #define MASK_FIELD(_name, _value) \ 728 ((_value) &= (_name ## _MASK)) 729 730 #define FIELD_VALUE(_name, _value) \ 731 ((_value & _name ## _MASK) << _name ## _SHIFT) 732 733 #define SET_FIELD(value, name, flag) \ 734 do { \ 735 (value) &= ~(name ## _MASK << name ## _SHIFT); \ 736 (value) |= (((u64)flag) << (name ## _SHIFT)); \ 737 } while (0) 738 739 #define GET_FIELD(value, name) \ 740 (((value) >> (name ## _SHIFT)) & name ## _MASK) 741 742 /* Debug print definitions */ 743 #define DP_ERR(cdev, fmt, ...) \ 744 do { \ 745 pr_err("[%s:%d(%s)]" fmt, \ 746 __func__, __LINE__, \ 747 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 748 ## __VA_ARGS__); \ 749 } while (0) 750 751 #define DP_NOTICE(cdev, fmt, ...) \ 752 do { \ 753 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \ 754 pr_notice("[%s:%d(%s)]" fmt, \ 755 __func__, __LINE__, \ 756 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 757 ## __VA_ARGS__); \ 758 \ 759 } \ 760 } while (0) 761 762 #define DP_INFO(cdev, fmt, ...) \ 763 do { \ 764 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \ 765 pr_notice("[%s:%d(%s)]" fmt, \ 766 __func__, __LINE__, \ 767 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 768 ## __VA_ARGS__); \ 769 } \ 770 } while (0) 771 772 #define DP_VERBOSE(cdev, module, fmt, ...) \ 773 do { \ 774 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \ 775 ((cdev)->dp_module & module))) { \ 776 pr_notice("[%s:%d(%s)]" fmt, \ 777 __func__, __LINE__, \ 778 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 779 ## __VA_ARGS__); \ 780 } \ 781 } while (0) 782 783 enum DP_LEVEL { 784 QED_LEVEL_VERBOSE = 0x0, 785 QED_LEVEL_INFO = 0x1, 786 QED_LEVEL_NOTICE = 0x2, 787 QED_LEVEL_ERR = 0x3, 788 }; 789 790 #define QED_LOG_LEVEL_SHIFT (30) 791 #define QED_LOG_VERBOSE_MASK (0x3fffffff) 792 #define QED_LOG_INFO_MASK (0x40000000) 793 #define QED_LOG_NOTICE_MASK (0x80000000) 794 795 enum DP_MODULE { 796 QED_MSG_SPQ = 0x10000, 797 QED_MSG_STATS = 0x20000, 798 QED_MSG_DCB = 0x40000, 799 QED_MSG_IOV = 0x80000, 800 QED_MSG_SP = 0x100000, 801 QED_MSG_STORAGE = 0x200000, 802 QED_MSG_CXT = 0x800000, 803 QED_MSG_LL2 = 0x1000000, 804 QED_MSG_ILT = 0x2000000, 805 QED_MSG_RDMA = 0x4000000, 806 QED_MSG_DEBUG = 0x8000000, 807 /* to be added...up to 0x8000000 */ 808 }; 809 810 enum qed_mf_mode { 811 QED_MF_DEFAULT, 812 QED_MF_OVLAN, 813 QED_MF_NPAR, 814 }; 815 816 struct qed_eth_stats_common { 817 u64 no_buff_discards; 818 u64 packet_too_big_discard; 819 u64 ttl0_discard; 820 u64 rx_ucast_bytes; 821 u64 rx_mcast_bytes; 822 u64 rx_bcast_bytes; 823 u64 rx_ucast_pkts; 824 u64 rx_mcast_pkts; 825 u64 rx_bcast_pkts; 826 u64 mftag_filter_discards; 827 u64 mac_filter_discards; 828 u64 tx_ucast_bytes; 829 u64 tx_mcast_bytes; 830 u64 tx_bcast_bytes; 831 u64 tx_ucast_pkts; 832 u64 tx_mcast_pkts; 833 u64 tx_bcast_pkts; 834 u64 tx_err_drop_pkts; 835 u64 tpa_coalesced_pkts; 836 u64 tpa_coalesced_events; 837 u64 tpa_aborts_num; 838 u64 tpa_not_coalesced_pkts; 839 u64 tpa_coalesced_bytes; 840 841 /* port */ 842 u64 rx_64_byte_packets; 843 u64 rx_65_to_127_byte_packets; 844 u64 rx_128_to_255_byte_packets; 845 u64 rx_256_to_511_byte_packets; 846 u64 rx_512_to_1023_byte_packets; 847 u64 rx_1024_to_1518_byte_packets; 848 u64 rx_crc_errors; 849 u64 rx_mac_crtl_frames; 850 u64 rx_pause_frames; 851 u64 rx_pfc_frames; 852 u64 rx_align_errors; 853 u64 rx_carrier_errors; 854 u64 rx_oversize_packets; 855 u64 rx_jabbers; 856 u64 rx_undersize_packets; 857 u64 rx_fragments; 858 u64 tx_64_byte_packets; 859 u64 tx_65_to_127_byte_packets; 860 u64 tx_128_to_255_byte_packets; 861 u64 tx_256_to_511_byte_packets; 862 u64 tx_512_to_1023_byte_packets; 863 u64 tx_1024_to_1518_byte_packets; 864 u64 tx_pause_frames; 865 u64 tx_pfc_frames; 866 u64 brb_truncates; 867 u64 brb_discards; 868 u64 rx_mac_bytes; 869 u64 rx_mac_uc_packets; 870 u64 rx_mac_mc_packets; 871 u64 rx_mac_bc_packets; 872 u64 rx_mac_frames_ok; 873 u64 tx_mac_bytes; 874 u64 tx_mac_uc_packets; 875 u64 tx_mac_mc_packets; 876 u64 tx_mac_bc_packets; 877 u64 tx_mac_ctrl_frames; 878 }; 879 880 struct qed_eth_stats_bb { 881 u64 rx_1519_to_1522_byte_packets; 882 u64 rx_1519_to_2047_byte_packets; 883 u64 rx_2048_to_4095_byte_packets; 884 u64 rx_4096_to_9216_byte_packets; 885 u64 rx_9217_to_16383_byte_packets; 886 u64 tx_1519_to_2047_byte_packets; 887 u64 tx_2048_to_4095_byte_packets; 888 u64 tx_4096_to_9216_byte_packets; 889 u64 tx_9217_to_16383_byte_packets; 890 u64 tx_lpi_entry_count; 891 u64 tx_total_collisions; 892 }; 893 894 struct qed_eth_stats_ah { 895 u64 rx_1519_to_max_byte_packets; 896 u64 tx_1519_to_max_byte_packets; 897 }; 898 899 struct qed_eth_stats { 900 struct qed_eth_stats_common common; 901 902 union { 903 struct qed_eth_stats_bb bb; 904 struct qed_eth_stats_ah ah; 905 }; 906 }; 907 908 #define QED_SB_IDX 0x0002 909 910 #define RX_PI 0 911 #define TX_PI(tc) (RX_PI + 1 + tc) 912 913 struct qed_sb_cnt_info { 914 /* Original, current, and free SBs for PF */ 915 int orig; 916 int cnt; 917 int free_cnt; 918 919 /* Original, current and free SBS for child VFs */ 920 int iov_orig; 921 int iov_cnt; 922 int free_cnt_iov; 923 }; 924 925 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info) 926 { 927 u32 prod = 0; 928 u16 rc = 0; 929 930 prod = le32_to_cpu(sb_info->sb_virt->prod_index) & 931 STATUS_BLOCK_PROD_INDEX_MASK; 932 if (sb_info->sb_ack != prod) { 933 sb_info->sb_ack = prod; 934 rc |= QED_SB_IDX; 935 } 936 937 /* Let SB update */ 938 mmiowb(); 939 return rc; 940 } 941 942 /** 943 * 944 * @brief This function creates an update command for interrupts that is 945 * written to the IGU. 946 * 947 * @param sb_info - This is the structure allocated and 948 * initialized per status block. Assumption is 949 * that it was initialized using qed_sb_init 950 * @param int_cmd - Enable/Disable/Nop 951 * @param upd_flg - whether igu consumer should be 952 * updated. 953 * 954 * @return inline void 955 */ 956 static inline void qed_sb_ack(struct qed_sb_info *sb_info, 957 enum igu_int_cmd int_cmd, 958 u8 upd_flg) 959 { 960 struct igu_prod_cons_update igu_ack = { 0 }; 961 962 igu_ack.sb_id_and_flags = 963 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 964 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 965 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 966 (IGU_SEG_ACCESS_REG << 967 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 968 969 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags); 970 971 /* Both segments (interrupts & acks) are written to same place address; 972 * Need to guarantee all commands will be received (in-order) by HW. 973 */ 974 mmiowb(); 975 barrier(); 976 } 977 978 static inline void __internal_ram_wr(void *p_hwfn, 979 void __iomem *addr, 980 int size, 981 u32 *data) 982 983 { 984 unsigned int i; 985 986 for (i = 0; i < size / sizeof(*data); i++) 987 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]); 988 } 989 990 static inline void internal_ram_wr(void __iomem *addr, 991 int size, 992 u32 *data) 993 { 994 __internal_ram_wr(NULL, addr, size, data); 995 } 996 997 enum qed_rss_caps { 998 QED_RSS_IPV4 = 0x1, 999 QED_RSS_IPV6 = 0x2, 1000 QED_RSS_IPV4_TCP = 0x4, 1001 QED_RSS_IPV6_TCP = 0x8, 1002 QED_RSS_IPV4_UDP = 0x10, 1003 QED_RSS_IPV6_UDP = 0x20, 1004 }; 1005 1006 #define QED_RSS_IND_TABLE_SIZE 128 1007 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */ 1008 #endif 1009