xref: /linux/include/linux/qed/qed_if.h (revision 6beeaf48db6c548fcfc2ad32739d33af2fef3a5b) 
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /* QLogic qed NIC Driver
3  * Copyright (c) 2015-2017  QLogic Corporation
4  * Copyright (c) 2019-2020 Marvell International Ltd.
5  */
6 
7 #ifndef _QED_IF_H
8 #define _QED_IF_H
9 
10 #include <linux/ethtool.h>
11 #include <linux/types.h>
12 #include <linux/interrupt.h>
13 #include <linux/netdevice.h>
14 #include <linux/pci.h>
15 #include <linux/skbuff.h>
16 #include <asm/byteorder.h>
17 #include <linux/io.h>
18 #include <linux/compiler.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/slab.h>
22 #include <linux/qed/common_hsi.h>
23 #include <linux/qed/qed_chain.h>
24 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <net/devlink.h>
26 
27 enum dcbx_protocol_type {
28 	DCBX_PROTOCOL_ISCSI,
29 	DCBX_PROTOCOL_FCOE,
30 	DCBX_PROTOCOL_ROCE,
31 	DCBX_PROTOCOL_ROCE_V2,
32 	DCBX_PROTOCOL_ETH,
33 	DCBX_MAX_PROTOCOL_TYPE
34 };
35 
36 #define QED_ROCE_PROTOCOL_INDEX (3)
37 
38 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4
39 #define QED_LLDP_PORT_ID_STAT_LEN 4
40 #define QED_DCBX_MAX_APP_PROTOCOL 32
41 #define QED_MAX_PFC_PRIORITIES 8
42 #define QED_DCBX_DSCP_SIZE 64
43 
44 struct qed_dcbx_lldp_remote {
45 	u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
46 	u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
47 	bool enable_rx;
48 	bool enable_tx;
49 	u32 tx_interval;
50 	u32 max_credit;
51 };
52 
53 struct qed_dcbx_lldp_local {
54 	u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
55 	u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
56 };
57 
58 struct qed_dcbx_app_prio {
59 	u8 roce;
60 	u8 roce_v2;
61 	u8 fcoe;
62 	u8 iscsi;
63 	u8 eth;
64 };
65 
66 struct qed_dbcx_pfc_params {
67 	bool willing;
68 	bool enabled;
69 	u8 prio[QED_MAX_PFC_PRIORITIES];
70 	u8 max_tc;
71 };
72 
73 enum qed_dcbx_sf_ieee_type {
74 	QED_DCBX_SF_IEEE_ETHTYPE,
75 	QED_DCBX_SF_IEEE_TCP_PORT,
76 	QED_DCBX_SF_IEEE_UDP_PORT,
77 	QED_DCBX_SF_IEEE_TCP_UDP_PORT
78 };
79 
80 struct qed_app_entry {
81 	bool ethtype;
82 	enum qed_dcbx_sf_ieee_type sf_ieee;
83 	bool enabled;
84 	u8 prio;
85 	u16 proto_id;
86 	enum dcbx_protocol_type proto_type;
87 };
88 
89 struct qed_dcbx_params {
90 	struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
91 	u16 num_app_entries;
92 	bool app_willing;
93 	bool app_valid;
94 	bool app_error;
95 	bool ets_willing;
96 	bool ets_enabled;
97 	bool ets_cbs;
98 	bool valid;
99 	u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
100 	u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
101 	u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
102 	struct qed_dbcx_pfc_params pfc;
103 	u8 max_ets_tc;
104 };
105 
106 struct qed_dcbx_admin_params {
107 	struct qed_dcbx_params params;
108 	bool valid;
109 };
110 
111 struct qed_dcbx_remote_params {
112 	struct qed_dcbx_params params;
113 	bool valid;
114 };
115 
116 struct qed_dcbx_operational_params {
117 	struct qed_dcbx_app_prio app_prio;
118 	struct qed_dcbx_params params;
119 	bool valid;
120 	bool enabled;
121 	bool ieee;
122 	bool cee;
123 	bool local;
124 	u32 err;
125 };
126 
127 struct qed_dcbx_get {
128 	struct qed_dcbx_operational_params operational;
129 	struct qed_dcbx_lldp_remote lldp_remote;
130 	struct qed_dcbx_lldp_local lldp_local;
131 	struct qed_dcbx_remote_params remote;
132 	struct qed_dcbx_admin_params local;
133 };
134 
135 enum qed_nvm_images {
136 	QED_NVM_IMAGE_ISCSI_CFG,
137 	QED_NVM_IMAGE_FCOE_CFG,
138 	QED_NVM_IMAGE_MDUMP,
139 	QED_NVM_IMAGE_NVM_CFG1,
140 	QED_NVM_IMAGE_DEFAULT_CFG,
141 	QED_NVM_IMAGE_NVM_META,
142 };
143 
144 struct qed_link_eee_params {
145 	u32 tx_lpi_timer;
146 #define QED_EEE_1G_ADV		BIT(0)
147 #define QED_EEE_10G_ADV		BIT(1)
148 
149 	/* Capabilities are represented using QED_EEE_*_ADV values */
150 	u8 adv_caps;
151 	u8 lp_adv_caps;
152 	bool enable;
153 	bool tx_lpi_enable;
154 };
155 
156 enum qed_led_mode {
157 	QED_LED_MODE_OFF,
158 	QED_LED_MODE_ON,
159 	QED_LED_MODE_RESTORE
160 };
161 
162 struct qed_mfw_tlv_eth {
163 	u16 lso_maxoff_size;
164 	bool lso_maxoff_size_set;
165 	u16 lso_minseg_size;
166 	bool lso_minseg_size_set;
167 	u8 prom_mode;
168 	bool prom_mode_set;
169 	u16 tx_descr_size;
170 	bool tx_descr_size_set;
171 	u16 rx_descr_size;
172 	bool rx_descr_size_set;
173 	u16 netq_count;
174 	bool netq_count_set;
175 	u32 tcp4_offloads;
176 	bool tcp4_offloads_set;
177 	u32 tcp6_offloads;
178 	bool tcp6_offloads_set;
179 	u16 tx_descr_qdepth;
180 	bool tx_descr_qdepth_set;
181 	u16 rx_descr_qdepth;
182 	bool rx_descr_qdepth_set;
183 	u8 iov_offload;
184 #define QED_MFW_TLV_IOV_OFFLOAD_NONE            (0)
185 #define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE      (1)
186 #define QED_MFW_TLV_IOV_OFFLOAD_VEB             (2)
187 #define QED_MFW_TLV_IOV_OFFLOAD_VEPA            (3)
188 	bool iov_offload_set;
189 	u8 txqs_empty;
190 	bool txqs_empty_set;
191 	u8 rxqs_empty;
192 	bool rxqs_empty_set;
193 	u8 num_txqs_full;
194 	bool num_txqs_full_set;
195 	u8 num_rxqs_full;
196 	bool num_rxqs_full_set;
197 };
198 
199 #define QED_MFW_TLV_TIME_SIZE	14
200 struct qed_mfw_tlv_time {
201 	bool b_set;
202 	u8 month;
203 	u8 day;
204 	u8 hour;
205 	u8 min;
206 	u16 msec;
207 	u16 usec;
208 };
209 
210 struct qed_mfw_tlv_fcoe {
211 	u8 scsi_timeout;
212 	bool scsi_timeout_set;
213 	u32 rt_tov;
214 	bool rt_tov_set;
215 	u32 ra_tov;
216 	bool ra_tov_set;
217 	u32 ed_tov;
218 	bool ed_tov_set;
219 	u32 cr_tov;
220 	bool cr_tov_set;
221 	u8 boot_type;
222 	bool boot_type_set;
223 	u8 npiv_state;
224 	bool npiv_state_set;
225 	u32 num_npiv_ids;
226 	bool num_npiv_ids_set;
227 	u8 switch_name[8];
228 	bool switch_name_set;
229 	u16 switch_portnum;
230 	bool switch_portnum_set;
231 	u8 switch_portid[3];
232 	bool switch_portid_set;
233 	u8 vendor_name[8];
234 	bool vendor_name_set;
235 	u8 switch_model[8];
236 	bool switch_model_set;
237 	u8 switch_fw_version[8];
238 	bool switch_fw_version_set;
239 	u8 qos_pri;
240 	bool qos_pri_set;
241 	u8 port_alias[3];
242 	bool port_alias_set;
243 	u8 port_state;
244 #define QED_MFW_TLV_PORT_STATE_OFFLINE  (0)
245 #define QED_MFW_TLV_PORT_STATE_LOOP             (1)
246 #define QED_MFW_TLV_PORT_STATE_P2P              (2)
247 #define QED_MFW_TLV_PORT_STATE_FABRIC           (3)
248 	bool port_state_set;
249 	u16 fip_tx_descr_size;
250 	bool fip_tx_descr_size_set;
251 	u16 fip_rx_descr_size;
252 	bool fip_rx_descr_size_set;
253 	u16 link_failures;
254 	bool link_failures_set;
255 	u8 fcoe_boot_progress;
256 	bool fcoe_boot_progress_set;
257 	u64 rx_bcast;
258 	bool rx_bcast_set;
259 	u64 tx_bcast;
260 	bool tx_bcast_set;
261 	u16 fcoe_txq_depth;
262 	bool fcoe_txq_depth_set;
263 	u16 fcoe_rxq_depth;
264 	bool fcoe_rxq_depth_set;
265 	u64 fcoe_rx_frames;
266 	bool fcoe_rx_frames_set;
267 	u64 fcoe_rx_bytes;
268 	bool fcoe_rx_bytes_set;
269 	u64 fcoe_tx_frames;
270 	bool fcoe_tx_frames_set;
271 	u64 fcoe_tx_bytes;
272 	bool fcoe_tx_bytes_set;
273 	u16 crc_count;
274 	bool crc_count_set;
275 	u32 crc_err_src_fcid[5];
276 	bool crc_err_src_fcid_set[5];
277 	struct qed_mfw_tlv_time crc_err[5];
278 	u16 losync_err;
279 	bool losync_err_set;
280 	u16 losig_err;
281 	bool losig_err_set;
282 	u16 primtive_err;
283 	bool primtive_err_set;
284 	u16 disparity_err;
285 	bool disparity_err_set;
286 	u16 code_violation_err;
287 	bool code_violation_err_set;
288 	u32 flogi_param[4];
289 	bool flogi_param_set[4];
290 	struct qed_mfw_tlv_time flogi_tstamp;
291 	u32 flogi_acc_param[4];
292 	bool flogi_acc_param_set[4];
293 	struct qed_mfw_tlv_time flogi_acc_tstamp;
294 	u32 flogi_rjt;
295 	bool flogi_rjt_set;
296 	struct qed_mfw_tlv_time flogi_rjt_tstamp;
297 	u32 fdiscs;
298 	bool fdiscs_set;
299 	u8 fdisc_acc;
300 	bool fdisc_acc_set;
301 	u8 fdisc_rjt;
302 	bool fdisc_rjt_set;
303 	u8 plogi;
304 	bool plogi_set;
305 	u8 plogi_acc;
306 	bool plogi_acc_set;
307 	u8 plogi_rjt;
308 	bool plogi_rjt_set;
309 	u32 plogi_dst_fcid[5];
310 	bool plogi_dst_fcid_set[5];
311 	struct qed_mfw_tlv_time plogi_tstamp[5];
312 	u32 plogi_acc_src_fcid[5];
313 	bool plogi_acc_src_fcid_set[5];
314 	struct qed_mfw_tlv_time plogi_acc_tstamp[5];
315 	u8 tx_plogos;
316 	bool tx_plogos_set;
317 	u8 plogo_acc;
318 	bool plogo_acc_set;
319 	u8 plogo_rjt;
320 	bool plogo_rjt_set;
321 	u32 plogo_src_fcid[5];
322 	bool plogo_src_fcid_set[5];
323 	struct qed_mfw_tlv_time plogo_tstamp[5];
324 	u8 rx_logos;
325 	bool rx_logos_set;
326 	u8 tx_accs;
327 	bool tx_accs_set;
328 	u8 tx_prlis;
329 	bool tx_prlis_set;
330 	u8 rx_accs;
331 	bool rx_accs_set;
332 	u8 tx_abts;
333 	bool tx_abts_set;
334 	u8 rx_abts_acc;
335 	bool rx_abts_acc_set;
336 	u8 rx_abts_rjt;
337 	bool rx_abts_rjt_set;
338 	u32 abts_dst_fcid[5];
339 	bool abts_dst_fcid_set[5];
340 	struct qed_mfw_tlv_time abts_tstamp[5];
341 	u8 rx_rscn;
342 	bool rx_rscn_set;
343 	u32 rx_rscn_nport[4];
344 	bool rx_rscn_nport_set[4];
345 	u8 tx_lun_rst;
346 	bool tx_lun_rst_set;
347 	u8 abort_task_sets;
348 	bool abort_task_sets_set;
349 	u8 tx_tprlos;
350 	bool tx_tprlos_set;
351 	u8 tx_nos;
352 	bool tx_nos_set;
353 	u8 rx_nos;
354 	bool rx_nos_set;
355 	u8 ols;
356 	bool ols_set;
357 	u8 lr;
358 	bool lr_set;
359 	u8 lrr;
360 	bool lrr_set;
361 	u8 tx_lip;
362 	bool tx_lip_set;
363 	u8 rx_lip;
364 	bool rx_lip_set;
365 	u8 eofa;
366 	bool eofa_set;
367 	u8 eofni;
368 	bool eofni_set;
369 	u8 scsi_chks;
370 	bool scsi_chks_set;
371 	u8 scsi_cond_met;
372 	bool scsi_cond_met_set;
373 	u8 scsi_busy;
374 	bool scsi_busy_set;
375 	u8 scsi_inter;
376 	bool scsi_inter_set;
377 	u8 scsi_inter_cond_met;
378 	bool scsi_inter_cond_met_set;
379 	u8 scsi_rsv_conflicts;
380 	bool scsi_rsv_conflicts_set;
381 	u8 scsi_tsk_full;
382 	bool scsi_tsk_full_set;
383 	u8 scsi_aca_active;
384 	bool scsi_aca_active_set;
385 	u8 scsi_tsk_abort;
386 	bool scsi_tsk_abort_set;
387 	u32 scsi_rx_chk[5];
388 	bool scsi_rx_chk_set[5];
389 	struct qed_mfw_tlv_time scsi_chk_tstamp[5];
390 };
391 
392 struct qed_mfw_tlv_iscsi {
393 	u8 target_llmnr;
394 	bool target_llmnr_set;
395 	u8 header_digest;
396 	bool header_digest_set;
397 	u8 data_digest;
398 	bool data_digest_set;
399 	u8 auth_method;
400 #define QED_MFW_TLV_AUTH_METHOD_NONE            (1)
401 #define QED_MFW_TLV_AUTH_METHOD_CHAP            (2)
402 #define QED_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP     (3)
403 	bool auth_method_set;
404 	u16 boot_taget_portal;
405 	bool boot_taget_portal_set;
406 	u16 frame_size;
407 	bool frame_size_set;
408 	u16 tx_desc_size;
409 	bool tx_desc_size_set;
410 	u16 rx_desc_size;
411 	bool rx_desc_size_set;
412 	u8 boot_progress;
413 	bool boot_progress_set;
414 	u16 tx_desc_qdepth;
415 	bool tx_desc_qdepth_set;
416 	u16 rx_desc_qdepth;
417 	bool rx_desc_qdepth_set;
418 	u64 rx_frames;
419 	bool rx_frames_set;
420 	u64 rx_bytes;
421 	bool rx_bytes_set;
422 	u64 tx_frames;
423 	bool tx_frames_set;
424 	u64 tx_bytes;
425 	bool tx_bytes_set;
426 };
427 
428 enum qed_db_rec_width {
429 	DB_REC_WIDTH_32B,
430 	DB_REC_WIDTH_64B,
431 };
432 
433 enum qed_db_rec_space {
434 	DB_REC_KERNEL,
435 	DB_REC_USER,
436 };
437 
438 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
439 					    (void __iomem *)(reg_addr))
440 
441 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
442 
443 #define DIRECT_REG_WR64(reg_addr, val) writeq((u64)val,	\
444 					      (void __iomem *)(reg_addr))
445 
446 #define QED_COALESCE_MAX 0x1FF
447 #define QED_DEFAULT_RX_USECS 12
448 #define QED_DEFAULT_TX_USECS 48
449 
450 /* forward */
451 struct qed_dev;
452 
453 struct qed_eth_pf_params {
454 	/* The following parameters are used during HW-init
455 	 * and these parameters need to be passed as arguments
456 	 * to update_pf_params routine invoked before slowpath start
457 	 */
458 	u16 num_cons;
459 
460 	/* per-VF number of CIDs */
461 	u8 num_vf_cons;
462 #define ETH_PF_PARAMS_VF_CONS_DEFAULT	(32)
463 
464 	/* To enable arfs, previous to HW-init a positive number needs to be
465 	 * set [as filters require allocated searcher ILT memory].
466 	 * This will set the maximal number of configured steering-filters.
467 	 */
468 	u32 num_arfs_filters;
469 };
470 
471 struct qed_fcoe_pf_params {
472 	/* The following parameters are used during protocol-init */
473 	u64 glbl_q_params_addr;
474 	u64 bdq_pbl_base_addr[2];
475 
476 	/* The following parameters are used during HW-init
477 	 * and these parameters need to be passed as arguments
478 	 * to update_pf_params routine invoked before slowpath start
479 	 */
480 	u16 num_cons;
481 	u16 num_tasks;
482 
483 	/* The following parameters are used during protocol-init */
484 	u16 sq_num_pbl_pages;
485 
486 	u16 cq_num_entries;
487 	u16 cmdq_num_entries;
488 	u16 rq_buffer_log_size;
489 	u16 mtu;
490 	u16 dummy_icid;
491 	u16 bdq_xoff_threshold[2];
492 	u16 bdq_xon_threshold[2];
493 	u16 rq_buffer_size;
494 	u8 num_cqs;		/* num of global CQs */
495 	u8 log_page_size;
496 	u8 gl_rq_pi;
497 	u8 gl_cmd_pi;
498 	u8 debug_mode;
499 	u8 is_target;
500 	u8 bdq_pbl_num_entries[2];
501 };
502 
503 /* Most of the parameters below are described in the FW iSCSI / TCP HSI */
504 struct qed_iscsi_pf_params {
505 	u64 glbl_q_params_addr;
506 	u64 bdq_pbl_base_addr[3];
507 	u16 cq_num_entries;
508 	u16 cmdq_num_entries;
509 	u32 two_msl_timer;
510 	u16 tx_sws_timer;
511 
512 	/* The following parameters are used during HW-init
513 	 * and these parameters need to be passed as arguments
514 	 * to update_pf_params routine invoked before slowpath start
515 	 */
516 	u16 num_cons;
517 	u16 num_tasks;
518 
519 	/* The following parameters are used during protocol-init */
520 	u16 half_way_close_timeout;
521 	u16 bdq_xoff_threshold[3];
522 	u16 bdq_xon_threshold[3];
523 	u16 cmdq_xoff_threshold;
524 	u16 cmdq_xon_threshold;
525 	u16 rq_buffer_size;
526 
527 	u8 num_sq_pages_in_ring;
528 	u8 num_r2tq_pages_in_ring;
529 	u8 num_uhq_pages_in_ring;
530 	u8 num_queues;
531 	u8 log_page_size;
532 	u8 rqe_log_size;
533 	u8 max_fin_rt;
534 	u8 gl_rq_pi;
535 	u8 gl_cmd_pi;
536 	u8 debug_mode;
537 	u8 ll2_ooo_queue_id;
538 
539 	u8 is_target;
540 	u8 is_soc_en;
541 	u8 soc_num_of_blocks_log;
542 	u8 bdq_pbl_num_entries[3];
543 };
544 
545 struct qed_nvmetcp_pf_params {
546 	u64 glbl_q_params_addr;
547 	u16 cq_num_entries;
548 	u16 num_cons;
549 	u16 num_tasks;
550 	u8 num_sq_pages_in_ring;
551 	u8 num_r2tq_pages_in_ring;
552 	u8 num_uhq_pages_in_ring;
553 	u8 num_queues;
554 	u8 gl_rq_pi;
555 	u8 gl_cmd_pi;
556 	u8 debug_mode;
557 	u8 ll2_ooo_queue_id;
558 	u16 min_rto;
559 };
560 
561 struct qed_rdma_pf_params {
562 	/* Supplied to QED during resource allocation (may affect the ILT and
563 	 * the doorbell BAR).
564 	 */
565 	u32 min_dpis;		/* number of requested DPIs */
566 	u32 num_qps;		/* number of requested Queue Pairs */
567 	u32 num_srqs;		/* number of requested SRQ */
568 	u8 roce_edpm_mode;	/* see QED_ROCE_EDPM_MODE_ENABLE */
569 	u8 gl_pi;		/* protocol index */
570 
571 	/* Will allocate rate limiters to be used with QPs */
572 	u8 enable_dcqcn;
573 };
574 
575 struct qed_pf_params {
576 	struct qed_eth_pf_params eth_pf_params;
577 	struct qed_fcoe_pf_params fcoe_pf_params;
578 	struct qed_iscsi_pf_params iscsi_pf_params;
579 	struct qed_nvmetcp_pf_params nvmetcp_pf_params;
580 	struct qed_rdma_pf_params rdma_pf_params;
581 };
582 
583 enum qed_int_mode {
584 	QED_INT_MODE_INTA,
585 	QED_INT_MODE_MSIX,
586 	QED_INT_MODE_MSI,
587 	QED_INT_MODE_POLL,
588 };
589 
590 struct qed_sb_info {
591 	struct status_block_e4 *sb_virt;
592 	dma_addr_t sb_phys;
593 	u32 sb_ack; /* Last given ack */
594 	u16 igu_sb_id;
595 	void __iomem *igu_addr;
596 	u8 flags;
597 #define QED_SB_INFO_INIT	0x1
598 #define QED_SB_INFO_SETUP	0x2
599 
600 	struct qed_dev *cdev;
601 };
602 
603 enum qed_hw_err_type {
604 	QED_HW_ERR_FAN_FAIL,
605 	QED_HW_ERR_MFW_RESP_FAIL,
606 	QED_HW_ERR_HW_ATTN,
607 	QED_HW_ERR_DMAE_FAIL,
608 	QED_HW_ERR_RAMROD_FAIL,
609 	QED_HW_ERR_FW_ASSERT,
610 	QED_HW_ERR_LAST,
611 };
612 
613 enum qed_dev_type {
614 	QED_DEV_TYPE_BB,
615 	QED_DEV_TYPE_AH,
616 	QED_DEV_TYPE_E5,
617 };
618 
619 struct qed_dev_info {
620 	unsigned long	pci_mem_start;
621 	unsigned long	pci_mem_end;
622 	unsigned int	pci_irq;
623 	u8		num_hwfns;
624 
625 	u8		hw_mac[ETH_ALEN];
626 
627 	/* FW version */
628 	u16		fw_major;
629 	u16		fw_minor;
630 	u16		fw_rev;
631 	u16		fw_eng;
632 
633 	/* MFW version */
634 	u32		mfw_rev;
635 #define QED_MFW_VERSION_0_MASK		0x000000FF
636 #define QED_MFW_VERSION_0_OFFSET	0
637 #define QED_MFW_VERSION_1_MASK		0x0000FF00
638 #define QED_MFW_VERSION_1_OFFSET	8
639 #define QED_MFW_VERSION_2_MASK		0x00FF0000
640 #define QED_MFW_VERSION_2_OFFSET	16
641 #define QED_MFW_VERSION_3_MASK		0xFF000000
642 #define QED_MFW_VERSION_3_OFFSET	24
643 
644 	u32		flash_size;
645 	bool		b_arfs_capable;
646 	bool		b_inter_pf_switch;
647 	bool		tx_switching;
648 	bool		rdma_supported;
649 	u16		mtu;
650 
651 	bool wol_support;
652 	bool smart_an;
653 
654 	/* MBI version */
655 	u32 mbi_version;
656 #define QED_MBI_VERSION_0_MASK		0x000000FF
657 #define QED_MBI_VERSION_0_OFFSET	0
658 #define QED_MBI_VERSION_1_MASK		0x0000FF00
659 #define QED_MBI_VERSION_1_OFFSET	8
660 #define QED_MBI_VERSION_2_MASK		0x00FF0000
661 #define QED_MBI_VERSION_2_OFFSET	16
662 
663 	enum qed_dev_type dev_type;
664 
665 	/* Output parameters for qede */
666 	bool		vxlan_enable;
667 	bool		gre_enable;
668 	bool		geneve_enable;
669 
670 	u8		abs_pf_id;
671 };
672 
673 enum qed_sb_type {
674 	QED_SB_TYPE_L2_QUEUE,
675 	QED_SB_TYPE_CNQ,
676 	QED_SB_TYPE_STORAGE,
677 };
678 
679 enum qed_protocol {
680 	QED_PROTOCOL_ETH,
681 	QED_PROTOCOL_ISCSI,
682 	QED_PROTOCOL_NVMETCP = QED_PROTOCOL_ISCSI,
683 	QED_PROTOCOL_FCOE,
684 };
685 
686 enum qed_fec_mode {
687 	QED_FEC_MODE_NONE			= BIT(0),
688 	QED_FEC_MODE_FIRECODE			= BIT(1),
689 	QED_FEC_MODE_RS				= BIT(2),
690 	QED_FEC_MODE_AUTO			= BIT(3),
691 	QED_FEC_MODE_UNSUPPORTED		= BIT(4),
692 };
693 
694 struct qed_link_params {
695 	bool					link_up;
696 
697 	u32					override_flags;
698 #define QED_LINK_OVERRIDE_SPEED_AUTONEG		BIT(0)
699 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS	BIT(1)
700 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED	BIT(2)
701 #define QED_LINK_OVERRIDE_PAUSE_CONFIG		BIT(3)
702 #define QED_LINK_OVERRIDE_LOOPBACK_MODE		BIT(4)
703 #define QED_LINK_OVERRIDE_EEE_CONFIG		BIT(5)
704 #define QED_LINK_OVERRIDE_FEC_CONFIG		BIT(6)
705 
706 	bool					autoneg;
707 	__ETHTOOL_DECLARE_LINK_MODE_MASK(adv_speeds);
708 	u32					forced_speed;
709 
710 	u32					pause_config;
711 #define QED_LINK_PAUSE_AUTONEG_ENABLE		BIT(0)
712 #define QED_LINK_PAUSE_RX_ENABLE		BIT(1)
713 #define QED_LINK_PAUSE_TX_ENABLE		BIT(2)
714 
715 	u32					loopback_mode;
716 #define QED_LINK_LOOPBACK_NONE			BIT(0)
717 #define QED_LINK_LOOPBACK_INT_PHY		BIT(1)
718 #define QED_LINK_LOOPBACK_EXT_PHY		BIT(2)
719 #define QED_LINK_LOOPBACK_EXT			BIT(3)
720 #define QED_LINK_LOOPBACK_MAC			BIT(4)
721 #define QED_LINK_LOOPBACK_CNIG_AH_ONLY_0123	BIT(5)
722 #define QED_LINK_LOOPBACK_CNIG_AH_ONLY_2301	BIT(6)
723 #define QED_LINK_LOOPBACK_PCS_AH_ONLY		BIT(7)
724 #define QED_LINK_LOOPBACK_REVERSE_MAC_AH_ONLY	BIT(8)
725 #define QED_LINK_LOOPBACK_INT_PHY_FEA_AH_ONLY	BIT(9)
726 
727 	struct qed_link_eee_params		eee;
728 	u32					fec;
729 };
730 
731 struct qed_link_output {
732 	bool					link_up;
733 
734 	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported_caps);
735 	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertised_caps);
736 	__ETHTOOL_DECLARE_LINK_MODE_MASK(lp_caps);
737 
738 	u32					speed;	   /* In Mb/s */
739 	u8					duplex;	   /* In DUPLEX defs */
740 	u8					port;	   /* In PORT defs */
741 	bool					autoneg;
742 	u32					pause_config;
743 
744 	/* EEE - capability & param */
745 	bool					eee_supported;
746 	bool					eee_active;
747 	u8					sup_caps;
748 	struct qed_link_eee_params		eee;
749 
750 	u32					sup_fec;
751 	u32					active_fec;
752 };
753 
754 struct qed_probe_params {
755 	enum qed_protocol protocol;
756 	u32 dp_module;
757 	u8 dp_level;
758 	bool is_vf;
759 	bool recov_in_prog;
760 };
761 
762 #define QED_DRV_VER_STR_SIZE 12
763 struct qed_slowpath_params {
764 	u32	int_mode;
765 	u8	drv_major;
766 	u8	drv_minor;
767 	u8	drv_rev;
768 	u8	drv_eng;
769 	u8	name[QED_DRV_VER_STR_SIZE];
770 };
771 
772 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
773 
774 struct qed_int_info {
775 	struct msix_entry	*msix;
776 	u8			msix_cnt;
777 
778 	/* This should be updated by the protocol driver */
779 	u8			used_cnt;
780 };
781 
782 struct qed_generic_tlvs {
783 #define QED_TLV_IP_CSUM         BIT(0)
784 #define QED_TLV_LSO             BIT(1)
785 	u16 feat_flags;
786 #define QED_TLV_MAC_COUNT	3
787 	u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN];
788 };
789 
790 #define QED_I2C_DEV_ADDR_A0 0xA0
791 #define QED_I2C_DEV_ADDR_A2 0xA2
792 
793 #define QED_NVM_SIGNATURE 0x12435687
794 
795 enum qed_nvm_flash_cmd {
796 	QED_NVM_FLASH_CMD_FILE_DATA = 0x2,
797 	QED_NVM_FLASH_CMD_FILE_START = 0x3,
798 	QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4,
799 	QED_NVM_FLASH_CMD_NVM_CFG_ID = 0x5,
800 	QED_NVM_FLASH_CMD_NVM_MAX,
801 };
802 
803 struct qed_devlink {
804 	struct qed_dev *cdev;
805 	struct devlink_health_reporter *fw_reporter;
806 };
807 
808 struct qed_common_cb_ops {
809 	void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc);
810 	void (*link_update)(void *dev, struct qed_link_output *link);
811 	void (*schedule_recovery_handler)(void *dev);
812 	void (*schedule_hw_err_handler)(void *dev,
813 					enum qed_hw_err_type err_type);
814 	void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
815 	void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data);
816 	void (*get_protocol_tlv_data)(void *dev, void *data);
817 	void (*bw_update)(void *dev);
818 };
819 
820 struct qed_selftest_ops {
821 /**
822  * @brief selftest_interrupt - Perform interrupt test
823  *
824  * @param cdev
825  *
826  * @return 0 on success, error otherwise.
827  */
828 	int (*selftest_interrupt)(struct qed_dev *cdev);
829 
830 /**
831  * @brief selftest_memory - Perform memory test
832  *
833  * @param cdev
834  *
835  * @return 0 on success, error otherwise.
836  */
837 	int (*selftest_memory)(struct qed_dev *cdev);
838 
839 /**
840  * @brief selftest_register - Perform register test
841  *
842  * @param cdev
843  *
844  * @return 0 on success, error otherwise.
845  */
846 	int (*selftest_register)(struct qed_dev *cdev);
847 
848 /**
849  * @brief selftest_clock - Perform clock test
850  *
851  * @param cdev
852  *
853  * @return 0 on success, error otherwise.
854  */
855 	int (*selftest_clock)(struct qed_dev *cdev);
856 
857 /**
858  * @brief selftest_nvram - Perform nvram test
859  *
860  * @param cdev
861  *
862  * @return 0 on success, error otherwise.
863  */
864 	int (*selftest_nvram) (struct qed_dev *cdev);
865 };
866 
867 struct qed_common_ops {
868 	struct qed_selftest_ops *selftest;
869 
870 	struct qed_dev*	(*probe)(struct pci_dev *dev,
871 				 struct qed_probe_params *params);
872 
873 	void (*remove)(struct qed_dev *cdev);
874 
875 	int (*set_power_state)(struct qed_dev *cdev, pci_power_t state);
876 
877 	void (*set_name) (struct qed_dev *cdev, char name[]);
878 
879 	/* Client drivers need to make this call before slowpath_start.
880 	 * PF params required for the call before slowpath_start is
881 	 * documented within the qed_pf_params structure definition.
882 	 */
883 	void (*update_pf_params)(struct qed_dev *cdev,
884 				 struct qed_pf_params *params);
885 
886 	int (*slowpath_start)(struct qed_dev *cdev,
887 			      struct qed_slowpath_params *params);
888 
889 	int (*slowpath_stop)(struct qed_dev *cdev);
890 
891 	/* Requests to use `cnt' interrupts for fastpath.
892 	 * upon success, returns number of interrupts allocated for fastpath.
893 	 */
894 	int (*set_fp_int)(struct qed_dev *cdev, u16 cnt);
895 
896 	/* Fills `info' with pointers required for utilizing interrupts */
897 	int (*get_fp_int)(struct qed_dev *cdev, struct qed_int_info *info);
898 
899 	u32 (*sb_init)(struct qed_dev *cdev,
900 		       struct qed_sb_info *sb_info,
901 		       void *sb_virt_addr,
902 		       dma_addr_t sb_phy_addr,
903 		       u16 sb_id,
904 		       enum qed_sb_type type);
905 
906 	u32 (*sb_release)(struct qed_dev *cdev,
907 			  struct qed_sb_info *sb_info,
908 			  u16 sb_id,
909 			  enum qed_sb_type type);
910 
911 	void (*simd_handler_config)(struct qed_dev *cdev,
912 				    void *token,
913 				    int index,
914 				    void (*handler)(void *));
915 
916 	void (*simd_handler_clean)(struct qed_dev *cdev, int index);
917 
918 	int (*dbg_grc)(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes);
919 
920 	int (*dbg_grc_size)(struct qed_dev *cdev);
921 
922 	int (*dbg_all_data)(struct qed_dev *cdev, void *buffer);
923 
924 	int (*dbg_all_data_size)(struct qed_dev *cdev);
925 
926 	int (*report_fatal_error)(struct devlink *devlink,
927 				  enum qed_hw_err_type err_type);
928 
929 /**
930  * @brief can_link_change - can the instance change the link or not
931  *
932  * @param cdev
933  *
934  * @return true if link-change is allowed, false otherwise.
935  */
936 	bool (*can_link_change)(struct qed_dev *cdev);
937 
938 /**
939  * @brief set_link - set links according to params
940  *
941  * @param cdev
942  * @param params - values used to override the default link configuration
943  *
944  * @return 0 on success, error otherwise.
945  */
946 	int		(*set_link)(struct qed_dev *cdev,
947 				    struct qed_link_params *params);
948 
949 /**
950  * @brief get_link - returns the current link state.
951  *
952  * @param cdev
953  * @param if_link - structure to be filled with current link configuration.
954  */
955 	void		(*get_link)(struct qed_dev *cdev,
956 				    struct qed_link_output *if_link);
957 
958 /**
959  * @brief - drains chip in case Tx completions fail to arrive due to pause.
960  *
961  * @param cdev
962  */
963 	int		(*drain)(struct qed_dev *cdev);
964 
965 /**
966  * @brief update_msglvl - update module debug level
967  *
968  * @param cdev
969  * @param dp_module
970  * @param dp_level
971  */
972 	void		(*update_msglvl)(struct qed_dev *cdev,
973 					 u32 dp_module,
974 					 u8 dp_level);
975 
976 	int		(*chain_alloc)(struct qed_dev *cdev,
977 				       struct qed_chain *chain,
978 				       struct qed_chain_init_params *params);
979 
980 	void		(*chain_free)(struct qed_dev *cdev,
981 				      struct qed_chain *p_chain);
982 
983 /**
984  * @brief nvm_flash - Flash nvm data.
985  *
986  * @param cdev
987  * @param name - file containing the data
988  *
989  * @return 0 on success, error otherwise.
990  */
991 	int (*nvm_flash)(struct qed_dev *cdev, const char *name);
992 
993 /**
994  * @brief nvm_get_image - reads an entire image from nvram
995  *
996  * @param cdev
997  * @param type - type of the request nvram image
998  * @param buf - preallocated buffer to fill with the image
999  * @param len - length of the allocated buffer
1000  *
1001  * @return 0 on success, error otherwise
1002  */
1003 	int (*nvm_get_image)(struct qed_dev *cdev,
1004 			     enum qed_nvm_images type, u8 *buf, u16 len);
1005 
1006 /**
1007  * @brief set_coalesce - Configure Rx coalesce value in usec
1008  *
1009  * @param cdev
1010  * @param rx_coal - Rx coalesce value in usec
1011  * @param tx_coal - Tx coalesce value in usec
1012  * @param qid - Queue index
1013  * @param sb_id - Status Block Id
1014  *
1015  * @return 0 on success, error otherwise.
1016  */
1017 	int (*set_coalesce)(struct qed_dev *cdev,
1018 			    u16 rx_coal, u16 tx_coal, void *handle);
1019 
1020 /**
1021  * @brief set_led - Configure LED mode
1022  *
1023  * @param cdev
1024  * @param mode - LED mode
1025  *
1026  * @return 0 on success, error otherwise.
1027  */
1028 	int (*set_led)(struct qed_dev *cdev,
1029 		       enum qed_led_mode mode);
1030 
1031 /**
1032  * @brief attn_clr_enable - Prevent attentions from being reasserted
1033  *
1034  * @param cdev
1035  * @param clr_enable
1036  */
1037 	void (*attn_clr_enable)(struct qed_dev *cdev, bool clr_enable);
1038 
1039 /**
1040  * @brief db_recovery_add - add doorbell information to the doorbell
1041  * recovery mechanism.
1042  *
1043  * @param cdev
1044  * @param db_addr - doorbell address
1045  * @param db_data - address of where db_data is stored
1046  * @param db_is_32b - doorbell is 32b pr 64b
1047  * @param db_is_user - doorbell recovery addresses are user or kernel space
1048  */
1049 	int (*db_recovery_add)(struct qed_dev *cdev,
1050 			       void __iomem *db_addr,
1051 			       void *db_data,
1052 			       enum qed_db_rec_width db_width,
1053 			       enum qed_db_rec_space db_space);
1054 
1055 /**
1056  * @brief db_recovery_del - remove doorbell information from the doorbell
1057  * recovery mechanism. db_data serves as key (db_addr is not unique).
1058  *
1059  * @param cdev
1060  * @param db_addr - doorbell address
1061  * @param db_data - address where db_data is stored. Serves as key for the
1062  *		    entry to delete.
1063  */
1064 	int (*db_recovery_del)(struct qed_dev *cdev,
1065 			       void __iomem *db_addr, void *db_data);
1066 
1067 /**
1068  * @brief recovery_process - Trigger a recovery process
1069  *
1070  * @param cdev
1071  *
1072  * @return 0 on success, error otherwise.
1073  */
1074 	int (*recovery_process)(struct qed_dev *cdev);
1075 
1076 /**
1077  * @brief recovery_prolog - Execute the prolog operations of a recovery process
1078  *
1079  * @param cdev
1080  *
1081  * @return 0 on success, error otherwise.
1082  */
1083 	int (*recovery_prolog)(struct qed_dev *cdev);
1084 
1085 /**
1086  * @brief update_drv_state - API to inform the change in the driver state.
1087  *
1088  * @param cdev
1089  * @param active
1090  *
1091  */
1092 	int (*update_drv_state)(struct qed_dev *cdev, bool active);
1093 
1094 /**
1095  * @brief update_mac - API to inform the change in the mac address
1096  *
1097  * @param cdev
1098  * @param mac
1099  *
1100  */
1101 	int (*update_mac)(struct qed_dev *cdev, u8 *mac);
1102 
1103 /**
1104  * @brief update_mtu - API to inform the change in the mtu
1105  *
1106  * @param cdev
1107  * @param mtu
1108  *
1109  */
1110 	int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
1111 
1112 /**
1113  * @brief update_wol - update of changes in the WoL configuration
1114  *
1115  * @param cdev
1116  * @param enabled - true iff WoL should be enabled.
1117  */
1118 	int (*update_wol) (struct qed_dev *cdev, bool enabled);
1119 
1120 /**
1121  * @brief read_module_eeprom
1122  *
1123  * @param cdev
1124  * @param buf - buffer
1125  * @param dev_addr - PHY device memory region
1126  * @param offset - offset into eeprom contents to be read
1127  * @param len - buffer length, i.e., max bytes to be read
1128  */
1129 	int (*read_module_eeprom)(struct qed_dev *cdev,
1130 				  char *buf, u8 dev_addr, u32 offset, u32 len);
1131 
1132 /**
1133  * @brief get_affin_hwfn_idx
1134  *
1135  * @param cdev
1136  */
1137 	u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev);
1138 
1139 /**
1140  * @brief read_nvm_cfg - Read NVM config attribute value.
1141  * @param cdev
1142  * @param buf - buffer
1143  * @param cmd - NVM CFG command id
1144  * @param entity_id - Entity id
1145  *
1146  */
1147 	int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd,
1148 			    u32 entity_id);
1149 /**
1150  * @brief read_nvm_cfg - Read NVM config attribute value.
1151  * @param cdev
1152  * @param cmd - NVM CFG command id
1153  *
1154  * @return config id length, 0 on error.
1155  */
1156 	int (*read_nvm_cfg_len)(struct qed_dev *cdev, u32 cmd);
1157 
1158 /**
1159  * @brief set_grc_config - Configure value for grc config id.
1160  * @param cdev
1161  * @param cfg_id - grc config id
1162  * @param val - grc config value
1163  *
1164  */
1165 	int (*set_grc_config)(struct qed_dev *cdev, u32 cfg_id, u32 val);
1166 
1167 	struct devlink* (*devlink_register)(struct qed_dev *cdev);
1168 
1169 	void (*devlink_unregister)(struct devlink *devlink);
1170 };
1171 
1172 #define MASK_FIELD(_name, _value) \
1173 	((_value) &= (_name ## _MASK))
1174 
1175 #define FIELD_VALUE(_name, _value) \
1176 	((_value & _name ## _MASK) << _name ## _SHIFT)
1177 
1178 #define SET_FIELD(value, name, flag)			       \
1179 	do {						       \
1180 		(value) &= ~(name ## _MASK << name ## _SHIFT); \
1181 		(value) |= (((u64)flag) << (name ## _SHIFT));  \
1182 	} while (0)
1183 
1184 #define GET_FIELD(value, name) \
1185 	(((value) >> (name ## _SHIFT)) & name ## _MASK)
1186 
1187 #define GET_MFW_FIELD(name, field) \
1188 	(((name) & (field ## _MASK)) >> (field ## _OFFSET))
1189 
1190 #define SET_MFW_FIELD(name, field, value)				 \
1191 	do {								 \
1192 		(name) &= ~(field ## _MASK);				 \
1193 		(name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK));\
1194 	} while (0)
1195 
1196 #define DB_ADDR_SHIFT(addr) ((addr) << DB_PWM_ADDR_OFFSET_SHIFT)
1197 
1198 /* Debug print definitions */
1199 #define DP_ERR(cdev, fmt, ...)					\
1200 	do {							\
1201 		pr_err("[%s:%d(%s)]" fmt,			\
1202 		       __func__, __LINE__,			\
1203 		       DP_NAME(cdev) ? DP_NAME(cdev) : "",	\
1204 		       ## __VA_ARGS__);				\
1205 	} while (0)
1206 
1207 #define DP_NOTICE(cdev, fmt, ...)				      \
1208 	do {							      \
1209 		if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
1210 			pr_notice("[%s:%d(%s)]" fmt,		      \
1211 				  __func__, __LINE__,		      \
1212 				  DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1213 				  ## __VA_ARGS__);		      \
1214 								      \
1215 		}						      \
1216 	} while (0)
1217 
1218 #define DP_INFO(cdev, fmt, ...)					      \
1219 	do {							      \
1220 		if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) {   \
1221 			pr_notice("[%s:%d(%s)]" fmt,		      \
1222 				  __func__, __LINE__,		      \
1223 				  DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1224 				  ## __VA_ARGS__);		      \
1225 		}						      \
1226 	} while (0)
1227 
1228 #define DP_VERBOSE(cdev, module, fmt, ...)				\
1229 	do {								\
1230 		if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) &&	\
1231 			     ((cdev)->dp_module & module))) {		\
1232 			pr_notice("[%s:%d(%s)]" fmt,			\
1233 				  __func__, __LINE__,			\
1234 				  DP_NAME(cdev) ? DP_NAME(cdev) : "",	\
1235 				  ## __VA_ARGS__);			\
1236 		}							\
1237 	} while (0)
1238 
1239 enum DP_LEVEL {
1240 	QED_LEVEL_VERBOSE	= 0x0,
1241 	QED_LEVEL_INFO		= 0x1,
1242 	QED_LEVEL_NOTICE	= 0x2,
1243 	QED_LEVEL_ERR		= 0x3,
1244 };
1245 
1246 #define QED_LOG_LEVEL_SHIFT     (30)
1247 #define QED_LOG_VERBOSE_MASK    (0x3fffffff)
1248 #define QED_LOG_INFO_MASK       (0x40000000)
1249 #define QED_LOG_NOTICE_MASK     (0x80000000)
1250 
1251 enum DP_MODULE {
1252 	QED_MSG_SPQ	= 0x10000,
1253 	QED_MSG_STATS	= 0x20000,
1254 	QED_MSG_DCB	= 0x40000,
1255 	QED_MSG_IOV	= 0x80000,
1256 	QED_MSG_SP	= 0x100000,
1257 	QED_MSG_STORAGE = 0x200000,
1258 	QED_MSG_CXT	= 0x800000,
1259 	QED_MSG_LL2	= 0x1000000,
1260 	QED_MSG_ILT	= 0x2000000,
1261 	QED_MSG_RDMA	= 0x4000000,
1262 	QED_MSG_DEBUG	= 0x8000000,
1263 	/* to be added...up to 0x8000000 */
1264 };
1265 
1266 enum qed_mf_mode {
1267 	QED_MF_DEFAULT,
1268 	QED_MF_OVLAN,
1269 	QED_MF_NPAR,
1270 };
1271 
1272 struct qed_eth_stats_common {
1273 	u64	no_buff_discards;
1274 	u64	packet_too_big_discard;
1275 	u64	ttl0_discard;
1276 	u64	rx_ucast_bytes;
1277 	u64	rx_mcast_bytes;
1278 	u64	rx_bcast_bytes;
1279 	u64	rx_ucast_pkts;
1280 	u64	rx_mcast_pkts;
1281 	u64	rx_bcast_pkts;
1282 	u64	mftag_filter_discards;
1283 	u64	mac_filter_discards;
1284 	u64	gft_filter_drop;
1285 	u64	tx_ucast_bytes;
1286 	u64	tx_mcast_bytes;
1287 	u64	tx_bcast_bytes;
1288 	u64	tx_ucast_pkts;
1289 	u64	tx_mcast_pkts;
1290 	u64	tx_bcast_pkts;
1291 	u64	tx_err_drop_pkts;
1292 	u64	tpa_coalesced_pkts;
1293 	u64	tpa_coalesced_events;
1294 	u64	tpa_aborts_num;
1295 	u64	tpa_not_coalesced_pkts;
1296 	u64	tpa_coalesced_bytes;
1297 
1298 	/* port */
1299 	u64	rx_64_byte_packets;
1300 	u64	rx_65_to_127_byte_packets;
1301 	u64	rx_128_to_255_byte_packets;
1302 	u64	rx_256_to_511_byte_packets;
1303 	u64	rx_512_to_1023_byte_packets;
1304 	u64	rx_1024_to_1518_byte_packets;
1305 	u64	rx_crc_errors;
1306 	u64	rx_mac_crtl_frames;
1307 	u64	rx_pause_frames;
1308 	u64	rx_pfc_frames;
1309 	u64	rx_align_errors;
1310 	u64	rx_carrier_errors;
1311 	u64	rx_oversize_packets;
1312 	u64	rx_jabbers;
1313 	u64	rx_undersize_packets;
1314 	u64	rx_fragments;
1315 	u64	tx_64_byte_packets;
1316 	u64	tx_65_to_127_byte_packets;
1317 	u64	tx_128_to_255_byte_packets;
1318 	u64	tx_256_to_511_byte_packets;
1319 	u64	tx_512_to_1023_byte_packets;
1320 	u64	tx_1024_to_1518_byte_packets;
1321 	u64	tx_pause_frames;
1322 	u64	tx_pfc_frames;
1323 	u64	brb_truncates;
1324 	u64	brb_discards;
1325 	u64	rx_mac_bytes;
1326 	u64	rx_mac_uc_packets;
1327 	u64	rx_mac_mc_packets;
1328 	u64	rx_mac_bc_packets;
1329 	u64	rx_mac_frames_ok;
1330 	u64	tx_mac_bytes;
1331 	u64	tx_mac_uc_packets;
1332 	u64	tx_mac_mc_packets;
1333 	u64	tx_mac_bc_packets;
1334 	u64	tx_mac_ctrl_frames;
1335 	u64	link_change_count;
1336 };
1337 
1338 struct qed_eth_stats_bb {
1339 	u64 rx_1519_to_1522_byte_packets;
1340 	u64 rx_1519_to_2047_byte_packets;
1341 	u64 rx_2048_to_4095_byte_packets;
1342 	u64 rx_4096_to_9216_byte_packets;
1343 	u64 rx_9217_to_16383_byte_packets;
1344 	u64 tx_1519_to_2047_byte_packets;
1345 	u64 tx_2048_to_4095_byte_packets;
1346 	u64 tx_4096_to_9216_byte_packets;
1347 	u64 tx_9217_to_16383_byte_packets;
1348 	u64 tx_lpi_entry_count;
1349 	u64 tx_total_collisions;
1350 };
1351 
1352 struct qed_eth_stats_ah {
1353 	u64 rx_1519_to_max_byte_packets;
1354 	u64 tx_1519_to_max_byte_packets;
1355 };
1356 
1357 struct qed_eth_stats {
1358 	struct qed_eth_stats_common common;
1359 
1360 	union {
1361 		struct qed_eth_stats_bb bb;
1362 		struct qed_eth_stats_ah ah;
1363 	};
1364 };
1365 
1366 #define QED_SB_IDX              0x0002
1367 
1368 #define RX_PI           0
1369 #define TX_PI(tc)       (RX_PI + 1 + tc)
1370 
1371 struct qed_sb_cnt_info {
1372 	/* Original, current, and free SBs for PF */
1373 	int orig;
1374 	int cnt;
1375 	int free_cnt;
1376 
1377 	/* Original, current and free SBS for child VFs */
1378 	int iov_orig;
1379 	int iov_cnt;
1380 	int free_cnt_iov;
1381 };
1382 
1383 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
1384 {
1385 	u32 prod = 0;
1386 	u16 rc = 0;
1387 
1388 	prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
1389 	       STATUS_BLOCK_E4_PROD_INDEX_MASK;
1390 	if (sb_info->sb_ack != prod) {
1391 		sb_info->sb_ack = prod;
1392 		rc |= QED_SB_IDX;
1393 	}
1394 
1395 	/* Let SB update */
1396 	return rc;
1397 }
1398 
1399 /**
1400  *
1401  * @brief This function creates an update command for interrupts that is
1402  *        written to the IGU.
1403  *
1404  * @param sb_info       - This is the structure allocated and
1405  *                 initialized per status block. Assumption is
1406  *                 that it was initialized using qed_sb_init
1407  * @param int_cmd       - Enable/Disable/Nop
1408  * @param upd_flg       - whether igu consumer should be
1409  *                 updated.
1410  *
1411  * @return inline void
1412  */
1413 static inline void qed_sb_ack(struct qed_sb_info *sb_info,
1414 			      enum igu_int_cmd int_cmd,
1415 			      u8 upd_flg)
1416 {
1417 	u32 igu_ack;
1418 
1419 	igu_ack = ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1420 		   (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1421 		   (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1422 		   (IGU_SEG_ACCESS_REG <<
1423 		    IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1424 
1425 	DIRECT_REG_WR(sb_info->igu_addr, igu_ack);
1426 
1427 	/* Both segments (interrupts & acks) are written to same place address;
1428 	 * Need to guarantee all commands will be received (in-order) by HW.
1429 	 */
1430 	barrier();
1431 }
1432 
1433 static inline void __internal_ram_wr(void *p_hwfn,
1434 				     void __iomem *addr,
1435 				     int size,
1436 				     u32 *data)
1437 
1438 {
1439 	unsigned int i;
1440 
1441 	for (i = 0; i < size / sizeof(*data); i++)
1442 		DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
1443 }
1444 
1445 static inline void internal_ram_wr(void __iomem *addr,
1446 				   int size,
1447 				   u32 *data)
1448 {
1449 	__internal_ram_wr(NULL, addr, size, data);
1450 }
1451 
1452 enum qed_rss_caps {
1453 	QED_RSS_IPV4		= 0x1,
1454 	QED_RSS_IPV6		= 0x2,
1455 	QED_RSS_IPV4_TCP	= 0x4,
1456 	QED_RSS_IPV6_TCP	= 0x8,
1457 	QED_RSS_IPV4_UDP	= 0x10,
1458 	QED_RSS_IPV6_UDP	= 0x20,
1459 };
1460 
1461 #define QED_RSS_IND_TABLE_SIZE 128
1462 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
1463 #endif
1464