1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _QED_IF_H 34 #define _QED_IF_H 35 36 #include <linux/types.h> 37 #include <linux/interrupt.h> 38 #include <linux/netdevice.h> 39 #include <linux/pci.h> 40 #include <linux/skbuff.h> 41 #include <asm/byteorder.h> 42 #include <linux/io.h> 43 #include <linux/compiler.h> 44 #include <linux/kernel.h> 45 #include <linux/list.h> 46 #include <linux/slab.h> 47 #include <linux/qed/common_hsi.h> 48 #include <linux/qed/qed_chain.h> 49 #include <linux/io-64-nonatomic-lo-hi.h> 50 51 enum dcbx_protocol_type { 52 DCBX_PROTOCOL_ISCSI, 53 DCBX_PROTOCOL_FCOE, 54 DCBX_PROTOCOL_ROCE, 55 DCBX_PROTOCOL_ROCE_V2, 56 DCBX_PROTOCOL_ETH, 57 DCBX_MAX_PROTOCOL_TYPE 58 }; 59 60 #define QED_ROCE_PROTOCOL_INDEX (3) 61 62 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4 63 #define QED_LLDP_PORT_ID_STAT_LEN 4 64 #define QED_DCBX_MAX_APP_PROTOCOL 32 65 #define QED_MAX_PFC_PRIORITIES 8 66 #define QED_DCBX_DSCP_SIZE 64 67 68 struct qed_dcbx_lldp_remote { 69 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 70 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 71 bool enable_rx; 72 bool enable_tx; 73 u32 tx_interval; 74 u32 max_credit; 75 }; 76 77 struct qed_dcbx_lldp_local { 78 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 79 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 80 }; 81 82 struct qed_dcbx_app_prio { 83 u8 roce; 84 u8 roce_v2; 85 u8 fcoe; 86 u8 iscsi; 87 u8 eth; 88 }; 89 90 struct qed_dbcx_pfc_params { 91 bool willing; 92 bool enabled; 93 u8 prio[QED_MAX_PFC_PRIORITIES]; 94 u8 max_tc; 95 }; 96 97 enum qed_dcbx_sf_ieee_type { 98 QED_DCBX_SF_IEEE_ETHTYPE, 99 QED_DCBX_SF_IEEE_TCP_PORT, 100 QED_DCBX_SF_IEEE_UDP_PORT, 101 QED_DCBX_SF_IEEE_TCP_UDP_PORT 102 }; 103 104 struct qed_app_entry { 105 bool ethtype; 106 enum qed_dcbx_sf_ieee_type sf_ieee; 107 bool enabled; 108 u8 prio; 109 u16 proto_id; 110 enum dcbx_protocol_type proto_type; 111 }; 112 113 struct qed_dcbx_params { 114 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL]; 115 u16 num_app_entries; 116 bool app_willing; 117 bool app_valid; 118 bool app_error; 119 bool ets_willing; 120 bool ets_enabled; 121 bool ets_cbs; 122 bool valid; 123 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES]; 124 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES]; 125 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES]; 126 struct qed_dbcx_pfc_params pfc; 127 u8 max_ets_tc; 128 }; 129 130 struct qed_dcbx_admin_params { 131 struct qed_dcbx_params params; 132 bool valid; 133 }; 134 135 struct qed_dcbx_remote_params { 136 struct qed_dcbx_params params; 137 bool valid; 138 }; 139 140 struct qed_dcbx_operational_params { 141 struct qed_dcbx_app_prio app_prio; 142 struct qed_dcbx_params params; 143 bool valid; 144 bool enabled; 145 bool ieee; 146 bool cee; 147 bool local; 148 u32 err; 149 }; 150 151 struct qed_dcbx_get { 152 struct qed_dcbx_operational_params operational; 153 struct qed_dcbx_lldp_remote lldp_remote; 154 struct qed_dcbx_lldp_local lldp_local; 155 struct qed_dcbx_remote_params remote; 156 struct qed_dcbx_admin_params local; 157 }; 158 159 enum qed_nvm_images { 160 QED_NVM_IMAGE_ISCSI_CFG, 161 QED_NVM_IMAGE_FCOE_CFG, 162 QED_NVM_IMAGE_MDUMP, 163 QED_NVM_IMAGE_NVM_CFG1, 164 QED_NVM_IMAGE_DEFAULT_CFG, 165 QED_NVM_IMAGE_NVM_META, 166 }; 167 168 struct qed_link_eee_params { 169 u32 tx_lpi_timer; 170 #define QED_EEE_1G_ADV BIT(0) 171 #define QED_EEE_10G_ADV BIT(1) 172 173 /* Capabilities are represented using QED_EEE_*_ADV values */ 174 u8 adv_caps; 175 u8 lp_adv_caps; 176 bool enable; 177 bool tx_lpi_enable; 178 }; 179 180 enum qed_led_mode { 181 QED_LED_MODE_OFF, 182 QED_LED_MODE_ON, 183 QED_LED_MODE_RESTORE 184 }; 185 186 struct qed_mfw_tlv_eth { 187 u16 lso_maxoff_size; 188 bool lso_maxoff_size_set; 189 u16 lso_minseg_size; 190 bool lso_minseg_size_set; 191 u8 prom_mode; 192 bool prom_mode_set; 193 u16 tx_descr_size; 194 bool tx_descr_size_set; 195 u16 rx_descr_size; 196 bool rx_descr_size_set; 197 u16 netq_count; 198 bool netq_count_set; 199 u32 tcp4_offloads; 200 bool tcp4_offloads_set; 201 u32 tcp6_offloads; 202 bool tcp6_offloads_set; 203 u16 tx_descr_qdepth; 204 bool tx_descr_qdepth_set; 205 u16 rx_descr_qdepth; 206 bool rx_descr_qdepth_set; 207 u8 iov_offload; 208 #define QED_MFW_TLV_IOV_OFFLOAD_NONE (0) 209 #define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE (1) 210 #define QED_MFW_TLV_IOV_OFFLOAD_VEB (2) 211 #define QED_MFW_TLV_IOV_OFFLOAD_VEPA (3) 212 bool iov_offload_set; 213 u8 txqs_empty; 214 bool txqs_empty_set; 215 u8 rxqs_empty; 216 bool rxqs_empty_set; 217 u8 num_txqs_full; 218 bool num_txqs_full_set; 219 u8 num_rxqs_full; 220 bool num_rxqs_full_set; 221 }; 222 223 #define QED_MFW_TLV_TIME_SIZE 14 224 struct qed_mfw_tlv_time { 225 bool b_set; 226 u8 month; 227 u8 day; 228 u8 hour; 229 u8 min; 230 u16 msec; 231 u16 usec; 232 }; 233 234 struct qed_mfw_tlv_fcoe { 235 u8 scsi_timeout; 236 bool scsi_timeout_set; 237 u32 rt_tov; 238 bool rt_tov_set; 239 u32 ra_tov; 240 bool ra_tov_set; 241 u32 ed_tov; 242 bool ed_tov_set; 243 u32 cr_tov; 244 bool cr_tov_set; 245 u8 boot_type; 246 bool boot_type_set; 247 u8 npiv_state; 248 bool npiv_state_set; 249 u32 num_npiv_ids; 250 bool num_npiv_ids_set; 251 u8 switch_name[8]; 252 bool switch_name_set; 253 u16 switch_portnum; 254 bool switch_portnum_set; 255 u8 switch_portid[3]; 256 bool switch_portid_set; 257 u8 vendor_name[8]; 258 bool vendor_name_set; 259 u8 switch_model[8]; 260 bool switch_model_set; 261 u8 switch_fw_version[8]; 262 bool switch_fw_version_set; 263 u8 qos_pri; 264 bool qos_pri_set; 265 u8 port_alias[3]; 266 bool port_alias_set; 267 u8 port_state; 268 #define QED_MFW_TLV_PORT_STATE_OFFLINE (0) 269 #define QED_MFW_TLV_PORT_STATE_LOOP (1) 270 #define QED_MFW_TLV_PORT_STATE_P2P (2) 271 #define QED_MFW_TLV_PORT_STATE_FABRIC (3) 272 bool port_state_set; 273 u16 fip_tx_descr_size; 274 bool fip_tx_descr_size_set; 275 u16 fip_rx_descr_size; 276 bool fip_rx_descr_size_set; 277 u16 link_failures; 278 bool link_failures_set; 279 u8 fcoe_boot_progress; 280 bool fcoe_boot_progress_set; 281 u64 rx_bcast; 282 bool rx_bcast_set; 283 u64 tx_bcast; 284 bool tx_bcast_set; 285 u16 fcoe_txq_depth; 286 bool fcoe_txq_depth_set; 287 u16 fcoe_rxq_depth; 288 bool fcoe_rxq_depth_set; 289 u64 fcoe_rx_frames; 290 bool fcoe_rx_frames_set; 291 u64 fcoe_rx_bytes; 292 bool fcoe_rx_bytes_set; 293 u64 fcoe_tx_frames; 294 bool fcoe_tx_frames_set; 295 u64 fcoe_tx_bytes; 296 bool fcoe_tx_bytes_set; 297 u16 crc_count; 298 bool crc_count_set; 299 u32 crc_err_src_fcid[5]; 300 bool crc_err_src_fcid_set[5]; 301 struct qed_mfw_tlv_time crc_err[5]; 302 u16 losync_err; 303 bool losync_err_set; 304 u16 losig_err; 305 bool losig_err_set; 306 u16 primtive_err; 307 bool primtive_err_set; 308 u16 disparity_err; 309 bool disparity_err_set; 310 u16 code_violation_err; 311 bool code_violation_err_set; 312 u32 flogi_param[4]; 313 bool flogi_param_set[4]; 314 struct qed_mfw_tlv_time flogi_tstamp; 315 u32 flogi_acc_param[4]; 316 bool flogi_acc_param_set[4]; 317 struct qed_mfw_tlv_time flogi_acc_tstamp; 318 u32 flogi_rjt; 319 bool flogi_rjt_set; 320 struct qed_mfw_tlv_time flogi_rjt_tstamp; 321 u32 fdiscs; 322 bool fdiscs_set; 323 u8 fdisc_acc; 324 bool fdisc_acc_set; 325 u8 fdisc_rjt; 326 bool fdisc_rjt_set; 327 u8 plogi; 328 bool plogi_set; 329 u8 plogi_acc; 330 bool plogi_acc_set; 331 u8 plogi_rjt; 332 bool plogi_rjt_set; 333 u32 plogi_dst_fcid[5]; 334 bool plogi_dst_fcid_set[5]; 335 struct qed_mfw_tlv_time plogi_tstamp[5]; 336 u32 plogi_acc_src_fcid[5]; 337 bool plogi_acc_src_fcid_set[5]; 338 struct qed_mfw_tlv_time plogi_acc_tstamp[5]; 339 u8 tx_plogos; 340 bool tx_plogos_set; 341 u8 plogo_acc; 342 bool plogo_acc_set; 343 u8 plogo_rjt; 344 bool plogo_rjt_set; 345 u32 plogo_src_fcid[5]; 346 bool plogo_src_fcid_set[5]; 347 struct qed_mfw_tlv_time plogo_tstamp[5]; 348 u8 rx_logos; 349 bool rx_logos_set; 350 u8 tx_accs; 351 bool tx_accs_set; 352 u8 tx_prlis; 353 bool tx_prlis_set; 354 u8 rx_accs; 355 bool rx_accs_set; 356 u8 tx_abts; 357 bool tx_abts_set; 358 u8 rx_abts_acc; 359 bool rx_abts_acc_set; 360 u8 rx_abts_rjt; 361 bool rx_abts_rjt_set; 362 u32 abts_dst_fcid[5]; 363 bool abts_dst_fcid_set[5]; 364 struct qed_mfw_tlv_time abts_tstamp[5]; 365 u8 rx_rscn; 366 bool rx_rscn_set; 367 u32 rx_rscn_nport[4]; 368 bool rx_rscn_nport_set[4]; 369 u8 tx_lun_rst; 370 bool tx_lun_rst_set; 371 u8 abort_task_sets; 372 bool abort_task_sets_set; 373 u8 tx_tprlos; 374 bool tx_tprlos_set; 375 u8 tx_nos; 376 bool tx_nos_set; 377 u8 rx_nos; 378 bool rx_nos_set; 379 u8 ols; 380 bool ols_set; 381 u8 lr; 382 bool lr_set; 383 u8 lrr; 384 bool lrr_set; 385 u8 tx_lip; 386 bool tx_lip_set; 387 u8 rx_lip; 388 bool rx_lip_set; 389 u8 eofa; 390 bool eofa_set; 391 u8 eofni; 392 bool eofni_set; 393 u8 scsi_chks; 394 bool scsi_chks_set; 395 u8 scsi_cond_met; 396 bool scsi_cond_met_set; 397 u8 scsi_busy; 398 bool scsi_busy_set; 399 u8 scsi_inter; 400 bool scsi_inter_set; 401 u8 scsi_inter_cond_met; 402 bool scsi_inter_cond_met_set; 403 u8 scsi_rsv_conflicts; 404 bool scsi_rsv_conflicts_set; 405 u8 scsi_tsk_full; 406 bool scsi_tsk_full_set; 407 u8 scsi_aca_active; 408 bool scsi_aca_active_set; 409 u8 scsi_tsk_abort; 410 bool scsi_tsk_abort_set; 411 u32 scsi_rx_chk[5]; 412 bool scsi_rx_chk_set[5]; 413 struct qed_mfw_tlv_time scsi_chk_tstamp[5]; 414 }; 415 416 struct qed_mfw_tlv_iscsi { 417 u8 target_llmnr; 418 bool target_llmnr_set; 419 u8 header_digest; 420 bool header_digest_set; 421 u8 data_digest; 422 bool data_digest_set; 423 u8 auth_method; 424 #define QED_MFW_TLV_AUTH_METHOD_NONE (1) 425 #define QED_MFW_TLV_AUTH_METHOD_CHAP (2) 426 #define QED_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP (3) 427 bool auth_method_set; 428 u16 boot_taget_portal; 429 bool boot_taget_portal_set; 430 u16 frame_size; 431 bool frame_size_set; 432 u16 tx_desc_size; 433 bool tx_desc_size_set; 434 u16 rx_desc_size; 435 bool rx_desc_size_set; 436 u8 boot_progress; 437 bool boot_progress_set; 438 u16 tx_desc_qdepth; 439 bool tx_desc_qdepth_set; 440 u16 rx_desc_qdepth; 441 bool rx_desc_qdepth_set; 442 u64 rx_frames; 443 bool rx_frames_set; 444 u64 rx_bytes; 445 bool rx_bytes_set; 446 u64 tx_frames; 447 bool tx_frames_set; 448 u64 tx_bytes; 449 bool tx_bytes_set; 450 }; 451 452 enum qed_db_rec_width { 453 DB_REC_WIDTH_32B, 454 DB_REC_WIDTH_64B, 455 }; 456 457 enum qed_db_rec_space { 458 DB_REC_KERNEL, 459 DB_REC_USER, 460 }; 461 462 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \ 463 (void __iomem *)(reg_addr)) 464 465 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr)) 466 467 #define DIRECT_REG_WR64(reg_addr, val) writeq((u64)val, \ 468 (void __iomem *)(reg_addr)) 469 470 #define QED_COALESCE_MAX 0x1FF 471 #define QED_DEFAULT_RX_USECS 12 472 #define QED_DEFAULT_TX_USECS 48 473 474 /* forward */ 475 struct qed_dev; 476 477 struct qed_eth_pf_params { 478 /* The following parameters are used during HW-init 479 * and these parameters need to be passed as arguments 480 * to update_pf_params routine invoked before slowpath start 481 */ 482 u16 num_cons; 483 484 /* per-VF number of CIDs */ 485 u8 num_vf_cons; 486 #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32) 487 488 /* To enable arfs, previous to HW-init a positive number needs to be 489 * set [as filters require allocated searcher ILT memory]. 490 * This will set the maximal number of configured steering-filters. 491 */ 492 u32 num_arfs_filters; 493 }; 494 495 struct qed_fcoe_pf_params { 496 /* The following parameters are used during protocol-init */ 497 u64 glbl_q_params_addr; 498 u64 bdq_pbl_base_addr[2]; 499 500 /* The following parameters are used during HW-init 501 * and these parameters need to be passed as arguments 502 * to update_pf_params routine invoked before slowpath start 503 */ 504 u16 num_cons; 505 u16 num_tasks; 506 507 /* The following parameters are used during protocol-init */ 508 u16 sq_num_pbl_pages; 509 510 u16 cq_num_entries; 511 u16 cmdq_num_entries; 512 u16 rq_buffer_log_size; 513 u16 mtu; 514 u16 dummy_icid; 515 u16 bdq_xoff_threshold[2]; 516 u16 bdq_xon_threshold[2]; 517 u16 rq_buffer_size; 518 u8 num_cqs; /* num of global CQs */ 519 u8 log_page_size; 520 u8 gl_rq_pi; 521 u8 gl_cmd_pi; 522 u8 debug_mode; 523 u8 is_target; 524 u8 bdq_pbl_num_entries[2]; 525 }; 526 527 /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */ 528 struct qed_iscsi_pf_params { 529 u64 glbl_q_params_addr; 530 u64 bdq_pbl_base_addr[3]; 531 u16 cq_num_entries; 532 u16 cmdq_num_entries; 533 u32 two_msl_timer; 534 u16 tx_sws_timer; 535 536 /* The following parameters are used during HW-init 537 * and these parameters need to be passed as arguments 538 * to update_pf_params routine invoked before slowpath start 539 */ 540 u16 num_cons; 541 u16 num_tasks; 542 543 /* The following parameters are used during protocol-init */ 544 u16 half_way_close_timeout; 545 u16 bdq_xoff_threshold[3]; 546 u16 bdq_xon_threshold[3]; 547 u16 cmdq_xoff_threshold; 548 u16 cmdq_xon_threshold; 549 u16 rq_buffer_size; 550 551 u8 num_sq_pages_in_ring; 552 u8 num_r2tq_pages_in_ring; 553 u8 num_uhq_pages_in_ring; 554 u8 num_queues; 555 u8 log_page_size; 556 u8 rqe_log_size; 557 u8 max_fin_rt; 558 u8 gl_rq_pi; 559 u8 gl_cmd_pi; 560 u8 debug_mode; 561 u8 ll2_ooo_queue_id; 562 563 u8 is_target; 564 u8 is_soc_en; 565 u8 soc_num_of_blocks_log; 566 u8 bdq_pbl_num_entries[3]; 567 }; 568 569 struct qed_rdma_pf_params { 570 /* Supplied to QED during resource allocation (may affect the ILT and 571 * the doorbell BAR). 572 */ 573 u32 min_dpis; /* number of requested DPIs */ 574 u32 num_qps; /* number of requested Queue Pairs */ 575 u32 num_srqs; /* number of requested SRQ */ 576 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */ 577 u8 gl_pi; /* protocol index */ 578 579 /* Will allocate rate limiters to be used with QPs */ 580 u8 enable_dcqcn; 581 }; 582 583 struct qed_pf_params { 584 struct qed_eth_pf_params eth_pf_params; 585 struct qed_fcoe_pf_params fcoe_pf_params; 586 struct qed_iscsi_pf_params iscsi_pf_params; 587 struct qed_rdma_pf_params rdma_pf_params; 588 }; 589 590 enum qed_int_mode { 591 QED_INT_MODE_INTA, 592 QED_INT_MODE_MSIX, 593 QED_INT_MODE_MSI, 594 QED_INT_MODE_POLL, 595 }; 596 597 struct qed_sb_info { 598 struct status_block_e4 *sb_virt; 599 dma_addr_t sb_phys; 600 u32 sb_ack; /* Last given ack */ 601 u16 igu_sb_id; 602 void __iomem *igu_addr; 603 u8 flags; 604 #define QED_SB_INFO_INIT 0x1 605 #define QED_SB_INFO_SETUP 0x2 606 607 struct qed_dev *cdev; 608 }; 609 610 enum qed_hw_err_type { 611 QED_HW_ERR_FAN_FAIL, 612 QED_HW_ERR_MFW_RESP_FAIL, 613 QED_HW_ERR_HW_ATTN, 614 QED_HW_ERR_DMAE_FAIL, 615 QED_HW_ERR_RAMROD_FAIL, 616 QED_HW_ERR_FW_ASSERT, 617 QED_HW_ERR_LAST, 618 }; 619 620 enum qed_dev_type { 621 QED_DEV_TYPE_BB, 622 QED_DEV_TYPE_AH, 623 }; 624 625 struct qed_dev_info { 626 unsigned long pci_mem_start; 627 unsigned long pci_mem_end; 628 unsigned int pci_irq; 629 u8 num_hwfns; 630 631 u8 hw_mac[ETH_ALEN]; 632 633 /* FW version */ 634 u16 fw_major; 635 u16 fw_minor; 636 u16 fw_rev; 637 u16 fw_eng; 638 639 /* MFW version */ 640 u32 mfw_rev; 641 #define QED_MFW_VERSION_0_MASK 0x000000FF 642 #define QED_MFW_VERSION_0_OFFSET 0 643 #define QED_MFW_VERSION_1_MASK 0x0000FF00 644 #define QED_MFW_VERSION_1_OFFSET 8 645 #define QED_MFW_VERSION_2_MASK 0x00FF0000 646 #define QED_MFW_VERSION_2_OFFSET 16 647 #define QED_MFW_VERSION_3_MASK 0xFF000000 648 #define QED_MFW_VERSION_3_OFFSET 24 649 650 u32 flash_size; 651 bool b_inter_pf_switch; 652 bool tx_switching; 653 bool rdma_supported; 654 u16 mtu; 655 656 bool wol_support; 657 bool smart_an; 658 659 /* MBI version */ 660 u32 mbi_version; 661 #define QED_MBI_VERSION_0_MASK 0x000000FF 662 #define QED_MBI_VERSION_0_OFFSET 0 663 #define QED_MBI_VERSION_1_MASK 0x0000FF00 664 #define QED_MBI_VERSION_1_OFFSET 8 665 #define QED_MBI_VERSION_2_MASK 0x00FF0000 666 #define QED_MBI_VERSION_2_OFFSET 16 667 668 enum qed_dev_type dev_type; 669 670 /* Output parameters for qede */ 671 bool vxlan_enable; 672 bool gre_enable; 673 bool geneve_enable; 674 675 u8 abs_pf_id; 676 }; 677 678 enum qed_sb_type { 679 QED_SB_TYPE_L2_QUEUE, 680 QED_SB_TYPE_CNQ, 681 QED_SB_TYPE_STORAGE, 682 }; 683 684 enum qed_protocol { 685 QED_PROTOCOL_ETH, 686 QED_PROTOCOL_ISCSI, 687 QED_PROTOCOL_FCOE, 688 }; 689 690 enum qed_link_mode_bits { 691 QED_LM_FIBRE_BIT = BIT(0), 692 QED_LM_Autoneg_BIT = BIT(1), 693 QED_LM_Asym_Pause_BIT = BIT(2), 694 QED_LM_Pause_BIT = BIT(3), 695 QED_LM_1000baseT_Full_BIT = BIT(4), 696 QED_LM_10000baseT_Full_BIT = BIT(5), 697 QED_LM_10000baseKR_Full_BIT = BIT(6), 698 QED_LM_20000baseKR2_Full_BIT = BIT(7), 699 QED_LM_25000baseKR_Full_BIT = BIT(8), 700 QED_LM_40000baseLR4_Full_BIT = BIT(9), 701 QED_LM_50000baseKR2_Full_BIT = BIT(10), 702 QED_LM_100000baseKR4_Full_BIT = BIT(11), 703 QED_LM_TP_BIT = BIT(12), 704 QED_LM_Backplane_BIT = BIT(13), 705 QED_LM_1000baseKX_Full_BIT = BIT(14), 706 QED_LM_10000baseKX4_Full_BIT = BIT(15), 707 QED_LM_10000baseR_FEC_BIT = BIT(16), 708 QED_LM_40000baseKR4_Full_BIT = BIT(17), 709 QED_LM_40000baseCR4_Full_BIT = BIT(18), 710 QED_LM_40000baseSR4_Full_BIT = BIT(19), 711 QED_LM_25000baseCR_Full_BIT = BIT(20), 712 QED_LM_25000baseSR_Full_BIT = BIT(21), 713 QED_LM_50000baseCR2_Full_BIT = BIT(22), 714 QED_LM_100000baseSR4_Full_BIT = BIT(23), 715 QED_LM_100000baseCR4_Full_BIT = BIT(24), 716 QED_LM_100000baseLR4_ER4_Full_BIT = BIT(25), 717 QED_LM_50000baseSR2_Full_BIT = BIT(26), 718 QED_LM_1000baseX_Full_BIT = BIT(27), 719 QED_LM_10000baseCR_Full_BIT = BIT(28), 720 QED_LM_10000baseSR_Full_BIT = BIT(29), 721 QED_LM_10000baseLR_Full_BIT = BIT(30), 722 QED_LM_10000baseLRM_Full_BIT = BIT(31), 723 QED_LM_COUNT = 32 724 }; 725 726 struct qed_link_params { 727 bool link_up; 728 729 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0) 730 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1) 731 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2) 732 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3) 733 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4) 734 #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5) 735 u32 override_flags; 736 bool autoneg; 737 u32 adv_speeds; 738 u32 forced_speed; 739 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0) 740 #define QED_LINK_PAUSE_RX_ENABLE BIT(1) 741 #define QED_LINK_PAUSE_TX_ENABLE BIT(2) 742 u32 pause_config; 743 #define QED_LINK_LOOPBACK_NONE BIT(0) 744 #define QED_LINK_LOOPBACK_INT_PHY BIT(1) 745 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2) 746 #define QED_LINK_LOOPBACK_EXT BIT(3) 747 #define QED_LINK_LOOPBACK_MAC BIT(4) 748 u32 loopback_mode; 749 struct qed_link_eee_params eee; 750 }; 751 752 struct qed_link_output { 753 bool link_up; 754 755 /* In QED_LM_* defs */ 756 u32 supported_caps; 757 u32 advertised_caps; 758 u32 lp_caps; 759 760 u32 speed; /* In Mb/s */ 761 u8 duplex; /* In DUPLEX defs */ 762 u8 port; /* In PORT defs */ 763 bool autoneg; 764 u32 pause_config; 765 766 /* EEE - capability & param */ 767 bool eee_supported; 768 bool eee_active; 769 u8 sup_caps; 770 struct qed_link_eee_params eee; 771 }; 772 773 struct qed_probe_params { 774 enum qed_protocol protocol; 775 u32 dp_module; 776 u8 dp_level; 777 bool is_vf; 778 bool recov_in_prog; 779 }; 780 781 #define QED_DRV_VER_STR_SIZE 12 782 struct qed_slowpath_params { 783 u32 int_mode; 784 u8 drv_major; 785 u8 drv_minor; 786 u8 drv_rev; 787 u8 drv_eng; 788 u8 name[QED_DRV_VER_STR_SIZE]; 789 }; 790 791 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */ 792 793 struct qed_int_info { 794 struct msix_entry *msix; 795 u8 msix_cnt; 796 797 /* This should be updated by the protocol driver */ 798 u8 used_cnt; 799 }; 800 801 struct qed_generic_tlvs { 802 #define QED_TLV_IP_CSUM BIT(0) 803 #define QED_TLV_LSO BIT(1) 804 u16 feat_flags; 805 #define QED_TLV_MAC_COUNT 3 806 u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN]; 807 }; 808 809 #define QED_I2C_DEV_ADDR_A0 0xA0 810 #define QED_I2C_DEV_ADDR_A2 0xA2 811 812 #define QED_NVM_SIGNATURE 0x12435687 813 814 enum qed_nvm_flash_cmd { 815 QED_NVM_FLASH_CMD_FILE_DATA = 0x2, 816 QED_NVM_FLASH_CMD_FILE_START = 0x3, 817 QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4, 818 QED_NVM_FLASH_CMD_NVM_CFG_ID = 0x5, 819 QED_NVM_FLASH_CMD_NVM_MAX, 820 }; 821 822 struct qed_common_cb_ops { 823 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc); 824 void (*link_update)(void *dev, struct qed_link_output *link); 825 void (*schedule_recovery_handler)(void *dev); 826 void (*schedule_hw_err_handler)(void *dev, 827 enum qed_hw_err_type err_type); 828 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type); 829 void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data); 830 void (*get_protocol_tlv_data)(void *dev, void *data); 831 }; 832 833 struct qed_selftest_ops { 834 /** 835 * @brief selftest_interrupt - Perform interrupt test 836 * 837 * @param cdev 838 * 839 * @return 0 on success, error otherwise. 840 */ 841 int (*selftest_interrupt)(struct qed_dev *cdev); 842 843 /** 844 * @brief selftest_memory - Perform memory test 845 * 846 * @param cdev 847 * 848 * @return 0 on success, error otherwise. 849 */ 850 int (*selftest_memory)(struct qed_dev *cdev); 851 852 /** 853 * @brief selftest_register - Perform register test 854 * 855 * @param cdev 856 * 857 * @return 0 on success, error otherwise. 858 */ 859 int (*selftest_register)(struct qed_dev *cdev); 860 861 /** 862 * @brief selftest_clock - Perform clock test 863 * 864 * @param cdev 865 * 866 * @return 0 on success, error otherwise. 867 */ 868 int (*selftest_clock)(struct qed_dev *cdev); 869 870 /** 871 * @brief selftest_nvram - Perform nvram test 872 * 873 * @param cdev 874 * 875 * @return 0 on success, error otherwise. 876 */ 877 int (*selftest_nvram) (struct qed_dev *cdev); 878 }; 879 880 struct qed_common_ops { 881 struct qed_selftest_ops *selftest; 882 883 struct qed_dev* (*probe)(struct pci_dev *dev, 884 struct qed_probe_params *params); 885 886 void (*remove)(struct qed_dev *cdev); 887 888 int (*set_power_state)(struct qed_dev *cdev, 889 pci_power_t state); 890 891 void (*set_name) (struct qed_dev *cdev, char name[]); 892 893 /* Client drivers need to make this call before slowpath_start. 894 * PF params required for the call before slowpath_start is 895 * documented within the qed_pf_params structure definition. 896 */ 897 void (*update_pf_params)(struct qed_dev *cdev, 898 struct qed_pf_params *params); 899 int (*slowpath_start)(struct qed_dev *cdev, 900 struct qed_slowpath_params *params); 901 902 int (*slowpath_stop)(struct qed_dev *cdev); 903 904 /* Requests to use `cnt' interrupts for fastpath. 905 * upon success, returns number of interrupts allocated for fastpath. 906 */ 907 int (*set_fp_int)(struct qed_dev *cdev, 908 u16 cnt); 909 910 /* Fills `info' with pointers required for utilizing interrupts */ 911 int (*get_fp_int)(struct qed_dev *cdev, 912 struct qed_int_info *info); 913 914 u32 (*sb_init)(struct qed_dev *cdev, 915 struct qed_sb_info *sb_info, 916 void *sb_virt_addr, 917 dma_addr_t sb_phy_addr, 918 u16 sb_id, 919 enum qed_sb_type type); 920 921 u32 (*sb_release)(struct qed_dev *cdev, 922 struct qed_sb_info *sb_info, 923 u16 sb_id, 924 enum qed_sb_type type); 925 926 void (*simd_handler_config)(struct qed_dev *cdev, 927 void *token, 928 int index, 929 void (*handler)(void *)); 930 931 void (*simd_handler_clean)(struct qed_dev *cdev, 932 int index); 933 int (*dbg_grc)(struct qed_dev *cdev, 934 void *buffer, u32 *num_dumped_bytes); 935 936 int (*dbg_grc_size)(struct qed_dev *cdev); 937 938 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer); 939 940 int (*dbg_all_data_size) (struct qed_dev *cdev); 941 942 /** 943 * @brief can_link_change - can the instance change the link or not 944 * 945 * @param cdev 946 * 947 * @return true if link-change is allowed, false otherwise. 948 */ 949 bool (*can_link_change)(struct qed_dev *cdev); 950 951 /** 952 * @brief set_link - set links according to params 953 * 954 * @param cdev 955 * @param params - values used to override the default link configuration 956 * 957 * @return 0 on success, error otherwise. 958 */ 959 int (*set_link)(struct qed_dev *cdev, 960 struct qed_link_params *params); 961 962 /** 963 * @brief get_link - returns the current link state. 964 * 965 * @param cdev 966 * @param if_link - structure to be filled with current link configuration. 967 */ 968 void (*get_link)(struct qed_dev *cdev, 969 struct qed_link_output *if_link); 970 971 /** 972 * @brief - drains chip in case Tx completions fail to arrive due to pause. 973 * 974 * @param cdev 975 */ 976 int (*drain)(struct qed_dev *cdev); 977 978 /** 979 * @brief update_msglvl - update module debug level 980 * 981 * @param cdev 982 * @param dp_module 983 * @param dp_level 984 */ 985 void (*update_msglvl)(struct qed_dev *cdev, 986 u32 dp_module, 987 u8 dp_level); 988 989 int (*chain_alloc)(struct qed_dev *cdev, 990 enum qed_chain_use_mode intended_use, 991 enum qed_chain_mode mode, 992 enum qed_chain_cnt_type cnt_type, 993 u32 num_elems, 994 size_t elem_size, 995 struct qed_chain *p_chain, 996 struct qed_chain_ext_pbl *ext_pbl); 997 998 void (*chain_free)(struct qed_dev *cdev, 999 struct qed_chain *p_chain); 1000 1001 /** 1002 * @brief nvm_flash - Flash nvm data. 1003 * 1004 * @param cdev 1005 * @param name - file containing the data 1006 * 1007 * @return 0 on success, error otherwise. 1008 */ 1009 int (*nvm_flash)(struct qed_dev *cdev, const char *name); 1010 1011 /** 1012 * @brief nvm_get_image - reads an entire image from nvram 1013 * 1014 * @param cdev 1015 * @param type - type of the request nvram image 1016 * @param buf - preallocated buffer to fill with the image 1017 * @param len - length of the allocated buffer 1018 * 1019 * @return 0 on success, error otherwise 1020 */ 1021 int (*nvm_get_image)(struct qed_dev *cdev, 1022 enum qed_nvm_images type, u8 *buf, u16 len); 1023 1024 /** 1025 * @brief set_coalesce - Configure Rx coalesce value in usec 1026 * 1027 * @param cdev 1028 * @param rx_coal - Rx coalesce value in usec 1029 * @param tx_coal - Tx coalesce value in usec 1030 * @param qid - Queue index 1031 * @param sb_id - Status Block Id 1032 * 1033 * @return 0 on success, error otherwise. 1034 */ 1035 int (*set_coalesce)(struct qed_dev *cdev, 1036 u16 rx_coal, u16 tx_coal, void *handle); 1037 1038 /** 1039 * @brief set_led - Configure LED mode 1040 * 1041 * @param cdev 1042 * @param mode - LED mode 1043 * 1044 * @return 0 on success, error otherwise. 1045 */ 1046 int (*set_led)(struct qed_dev *cdev, 1047 enum qed_led_mode mode); 1048 1049 /** 1050 * @brief attn_clr_enable - Prevent attentions from being reasserted 1051 * 1052 * @param cdev 1053 * @param clr_enable 1054 */ 1055 void (*attn_clr_enable)(struct qed_dev *cdev, bool clr_enable); 1056 1057 /** 1058 * @brief db_recovery_add - add doorbell information to the doorbell 1059 * recovery mechanism. 1060 * 1061 * @param cdev 1062 * @param db_addr - doorbell address 1063 * @param db_data - address of where db_data is stored 1064 * @param db_is_32b - doorbell is 32b pr 64b 1065 * @param db_is_user - doorbell recovery addresses are user or kernel space 1066 */ 1067 int (*db_recovery_add)(struct qed_dev *cdev, 1068 void __iomem *db_addr, 1069 void *db_data, 1070 enum qed_db_rec_width db_width, 1071 enum qed_db_rec_space db_space); 1072 1073 /** 1074 * @brief db_recovery_del - remove doorbell information from the doorbell 1075 * recovery mechanism. db_data serves as key (db_addr is not unique). 1076 * 1077 * @param cdev 1078 * @param db_addr - doorbell address 1079 * @param db_data - address where db_data is stored. Serves as key for the 1080 * entry to delete. 1081 */ 1082 int (*db_recovery_del)(struct qed_dev *cdev, 1083 void __iomem *db_addr, void *db_data); 1084 1085 /** 1086 * @brief recovery_process - Trigger a recovery process 1087 * 1088 * @param cdev 1089 * 1090 * @return 0 on success, error otherwise. 1091 */ 1092 int (*recovery_process)(struct qed_dev *cdev); 1093 1094 /** 1095 * @brief recovery_prolog - Execute the prolog operations of a recovery process 1096 * 1097 * @param cdev 1098 * 1099 * @return 0 on success, error otherwise. 1100 */ 1101 int (*recovery_prolog)(struct qed_dev *cdev); 1102 1103 /** 1104 * @brief update_drv_state - API to inform the change in the driver state. 1105 * 1106 * @param cdev 1107 * @param active 1108 * 1109 */ 1110 int (*update_drv_state)(struct qed_dev *cdev, bool active); 1111 1112 /** 1113 * @brief update_mac - API to inform the change in the mac address 1114 * 1115 * @param cdev 1116 * @param mac 1117 * 1118 */ 1119 int (*update_mac)(struct qed_dev *cdev, u8 *mac); 1120 1121 /** 1122 * @brief update_mtu - API to inform the change in the mtu 1123 * 1124 * @param cdev 1125 * @param mtu 1126 * 1127 */ 1128 int (*update_mtu)(struct qed_dev *cdev, u16 mtu); 1129 1130 /** 1131 * @brief update_wol - update of changes in the WoL configuration 1132 * 1133 * @param cdev 1134 * @param enabled - true iff WoL should be enabled. 1135 */ 1136 int (*update_wol) (struct qed_dev *cdev, bool enabled); 1137 1138 /** 1139 * @brief read_module_eeprom 1140 * 1141 * @param cdev 1142 * @param buf - buffer 1143 * @param dev_addr - PHY device memory region 1144 * @param offset - offset into eeprom contents to be read 1145 * @param len - buffer length, i.e., max bytes to be read 1146 */ 1147 int (*read_module_eeprom)(struct qed_dev *cdev, 1148 char *buf, u8 dev_addr, u32 offset, u32 len); 1149 1150 /** 1151 * @brief get_affin_hwfn_idx 1152 * 1153 * @param cdev 1154 */ 1155 u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev); 1156 1157 /** 1158 * @brief read_nvm_cfg - Read NVM config attribute value. 1159 * @param cdev 1160 * @param buf - buffer 1161 * @param cmd - NVM CFG command id 1162 * @param entity_id - Entity id 1163 * 1164 */ 1165 int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd, 1166 u32 entity_id); 1167 /** 1168 * @brief read_nvm_cfg - Read NVM config attribute value. 1169 * @param cdev 1170 * @param cmd - NVM CFG command id 1171 * 1172 * @return config id length, 0 on error. 1173 */ 1174 int (*read_nvm_cfg_len)(struct qed_dev *cdev, u32 cmd); 1175 1176 /** 1177 * @brief set_grc_config - Configure value for grc config id. 1178 * @param cdev 1179 * @param cfg_id - grc config id 1180 * @param val - grc config value 1181 * 1182 */ 1183 int (*set_grc_config)(struct qed_dev *cdev, u32 cfg_id, u32 val); 1184 }; 1185 1186 #define MASK_FIELD(_name, _value) \ 1187 ((_value) &= (_name ## _MASK)) 1188 1189 #define FIELD_VALUE(_name, _value) \ 1190 ((_value & _name ## _MASK) << _name ## _SHIFT) 1191 1192 #define SET_FIELD(value, name, flag) \ 1193 do { \ 1194 (value) &= ~(name ## _MASK << name ## _SHIFT); \ 1195 (value) |= (((u64)flag) << (name ## _SHIFT)); \ 1196 } while (0) 1197 1198 #define GET_FIELD(value, name) \ 1199 (((value) >> (name ## _SHIFT)) & name ## _MASK) 1200 1201 #define GET_MFW_FIELD(name, field) \ 1202 (((name) & (field ## _MASK)) >> (field ## _OFFSET)) 1203 1204 #define SET_MFW_FIELD(name, field, value) \ 1205 do { \ 1206 (name) &= ~(field ## _MASK); \ 1207 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK));\ 1208 } while (0) 1209 1210 #define DB_ADDR_SHIFT(addr) ((addr) << DB_PWM_ADDR_OFFSET_SHIFT) 1211 1212 /* Debug print definitions */ 1213 #define DP_ERR(cdev, fmt, ...) \ 1214 do { \ 1215 pr_err("[%s:%d(%s)]" fmt, \ 1216 __func__, __LINE__, \ 1217 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 1218 ## __VA_ARGS__); \ 1219 } while (0) 1220 1221 #define DP_NOTICE(cdev, fmt, ...) \ 1222 do { \ 1223 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \ 1224 pr_notice("[%s:%d(%s)]" fmt, \ 1225 __func__, __LINE__, \ 1226 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 1227 ## __VA_ARGS__); \ 1228 \ 1229 } \ 1230 } while (0) 1231 1232 #define DP_INFO(cdev, fmt, ...) \ 1233 do { \ 1234 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \ 1235 pr_notice("[%s:%d(%s)]" fmt, \ 1236 __func__, __LINE__, \ 1237 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 1238 ## __VA_ARGS__); \ 1239 } \ 1240 } while (0) 1241 1242 #define DP_VERBOSE(cdev, module, fmt, ...) \ 1243 do { \ 1244 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \ 1245 ((cdev)->dp_module & module))) { \ 1246 pr_notice("[%s:%d(%s)]" fmt, \ 1247 __func__, __LINE__, \ 1248 DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 1249 ## __VA_ARGS__); \ 1250 } \ 1251 } while (0) 1252 1253 enum DP_LEVEL { 1254 QED_LEVEL_VERBOSE = 0x0, 1255 QED_LEVEL_INFO = 0x1, 1256 QED_LEVEL_NOTICE = 0x2, 1257 QED_LEVEL_ERR = 0x3, 1258 }; 1259 1260 #define QED_LOG_LEVEL_SHIFT (30) 1261 #define QED_LOG_VERBOSE_MASK (0x3fffffff) 1262 #define QED_LOG_INFO_MASK (0x40000000) 1263 #define QED_LOG_NOTICE_MASK (0x80000000) 1264 1265 enum DP_MODULE { 1266 QED_MSG_SPQ = 0x10000, 1267 QED_MSG_STATS = 0x20000, 1268 QED_MSG_DCB = 0x40000, 1269 QED_MSG_IOV = 0x80000, 1270 QED_MSG_SP = 0x100000, 1271 QED_MSG_STORAGE = 0x200000, 1272 QED_MSG_CXT = 0x800000, 1273 QED_MSG_LL2 = 0x1000000, 1274 QED_MSG_ILT = 0x2000000, 1275 QED_MSG_RDMA = 0x4000000, 1276 QED_MSG_DEBUG = 0x8000000, 1277 /* to be added...up to 0x8000000 */ 1278 }; 1279 1280 enum qed_mf_mode { 1281 QED_MF_DEFAULT, 1282 QED_MF_OVLAN, 1283 QED_MF_NPAR, 1284 }; 1285 1286 struct qed_eth_stats_common { 1287 u64 no_buff_discards; 1288 u64 packet_too_big_discard; 1289 u64 ttl0_discard; 1290 u64 rx_ucast_bytes; 1291 u64 rx_mcast_bytes; 1292 u64 rx_bcast_bytes; 1293 u64 rx_ucast_pkts; 1294 u64 rx_mcast_pkts; 1295 u64 rx_bcast_pkts; 1296 u64 mftag_filter_discards; 1297 u64 mac_filter_discards; 1298 u64 gft_filter_drop; 1299 u64 tx_ucast_bytes; 1300 u64 tx_mcast_bytes; 1301 u64 tx_bcast_bytes; 1302 u64 tx_ucast_pkts; 1303 u64 tx_mcast_pkts; 1304 u64 tx_bcast_pkts; 1305 u64 tx_err_drop_pkts; 1306 u64 tpa_coalesced_pkts; 1307 u64 tpa_coalesced_events; 1308 u64 tpa_aborts_num; 1309 u64 tpa_not_coalesced_pkts; 1310 u64 tpa_coalesced_bytes; 1311 1312 /* port */ 1313 u64 rx_64_byte_packets; 1314 u64 rx_65_to_127_byte_packets; 1315 u64 rx_128_to_255_byte_packets; 1316 u64 rx_256_to_511_byte_packets; 1317 u64 rx_512_to_1023_byte_packets; 1318 u64 rx_1024_to_1518_byte_packets; 1319 u64 rx_crc_errors; 1320 u64 rx_mac_crtl_frames; 1321 u64 rx_pause_frames; 1322 u64 rx_pfc_frames; 1323 u64 rx_align_errors; 1324 u64 rx_carrier_errors; 1325 u64 rx_oversize_packets; 1326 u64 rx_jabbers; 1327 u64 rx_undersize_packets; 1328 u64 rx_fragments; 1329 u64 tx_64_byte_packets; 1330 u64 tx_65_to_127_byte_packets; 1331 u64 tx_128_to_255_byte_packets; 1332 u64 tx_256_to_511_byte_packets; 1333 u64 tx_512_to_1023_byte_packets; 1334 u64 tx_1024_to_1518_byte_packets; 1335 u64 tx_pause_frames; 1336 u64 tx_pfc_frames; 1337 u64 brb_truncates; 1338 u64 brb_discards; 1339 u64 rx_mac_bytes; 1340 u64 rx_mac_uc_packets; 1341 u64 rx_mac_mc_packets; 1342 u64 rx_mac_bc_packets; 1343 u64 rx_mac_frames_ok; 1344 u64 tx_mac_bytes; 1345 u64 tx_mac_uc_packets; 1346 u64 tx_mac_mc_packets; 1347 u64 tx_mac_bc_packets; 1348 u64 tx_mac_ctrl_frames; 1349 u64 link_change_count; 1350 }; 1351 1352 struct qed_eth_stats_bb { 1353 u64 rx_1519_to_1522_byte_packets; 1354 u64 rx_1519_to_2047_byte_packets; 1355 u64 rx_2048_to_4095_byte_packets; 1356 u64 rx_4096_to_9216_byte_packets; 1357 u64 rx_9217_to_16383_byte_packets; 1358 u64 tx_1519_to_2047_byte_packets; 1359 u64 tx_2048_to_4095_byte_packets; 1360 u64 tx_4096_to_9216_byte_packets; 1361 u64 tx_9217_to_16383_byte_packets; 1362 u64 tx_lpi_entry_count; 1363 u64 tx_total_collisions; 1364 }; 1365 1366 struct qed_eth_stats_ah { 1367 u64 rx_1519_to_max_byte_packets; 1368 u64 tx_1519_to_max_byte_packets; 1369 }; 1370 1371 struct qed_eth_stats { 1372 struct qed_eth_stats_common common; 1373 1374 union { 1375 struct qed_eth_stats_bb bb; 1376 struct qed_eth_stats_ah ah; 1377 }; 1378 }; 1379 1380 #define QED_SB_IDX 0x0002 1381 1382 #define RX_PI 0 1383 #define TX_PI(tc) (RX_PI + 1 + tc) 1384 1385 struct qed_sb_cnt_info { 1386 /* Original, current, and free SBs for PF */ 1387 int orig; 1388 int cnt; 1389 int free_cnt; 1390 1391 /* Original, current and free SBS for child VFs */ 1392 int iov_orig; 1393 int iov_cnt; 1394 int free_cnt_iov; 1395 }; 1396 1397 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info) 1398 { 1399 u32 prod = 0; 1400 u16 rc = 0; 1401 1402 prod = le32_to_cpu(sb_info->sb_virt->prod_index) & 1403 STATUS_BLOCK_E4_PROD_INDEX_MASK; 1404 if (sb_info->sb_ack != prod) { 1405 sb_info->sb_ack = prod; 1406 rc |= QED_SB_IDX; 1407 } 1408 1409 /* Let SB update */ 1410 return rc; 1411 } 1412 1413 /** 1414 * 1415 * @brief This function creates an update command for interrupts that is 1416 * written to the IGU. 1417 * 1418 * @param sb_info - This is the structure allocated and 1419 * initialized per status block. Assumption is 1420 * that it was initialized using qed_sb_init 1421 * @param int_cmd - Enable/Disable/Nop 1422 * @param upd_flg - whether igu consumer should be 1423 * updated. 1424 * 1425 * @return inline void 1426 */ 1427 static inline void qed_sb_ack(struct qed_sb_info *sb_info, 1428 enum igu_int_cmd int_cmd, 1429 u8 upd_flg) 1430 { 1431 struct igu_prod_cons_update igu_ack = { 0 }; 1432 1433 igu_ack.sb_id_and_flags = 1434 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 1435 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 1436 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 1437 (IGU_SEG_ACCESS_REG << 1438 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 1439 1440 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags); 1441 1442 /* Both segments (interrupts & acks) are written to same place address; 1443 * Need to guarantee all commands will be received (in-order) by HW. 1444 */ 1445 barrier(); 1446 } 1447 1448 static inline void __internal_ram_wr(void *p_hwfn, 1449 void __iomem *addr, 1450 int size, 1451 u32 *data) 1452 1453 { 1454 unsigned int i; 1455 1456 for (i = 0; i < size / sizeof(*data); i++) 1457 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]); 1458 } 1459 1460 static inline void internal_ram_wr(void __iomem *addr, 1461 int size, 1462 u32 *data) 1463 { 1464 __internal_ram_wr(NULL, addr, size, data); 1465 } 1466 1467 enum qed_rss_caps { 1468 QED_RSS_IPV4 = 0x1, 1469 QED_RSS_IPV6 = 0x2, 1470 QED_RSS_IPV4_TCP = 0x4, 1471 QED_RSS_IPV6_TCP = 0x8, 1472 QED_RSS_IPV4_UDP = 0x10, 1473 QED_RSS_IPV6_UDP = 0x20, 1474 }; 1475 1476 #define QED_RSS_IND_TABLE_SIZE 128 1477 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */ 1478 #endif 1479