xref: /linux/include/linux/qed/qed_if.h (revision a91eb52abb504a1dd3248a5d07b54e7f95d5fcf1)
1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver
2fe56b9e6SYuval Mintz  *
3fe56b9e6SYuval Mintz  * Copyright (c) 2015 QLogic Corporation
4fe56b9e6SYuval Mintz  *
5fe56b9e6SYuval Mintz  * This software is available under the terms of the GNU General Public License
6fe56b9e6SYuval Mintz  * (GPL) Version 2, available from the file COPYING in the main directory of
7fe56b9e6SYuval Mintz  * this source tree.
8fe56b9e6SYuval Mintz  */
9fe56b9e6SYuval Mintz 
10fe56b9e6SYuval Mintz #ifndef _QED_IF_H
11fe56b9e6SYuval Mintz #define _QED_IF_H
12fe56b9e6SYuval Mintz 
13fe56b9e6SYuval Mintz #include <linux/types.h>
14fe56b9e6SYuval Mintz #include <linux/interrupt.h>
15fe56b9e6SYuval Mintz #include <linux/netdevice.h>
16fe56b9e6SYuval Mintz #include <linux/pci.h>
17fe56b9e6SYuval Mintz #include <linux/skbuff.h>
18fe56b9e6SYuval Mintz #include <linux/types.h>
19fe56b9e6SYuval Mintz #include <asm/byteorder.h>
20fe56b9e6SYuval Mintz #include <linux/io.h>
21fe56b9e6SYuval Mintz #include <linux/compiler.h>
22fe56b9e6SYuval Mintz #include <linux/kernel.h>
23fe56b9e6SYuval Mintz #include <linux/list.h>
24fe56b9e6SYuval Mintz #include <linux/slab.h>
25fe56b9e6SYuval Mintz #include <linux/qed/common_hsi.h>
26fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h>
27fe56b9e6SYuval Mintz 
2839651abdSSudarsana Reddy Kalluru enum dcbx_protocol_type {
2939651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_ISCSI,
3039651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_FCOE,
3139651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_ROCE,
3239651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_ROCE_V2,
3339651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_ETH,
3439651abdSSudarsana Reddy Kalluru 	DCBX_MAX_PROTOCOL_TYPE
3539651abdSSudarsana Reddy Kalluru };
3639651abdSSudarsana Reddy Kalluru 
3791420b83SSudarsana Kalluru enum qed_led_mode {
3891420b83SSudarsana Kalluru 	QED_LED_MODE_OFF,
3991420b83SSudarsana Kalluru 	QED_LED_MODE_ON,
4091420b83SSudarsana Kalluru 	QED_LED_MODE_RESTORE
4191420b83SSudarsana Kalluru };
4291420b83SSudarsana Kalluru 
43fe56b9e6SYuval Mintz #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
44fe56b9e6SYuval Mintz 					    (void __iomem *)(reg_addr))
45fe56b9e6SYuval Mintz 
46fe56b9e6SYuval Mintz #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
47fe56b9e6SYuval Mintz 
48fe56b9e6SYuval Mintz #define QED_COALESCE_MAX 0xFF
49fe56b9e6SYuval Mintz 
50fe56b9e6SYuval Mintz /* forward */
51fe56b9e6SYuval Mintz struct qed_dev;
52fe56b9e6SYuval Mintz 
53fe56b9e6SYuval Mintz struct qed_eth_pf_params {
54fe56b9e6SYuval Mintz 	/* The following parameters are used during HW-init
55fe56b9e6SYuval Mintz 	 * and these parameters need to be passed as arguments
56fe56b9e6SYuval Mintz 	 * to update_pf_params routine invoked before slowpath start
57fe56b9e6SYuval Mintz 	 */
58fe56b9e6SYuval Mintz 	u16 num_cons;
59fe56b9e6SYuval Mintz };
60fe56b9e6SYuval Mintz 
61fe56b9e6SYuval Mintz struct qed_pf_params {
62fe56b9e6SYuval Mintz 	struct qed_eth_pf_params eth_pf_params;
63fe56b9e6SYuval Mintz };
64fe56b9e6SYuval Mintz 
65fe56b9e6SYuval Mintz enum qed_int_mode {
66fe56b9e6SYuval Mintz 	QED_INT_MODE_INTA,
67fe56b9e6SYuval Mintz 	QED_INT_MODE_MSIX,
68fe56b9e6SYuval Mintz 	QED_INT_MODE_MSI,
69fe56b9e6SYuval Mintz 	QED_INT_MODE_POLL,
70fe56b9e6SYuval Mintz };
71fe56b9e6SYuval Mintz 
72fe56b9e6SYuval Mintz struct qed_sb_info {
73fe56b9e6SYuval Mintz 	struct status_block	*sb_virt;
74fe56b9e6SYuval Mintz 	dma_addr_t		sb_phys;
75fe56b9e6SYuval Mintz 	u32			sb_ack; /* Last given ack */
76fe56b9e6SYuval Mintz 	u16			igu_sb_id;
77fe56b9e6SYuval Mintz 	void __iomem		*igu_addr;
78fe56b9e6SYuval Mintz 	u8			flags;
79fe56b9e6SYuval Mintz #define QED_SB_INFO_INIT        0x1
80fe56b9e6SYuval Mintz #define QED_SB_INFO_SETUP       0x2
81fe56b9e6SYuval Mintz 
82fe56b9e6SYuval Mintz 	struct qed_dev		*cdev;
83fe56b9e6SYuval Mintz };
84fe56b9e6SYuval Mintz 
85fe56b9e6SYuval Mintz struct qed_dev_info {
86fe56b9e6SYuval Mintz 	unsigned long	pci_mem_start;
87fe56b9e6SYuval Mintz 	unsigned long	pci_mem_end;
88fe56b9e6SYuval Mintz 	unsigned int	pci_irq;
89fe56b9e6SYuval Mintz 	u8		num_hwfns;
90fe56b9e6SYuval Mintz 
91fe56b9e6SYuval Mintz 	u8		hw_mac[ETH_ALEN];
92fc48b7a6SYuval Mintz 	bool		is_mf_default;
93fe56b9e6SYuval Mintz 
94fe56b9e6SYuval Mintz 	/* FW version */
95fe56b9e6SYuval Mintz 	u16		fw_major;
96fe56b9e6SYuval Mintz 	u16		fw_minor;
97fe56b9e6SYuval Mintz 	u16		fw_rev;
98fe56b9e6SYuval Mintz 	u16		fw_eng;
99fe56b9e6SYuval Mintz 
100fe56b9e6SYuval Mintz 	/* MFW version */
101fe56b9e6SYuval Mintz 	u32		mfw_rev;
102fe56b9e6SYuval Mintz 
103fe56b9e6SYuval Mintz 	u32		flash_size;
104fe56b9e6SYuval Mintz 	u8		mf_mode;
105831bfb0eSYuval Mintz 	bool		tx_switching;
106fe56b9e6SYuval Mintz };
107fe56b9e6SYuval Mintz 
108fe56b9e6SYuval Mintz enum qed_sb_type {
109fe56b9e6SYuval Mintz 	QED_SB_TYPE_L2_QUEUE,
110fe56b9e6SYuval Mintz };
111fe56b9e6SYuval Mintz 
112fe56b9e6SYuval Mintz enum qed_protocol {
113fe56b9e6SYuval Mintz 	QED_PROTOCOL_ETH,
114fe56b9e6SYuval Mintz };
115fe56b9e6SYuval Mintz 
116fe56b9e6SYuval Mintz struct qed_link_params {
117fe56b9e6SYuval Mintz 	bool	link_up;
118fe56b9e6SYuval Mintz 
119fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_AUTONEG         BIT(0)
120fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS      BIT(1)
121fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED    BIT(2)
122fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_PAUSE_CONFIG          BIT(3)
12303dc76caSSudarsana Reddy Kalluru #define QED_LINK_OVERRIDE_LOOPBACK_MODE         BIT(4)
124fe56b9e6SYuval Mintz 	u32	override_flags;
125fe56b9e6SYuval Mintz 	bool	autoneg;
126fe56b9e6SYuval Mintz 	u32	adv_speeds;
127fe56b9e6SYuval Mintz 	u32	forced_speed;
128fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_AUTONEG_ENABLE           BIT(0)
129fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_RX_ENABLE                BIT(1)
130fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_TX_ENABLE                BIT(2)
131fe56b9e6SYuval Mintz 	u32	pause_config;
13203dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_NONE                  BIT(0)
13303dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_INT_PHY               BIT(1)
13403dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_EXT_PHY               BIT(2)
13503dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_EXT                   BIT(3)
13603dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_MAC                   BIT(4)
13703dc76caSSudarsana Reddy Kalluru 	u32	loopback_mode;
138fe56b9e6SYuval Mintz };
139fe56b9e6SYuval Mintz 
140fe56b9e6SYuval Mintz struct qed_link_output {
141fe56b9e6SYuval Mintz 	bool	link_up;
142fe56b9e6SYuval Mintz 
143fe56b9e6SYuval Mintz 	u32	supported_caps;         /* In SUPPORTED defs */
144fe56b9e6SYuval Mintz 	u32	advertised_caps;        /* In ADVERTISED defs */
145fe56b9e6SYuval Mintz 	u32	lp_caps;                /* In ADVERTISED defs */
146fe56b9e6SYuval Mintz 	u32	speed;                  /* In Mb/s */
147fe56b9e6SYuval Mintz 	u8	duplex;                 /* In DUPLEX defs */
148fe56b9e6SYuval Mintz 	u8	port;                   /* In PORT defs */
149fe56b9e6SYuval Mintz 	bool	autoneg;
150fe56b9e6SYuval Mintz 	u32	pause_config;
151fe56b9e6SYuval Mintz };
152fe56b9e6SYuval Mintz 
1531408cc1fSYuval Mintz struct qed_probe_params {
1541408cc1fSYuval Mintz 	enum qed_protocol protocol;
1551408cc1fSYuval Mintz 	u32 dp_module;
1561408cc1fSYuval Mintz 	u8 dp_level;
1571408cc1fSYuval Mintz 	bool is_vf;
1581408cc1fSYuval Mintz };
1591408cc1fSYuval Mintz 
160fe56b9e6SYuval Mintz #define QED_DRV_VER_STR_SIZE 12
161fe56b9e6SYuval Mintz struct qed_slowpath_params {
162fe56b9e6SYuval Mintz 	u32	int_mode;
163fe56b9e6SYuval Mintz 	u8	drv_major;
164fe56b9e6SYuval Mintz 	u8	drv_minor;
165fe56b9e6SYuval Mintz 	u8	drv_rev;
166fe56b9e6SYuval Mintz 	u8	drv_eng;
167fe56b9e6SYuval Mintz 	u8	name[QED_DRV_VER_STR_SIZE];
168fe56b9e6SYuval Mintz };
169fe56b9e6SYuval Mintz 
170fe56b9e6SYuval Mintz #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
171fe56b9e6SYuval Mintz 
172fe56b9e6SYuval Mintz struct qed_int_info {
173fe56b9e6SYuval Mintz 	struct msix_entry	*msix;
174fe56b9e6SYuval Mintz 	u8			msix_cnt;
175fe56b9e6SYuval Mintz 
176fe56b9e6SYuval Mintz 	/* This should be updated by the protocol driver */
177fe56b9e6SYuval Mintz 	u8			used_cnt;
178fe56b9e6SYuval Mintz };
179fe56b9e6SYuval Mintz 
180fe56b9e6SYuval Mintz struct qed_common_cb_ops {
181fe56b9e6SYuval Mintz 	void	(*link_update)(void			*dev,
182fe56b9e6SYuval Mintz 			       struct qed_link_output	*link);
183fe56b9e6SYuval Mintz };
184fe56b9e6SYuval Mintz 
18503dc76caSSudarsana Reddy Kalluru struct qed_selftest_ops {
18603dc76caSSudarsana Reddy Kalluru /**
18703dc76caSSudarsana Reddy Kalluru  * @brief selftest_interrupt - Perform interrupt test
18803dc76caSSudarsana Reddy Kalluru  *
18903dc76caSSudarsana Reddy Kalluru  * @param cdev
19003dc76caSSudarsana Reddy Kalluru  *
19103dc76caSSudarsana Reddy Kalluru  * @return 0 on success, error otherwise.
19203dc76caSSudarsana Reddy Kalluru  */
19303dc76caSSudarsana Reddy Kalluru 	int (*selftest_interrupt)(struct qed_dev *cdev);
19403dc76caSSudarsana Reddy Kalluru 
19503dc76caSSudarsana Reddy Kalluru /**
19603dc76caSSudarsana Reddy Kalluru  * @brief selftest_memory - Perform memory test
19703dc76caSSudarsana Reddy Kalluru  *
19803dc76caSSudarsana Reddy Kalluru  * @param cdev
19903dc76caSSudarsana Reddy Kalluru  *
20003dc76caSSudarsana Reddy Kalluru  * @return 0 on success, error otherwise.
20103dc76caSSudarsana Reddy Kalluru  */
20203dc76caSSudarsana Reddy Kalluru 	int (*selftest_memory)(struct qed_dev *cdev);
20303dc76caSSudarsana Reddy Kalluru 
20403dc76caSSudarsana Reddy Kalluru /**
20503dc76caSSudarsana Reddy Kalluru  * @brief selftest_register - Perform register test
20603dc76caSSudarsana Reddy Kalluru  *
20703dc76caSSudarsana Reddy Kalluru  * @param cdev
20803dc76caSSudarsana Reddy Kalluru  *
20903dc76caSSudarsana Reddy Kalluru  * @return 0 on success, error otherwise.
21003dc76caSSudarsana Reddy Kalluru  */
21103dc76caSSudarsana Reddy Kalluru 	int (*selftest_register)(struct qed_dev *cdev);
21203dc76caSSudarsana Reddy Kalluru 
21303dc76caSSudarsana Reddy Kalluru /**
21403dc76caSSudarsana Reddy Kalluru  * @brief selftest_clock - Perform clock test
21503dc76caSSudarsana Reddy Kalluru  *
21603dc76caSSudarsana Reddy Kalluru  * @param cdev
21703dc76caSSudarsana Reddy Kalluru  *
21803dc76caSSudarsana Reddy Kalluru  * @return 0 on success, error otherwise.
21903dc76caSSudarsana Reddy Kalluru  */
22003dc76caSSudarsana Reddy Kalluru 	int (*selftest_clock)(struct qed_dev *cdev);
22103dc76caSSudarsana Reddy Kalluru };
22203dc76caSSudarsana Reddy Kalluru 
223fe56b9e6SYuval Mintz struct qed_common_ops {
22403dc76caSSudarsana Reddy Kalluru 	struct qed_selftest_ops *selftest;
22503dc76caSSudarsana Reddy Kalluru 
226fe56b9e6SYuval Mintz 	struct qed_dev*	(*probe)(struct pci_dev *dev,
2271408cc1fSYuval Mintz 				 struct qed_probe_params *params);
228fe56b9e6SYuval Mintz 
229fe56b9e6SYuval Mintz 	void		(*remove)(struct qed_dev *cdev);
230fe56b9e6SYuval Mintz 
231fe56b9e6SYuval Mintz 	int		(*set_power_state)(struct qed_dev *cdev,
232fe56b9e6SYuval Mintz 					   pci_power_t state);
233fe56b9e6SYuval Mintz 
234fe56b9e6SYuval Mintz 	void		(*set_id)(struct qed_dev *cdev,
235fe56b9e6SYuval Mintz 				  char name[],
236fe56b9e6SYuval Mintz 				  char ver_str[]);
237fe56b9e6SYuval Mintz 
238fe56b9e6SYuval Mintz 	/* Client drivers need to make this call before slowpath_start.
239fe56b9e6SYuval Mintz 	 * PF params required for the call before slowpath_start is
240fe56b9e6SYuval Mintz 	 * documented within the qed_pf_params structure definition.
241fe56b9e6SYuval Mintz 	 */
242fe56b9e6SYuval Mintz 	void		(*update_pf_params)(struct qed_dev *cdev,
243fe56b9e6SYuval Mintz 					    struct qed_pf_params *params);
244fe56b9e6SYuval Mintz 	int		(*slowpath_start)(struct qed_dev *cdev,
245fe56b9e6SYuval Mintz 					  struct qed_slowpath_params *params);
246fe56b9e6SYuval Mintz 
247fe56b9e6SYuval Mintz 	int		(*slowpath_stop)(struct qed_dev *cdev);
248fe56b9e6SYuval Mintz 
249fe56b9e6SYuval Mintz 	/* Requests to use `cnt' interrupts for fastpath.
250fe56b9e6SYuval Mintz 	 * upon success, returns number of interrupts allocated for fastpath.
251fe56b9e6SYuval Mintz 	 */
252fe56b9e6SYuval Mintz 	int		(*set_fp_int)(struct qed_dev *cdev,
253fe56b9e6SYuval Mintz 				      u16 cnt);
254fe56b9e6SYuval Mintz 
255fe56b9e6SYuval Mintz 	/* Fills `info' with pointers required for utilizing interrupts */
256fe56b9e6SYuval Mintz 	int		(*get_fp_int)(struct qed_dev *cdev,
257fe56b9e6SYuval Mintz 				      struct qed_int_info *info);
258fe56b9e6SYuval Mintz 
259fe56b9e6SYuval Mintz 	u32		(*sb_init)(struct qed_dev *cdev,
260fe56b9e6SYuval Mintz 				   struct qed_sb_info *sb_info,
261fe56b9e6SYuval Mintz 				   void *sb_virt_addr,
262fe56b9e6SYuval Mintz 				   dma_addr_t sb_phy_addr,
263fe56b9e6SYuval Mintz 				   u16 sb_id,
264fe56b9e6SYuval Mintz 				   enum qed_sb_type type);
265fe56b9e6SYuval Mintz 
266fe56b9e6SYuval Mintz 	u32		(*sb_release)(struct qed_dev *cdev,
267fe56b9e6SYuval Mintz 				      struct qed_sb_info *sb_info,
268fe56b9e6SYuval Mintz 				      u16 sb_id);
269fe56b9e6SYuval Mintz 
270fe56b9e6SYuval Mintz 	void		(*simd_handler_config)(struct qed_dev *cdev,
271fe56b9e6SYuval Mintz 					       void *token,
272fe56b9e6SYuval Mintz 					       int index,
273fe56b9e6SYuval Mintz 					       void (*handler)(void *));
274fe56b9e6SYuval Mintz 
275fe56b9e6SYuval Mintz 	void		(*simd_handler_clean)(struct qed_dev *cdev,
276fe56b9e6SYuval Mintz 					      int index);
277fe7cd2bfSYuval Mintz 
278fe7cd2bfSYuval Mintz /**
279fe7cd2bfSYuval Mintz  * @brief can_link_change - can the instance change the link or not
280fe7cd2bfSYuval Mintz  *
281fe7cd2bfSYuval Mintz  * @param cdev
282fe7cd2bfSYuval Mintz  *
283fe7cd2bfSYuval Mintz  * @return true if link-change is allowed, false otherwise.
284fe7cd2bfSYuval Mintz  */
285fe7cd2bfSYuval Mintz 	bool (*can_link_change)(struct qed_dev *cdev);
286fe7cd2bfSYuval Mintz 
287fe56b9e6SYuval Mintz /**
288fe56b9e6SYuval Mintz  * @brief set_link - set links according to params
289fe56b9e6SYuval Mintz  *
290fe56b9e6SYuval Mintz  * @param cdev
291fe56b9e6SYuval Mintz  * @param params - values used to override the default link configuration
292fe56b9e6SYuval Mintz  *
293fe56b9e6SYuval Mintz  * @return 0 on success, error otherwise.
294fe56b9e6SYuval Mintz  */
295fe56b9e6SYuval Mintz 	int		(*set_link)(struct qed_dev *cdev,
296fe56b9e6SYuval Mintz 				    struct qed_link_params *params);
297fe56b9e6SYuval Mintz 
298fe56b9e6SYuval Mintz /**
299fe56b9e6SYuval Mintz  * @brief get_link - returns the current link state.
300fe56b9e6SYuval Mintz  *
301fe56b9e6SYuval Mintz  * @param cdev
302fe56b9e6SYuval Mintz  * @param if_link - structure to be filled with current link configuration.
303fe56b9e6SYuval Mintz  */
304fe56b9e6SYuval Mintz 	void		(*get_link)(struct qed_dev *cdev,
305fe56b9e6SYuval Mintz 				    struct qed_link_output *if_link);
306fe56b9e6SYuval Mintz 
307fe56b9e6SYuval Mintz /**
308fe56b9e6SYuval Mintz  * @brief - drains chip in case Tx completions fail to arrive due to pause.
309fe56b9e6SYuval Mintz  *
310fe56b9e6SYuval Mintz  * @param cdev
311fe56b9e6SYuval Mintz  */
312fe56b9e6SYuval Mintz 	int		(*drain)(struct qed_dev *cdev);
313fe56b9e6SYuval Mintz 
314fe56b9e6SYuval Mintz /**
315fe56b9e6SYuval Mintz  * @brief update_msglvl - update module debug level
316fe56b9e6SYuval Mintz  *
317fe56b9e6SYuval Mintz  * @param cdev
318fe56b9e6SYuval Mintz  * @param dp_module
319fe56b9e6SYuval Mintz  * @param dp_level
320fe56b9e6SYuval Mintz  */
321fe56b9e6SYuval Mintz 	void		(*update_msglvl)(struct qed_dev *cdev,
322fe56b9e6SYuval Mintz 					 u32 dp_module,
323fe56b9e6SYuval Mintz 					 u8 dp_level);
324fe56b9e6SYuval Mintz 
325fe56b9e6SYuval Mintz 	int		(*chain_alloc)(struct qed_dev *cdev,
326fe56b9e6SYuval Mintz 				       enum qed_chain_use_mode intended_use,
327fe56b9e6SYuval Mintz 				       enum qed_chain_mode mode,
328*a91eb52aSYuval Mintz 				       enum qed_chain_cnt_type cnt_type,
329*a91eb52aSYuval Mintz 				       u32 num_elems,
330fe56b9e6SYuval Mintz 				       size_t elem_size,
331fe56b9e6SYuval Mintz 				       struct qed_chain *p_chain);
332fe56b9e6SYuval Mintz 
333fe56b9e6SYuval Mintz 	void		(*chain_free)(struct qed_dev *cdev,
334fe56b9e6SYuval Mintz 				      struct qed_chain *p_chain);
33591420b83SSudarsana Kalluru 
33691420b83SSudarsana Kalluru /**
33791420b83SSudarsana Kalluru  * @brief set_led - Configure LED mode
33891420b83SSudarsana Kalluru  *
33991420b83SSudarsana Kalluru  * @param cdev
34091420b83SSudarsana Kalluru  * @param mode - LED mode
34191420b83SSudarsana Kalluru  *
34291420b83SSudarsana Kalluru  * @return 0 on success, error otherwise.
34391420b83SSudarsana Kalluru  */
34491420b83SSudarsana Kalluru 	int (*set_led)(struct qed_dev *cdev,
34591420b83SSudarsana Kalluru 		       enum qed_led_mode mode);
346fe56b9e6SYuval Mintz };
347fe56b9e6SYuval Mintz 
348fe56b9e6SYuval Mintz #define MASK_FIELD(_name, _value) \
349fe56b9e6SYuval Mintz 	((_value) &= (_name ## _MASK))
350fe56b9e6SYuval Mintz 
351fe56b9e6SYuval Mintz #define FIELD_VALUE(_name, _value) \
352fe56b9e6SYuval Mintz 	((_value & _name ## _MASK) << _name ## _SHIFT)
353fe56b9e6SYuval Mintz 
354fe56b9e6SYuval Mintz #define SET_FIELD(value, name, flag)			       \
355fe56b9e6SYuval Mintz 	do {						       \
356fe56b9e6SYuval Mintz 		(value) &= ~(name ## _MASK << name ## _SHIFT); \
357fe56b9e6SYuval Mintz 		(value) |= (((u64)flag) << (name ## _SHIFT));  \
358fe56b9e6SYuval Mintz 	} while (0)
359fe56b9e6SYuval Mintz 
360fe56b9e6SYuval Mintz #define GET_FIELD(value, name) \
361fe56b9e6SYuval Mintz 	(((value) >> (name ## _SHIFT)) & name ## _MASK)
362fe56b9e6SYuval Mintz 
363fe56b9e6SYuval Mintz /* Debug print definitions */
364fe56b9e6SYuval Mintz #define DP_ERR(cdev, fmt, ...)						     \
365fe56b9e6SYuval Mintz 		pr_err("[%s:%d(%s)]" fmt,				     \
366fe56b9e6SYuval Mintz 		       __func__, __LINE__,				     \
367fe56b9e6SYuval Mintz 		       DP_NAME(cdev) ? DP_NAME(cdev) : "",		     \
368fe56b9e6SYuval Mintz 		       ## __VA_ARGS__)					     \
369fe56b9e6SYuval Mintz 
370fe56b9e6SYuval Mintz #define DP_NOTICE(cdev, fmt, ...)				      \
371fe56b9e6SYuval Mintz 	do {							      \
372fe56b9e6SYuval Mintz 		if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
373fe56b9e6SYuval Mintz 			pr_notice("[%s:%d(%s)]" fmt,		      \
374fe56b9e6SYuval Mintz 				  __func__, __LINE__,		      \
375fe56b9e6SYuval Mintz 				  DP_NAME(cdev) ? DP_NAME(cdev) : "", \
376fe56b9e6SYuval Mintz 				  ## __VA_ARGS__);		      \
377fe56b9e6SYuval Mintz 								      \
378fe56b9e6SYuval Mintz 		}						      \
379fe56b9e6SYuval Mintz 	} while (0)
380fe56b9e6SYuval Mintz 
381fe56b9e6SYuval Mintz #define DP_INFO(cdev, fmt, ...)					      \
382fe56b9e6SYuval Mintz 	do {							      \
383fe56b9e6SYuval Mintz 		if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) {   \
384fe56b9e6SYuval Mintz 			pr_notice("[%s:%d(%s)]" fmt,		      \
385fe56b9e6SYuval Mintz 				  __func__, __LINE__,		      \
386fe56b9e6SYuval Mintz 				  DP_NAME(cdev) ? DP_NAME(cdev) : "", \
387fe56b9e6SYuval Mintz 				  ## __VA_ARGS__);		      \
388fe56b9e6SYuval Mintz 		}						      \
389fe56b9e6SYuval Mintz 	} while (0)
390fe56b9e6SYuval Mintz 
391fe56b9e6SYuval Mintz #define DP_VERBOSE(cdev, module, fmt, ...)				\
392fe56b9e6SYuval Mintz 	do {								\
393fe56b9e6SYuval Mintz 		if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) &&	\
394fe56b9e6SYuval Mintz 			     ((cdev)->dp_module & module))) {		\
395fe56b9e6SYuval Mintz 			pr_notice("[%s:%d(%s)]" fmt,			\
396fe56b9e6SYuval Mintz 				  __func__, __LINE__,			\
397fe56b9e6SYuval Mintz 				  DP_NAME(cdev) ? DP_NAME(cdev) : "",	\
398fe56b9e6SYuval Mintz 				  ## __VA_ARGS__);			\
399fe56b9e6SYuval Mintz 		}							\
400fe56b9e6SYuval Mintz 	} while (0)
401fe56b9e6SYuval Mintz 
402fe56b9e6SYuval Mintz enum DP_LEVEL {
403fe56b9e6SYuval Mintz 	QED_LEVEL_VERBOSE	= 0x0,
404fe56b9e6SYuval Mintz 	QED_LEVEL_INFO		= 0x1,
405fe56b9e6SYuval Mintz 	QED_LEVEL_NOTICE	= 0x2,
406fe56b9e6SYuval Mintz 	QED_LEVEL_ERR		= 0x3,
407fe56b9e6SYuval Mintz };
408fe56b9e6SYuval Mintz 
409fe56b9e6SYuval Mintz #define QED_LOG_LEVEL_SHIFT     (30)
410fe56b9e6SYuval Mintz #define QED_LOG_VERBOSE_MASK    (0x3fffffff)
411fe56b9e6SYuval Mintz #define QED_LOG_INFO_MASK       (0x40000000)
412fe56b9e6SYuval Mintz #define QED_LOG_NOTICE_MASK     (0x80000000)
413fe56b9e6SYuval Mintz 
414fe56b9e6SYuval Mintz enum DP_MODULE {
415fe56b9e6SYuval Mintz 	QED_MSG_SPQ	= 0x10000,
416fe56b9e6SYuval Mintz 	QED_MSG_STATS	= 0x20000,
417fe56b9e6SYuval Mintz 	QED_MSG_DCB	= 0x40000,
418fe56b9e6SYuval Mintz 	QED_MSG_IOV	= 0x80000,
419fe56b9e6SYuval Mintz 	QED_MSG_SP	= 0x100000,
420fe56b9e6SYuval Mintz 	QED_MSG_STORAGE = 0x200000,
421fe56b9e6SYuval Mintz 	QED_MSG_CXT	= 0x800000,
422fe56b9e6SYuval Mintz 	QED_MSG_ILT	= 0x2000000,
423fe56b9e6SYuval Mintz 	QED_MSG_ROCE	= 0x4000000,
424fe56b9e6SYuval Mintz 	QED_MSG_DEBUG	= 0x8000000,
425fe56b9e6SYuval Mintz 	/* to be added...up to 0x8000000 */
426fe56b9e6SYuval Mintz };
427fe56b9e6SYuval Mintz 
428fc48b7a6SYuval Mintz enum qed_mf_mode {
429fc48b7a6SYuval Mintz 	QED_MF_DEFAULT,
430fc48b7a6SYuval Mintz 	QED_MF_OVLAN,
431fc48b7a6SYuval Mintz 	QED_MF_NPAR,
432fc48b7a6SYuval Mintz };
433fc48b7a6SYuval Mintz 
434fe56b9e6SYuval Mintz struct qed_eth_stats {
435fe56b9e6SYuval Mintz 	u64	no_buff_discards;
436fe56b9e6SYuval Mintz 	u64	packet_too_big_discard;
437fe56b9e6SYuval Mintz 	u64	ttl0_discard;
438fe56b9e6SYuval Mintz 	u64	rx_ucast_bytes;
439fe56b9e6SYuval Mintz 	u64	rx_mcast_bytes;
440fe56b9e6SYuval Mintz 	u64	rx_bcast_bytes;
441fe56b9e6SYuval Mintz 	u64	rx_ucast_pkts;
442fe56b9e6SYuval Mintz 	u64	rx_mcast_pkts;
443fe56b9e6SYuval Mintz 	u64	rx_bcast_pkts;
444fe56b9e6SYuval Mintz 	u64	mftag_filter_discards;
445fe56b9e6SYuval Mintz 	u64	mac_filter_discards;
446fe56b9e6SYuval Mintz 	u64	tx_ucast_bytes;
447fe56b9e6SYuval Mintz 	u64	tx_mcast_bytes;
448fe56b9e6SYuval Mintz 	u64	tx_bcast_bytes;
449fe56b9e6SYuval Mintz 	u64	tx_ucast_pkts;
450fe56b9e6SYuval Mintz 	u64	tx_mcast_pkts;
451fe56b9e6SYuval Mintz 	u64	tx_bcast_pkts;
452fe56b9e6SYuval Mintz 	u64	tx_err_drop_pkts;
453fe56b9e6SYuval Mintz 	u64	tpa_coalesced_pkts;
454fe56b9e6SYuval Mintz 	u64	tpa_coalesced_events;
455fe56b9e6SYuval Mintz 	u64	tpa_aborts_num;
456fe56b9e6SYuval Mintz 	u64	tpa_not_coalesced_pkts;
457fe56b9e6SYuval Mintz 	u64	tpa_coalesced_bytes;
458fe56b9e6SYuval Mintz 
459fe56b9e6SYuval Mintz 	/* port */
460fe56b9e6SYuval Mintz 	u64	rx_64_byte_packets;
461d4967cf3SYuval Mintz 	u64	rx_65_to_127_byte_packets;
462d4967cf3SYuval Mintz 	u64	rx_128_to_255_byte_packets;
463d4967cf3SYuval Mintz 	u64	rx_256_to_511_byte_packets;
464d4967cf3SYuval Mintz 	u64	rx_512_to_1023_byte_packets;
465d4967cf3SYuval Mintz 	u64	rx_1024_to_1518_byte_packets;
466d4967cf3SYuval Mintz 	u64	rx_1519_to_1522_byte_packets;
467d4967cf3SYuval Mintz 	u64	rx_1519_to_2047_byte_packets;
468d4967cf3SYuval Mintz 	u64	rx_2048_to_4095_byte_packets;
469d4967cf3SYuval Mintz 	u64	rx_4096_to_9216_byte_packets;
470d4967cf3SYuval Mintz 	u64	rx_9217_to_16383_byte_packets;
471fe56b9e6SYuval Mintz 	u64	rx_crc_errors;
472fe56b9e6SYuval Mintz 	u64	rx_mac_crtl_frames;
473fe56b9e6SYuval Mintz 	u64	rx_pause_frames;
474fe56b9e6SYuval Mintz 	u64	rx_pfc_frames;
475fe56b9e6SYuval Mintz 	u64	rx_align_errors;
476fe56b9e6SYuval Mintz 	u64	rx_carrier_errors;
477fe56b9e6SYuval Mintz 	u64	rx_oversize_packets;
478fe56b9e6SYuval Mintz 	u64	rx_jabbers;
479fe56b9e6SYuval Mintz 	u64	rx_undersize_packets;
480fe56b9e6SYuval Mintz 	u64	rx_fragments;
481fe56b9e6SYuval Mintz 	u64	tx_64_byte_packets;
482fe56b9e6SYuval Mintz 	u64	tx_65_to_127_byte_packets;
483fe56b9e6SYuval Mintz 	u64	tx_128_to_255_byte_packets;
484fe56b9e6SYuval Mintz 	u64	tx_256_to_511_byte_packets;
485fe56b9e6SYuval Mintz 	u64	tx_512_to_1023_byte_packets;
486fe56b9e6SYuval Mintz 	u64	tx_1024_to_1518_byte_packets;
487fe56b9e6SYuval Mintz 	u64	tx_1519_to_2047_byte_packets;
488fe56b9e6SYuval Mintz 	u64	tx_2048_to_4095_byte_packets;
489fe56b9e6SYuval Mintz 	u64	tx_4096_to_9216_byte_packets;
490fe56b9e6SYuval Mintz 	u64	tx_9217_to_16383_byte_packets;
491fe56b9e6SYuval Mintz 	u64	tx_pause_frames;
492fe56b9e6SYuval Mintz 	u64	tx_pfc_frames;
493fe56b9e6SYuval Mintz 	u64	tx_lpi_entry_count;
494fe56b9e6SYuval Mintz 	u64	tx_total_collisions;
495fe56b9e6SYuval Mintz 	u64	brb_truncates;
496fe56b9e6SYuval Mintz 	u64	brb_discards;
497fe56b9e6SYuval Mintz 	u64	rx_mac_bytes;
498fe56b9e6SYuval Mintz 	u64	rx_mac_uc_packets;
499fe56b9e6SYuval Mintz 	u64	rx_mac_mc_packets;
500fe56b9e6SYuval Mintz 	u64	rx_mac_bc_packets;
501fe56b9e6SYuval Mintz 	u64	rx_mac_frames_ok;
502fe56b9e6SYuval Mintz 	u64	tx_mac_bytes;
503fe56b9e6SYuval Mintz 	u64	tx_mac_uc_packets;
504fe56b9e6SYuval Mintz 	u64	tx_mac_mc_packets;
505fe56b9e6SYuval Mintz 	u64	tx_mac_bc_packets;
506fe56b9e6SYuval Mintz 	u64	tx_mac_ctrl_frames;
507fe56b9e6SYuval Mintz };
508fe56b9e6SYuval Mintz 
509fe56b9e6SYuval Mintz #define QED_SB_IDX              0x0002
510fe56b9e6SYuval Mintz 
511fe56b9e6SYuval Mintz #define RX_PI           0
512fe56b9e6SYuval Mintz #define TX_PI(tc)       (RX_PI + 1 + tc)
513fe56b9e6SYuval Mintz 
5144ac801b7SYuval Mintz struct qed_sb_cnt_info {
5154ac801b7SYuval Mintz 	int	sb_cnt;
5164ac801b7SYuval Mintz 	int	sb_iov_cnt;
5174ac801b7SYuval Mintz 	int	sb_free_blk;
5184ac801b7SYuval Mintz };
5194ac801b7SYuval Mintz 
520fe56b9e6SYuval Mintz static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
521fe56b9e6SYuval Mintz {
522fe56b9e6SYuval Mintz 	u32 prod = 0;
523fe56b9e6SYuval Mintz 	u16 rc = 0;
524fe56b9e6SYuval Mintz 
525fe56b9e6SYuval Mintz 	prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
526fe56b9e6SYuval Mintz 	       STATUS_BLOCK_PROD_INDEX_MASK;
527fe56b9e6SYuval Mintz 	if (sb_info->sb_ack != prod) {
528fe56b9e6SYuval Mintz 		sb_info->sb_ack = prod;
529fe56b9e6SYuval Mintz 		rc |= QED_SB_IDX;
530fe56b9e6SYuval Mintz 	}
531fe56b9e6SYuval Mintz 
532fe56b9e6SYuval Mintz 	/* Let SB update */
533fe56b9e6SYuval Mintz 	mmiowb();
534fe56b9e6SYuval Mintz 	return rc;
535fe56b9e6SYuval Mintz }
536fe56b9e6SYuval Mintz 
537fe56b9e6SYuval Mintz /**
538fe56b9e6SYuval Mintz  *
539fe56b9e6SYuval Mintz  * @brief This function creates an update command for interrupts that is
540fe56b9e6SYuval Mintz  *        written to the IGU.
541fe56b9e6SYuval Mintz  *
542fe56b9e6SYuval Mintz  * @param sb_info       - This is the structure allocated and
543fe56b9e6SYuval Mintz  *                 initialized per status block. Assumption is
544fe56b9e6SYuval Mintz  *                 that it was initialized using qed_sb_init
545fe56b9e6SYuval Mintz  * @param int_cmd       - Enable/Disable/Nop
546fe56b9e6SYuval Mintz  * @param upd_flg       - whether igu consumer should be
547fe56b9e6SYuval Mintz  *                 updated.
548fe56b9e6SYuval Mintz  *
549fe56b9e6SYuval Mintz  * @return inline void
550fe56b9e6SYuval Mintz  */
551fe56b9e6SYuval Mintz static inline void qed_sb_ack(struct qed_sb_info *sb_info,
552fe56b9e6SYuval Mintz 			      enum igu_int_cmd int_cmd,
553fe56b9e6SYuval Mintz 			      u8 upd_flg)
554fe56b9e6SYuval Mintz {
555fe56b9e6SYuval Mintz 	struct igu_prod_cons_update igu_ack = { 0 };
556fe56b9e6SYuval Mintz 
557fe56b9e6SYuval Mintz 	igu_ack.sb_id_and_flags =
558fe56b9e6SYuval Mintz 		((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
559fe56b9e6SYuval Mintz 		 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
560fe56b9e6SYuval Mintz 		 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
561fe56b9e6SYuval Mintz 		 (IGU_SEG_ACCESS_REG <<
562fe56b9e6SYuval Mintz 		  IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
563fe56b9e6SYuval Mintz 
564fe56b9e6SYuval Mintz 	DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
565fe56b9e6SYuval Mintz 
566fe56b9e6SYuval Mintz 	/* Both segments (interrupts & acks) are written to same place address;
567fe56b9e6SYuval Mintz 	 * Need to guarantee all commands will be received (in-order) by HW.
568fe56b9e6SYuval Mintz 	 */
569fe56b9e6SYuval Mintz 	mmiowb();
570fe56b9e6SYuval Mintz 	barrier();
571fe56b9e6SYuval Mintz }
572fe56b9e6SYuval Mintz 
573fe56b9e6SYuval Mintz static inline void __internal_ram_wr(void *p_hwfn,
574fe56b9e6SYuval Mintz 				     void __iomem *addr,
575fe56b9e6SYuval Mintz 				     int size,
576fe56b9e6SYuval Mintz 				     u32 *data)
577fe56b9e6SYuval Mintz 
578fe56b9e6SYuval Mintz {
579fe56b9e6SYuval Mintz 	unsigned int i;
580fe56b9e6SYuval Mintz 
581fe56b9e6SYuval Mintz 	for (i = 0; i < size / sizeof(*data); i++)
582fe56b9e6SYuval Mintz 		DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
583fe56b9e6SYuval Mintz }
584fe56b9e6SYuval Mintz 
585fe56b9e6SYuval Mintz static inline void internal_ram_wr(void __iomem *addr,
586fe56b9e6SYuval Mintz 				   int size,
587fe56b9e6SYuval Mintz 				   u32 *data)
588fe56b9e6SYuval Mintz {
589fe56b9e6SYuval Mintz 	__internal_ram_wr(NULL, addr, size, data);
590fe56b9e6SYuval Mintz }
591fe56b9e6SYuval Mintz 
5928c5ebd0cSSudarsana Reddy Kalluru enum qed_rss_caps {
5938c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV4		= 0x1,
5948c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV6		= 0x2,
5958c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV4_TCP	= 0x4,
5968c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV6_TCP	= 0x8,
5978c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV4_UDP	= 0x10,
5988c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV6_UDP	= 0x20,
5998c5ebd0cSSudarsana Reddy Kalluru };
6008c5ebd0cSSudarsana Reddy Kalluru 
6018c5ebd0cSSudarsana Reddy Kalluru #define QED_RSS_IND_TABLE_SIZE 128
6028c5ebd0cSSudarsana Reddy Kalluru #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
603fe56b9e6SYuval Mintz #endif
604