xref: /linux/include/linux/qed/qed_if.h (revision 99785a87fc7d27207c7dca0f0fe04386f1981690)
11f4d4ed6SAlexander Lobakin /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver
3e8f1cb50SMintz, Yuval  * Copyright (c) 2015-2017  QLogic Corporation
4663eacd8SAlexander Lobakin  * Copyright (c) 2019-2020 Marvell International Ltd.
5fe56b9e6SYuval Mintz  */
6fe56b9e6SYuval Mintz 
7fe56b9e6SYuval Mintz #ifndef _QED_IF_H
8fe56b9e6SYuval Mintz #define _QED_IF_H
9fe56b9e6SYuval Mintz 
10fe56b9e6SYuval Mintz #include <linux/types.h>
11fe56b9e6SYuval Mintz #include <linux/interrupt.h>
12fe56b9e6SYuval Mintz #include <linux/netdevice.h>
13fe56b9e6SYuval Mintz #include <linux/pci.h>
14fe56b9e6SYuval Mintz #include <linux/skbuff.h>
15fe56b9e6SYuval Mintz #include <asm/byteorder.h>
16fe56b9e6SYuval Mintz #include <linux/io.h>
17fe56b9e6SYuval Mintz #include <linux/compiler.h>
18fe56b9e6SYuval Mintz #include <linux/kernel.h>
19fe56b9e6SYuval Mintz #include <linux/list.h>
20fe56b9e6SYuval Mintz #include <linux/slab.h>
21fe56b9e6SYuval Mintz #include <linux/qed/common_hsi.h>
22fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h>
2336907cd5SAriel Elior #include <linux/io-64-nonatomic-lo-hi.h>
24fe56b9e6SYuval Mintz 
2539651abdSSudarsana Reddy Kalluru enum dcbx_protocol_type {
2639651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_ISCSI,
2739651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_FCOE,
2839651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_ROCE,
2939651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_ROCE_V2,
3039651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_ETH,
3139651abdSSudarsana Reddy Kalluru 	DCBX_MAX_PROTOCOL_TYPE
3239651abdSSudarsana Reddy Kalluru };
3339651abdSSudarsana Reddy Kalluru 
3451ff1725SRam Amrani #define QED_ROCE_PROTOCOL_INDEX (3)
3551ff1725SRam Amrani 
366ad8c632SSudarsana Reddy Kalluru #define QED_LLDP_CHASSIS_ID_STAT_LEN 4
376ad8c632SSudarsana Reddy Kalluru #define QED_LLDP_PORT_ID_STAT_LEN 4
386ad8c632SSudarsana Reddy Kalluru #define QED_DCBX_MAX_APP_PROTOCOL 32
396ad8c632SSudarsana Reddy Kalluru #define QED_MAX_PFC_PRIORITIES 8
406ad8c632SSudarsana Reddy Kalluru #define QED_DCBX_DSCP_SIZE 64
416ad8c632SSudarsana Reddy Kalluru 
426ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_remote {
436ad8c632SSudarsana Reddy Kalluru 	u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
446ad8c632SSudarsana Reddy Kalluru 	u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
456ad8c632SSudarsana Reddy Kalluru 	bool enable_rx;
466ad8c632SSudarsana Reddy Kalluru 	bool enable_tx;
476ad8c632SSudarsana Reddy Kalluru 	u32 tx_interval;
486ad8c632SSudarsana Reddy Kalluru 	u32 max_credit;
496ad8c632SSudarsana Reddy Kalluru };
506ad8c632SSudarsana Reddy Kalluru 
516ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_local {
526ad8c632SSudarsana Reddy Kalluru 	u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
536ad8c632SSudarsana Reddy Kalluru 	u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
546ad8c632SSudarsana Reddy Kalluru };
556ad8c632SSudarsana Reddy Kalluru 
566ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_app_prio {
576ad8c632SSudarsana Reddy Kalluru 	u8 roce;
586ad8c632SSudarsana Reddy Kalluru 	u8 roce_v2;
596ad8c632SSudarsana Reddy Kalluru 	u8 fcoe;
606ad8c632SSudarsana Reddy Kalluru 	u8 iscsi;
616ad8c632SSudarsana Reddy Kalluru 	u8 eth;
626ad8c632SSudarsana Reddy Kalluru };
636ad8c632SSudarsana Reddy Kalluru 
646ad8c632SSudarsana Reddy Kalluru struct qed_dbcx_pfc_params {
656ad8c632SSudarsana Reddy Kalluru 	bool willing;
666ad8c632SSudarsana Reddy Kalluru 	bool enabled;
676ad8c632SSudarsana Reddy Kalluru 	u8 prio[QED_MAX_PFC_PRIORITIES];
686ad8c632SSudarsana Reddy Kalluru 	u8 max_tc;
696ad8c632SSudarsana Reddy Kalluru };
706ad8c632SSudarsana Reddy Kalluru 
7159bcb797SSudarsana Reddy Kalluru enum qed_dcbx_sf_ieee_type {
7259bcb797SSudarsana Reddy Kalluru 	QED_DCBX_SF_IEEE_ETHTYPE,
7359bcb797SSudarsana Reddy Kalluru 	QED_DCBX_SF_IEEE_TCP_PORT,
7459bcb797SSudarsana Reddy Kalluru 	QED_DCBX_SF_IEEE_UDP_PORT,
7559bcb797SSudarsana Reddy Kalluru 	QED_DCBX_SF_IEEE_TCP_UDP_PORT
7659bcb797SSudarsana Reddy Kalluru };
7759bcb797SSudarsana Reddy Kalluru 
786ad8c632SSudarsana Reddy Kalluru struct qed_app_entry {
796ad8c632SSudarsana Reddy Kalluru 	bool ethtype;
8059bcb797SSudarsana Reddy Kalluru 	enum qed_dcbx_sf_ieee_type sf_ieee;
816ad8c632SSudarsana Reddy Kalluru 	bool enabled;
826ad8c632SSudarsana Reddy Kalluru 	u8 prio;
836ad8c632SSudarsana Reddy Kalluru 	u16 proto_id;
846ad8c632SSudarsana Reddy Kalluru 	enum dcbx_protocol_type proto_type;
856ad8c632SSudarsana Reddy Kalluru };
866ad8c632SSudarsana Reddy Kalluru 
876ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params {
886ad8c632SSudarsana Reddy Kalluru 	struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
896ad8c632SSudarsana Reddy Kalluru 	u16 num_app_entries;
906ad8c632SSudarsana Reddy Kalluru 	bool app_willing;
916ad8c632SSudarsana Reddy Kalluru 	bool app_valid;
926ad8c632SSudarsana Reddy Kalluru 	bool app_error;
936ad8c632SSudarsana Reddy Kalluru 	bool ets_willing;
946ad8c632SSudarsana Reddy Kalluru 	bool ets_enabled;
956ad8c632SSudarsana Reddy Kalluru 	bool ets_cbs;
966ad8c632SSudarsana Reddy Kalluru 	bool valid;
976ad8c632SSudarsana Reddy Kalluru 	u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
986ad8c632SSudarsana Reddy Kalluru 	u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
996ad8c632SSudarsana Reddy Kalluru 	u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
1006ad8c632SSudarsana Reddy Kalluru 	struct qed_dbcx_pfc_params pfc;
1016ad8c632SSudarsana Reddy Kalluru 	u8 max_ets_tc;
1026ad8c632SSudarsana Reddy Kalluru };
1036ad8c632SSudarsana Reddy Kalluru 
1046ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_admin_params {
1056ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_params params;
1066ad8c632SSudarsana Reddy Kalluru 	bool valid;
1076ad8c632SSudarsana Reddy Kalluru };
1086ad8c632SSudarsana Reddy Kalluru 
1096ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_remote_params {
1106ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_params params;
1116ad8c632SSudarsana Reddy Kalluru 	bool valid;
1126ad8c632SSudarsana Reddy Kalluru };
1136ad8c632SSudarsana Reddy Kalluru 
1146ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_operational_params {
1156ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_app_prio app_prio;
1166ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_params params;
1176ad8c632SSudarsana Reddy Kalluru 	bool valid;
1186ad8c632SSudarsana Reddy Kalluru 	bool enabled;
1196ad8c632SSudarsana Reddy Kalluru 	bool ieee;
1206ad8c632SSudarsana Reddy Kalluru 	bool cee;
12149632b58Ssudarsana.kalluru@cavium.com 	bool local;
1226ad8c632SSudarsana Reddy Kalluru 	u32 err;
1236ad8c632SSudarsana Reddy Kalluru };
1246ad8c632SSudarsana Reddy Kalluru 
1256ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_get {
1266ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_operational_params operational;
1276ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_lldp_remote lldp_remote;
1286ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_lldp_local lldp_local;
1296ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_remote_params remote;
1306ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_admin_params local;
1316ad8c632SSudarsana Reddy Kalluru };
1326ad8c632SSudarsana Reddy Kalluru 
13320675b37SMintz, Yuval enum qed_nvm_images {
13420675b37SMintz, Yuval 	QED_NVM_IMAGE_ISCSI_CFG,
13520675b37SMintz, Yuval 	QED_NVM_IMAGE_FCOE_CFG,
1368a52bbabSMichal Kalderon 	QED_NVM_IMAGE_MDUMP,
1371ac4329aSDenis Bolotin 	QED_NVM_IMAGE_NVM_CFG1,
1381ac4329aSDenis Bolotin 	QED_NVM_IMAGE_DEFAULT_CFG,
1391ac4329aSDenis Bolotin 	QED_NVM_IMAGE_NVM_META,
14020675b37SMintz, Yuval };
14120675b37SMintz, Yuval 
142645874e5SSudarsana Reddy Kalluru struct qed_link_eee_params {
143645874e5SSudarsana Reddy Kalluru 	u32 tx_lpi_timer;
144645874e5SSudarsana Reddy Kalluru #define QED_EEE_1G_ADV		BIT(0)
145645874e5SSudarsana Reddy Kalluru #define QED_EEE_10G_ADV		BIT(1)
146645874e5SSudarsana Reddy Kalluru 
147645874e5SSudarsana Reddy Kalluru 	/* Capabilities are represented using QED_EEE_*_ADV values */
148645874e5SSudarsana Reddy Kalluru 	u8 adv_caps;
149645874e5SSudarsana Reddy Kalluru 	u8 lp_adv_caps;
150645874e5SSudarsana Reddy Kalluru 	bool enable;
151645874e5SSudarsana Reddy Kalluru 	bool tx_lpi_enable;
152645874e5SSudarsana Reddy Kalluru };
153645874e5SSudarsana Reddy Kalluru 
15491420b83SSudarsana Kalluru enum qed_led_mode {
15591420b83SSudarsana Kalluru 	QED_LED_MODE_OFF,
15691420b83SSudarsana Kalluru 	QED_LED_MODE_ON,
15791420b83SSudarsana Kalluru 	QED_LED_MODE_RESTORE
15891420b83SSudarsana Kalluru };
15991420b83SSudarsana Kalluru 
1602528c389SSudarsana Reddy Kalluru struct qed_mfw_tlv_eth {
1612528c389SSudarsana Reddy Kalluru 	u16 lso_maxoff_size;
1622528c389SSudarsana Reddy Kalluru 	bool lso_maxoff_size_set;
1632528c389SSudarsana Reddy Kalluru 	u16 lso_minseg_size;
1642528c389SSudarsana Reddy Kalluru 	bool lso_minseg_size_set;
1652528c389SSudarsana Reddy Kalluru 	u8 prom_mode;
1662528c389SSudarsana Reddy Kalluru 	bool prom_mode_set;
1672528c389SSudarsana Reddy Kalluru 	u16 tx_descr_size;
1682528c389SSudarsana Reddy Kalluru 	bool tx_descr_size_set;
1692528c389SSudarsana Reddy Kalluru 	u16 rx_descr_size;
1702528c389SSudarsana Reddy Kalluru 	bool rx_descr_size_set;
1712528c389SSudarsana Reddy Kalluru 	u16 netq_count;
1722528c389SSudarsana Reddy Kalluru 	bool netq_count_set;
1732528c389SSudarsana Reddy Kalluru 	u32 tcp4_offloads;
1742528c389SSudarsana Reddy Kalluru 	bool tcp4_offloads_set;
1752528c389SSudarsana Reddy Kalluru 	u32 tcp6_offloads;
1762528c389SSudarsana Reddy Kalluru 	bool tcp6_offloads_set;
1772528c389SSudarsana Reddy Kalluru 	u16 tx_descr_qdepth;
1782528c389SSudarsana Reddy Kalluru 	bool tx_descr_qdepth_set;
1792528c389SSudarsana Reddy Kalluru 	u16 rx_descr_qdepth;
1802528c389SSudarsana Reddy Kalluru 	bool rx_descr_qdepth_set;
1812528c389SSudarsana Reddy Kalluru 	u8 iov_offload;
1822528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_IOV_OFFLOAD_NONE            (0)
1832528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE      (1)
1842528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_IOV_OFFLOAD_VEB             (2)
1852528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_IOV_OFFLOAD_VEPA            (3)
1862528c389SSudarsana Reddy Kalluru 	bool iov_offload_set;
1872528c389SSudarsana Reddy Kalluru 	u8 txqs_empty;
1882528c389SSudarsana Reddy Kalluru 	bool txqs_empty_set;
1892528c389SSudarsana Reddy Kalluru 	u8 rxqs_empty;
1902528c389SSudarsana Reddy Kalluru 	bool rxqs_empty_set;
1912528c389SSudarsana Reddy Kalluru 	u8 num_txqs_full;
1922528c389SSudarsana Reddy Kalluru 	bool num_txqs_full_set;
1932528c389SSudarsana Reddy Kalluru 	u8 num_rxqs_full;
1942528c389SSudarsana Reddy Kalluru 	bool num_rxqs_full_set;
1952528c389SSudarsana Reddy Kalluru };
1962528c389SSudarsana Reddy Kalluru 
197f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_TIME_SIZE	14
198f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_time {
199f240b688SSudarsana Reddy Kalluru 	bool b_set;
200f240b688SSudarsana Reddy Kalluru 	u8 month;
201f240b688SSudarsana Reddy Kalluru 	u8 day;
202f240b688SSudarsana Reddy Kalluru 	u8 hour;
203f240b688SSudarsana Reddy Kalluru 	u8 min;
204f240b688SSudarsana Reddy Kalluru 	u16 msec;
205f240b688SSudarsana Reddy Kalluru 	u16 usec;
206f240b688SSudarsana Reddy Kalluru };
207f240b688SSudarsana Reddy Kalluru 
208f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_fcoe {
209f240b688SSudarsana Reddy Kalluru 	u8 scsi_timeout;
210f240b688SSudarsana Reddy Kalluru 	bool scsi_timeout_set;
211f240b688SSudarsana Reddy Kalluru 	u32 rt_tov;
212f240b688SSudarsana Reddy Kalluru 	bool rt_tov_set;
213f240b688SSudarsana Reddy Kalluru 	u32 ra_tov;
214f240b688SSudarsana Reddy Kalluru 	bool ra_tov_set;
215f240b688SSudarsana Reddy Kalluru 	u32 ed_tov;
216f240b688SSudarsana Reddy Kalluru 	bool ed_tov_set;
217f240b688SSudarsana Reddy Kalluru 	u32 cr_tov;
218f240b688SSudarsana Reddy Kalluru 	bool cr_tov_set;
219f240b688SSudarsana Reddy Kalluru 	u8 boot_type;
220f240b688SSudarsana Reddy Kalluru 	bool boot_type_set;
221f240b688SSudarsana Reddy Kalluru 	u8 npiv_state;
222f240b688SSudarsana Reddy Kalluru 	bool npiv_state_set;
223f240b688SSudarsana Reddy Kalluru 	u32 num_npiv_ids;
224f240b688SSudarsana Reddy Kalluru 	bool num_npiv_ids_set;
225f240b688SSudarsana Reddy Kalluru 	u8 switch_name[8];
226f240b688SSudarsana Reddy Kalluru 	bool switch_name_set;
227f240b688SSudarsana Reddy Kalluru 	u16 switch_portnum;
228f240b688SSudarsana Reddy Kalluru 	bool switch_portnum_set;
229f240b688SSudarsana Reddy Kalluru 	u8 switch_portid[3];
230f240b688SSudarsana Reddy Kalluru 	bool switch_portid_set;
231f240b688SSudarsana Reddy Kalluru 	u8 vendor_name[8];
232f240b688SSudarsana Reddy Kalluru 	bool vendor_name_set;
233f240b688SSudarsana Reddy Kalluru 	u8 switch_model[8];
234f240b688SSudarsana Reddy Kalluru 	bool switch_model_set;
235f240b688SSudarsana Reddy Kalluru 	u8 switch_fw_version[8];
236f240b688SSudarsana Reddy Kalluru 	bool switch_fw_version_set;
237f240b688SSudarsana Reddy Kalluru 	u8 qos_pri;
238f240b688SSudarsana Reddy Kalluru 	bool qos_pri_set;
239f240b688SSudarsana Reddy Kalluru 	u8 port_alias[3];
240f240b688SSudarsana Reddy Kalluru 	bool port_alias_set;
241f240b688SSudarsana Reddy Kalluru 	u8 port_state;
242f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_PORT_STATE_OFFLINE  (0)
243f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_PORT_STATE_LOOP             (1)
244f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_PORT_STATE_P2P              (2)
245f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_PORT_STATE_FABRIC           (3)
246f240b688SSudarsana Reddy Kalluru 	bool port_state_set;
247f240b688SSudarsana Reddy Kalluru 	u16 fip_tx_descr_size;
248f240b688SSudarsana Reddy Kalluru 	bool fip_tx_descr_size_set;
249f240b688SSudarsana Reddy Kalluru 	u16 fip_rx_descr_size;
250f240b688SSudarsana Reddy Kalluru 	bool fip_rx_descr_size_set;
251f240b688SSudarsana Reddy Kalluru 	u16 link_failures;
252f240b688SSudarsana Reddy Kalluru 	bool link_failures_set;
253f240b688SSudarsana Reddy Kalluru 	u8 fcoe_boot_progress;
254f240b688SSudarsana Reddy Kalluru 	bool fcoe_boot_progress_set;
255f240b688SSudarsana Reddy Kalluru 	u64 rx_bcast;
256f240b688SSudarsana Reddy Kalluru 	bool rx_bcast_set;
257f240b688SSudarsana Reddy Kalluru 	u64 tx_bcast;
258f240b688SSudarsana Reddy Kalluru 	bool tx_bcast_set;
259f240b688SSudarsana Reddy Kalluru 	u16 fcoe_txq_depth;
260f240b688SSudarsana Reddy Kalluru 	bool fcoe_txq_depth_set;
261f240b688SSudarsana Reddy Kalluru 	u16 fcoe_rxq_depth;
262f240b688SSudarsana Reddy Kalluru 	bool fcoe_rxq_depth_set;
263f240b688SSudarsana Reddy Kalluru 	u64 fcoe_rx_frames;
264f240b688SSudarsana Reddy Kalluru 	bool fcoe_rx_frames_set;
265f240b688SSudarsana Reddy Kalluru 	u64 fcoe_rx_bytes;
266f240b688SSudarsana Reddy Kalluru 	bool fcoe_rx_bytes_set;
267f240b688SSudarsana Reddy Kalluru 	u64 fcoe_tx_frames;
268f240b688SSudarsana Reddy Kalluru 	bool fcoe_tx_frames_set;
269f240b688SSudarsana Reddy Kalluru 	u64 fcoe_tx_bytes;
270f240b688SSudarsana Reddy Kalluru 	bool fcoe_tx_bytes_set;
271f240b688SSudarsana Reddy Kalluru 	u16 crc_count;
272f240b688SSudarsana Reddy Kalluru 	bool crc_count_set;
273f240b688SSudarsana Reddy Kalluru 	u32 crc_err_src_fcid[5];
274f240b688SSudarsana Reddy Kalluru 	bool crc_err_src_fcid_set[5];
275f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time crc_err[5];
276f240b688SSudarsana Reddy Kalluru 	u16 losync_err;
277f240b688SSudarsana Reddy Kalluru 	bool losync_err_set;
278f240b688SSudarsana Reddy Kalluru 	u16 losig_err;
279f240b688SSudarsana Reddy Kalluru 	bool losig_err_set;
280f240b688SSudarsana Reddy Kalluru 	u16 primtive_err;
281f240b688SSudarsana Reddy Kalluru 	bool primtive_err_set;
282f240b688SSudarsana Reddy Kalluru 	u16 disparity_err;
283f240b688SSudarsana Reddy Kalluru 	bool disparity_err_set;
284f240b688SSudarsana Reddy Kalluru 	u16 code_violation_err;
285f240b688SSudarsana Reddy Kalluru 	bool code_violation_err_set;
286f240b688SSudarsana Reddy Kalluru 	u32 flogi_param[4];
287f240b688SSudarsana Reddy Kalluru 	bool flogi_param_set[4];
288f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time flogi_tstamp;
289f240b688SSudarsana Reddy Kalluru 	u32 flogi_acc_param[4];
290f240b688SSudarsana Reddy Kalluru 	bool flogi_acc_param_set[4];
291f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time flogi_acc_tstamp;
292f240b688SSudarsana Reddy Kalluru 	u32 flogi_rjt;
293f240b688SSudarsana Reddy Kalluru 	bool flogi_rjt_set;
294f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time flogi_rjt_tstamp;
295f240b688SSudarsana Reddy Kalluru 	u32 fdiscs;
296f240b688SSudarsana Reddy Kalluru 	bool fdiscs_set;
297f240b688SSudarsana Reddy Kalluru 	u8 fdisc_acc;
298f240b688SSudarsana Reddy Kalluru 	bool fdisc_acc_set;
299f240b688SSudarsana Reddy Kalluru 	u8 fdisc_rjt;
300f240b688SSudarsana Reddy Kalluru 	bool fdisc_rjt_set;
301f240b688SSudarsana Reddy Kalluru 	u8 plogi;
302f240b688SSudarsana Reddy Kalluru 	bool plogi_set;
303f240b688SSudarsana Reddy Kalluru 	u8 plogi_acc;
304f240b688SSudarsana Reddy Kalluru 	bool plogi_acc_set;
305f240b688SSudarsana Reddy Kalluru 	u8 plogi_rjt;
306f240b688SSudarsana Reddy Kalluru 	bool plogi_rjt_set;
307f240b688SSudarsana Reddy Kalluru 	u32 plogi_dst_fcid[5];
308f240b688SSudarsana Reddy Kalluru 	bool plogi_dst_fcid_set[5];
309f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time plogi_tstamp[5];
310f240b688SSudarsana Reddy Kalluru 	u32 plogi_acc_src_fcid[5];
311f240b688SSudarsana Reddy Kalluru 	bool plogi_acc_src_fcid_set[5];
312f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time plogi_acc_tstamp[5];
313f240b688SSudarsana Reddy Kalluru 	u8 tx_plogos;
314f240b688SSudarsana Reddy Kalluru 	bool tx_plogos_set;
315f240b688SSudarsana Reddy Kalluru 	u8 plogo_acc;
316f240b688SSudarsana Reddy Kalluru 	bool plogo_acc_set;
317f240b688SSudarsana Reddy Kalluru 	u8 plogo_rjt;
318f240b688SSudarsana Reddy Kalluru 	bool plogo_rjt_set;
319f240b688SSudarsana Reddy Kalluru 	u32 plogo_src_fcid[5];
320f240b688SSudarsana Reddy Kalluru 	bool plogo_src_fcid_set[5];
321f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time plogo_tstamp[5];
322f240b688SSudarsana Reddy Kalluru 	u8 rx_logos;
323f240b688SSudarsana Reddy Kalluru 	bool rx_logos_set;
324f240b688SSudarsana Reddy Kalluru 	u8 tx_accs;
325f240b688SSudarsana Reddy Kalluru 	bool tx_accs_set;
326f240b688SSudarsana Reddy Kalluru 	u8 tx_prlis;
327f240b688SSudarsana Reddy Kalluru 	bool tx_prlis_set;
328f240b688SSudarsana Reddy Kalluru 	u8 rx_accs;
329f240b688SSudarsana Reddy Kalluru 	bool rx_accs_set;
330f240b688SSudarsana Reddy Kalluru 	u8 tx_abts;
331f240b688SSudarsana Reddy Kalluru 	bool tx_abts_set;
332f240b688SSudarsana Reddy Kalluru 	u8 rx_abts_acc;
333f240b688SSudarsana Reddy Kalluru 	bool rx_abts_acc_set;
334f240b688SSudarsana Reddy Kalluru 	u8 rx_abts_rjt;
335f240b688SSudarsana Reddy Kalluru 	bool rx_abts_rjt_set;
336f240b688SSudarsana Reddy Kalluru 	u32 abts_dst_fcid[5];
337f240b688SSudarsana Reddy Kalluru 	bool abts_dst_fcid_set[5];
338f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time abts_tstamp[5];
339f240b688SSudarsana Reddy Kalluru 	u8 rx_rscn;
340f240b688SSudarsana Reddy Kalluru 	bool rx_rscn_set;
341f240b688SSudarsana Reddy Kalluru 	u32 rx_rscn_nport[4];
342f240b688SSudarsana Reddy Kalluru 	bool rx_rscn_nport_set[4];
343f240b688SSudarsana Reddy Kalluru 	u8 tx_lun_rst;
344f240b688SSudarsana Reddy Kalluru 	bool tx_lun_rst_set;
345f240b688SSudarsana Reddy Kalluru 	u8 abort_task_sets;
346f240b688SSudarsana Reddy Kalluru 	bool abort_task_sets_set;
347f240b688SSudarsana Reddy Kalluru 	u8 tx_tprlos;
348f240b688SSudarsana Reddy Kalluru 	bool tx_tprlos_set;
349f240b688SSudarsana Reddy Kalluru 	u8 tx_nos;
350f240b688SSudarsana Reddy Kalluru 	bool tx_nos_set;
351f240b688SSudarsana Reddy Kalluru 	u8 rx_nos;
352f240b688SSudarsana Reddy Kalluru 	bool rx_nos_set;
353f240b688SSudarsana Reddy Kalluru 	u8 ols;
354f240b688SSudarsana Reddy Kalluru 	bool ols_set;
355f240b688SSudarsana Reddy Kalluru 	u8 lr;
356f240b688SSudarsana Reddy Kalluru 	bool lr_set;
357f240b688SSudarsana Reddy Kalluru 	u8 lrr;
358f240b688SSudarsana Reddy Kalluru 	bool lrr_set;
359f240b688SSudarsana Reddy Kalluru 	u8 tx_lip;
360f240b688SSudarsana Reddy Kalluru 	bool tx_lip_set;
361f240b688SSudarsana Reddy Kalluru 	u8 rx_lip;
362f240b688SSudarsana Reddy Kalluru 	bool rx_lip_set;
363f240b688SSudarsana Reddy Kalluru 	u8 eofa;
364f240b688SSudarsana Reddy Kalluru 	bool eofa_set;
365f240b688SSudarsana Reddy Kalluru 	u8 eofni;
366f240b688SSudarsana Reddy Kalluru 	bool eofni_set;
367f240b688SSudarsana Reddy Kalluru 	u8 scsi_chks;
368f240b688SSudarsana Reddy Kalluru 	bool scsi_chks_set;
369f240b688SSudarsana Reddy Kalluru 	u8 scsi_cond_met;
370f240b688SSudarsana Reddy Kalluru 	bool scsi_cond_met_set;
371f240b688SSudarsana Reddy Kalluru 	u8 scsi_busy;
372f240b688SSudarsana Reddy Kalluru 	bool scsi_busy_set;
373f240b688SSudarsana Reddy Kalluru 	u8 scsi_inter;
374f240b688SSudarsana Reddy Kalluru 	bool scsi_inter_set;
375f240b688SSudarsana Reddy Kalluru 	u8 scsi_inter_cond_met;
376f240b688SSudarsana Reddy Kalluru 	bool scsi_inter_cond_met_set;
377f240b688SSudarsana Reddy Kalluru 	u8 scsi_rsv_conflicts;
378f240b688SSudarsana Reddy Kalluru 	bool scsi_rsv_conflicts_set;
379f240b688SSudarsana Reddy Kalluru 	u8 scsi_tsk_full;
380f240b688SSudarsana Reddy Kalluru 	bool scsi_tsk_full_set;
381f240b688SSudarsana Reddy Kalluru 	u8 scsi_aca_active;
382f240b688SSudarsana Reddy Kalluru 	bool scsi_aca_active_set;
383f240b688SSudarsana Reddy Kalluru 	u8 scsi_tsk_abort;
384f240b688SSudarsana Reddy Kalluru 	bool scsi_tsk_abort_set;
385f240b688SSudarsana Reddy Kalluru 	u32 scsi_rx_chk[5];
386f240b688SSudarsana Reddy Kalluru 	bool scsi_rx_chk_set[5];
387f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time scsi_chk_tstamp[5];
388f240b688SSudarsana Reddy Kalluru };
389f240b688SSudarsana Reddy Kalluru 
39077a509e4SSudarsana Reddy Kalluru struct qed_mfw_tlv_iscsi {
39177a509e4SSudarsana Reddy Kalluru 	u8 target_llmnr;
39277a509e4SSudarsana Reddy Kalluru 	bool target_llmnr_set;
39377a509e4SSudarsana Reddy Kalluru 	u8 header_digest;
39477a509e4SSudarsana Reddy Kalluru 	bool header_digest_set;
39577a509e4SSudarsana Reddy Kalluru 	u8 data_digest;
39677a509e4SSudarsana Reddy Kalluru 	bool data_digest_set;
39777a509e4SSudarsana Reddy Kalluru 	u8 auth_method;
39877a509e4SSudarsana Reddy Kalluru #define QED_MFW_TLV_AUTH_METHOD_NONE            (1)
39977a509e4SSudarsana Reddy Kalluru #define QED_MFW_TLV_AUTH_METHOD_CHAP            (2)
40077a509e4SSudarsana Reddy Kalluru #define QED_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP     (3)
40177a509e4SSudarsana Reddy Kalluru 	bool auth_method_set;
40277a509e4SSudarsana Reddy Kalluru 	u16 boot_taget_portal;
40377a509e4SSudarsana Reddy Kalluru 	bool boot_taget_portal_set;
40477a509e4SSudarsana Reddy Kalluru 	u16 frame_size;
40577a509e4SSudarsana Reddy Kalluru 	bool frame_size_set;
40677a509e4SSudarsana Reddy Kalluru 	u16 tx_desc_size;
40777a509e4SSudarsana Reddy Kalluru 	bool tx_desc_size_set;
40877a509e4SSudarsana Reddy Kalluru 	u16 rx_desc_size;
40977a509e4SSudarsana Reddy Kalluru 	bool rx_desc_size_set;
41077a509e4SSudarsana Reddy Kalluru 	u8 boot_progress;
41177a509e4SSudarsana Reddy Kalluru 	bool boot_progress_set;
41277a509e4SSudarsana Reddy Kalluru 	u16 tx_desc_qdepth;
41377a509e4SSudarsana Reddy Kalluru 	bool tx_desc_qdepth_set;
41477a509e4SSudarsana Reddy Kalluru 	u16 rx_desc_qdepth;
41577a509e4SSudarsana Reddy Kalluru 	bool rx_desc_qdepth_set;
41677a509e4SSudarsana Reddy Kalluru 	u64 rx_frames;
41777a509e4SSudarsana Reddy Kalluru 	bool rx_frames_set;
41877a509e4SSudarsana Reddy Kalluru 	u64 rx_bytes;
41977a509e4SSudarsana Reddy Kalluru 	bool rx_bytes_set;
42077a509e4SSudarsana Reddy Kalluru 	u64 tx_frames;
42177a509e4SSudarsana Reddy Kalluru 	bool tx_frames_set;
42277a509e4SSudarsana Reddy Kalluru 	u64 tx_bytes;
42377a509e4SSudarsana Reddy Kalluru 	bool tx_bytes_set;
42477a509e4SSudarsana Reddy Kalluru };
42577a509e4SSudarsana Reddy Kalluru 
42636907cd5SAriel Elior enum qed_db_rec_width {
42736907cd5SAriel Elior 	DB_REC_WIDTH_32B,
42836907cd5SAriel Elior 	DB_REC_WIDTH_64B,
42936907cd5SAriel Elior };
43036907cd5SAriel Elior 
43136907cd5SAriel Elior enum qed_db_rec_space {
43236907cd5SAriel Elior 	DB_REC_KERNEL,
43336907cd5SAriel Elior 	DB_REC_USER,
43436907cd5SAriel Elior };
43536907cd5SAriel Elior 
436fe56b9e6SYuval Mintz #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
437fe56b9e6SYuval Mintz 					    (void __iomem *)(reg_addr))
438fe56b9e6SYuval Mintz 
439fe56b9e6SYuval Mintz #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
440fe56b9e6SYuval Mintz 
441997af5dfSMichal Kalderon #define DIRECT_REG_WR64(reg_addr, val) writeq((u64)val,	\
44236907cd5SAriel Elior 					      (void __iomem *)(reg_addr))
44336907cd5SAriel Elior 
44441822878SRahul Verma #define QED_COALESCE_MAX 0x1FF
4450e191827SSudarsana Reddy Kalluru #define QED_DEFAULT_RX_USECS 12
446bf5a94bfSRahul Verma #define QED_DEFAULT_TX_USECS 48
447fe56b9e6SYuval Mintz 
448fe56b9e6SYuval Mintz /* forward */
449fe56b9e6SYuval Mintz struct qed_dev;
450fe56b9e6SYuval Mintz 
451fe56b9e6SYuval Mintz struct qed_eth_pf_params {
452fe56b9e6SYuval Mintz 	/* The following parameters are used during HW-init
453fe56b9e6SYuval Mintz 	 * and these parameters need to be passed as arguments
454fe56b9e6SYuval Mintz 	 * to update_pf_params routine invoked before slowpath start
455fe56b9e6SYuval Mintz 	 */
456fe56b9e6SYuval Mintz 	u16 num_cons;
457d51e4af5SChopra, Manish 
45808bc8f15SMintz, Yuval 	/* per-VF number of CIDs */
45908bc8f15SMintz, Yuval 	u8 num_vf_cons;
46008bc8f15SMintz, Yuval #define ETH_PF_PARAMS_VF_CONS_DEFAULT	(32)
46108bc8f15SMintz, Yuval 
462d51e4af5SChopra, Manish 	/* To enable arfs, previous to HW-init a positive number needs to be
463d51e4af5SChopra, Manish 	 * set [as filters require allocated searcher ILT memory].
464d51e4af5SChopra, Manish 	 * This will set the maximal number of configured steering-filters.
465d51e4af5SChopra, Manish 	 */
466d51e4af5SChopra, Manish 	u32 num_arfs_filters;
467fe56b9e6SYuval Mintz };
468fe56b9e6SYuval Mintz 
4691e128c81SArun Easi struct qed_fcoe_pf_params {
4701e128c81SArun Easi 	/* The following parameters are used during protocol-init */
4711e128c81SArun Easi 	u64 glbl_q_params_addr;
4721e128c81SArun Easi 	u64 bdq_pbl_base_addr[2];
4731e128c81SArun Easi 
4741e128c81SArun Easi 	/* The following parameters are used during HW-init
4751e128c81SArun Easi 	 * and these parameters need to be passed as arguments
4761e128c81SArun Easi 	 * to update_pf_params routine invoked before slowpath start
4771e128c81SArun Easi 	 */
4781e128c81SArun Easi 	u16 num_cons;
4791e128c81SArun Easi 	u16 num_tasks;
4801e128c81SArun Easi 
4811e128c81SArun Easi 	/* The following parameters are used during protocol-init */
4821e128c81SArun Easi 	u16 sq_num_pbl_pages;
4831e128c81SArun Easi 
4841e128c81SArun Easi 	u16 cq_num_entries;
4851e128c81SArun Easi 	u16 cmdq_num_entries;
4861e128c81SArun Easi 	u16 rq_buffer_log_size;
4871e128c81SArun Easi 	u16 mtu;
4881e128c81SArun Easi 	u16 dummy_icid;
4891e128c81SArun Easi 	u16 bdq_xoff_threshold[2];
4901e128c81SArun Easi 	u16 bdq_xon_threshold[2];
4911e128c81SArun Easi 	u16 rq_buffer_size;
4921e128c81SArun Easi 	u8 num_cqs;		/* num of global CQs */
4931e128c81SArun Easi 	u8 log_page_size;
4941e128c81SArun Easi 	u8 gl_rq_pi;
4951e128c81SArun Easi 	u8 gl_cmd_pi;
4961e128c81SArun Easi 	u8 debug_mode;
4971e128c81SArun Easi 	u8 is_target;
4981e128c81SArun Easi 	u8 bdq_pbl_num_entries[2];
4991e128c81SArun Easi };
5001e128c81SArun Easi 
5010d80b761SRandy Dunlap /* Most of the parameters below are described in the FW iSCSI / TCP HSI */
502c5ac9319SYuval Mintz struct qed_iscsi_pf_params {
503c5ac9319SYuval Mintz 	u64 glbl_q_params_addr;
504da090917STomer Tayar 	u64 bdq_pbl_base_addr[3];
505c5ac9319SYuval Mintz 	u16 cq_num_entries;
506c5ac9319SYuval Mintz 	u16 cmdq_num_entries;
507fc831825SYuval Mintz 	u32 two_msl_timer;
508c5ac9319SYuval Mintz 	u16 tx_sws_timer;
509c5ac9319SYuval Mintz 
510c5ac9319SYuval Mintz 	/* The following parameters are used during HW-init
511c5ac9319SYuval Mintz 	 * and these parameters need to be passed as arguments
512c5ac9319SYuval Mintz 	 * to update_pf_params routine invoked before slowpath start
513c5ac9319SYuval Mintz 	 */
514c5ac9319SYuval Mintz 	u16 num_cons;
515c5ac9319SYuval Mintz 	u16 num_tasks;
516c5ac9319SYuval Mintz 
517c5ac9319SYuval Mintz 	/* The following parameters are used during protocol-init */
518c5ac9319SYuval Mintz 	u16 half_way_close_timeout;
519da090917STomer Tayar 	u16 bdq_xoff_threshold[3];
520da090917STomer Tayar 	u16 bdq_xon_threshold[3];
521c5ac9319SYuval Mintz 	u16 cmdq_xoff_threshold;
522c5ac9319SYuval Mintz 	u16 cmdq_xon_threshold;
523c5ac9319SYuval Mintz 	u16 rq_buffer_size;
524c5ac9319SYuval Mintz 
525c5ac9319SYuval Mintz 	u8 num_sq_pages_in_ring;
526c5ac9319SYuval Mintz 	u8 num_r2tq_pages_in_ring;
527c5ac9319SYuval Mintz 	u8 num_uhq_pages_in_ring;
528c5ac9319SYuval Mintz 	u8 num_queues;
529c5ac9319SYuval Mintz 	u8 log_page_size;
530c5ac9319SYuval Mintz 	u8 rqe_log_size;
531c5ac9319SYuval Mintz 	u8 max_fin_rt;
532c5ac9319SYuval Mintz 	u8 gl_rq_pi;
533c5ac9319SYuval Mintz 	u8 gl_cmd_pi;
534c5ac9319SYuval Mintz 	u8 debug_mode;
535c5ac9319SYuval Mintz 	u8 ll2_ooo_queue_id;
536c5ac9319SYuval Mintz 
537c5ac9319SYuval Mintz 	u8 is_target;
538da090917STomer Tayar 	u8 is_soc_en;
539da090917STomer Tayar 	u8 soc_num_of_blocks_log;
540da090917STomer Tayar 	u8 bdq_pbl_num_entries[3];
541c5ac9319SYuval Mintz };
542c5ac9319SYuval Mintz 
543c5ac9319SYuval Mintz struct qed_rdma_pf_params {
544c5ac9319SYuval Mintz 	/* Supplied to QED during resource allocation (may affect the ILT and
545c5ac9319SYuval Mintz 	 * the doorbell BAR).
546c5ac9319SYuval Mintz 	 */
547c5ac9319SYuval Mintz 	u32 min_dpis;		/* number of requested DPIs */
548c5ac9319SYuval Mintz 	u32 num_qps;		/* number of requested Queue Pairs */
549c5ac9319SYuval Mintz 	u32 num_srqs;		/* number of requested SRQ */
550c5ac9319SYuval Mintz 	u8 roce_edpm_mode;	/* see QED_ROCE_EDPM_MODE_ENABLE */
551c5ac9319SYuval Mintz 	u8 gl_pi;		/* protocol index */
552c5ac9319SYuval Mintz 
553c5ac9319SYuval Mintz 	/* Will allocate rate limiters to be used with QPs */
554c5ac9319SYuval Mintz 	u8 enable_dcqcn;
555c5ac9319SYuval Mintz };
556c5ac9319SYuval Mintz 
557fe56b9e6SYuval Mintz struct qed_pf_params {
558fe56b9e6SYuval Mintz 	struct qed_eth_pf_params eth_pf_params;
5591e128c81SArun Easi 	struct qed_fcoe_pf_params fcoe_pf_params;
560c5ac9319SYuval Mintz 	struct qed_iscsi_pf_params iscsi_pf_params;
561c5ac9319SYuval Mintz 	struct qed_rdma_pf_params rdma_pf_params;
562fe56b9e6SYuval Mintz };
563fe56b9e6SYuval Mintz 
564fe56b9e6SYuval Mintz enum qed_int_mode {
565fe56b9e6SYuval Mintz 	QED_INT_MODE_INTA,
566fe56b9e6SYuval Mintz 	QED_INT_MODE_MSIX,
567fe56b9e6SYuval Mintz 	QED_INT_MODE_MSI,
568fe56b9e6SYuval Mintz 	QED_INT_MODE_POLL,
569fe56b9e6SYuval Mintz };
570fe56b9e6SYuval Mintz 
571fe56b9e6SYuval Mintz struct qed_sb_info {
57221dd79e8STomer Tayar 	struct status_block_e4 *sb_virt;
573fe56b9e6SYuval Mintz 	dma_addr_t sb_phys;
574fe56b9e6SYuval Mintz 	u32 sb_ack; /* Last given ack */
575fe56b9e6SYuval Mintz 	u16 igu_sb_id;
576fe56b9e6SYuval Mintz 	void __iomem *igu_addr;
577fe56b9e6SYuval Mintz 	u8 flags;
578fe56b9e6SYuval Mintz #define QED_SB_INFO_INIT	0x1
579fe56b9e6SYuval Mintz #define QED_SB_INFO_SETUP	0x2
580fe56b9e6SYuval Mintz 
581fe56b9e6SYuval Mintz 	struct qed_dev *cdev;
582fe56b9e6SYuval Mintz };
583fe56b9e6SYuval Mintz 
584d639836aSIgor Russkikh enum qed_hw_err_type {
585d639836aSIgor Russkikh 	QED_HW_ERR_FAN_FAIL,
586d639836aSIgor Russkikh 	QED_HW_ERR_MFW_RESP_FAIL,
587d639836aSIgor Russkikh 	QED_HW_ERR_HW_ATTN,
588d639836aSIgor Russkikh 	QED_HW_ERR_DMAE_FAIL,
589d639836aSIgor Russkikh 	QED_HW_ERR_RAMROD_FAIL,
590d639836aSIgor Russkikh 	QED_HW_ERR_FW_ASSERT,
591d639836aSIgor Russkikh 	QED_HW_ERR_LAST,
592d639836aSIgor Russkikh };
593d639836aSIgor Russkikh 
5949c79ddaaSMintz, Yuval enum qed_dev_type {
5959c79ddaaSMintz, Yuval 	QED_DEV_TYPE_BB,
5969c79ddaaSMintz, Yuval 	QED_DEV_TYPE_AH,
597*99785a87SAlexander Lobakin 	QED_DEV_TYPE_E5,
5989c79ddaaSMintz, Yuval };
5999c79ddaaSMintz, Yuval 
600fe56b9e6SYuval Mintz struct qed_dev_info {
601fe56b9e6SYuval Mintz 	unsigned long	pci_mem_start;
602fe56b9e6SYuval Mintz 	unsigned long	pci_mem_end;
603fe56b9e6SYuval Mintz 	unsigned int	pci_irq;
604fe56b9e6SYuval Mintz 	u8		num_hwfns;
605fe56b9e6SYuval Mintz 
606fe56b9e6SYuval Mintz 	u8		hw_mac[ETH_ALEN];
607fe56b9e6SYuval Mintz 
608fe56b9e6SYuval Mintz 	/* FW version */
609fe56b9e6SYuval Mintz 	u16		fw_major;
610fe56b9e6SYuval Mintz 	u16		fw_minor;
611fe56b9e6SYuval Mintz 	u16		fw_rev;
612fe56b9e6SYuval Mintz 	u16		fw_eng;
613fe56b9e6SYuval Mintz 
614fe56b9e6SYuval Mintz 	/* MFW version */
615fe56b9e6SYuval Mintz 	u32		mfw_rev;
616ae33666aSTomer Tayar #define QED_MFW_VERSION_0_MASK		0x000000FF
617ae33666aSTomer Tayar #define QED_MFW_VERSION_0_OFFSET	0
618ae33666aSTomer Tayar #define QED_MFW_VERSION_1_MASK		0x0000FF00
619ae33666aSTomer Tayar #define QED_MFW_VERSION_1_OFFSET	8
620ae33666aSTomer Tayar #define QED_MFW_VERSION_2_MASK		0x00FF0000
621ae33666aSTomer Tayar #define QED_MFW_VERSION_2_OFFSET	16
622ae33666aSTomer Tayar #define QED_MFW_VERSION_3_MASK		0xFF000000
623ae33666aSTomer Tayar #define QED_MFW_VERSION_3_OFFSET	24
624fe56b9e6SYuval Mintz 
625fe56b9e6SYuval Mintz 	u32		flash_size;
6260bc5fe85SSudarsana Reddy Kalluru 	bool		b_inter_pf_switch;
627831bfb0eSYuval Mintz 	bool		tx_switching;
628cee9fbd8SRam Amrani 	bool		rdma_supported;
6290fefbfbaSSudarsana Kalluru 	u16		mtu;
63014d39648SMintz, Yuval 
63114d39648SMintz, Yuval 	bool wol_support;
632df9c716dSSudarsana Reddy Kalluru 	bool smart_an;
6339c79ddaaSMintz, Yuval 
634ae33666aSTomer Tayar 	/* MBI version */
635ae33666aSTomer Tayar 	u32 mbi_version;
636ae33666aSTomer Tayar #define QED_MBI_VERSION_0_MASK		0x000000FF
637ae33666aSTomer Tayar #define QED_MBI_VERSION_0_OFFSET	0
638ae33666aSTomer Tayar #define QED_MBI_VERSION_1_MASK		0x0000FF00
639ae33666aSTomer Tayar #define QED_MBI_VERSION_1_OFFSET	8
640ae33666aSTomer Tayar #define QED_MBI_VERSION_2_MASK		0x00FF0000
641ae33666aSTomer Tayar #define QED_MBI_VERSION_2_OFFSET	16
642ae33666aSTomer Tayar 
6439c79ddaaSMintz, Yuval 	enum qed_dev_type dev_type;
64419489c7fSChopra, Manish 
64519489c7fSChopra, Manish 	/* Output parameters for qede */
64619489c7fSChopra, Manish 	bool		vxlan_enable;
64719489c7fSChopra, Manish 	bool		gre_enable;
64819489c7fSChopra, Manish 	bool		geneve_enable;
6493c5da942SMintz, Yuval 
6503c5da942SMintz, Yuval 	u8		abs_pf_id;
651fe56b9e6SYuval Mintz };
652fe56b9e6SYuval Mintz 
653fe56b9e6SYuval Mintz enum qed_sb_type {
654fe56b9e6SYuval Mintz 	QED_SB_TYPE_L2_QUEUE,
65551ff1725SRam Amrani 	QED_SB_TYPE_CNQ,
656fc831825SYuval Mintz 	QED_SB_TYPE_STORAGE,
657fe56b9e6SYuval Mintz };
658fe56b9e6SYuval Mintz 
659fe56b9e6SYuval Mintz enum qed_protocol {
660fe56b9e6SYuval Mintz 	QED_PROTOCOL_ETH,
661c5ac9319SYuval Mintz 	QED_PROTOCOL_ISCSI,
6621e128c81SArun Easi 	QED_PROTOCOL_FCOE,
663fe56b9e6SYuval Mintz };
664fe56b9e6SYuval Mintz 
665ae7e6937SAlexander Lobakin enum qed_fec_mode {
666ae7e6937SAlexander Lobakin 	QED_FEC_MODE_NONE			= BIT(0),
667ae7e6937SAlexander Lobakin 	QED_FEC_MODE_FIRECODE			= BIT(1),
668ae7e6937SAlexander Lobakin 	QED_FEC_MODE_RS				= BIT(2),
669ae7e6937SAlexander Lobakin 	QED_FEC_MODE_AUTO			= BIT(3),
670ae7e6937SAlexander Lobakin 	QED_FEC_MODE_UNSUPPORTED		= BIT(4),
671ae7e6937SAlexander Lobakin };
672ae7e6937SAlexander Lobakin 
673fe56b9e6SYuval Mintz struct qed_link_params {
674fe56b9e6SYuval Mintz 	bool					link_up;
675fe56b9e6SYuval Mintz 
67637237b5bSAlexander Lobakin 	u32					override_flags;
677fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_AUTONEG		BIT(0)
678fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS	BIT(1)
679fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED	BIT(2)
680fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_PAUSE_CONFIG		BIT(3)
68103dc76caSSudarsana Reddy Kalluru #define QED_LINK_OVERRIDE_LOOPBACK_MODE		BIT(4)
682645874e5SSudarsana Reddy Kalluru #define QED_LINK_OVERRIDE_EEE_CONFIG		BIT(5)
683ae7e6937SAlexander Lobakin #define QED_LINK_OVERRIDE_FEC_CONFIG		BIT(6)
68437237b5bSAlexander Lobakin 
685fe56b9e6SYuval Mintz 	bool					autoneg;
686bdb5d8ecSAlexander Lobakin 	__ETHTOOL_DECLARE_LINK_MODE_MASK(adv_speeds);
687fe56b9e6SYuval Mintz 	u32					forced_speed;
68837237b5bSAlexander Lobakin 
68937237b5bSAlexander Lobakin 	u32					pause_config;
690fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_AUTONEG_ENABLE		BIT(0)
691fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_RX_ENABLE		BIT(1)
692fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_TX_ENABLE		BIT(2)
69337237b5bSAlexander Lobakin 
69437237b5bSAlexander Lobakin 	u32					loopback_mode;
69503dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_NONE			BIT(0)
69603dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_INT_PHY		BIT(1)
69703dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_EXT_PHY		BIT(2)
69803dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_EXT			BIT(3)
69903dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_MAC			BIT(4)
70098e675ecSAlexander Lobakin #define QED_LINK_LOOPBACK_CNIG_AH_ONLY_0123	BIT(5)
70198e675ecSAlexander Lobakin #define QED_LINK_LOOPBACK_CNIG_AH_ONLY_2301	BIT(6)
70298e675ecSAlexander Lobakin #define QED_LINK_LOOPBACK_PCS_AH_ONLY		BIT(7)
70398e675ecSAlexander Lobakin #define QED_LINK_LOOPBACK_REVERSE_MAC_AH_ONLY	BIT(8)
70498e675ecSAlexander Lobakin #define QED_LINK_LOOPBACK_INT_PHY_FEA_AH_ONLY	BIT(9)
70537237b5bSAlexander Lobakin 
706645874e5SSudarsana Reddy Kalluru 	struct qed_link_eee_params		eee;
707ae7e6937SAlexander Lobakin 	u32					fec;
708fe56b9e6SYuval Mintz };
709fe56b9e6SYuval Mintz 
710fe56b9e6SYuval Mintz struct qed_link_output {
711fe56b9e6SYuval Mintz 	bool					link_up;
712fe56b9e6SYuval Mintz 
713bdb5d8ecSAlexander Lobakin 	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported_caps);
714bdb5d8ecSAlexander Lobakin 	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertised_caps);
715bdb5d8ecSAlexander Lobakin 	__ETHTOOL_DECLARE_LINK_MODE_MASK(lp_caps);
716d194fd26SYuval Mintz 
717fe56b9e6SYuval Mintz 	u32					speed;	   /* In Mb/s */
718fe56b9e6SYuval Mintz 	u8					duplex;	   /* In DUPLEX defs */
719fe56b9e6SYuval Mintz 	u8					port;	   /* In PORT defs */
720fe56b9e6SYuval Mintz 	bool					autoneg;
721fe56b9e6SYuval Mintz 	u32					pause_config;
722645874e5SSudarsana Reddy Kalluru 
723645874e5SSudarsana Reddy Kalluru 	/* EEE - capability & param */
724645874e5SSudarsana Reddy Kalluru 	bool					eee_supported;
725645874e5SSudarsana Reddy Kalluru 	bool					eee_active;
726645874e5SSudarsana Reddy Kalluru 	u8					sup_caps;
727645874e5SSudarsana Reddy Kalluru 	struct qed_link_eee_params		eee;
728ae7e6937SAlexander Lobakin 
729ae7e6937SAlexander Lobakin 	u32					sup_fec;
730ae7e6937SAlexander Lobakin 	u32					active_fec;
731fe56b9e6SYuval Mintz };
732fe56b9e6SYuval Mintz 
7331408cc1fSYuval Mintz struct qed_probe_params {
7341408cc1fSYuval Mintz 	enum qed_protocol protocol;
7351408cc1fSYuval Mintz 	u32 dp_module;
7361408cc1fSYuval Mintz 	u8 dp_level;
7371408cc1fSYuval Mintz 	bool is_vf;
73864515dc8STomer Tayar 	bool recov_in_prog;
7391408cc1fSYuval Mintz };
7401408cc1fSYuval Mintz 
741fe56b9e6SYuval Mintz #define QED_DRV_VER_STR_SIZE 12
742fe56b9e6SYuval Mintz struct qed_slowpath_params {
743fe56b9e6SYuval Mintz 	u32	int_mode;
744fe56b9e6SYuval Mintz 	u8	drv_major;
745fe56b9e6SYuval Mintz 	u8	drv_minor;
746fe56b9e6SYuval Mintz 	u8	drv_rev;
747fe56b9e6SYuval Mintz 	u8	drv_eng;
748fe56b9e6SYuval Mintz 	u8	name[QED_DRV_VER_STR_SIZE];
749fe56b9e6SYuval Mintz };
750fe56b9e6SYuval Mintz 
751fe56b9e6SYuval Mintz #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
752fe56b9e6SYuval Mintz 
753fe56b9e6SYuval Mintz struct qed_int_info {
754fe56b9e6SYuval Mintz 	struct msix_entry	*msix;
755fe56b9e6SYuval Mintz 	u8			msix_cnt;
756fe56b9e6SYuval Mintz 
757fe56b9e6SYuval Mintz 	/* This should be updated by the protocol driver */
758fe56b9e6SYuval Mintz 	u8			used_cnt;
759fe56b9e6SYuval Mintz };
760fe56b9e6SYuval Mintz 
76159ccf86fSSudarsana Reddy Kalluru struct qed_generic_tlvs {
76259ccf86fSSudarsana Reddy Kalluru #define QED_TLV_IP_CSUM         BIT(0)
76359ccf86fSSudarsana Reddy Kalluru #define QED_TLV_LSO             BIT(1)
76459ccf86fSSudarsana Reddy Kalluru 	u16 feat_flags;
76559ccf86fSSudarsana Reddy Kalluru #define QED_TLV_MAC_COUNT	3
76659ccf86fSSudarsana Reddy Kalluru 	u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN];
76759ccf86fSSudarsana Reddy Kalluru };
76859ccf86fSSudarsana Reddy Kalluru 
769b51dab46SSudarsana Reddy Kalluru #define QED_I2C_DEV_ADDR_A0 0xA0
770b51dab46SSudarsana Reddy Kalluru #define QED_I2C_DEV_ADDR_A2 0xA2
771b51dab46SSudarsana Reddy Kalluru 
7723a69cae8SSudarsana Reddy Kalluru #define QED_NVM_SIGNATURE 0x12435687
7733a69cae8SSudarsana Reddy Kalluru 
7743a69cae8SSudarsana Reddy Kalluru enum qed_nvm_flash_cmd {
7753a69cae8SSudarsana Reddy Kalluru 	QED_NVM_FLASH_CMD_FILE_DATA = 0x2,
7763a69cae8SSudarsana Reddy Kalluru 	QED_NVM_FLASH_CMD_FILE_START = 0x3,
7773a69cae8SSudarsana Reddy Kalluru 	QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4,
7780dabbe1bSSudarsana Reddy Kalluru 	QED_NVM_FLASH_CMD_NVM_CFG_ID = 0x5,
7793a69cae8SSudarsana Reddy Kalluru 	QED_NVM_FLASH_CMD_NVM_MAX,
7803a69cae8SSudarsana Reddy Kalluru };
7813a69cae8SSudarsana Reddy Kalluru 
782fe56b9e6SYuval Mintz struct qed_common_cb_ops {
783d51e4af5SChopra, Manish 	void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc);
7848f76812eSIgor Russkikh 	void (*link_update)(void *dev, struct qed_link_output *link);
78564515dc8STomer Tayar 	void (*schedule_recovery_handler)(void *dev);
786d639836aSIgor Russkikh 	void (*schedule_hw_err_handler)(void *dev,
787d639836aSIgor Russkikh 					enum qed_hw_err_type err_type);
7881e128c81SArun Easi 	void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
78959ccf86fSSudarsana Reddy Kalluru 	void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data);
79059ccf86fSSudarsana Reddy Kalluru 	void (*get_protocol_tlv_data)(void *dev, void *data);
791699fed4aSSudarsana Reddy Kalluru 	void (*bw_update)(void *dev);
792fe56b9e6SYuval Mintz };
793fe56b9e6SYuval Mintz 
79403dc76caSSudarsana Reddy Kalluru struct qed_selftest_ops {
79503dc76caSSudarsana Reddy Kalluru /**
79603dc76caSSudarsana Reddy Kalluru  * @brief selftest_interrupt - Perform interrupt test
79703dc76caSSudarsana Reddy Kalluru  *
79803dc76caSSudarsana Reddy Kalluru  * @param cdev
79903dc76caSSudarsana Reddy Kalluru  *
80003dc76caSSudarsana Reddy Kalluru  * @return 0 on success, error otherwise.
80103dc76caSSudarsana Reddy Kalluru  */
80203dc76caSSudarsana Reddy Kalluru 	int (*selftest_interrupt)(struct qed_dev *cdev);
80303dc76caSSudarsana Reddy Kalluru 
80403dc76caSSudarsana Reddy Kalluru /**
80503dc76caSSudarsana Reddy Kalluru  * @brief selftest_memory - Perform memory test
80603dc76caSSudarsana Reddy Kalluru  *
80703dc76caSSudarsana Reddy Kalluru  * @param cdev
80803dc76caSSudarsana Reddy Kalluru  *
80903dc76caSSudarsana Reddy Kalluru  * @return 0 on success, error otherwise.
81003dc76caSSudarsana Reddy Kalluru  */
81103dc76caSSudarsana Reddy Kalluru 	int (*selftest_memory)(struct qed_dev *cdev);
81203dc76caSSudarsana Reddy Kalluru 
81303dc76caSSudarsana Reddy Kalluru /**
81403dc76caSSudarsana Reddy Kalluru  * @brief selftest_register - Perform register test
81503dc76caSSudarsana Reddy Kalluru  *
81603dc76caSSudarsana Reddy Kalluru  * @param cdev
81703dc76caSSudarsana Reddy Kalluru  *
81803dc76caSSudarsana Reddy Kalluru  * @return 0 on success, error otherwise.
81903dc76caSSudarsana Reddy Kalluru  */
82003dc76caSSudarsana Reddy Kalluru 	int (*selftest_register)(struct qed_dev *cdev);
82103dc76caSSudarsana Reddy Kalluru 
82203dc76caSSudarsana Reddy Kalluru /**
82303dc76caSSudarsana Reddy Kalluru  * @brief selftest_clock - Perform clock test
82403dc76caSSudarsana Reddy Kalluru  *
82503dc76caSSudarsana Reddy Kalluru  * @param cdev
82603dc76caSSudarsana Reddy Kalluru  *
82703dc76caSSudarsana Reddy Kalluru  * @return 0 on success, error otherwise.
82803dc76caSSudarsana Reddy Kalluru  */
82903dc76caSSudarsana Reddy Kalluru 	int (*selftest_clock)(struct qed_dev *cdev);
8307a4b21b7SMintz, Yuval 
8317a4b21b7SMintz, Yuval /**
8327a4b21b7SMintz, Yuval  * @brief selftest_nvram - Perform nvram test
8337a4b21b7SMintz, Yuval  *
8347a4b21b7SMintz, Yuval  * @param cdev
8357a4b21b7SMintz, Yuval  *
8367a4b21b7SMintz, Yuval  * @return 0 on success, error otherwise.
8377a4b21b7SMintz, Yuval  */
8387a4b21b7SMintz, Yuval 	int (*selftest_nvram) (struct qed_dev *cdev);
83903dc76caSSudarsana Reddy Kalluru };
84003dc76caSSudarsana Reddy Kalluru 
841fe56b9e6SYuval Mintz struct qed_common_ops {
84203dc76caSSudarsana Reddy Kalluru 	struct qed_selftest_ops *selftest;
84303dc76caSSudarsana Reddy Kalluru 
844fe56b9e6SYuval Mintz 	struct qed_dev*	(*probe)(struct pci_dev *dev,
8451408cc1fSYuval Mintz 				 struct qed_probe_params *params);
846fe56b9e6SYuval Mintz 
847fe56b9e6SYuval Mintz 	void		(*remove)(struct qed_dev *cdev);
848fe56b9e6SYuval Mintz 
849fe56b9e6SYuval Mintz 	int		(*set_power_state)(struct qed_dev *cdev,
850fe56b9e6SYuval Mintz 					   pci_power_t state);
851fe56b9e6SYuval Mintz 
852712c3cbfSMintz, Yuval 	void (*set_name) (struct qed_dev *cdev, char name[]);
853fe56b9e6SYuval Mintz 
854fe56b9e6SYuval Mintz 	/* Client drivers need to make this call before slowpath_start.
855fe56b9e6SYuval Mintz 	 * PF params required for the call before slowpath_start is
856fe56b9e6SYuval Mintz 	 * documented within the qed_pf_params structure definition.
857fe56b9e6SYuval Mintz 	 */
858fe56b9e6SYuval Mintz 	void		(*update_pf_params)(struct qed_dev *cdev,
859fe56b9e6SYuval Mintz 					    struct qed_pf_params *params);
860fe56b9e6SYuval Mintz 	int		(*slowpath_start)(struct qed_dev *cdev,
861fe56b9e6SYuval Mintz 					  struct qed_slowpath_params *params);
862fe56b9e6SYuval Mintz 
863fe56b9e6SYuval Mintz 	int		(*slowpath_stop)(struct qed_dev *cdev);
864fe56b9e6SYuval Mintz 
865fe56b9e6SYuval Mintz 	/* Requests to use `cnt' interrupts for fastpath.
866fe56b9e6SYuval Mintz 	 * upon success, returns number of interrupts allocated for fastpath.
867fe56b9e6SYuval Mintz 	 */
868fe56b9e6SYuval Mintz 	int		(*set_fp_int)(struct qed_dev *cdev,
869fe56b9e6SYuval Mintz 				      u16 cnt);
870fe56b9e6SYuval Mintz 
871fe56b9e6SYuval Mintz 	/* Fills `info' with pointers required for utilizing interrupts */
872fe56b9e6SYuval Mintz 	int		(*get_fp_int)(struct qed_dev *cdev,
873fe56b9e6SYuval Mintz 				      struct qed_int_info *info);
874fe56b9e6SYuval Mintz 
875fe56b9e6SYuval Mintz 	u32		(*sb_init)(struct qed_dev *cdev,
876fe56b9e6SYuval Mintz 				   struct qed_sb_info *sb_info,
877fe56b9e6SYuval Mintz 				   void *sb_virt_addr,
878fe56b9e6SYuval Mintz 				   dma_addr_t sb_phy_addr,
879fe56b9e6SYuval Mintz 				   u16 sb_id,
880fe56b9e6SYuval Mintz 				   enum qed_sb_type type);
881fe56b9e6SYuval Mintz 
882fe56b9e6SYuval Mintz 	u32		(*sb_release)(struct qed_dev *cdev,
883fe56b9e6SYuval Mintz 				      struct qed_sb_info *sb_info,
88408eb1fb0SMichal Kalderon 				      u16 sb_id,
88508eb1fb0SMichal Kalderon 				      enum qed_sb_type type);
886fe56b9e6SYuval Mintz 
887fe56b9e6SYuval Mintz 	void		(*simd_handler_config)(struct qed_dev *cdev,
888fe56b9e6SYuval Mintz 					       void *token,
889fe56b9e6SYuval Mintz 					       int index,
890fe56b9e6SYuval Mintz 					       void (*handler)(void *));
891fe56b9e6SYuval Mintz 
892fe56b9e6SYuval Mintz 	void		(*simd_handler_clean)(struct qed_dev *cdev,
893fe56b9e6SYuval Mintz 					      int index);
8941e128c81SArun Easi 	int (*dbg_grc)(struct qed_dev *cdev,
8951e128c81SArun Easi 		       void *buffer, u32 *num_dumped_bytes);
8961e128c81SArun Easi 
8971e128c81SArun Easi 	int (*dbg_grc_size)(struct qed_dev *cdev);
898fe7cd2bfSYuval Mintz 
899e0971c83STomer Tayar 	int (*dbg_all_data) (struct qed_dev *cdev, void *buffer);
900e0971c83STomer Tayar 
901e0971c83STomer Tayar 	int (*dbg_all_data_size) (struct qed_dev *cdev);
902e0971c83STomer Tayar 
903fe7cd2bfSYuval Mintz /**
904fe7cd2bfSYuval Mintz  * @brief can_link_change - can the instance change the link or not
905fe7cd2bfSYuval Mintz  *
906fe7cd2bfSYuval Mintz  * @param cdev
907fe7cd2bfSYuval Mintz  *
908fe7cd2bfSYuval Mintz  * @return true if link-change is allowed, false otherwise.
909fe7cd2bfSYuval Mintz  */
910fe7cd2bfSYuval Mintz 	bool (*can_link_change)(struct qed_dev *cdev);
911fe7cd2bfSYuval Mintz 
912fe56b9e6SYuval Mintz /**
913fe56b9e6SYuval Mintz  * @brief set_link - set links according to params
914fe56b9e6SYuval Mintz  *
915fe56b9e6SYuval Mintz  * @param cdev
916fe56b9e6SYuval Mintz  * @param params - values used to override the default link configuration
917fe56b9e6SYuval Mintz  *
918fe56b9e6SYuval Mintz  * @return 0 on success, error otherwise.
919fe56b9e6SYuval Mintz  */
920fe56b9e6SYuval Mintz 	int		(*set_link)(struct qed_dev *cdev,
921fe56b9e6SYuval Mintz 				    struct qed_link_params *params);
922fe56b9e6SYuval Mintz 
923fe56b9e6SYuval Mintz /**
924fe56b9e6SYuval Mintz  * @brief get_link - returns the current link state.
925fe56b9e6SYuval Mintz  *
926fe56b9e6SYuval Mintz  * @param cdev
927fe56b9e6SYuval Mintz  * @param if_link - structure to be filled with current link configuration.
928fe56b9e6SYuval Mintz  */
929fe56b9e6SYuval Mintz 	void		(*get_link)(struct qed_dev *cdev,
930fe56b9e6SYuval Mintz 				    struct qed_link_output *if_link);
931fe56b9e6SYuval Mintz 
932fe56b9e6SYuval Mintz /**
933fe56b9e6SYuval Mintz  * @brief - drains chip in case Tx completions fail to arrive due to pause.
934fe56b9e6SYuval Mintz  *
935fe56b9e6SYuval Mintz  * @param cdev
936fe56b9e6SYuval Mintz  */
937fe56b9e6SYuval Mintz 	int		(*drain)(struct qed_dev *cdev);
938fe56b9e6SYuval Mintz 
939fe56b9e6SYuval Mintz /**
940fe56b9e6SYuval Mintz  * @brief update_msglvl - update module debug level
941fe56b9e6SYuval Mintz  *
942fe56b9e6SYuval Mintz  * @param cdev
943fe56b9e6SYuval Mintz  * @param dp_module
944fe56b9e6SYuval Mintz  * @param dp_level
945fe56b9e6SYuval Mintz  */
946fe56b9e6SYuval Mintz 	void		(*update_msglvl)(struct qed_dev *cdev,
947fe56b9e6SYuval Mintz 					 u32 dp_module,
948fe56b9e6SYuval Mintz 					 u8 dp_level);
949fe56b9e6SYuval Mintz 
950fe56b9e6SYuval Mintz 	int		(*chain_alloc)(struct qed_dev *cdev,
951fe56b9e6SYuval Mintz 				       enum qed_chain_use_mode intended_use,
952fe56b9e6SYuval Mintz 				       enum qed_chain_mode mode,
953a91eb52aSYuval Mintz 				       enum qed_chain_cnt_type cnt_type,
954a91eb52aSYuval Mintz 				       u32 num_elems,
955fe56b9e6SYuval Mintz 				       size_t elem_size,
9561a4a6975SMintz, Yuval 				       struct qed_chain *p_chain,
9571a4a6975SMintz, Yuval 				       struct qed_chain_ext_pbl *ext_pbl);
958fe56b9e6SYuval Mintz 
959fe56b9e6SYuval Mintz 	void		(*chain_free)(struct qed_dev *cdev,
960fe56b9e6SYuval Mintz 				      struct qed_chain *p_chain);
96191420b83SSudarsana Kalluru 
96291420b83SSudarsana Kalluru /**
9633a69cae8SSudarsana Reddy Kalluru  * @brief nvm_flash - Flash nvm data.
9643a69cae8SSudarsana Reddy Kalluru  *
9653a69cae8SSudarsana Reddy Kalluru  * @param cdev
9663a69cae8SSudarsana Reddy Kalluru  * @param name - file containing the data
9673a69cae8SSudarsana Reddy Kalluru  *
9683a69cae8SSudarsana Reddy Kalluru  * @return 0 on success, error otherwise.
9693a69cae8SSudarsana Reddy Kalluru  */
9703a69cae8SSudarsana Reddy Kalluru 	int (*nvm_flash)(struct qed_dev *cdev, const char *name);
9713a69cae8SSudarsana Reddy Kalluru 
9723a69cae8SSudarsana Reddy Kalluru /**
97320675b37SMintz, Yuval  * @brief nvm_get_image - reads an entire image from nvram
97420675b37SMintz, Yuval  *
97520675b37SMintz, Yuval  * @param cdev
97620675b37SMintz, Yuval  * @param type - type of the request nvram image
97720675b37SMintz, Yuval  * @param buf - preallocated buffer to fill with the image
97820675b37SMintz, Yuval  * @param len - length of the allocated buffer
97920675b37SMintz, Yuval  *
98020675b37SMintz, Yuval  * @return 0 on success, error otherwise
98120675b37SMintz, Yuval  */
98220675b37SMintz, Yuval 	int (*nvm_get_image)(struct qed_dev *cdev,
98320675b37SMintz, Yuval 			     enum qed_nvm_images type, u8 *buf, u16 len);
98420675b37SMintz, Yuval 
98520675b37SMintz, Yuval /**
986722003acSSudarsana Reddy Kalluru  * @brief set_coalesce - Configure Rx coalesce value in usec
987722003acSSudarsana Reddy Kalluru  *
988722003acSSudarsana Reddy Kalluru  * @param cdev
989722003acSSudarsana Reddy Kalluru  * @param rx_coal - Rx coalesce value in usec
990722003acSSudarsana Reddy Kalluru  * @param tx_coal - Tx coalesce value in usec
991722003acSSudarsana Reddy Kalluru  * @param qid - Queue index
992722003acSSudarsana Reddy Kalluru  * @param sb_id - Status Block Id
993722003acSSudarsana Reddy Kalluru  *
994722003acSSudarsana Reddy Kalluru  * @return 0 on success, error otherwise.
995722003acSSudarsana Reddy Kalluru  */
996477f2d14SRahul Verma 	int (*set_coalesce)(struct qed_dev *cdev,
997477f2d14SRahul Verma 			    u16 rx_coal, u16 tx_coal, void *handle);
998722003acSSudarsana Reddy Kalluru 
999722003acSSudarsana Reddy Kalluru /**
100091420b83SSudarsana Kalluru  * @brief set_led - Configure LED mode
100191420b83SSudarsana Kalluru  *
100291420b83SSudarsana Kalluru  * @param cdev
100391420b83SSudarsana Kalluru  * @param mode - LED mode
100491420b83SSudarsana Kalluru  *
100591420b83SSudarsana Kalluru  * @return 0 on success, error otherwise.
100691420b83SSudarsana Kalluru  */
100791420b83SSudarsana Kalluru 	int (*set_led)(struct qed_dev *cdev,
100891420b83SSudarsana Kalluru 		       enum qed_led_mode mode);
1009936c7ba4SIgor Russkikh 
1010936c7ba4SIgor Russkikh /**
1011936c7ba4SIgor Russkikh  * @brief attn_clr_enable - Prevent attentions from being reasserted
1012936c7ba4SIgor Russkikh  *
1013936c7ba4SIgor Russkikh  * @param cdev
1014936c7ba4SIgor Russkikh  * @param clr_enable
1015936c7ba4SIgor Russkikh  */
1016936c7ba4SIgor Russkikh 	void (*attn_clr_enable)(struct qed_dev *cdev, bool clr_enable);
1017936c7ba4SIgor Russkikh 
10180e1f1044SAriel Elior /**
10190e1f1044SAriel Elior  * @brief db_recovery_add - add doorbell information to the doorbell
10200e1f1044SAriel Elior  * recovery mechanism.
10210e1f1044SAriel Elior  *
10220e1f1044SAriel Elior  * @param cdev
10230e1f1044SAriel Elior  * @param db_addr - doorbell address
10240e1f1044SAriel Elior  * @param db_data - address of where db_data is stored
10250e1f1044SAriel Elior  * @param db_is_32b - doorbell is 32b pr 64b
10260e1f1044SAriel Elior  * @param db_is_user - doorbell recovery addresses are user or kernel space
10270e1f1044SAriel Elior  */
10280e1f1044SAriel Elior 	int (*db_recovery_add)(struct qed_dev *cdev,
10290e1f1044SAriel Elior 			       void __iomem *db_addr,
10300e1f1044SAriel Elior 			       void *db_data,
10310e1f1044SAriel Elior 			       enum qed_db_rec_width db_width,
10320e1f1044SAriel Elior 			       enum qed_db_rec_space db_space);
10330e1f1044SAriel Elior 
10340e1f1044SAriel Elior /**
10350e1f1044SAriel Elior  * @brief db_recovery_del - remove doorbell information from the doorbell
10360e1f1044SAriel Elior  * recovery mechanism. db_data serves as key (db_addr is not unique).
10370e1f1044SAriel Elior  *
10380e1f1044SAriel Elior  * @param cdev
10390e1f1044SAriel Elior  * @param db_addr - doorbell address
10400e1f1044SAriel Elior  * @param db_data - address where db_data is stored. Serves as key for the
10410e1f1044SAriel Elior  *		    entry to delete.
10420e1f1044SAriel Elior  */
10430e1f1044SAriel Elior 	int (*db_recovery_del)(struct qed_dev *cdev,
10440e1f1044SAriel Elior 			       void __iomem *db_addr, void *db_data);
10450fefbfbaSSudarsana Kalluru 
10460fefbfbaSSudarsana Kalluru /**
104764515dc8STomer Tayar  * @brief recovery_process - Trigger a recovery process
104864515dc8STomer Tayar  *
104964515dc8STomer Tayar  * @param cdev
105064515dc8STomer Tayar  *
105164515dc8STomer Tayar  * @return 0 on success, error otherwise.
105264515dc8STomer Tayar  */
105364515dc8STomer Tayar 	int (*recovery_process)(struct qed_dev *cdev);
105464515dc8STomer Tayar 
105564515dc8STomer Tayar /**
105664515dc8STomer Tayar  * @brief recovery_prolog - Execute the prolog operations of a recovery process
105764515dc8STomer Tayar  *
105864515dc8STomer Tayar  * @param cdev
105964515dc8STomer Tayar  *
106064515dc8STomer Tayar  * @return 0 on success, error otherwise.
106164515dc8STomer Tayar  */
106264515dc8STomer Tayar 	int (*recovery_prolog)(struct qed_dev *cdev);
106364515dc8STomer Tayar 
106464515dc8STomer Tayar /**
10650fefbfbaSSudarsana Kalluru  * @brief update_drv_state - API to inform the change in the driver state.
10660fefbfbaSSudarsana Kalluru  *
10670fefbfbaSSudarsana Kalluru  * @param cdev
10680fefbfbaSSudarsana Kalluru  * @param active
10690fefbfbaSSudarsana Kalluru  *
10700fefbfbaSSudarsana Kalluru  */
10710fefbfbaSSudarsana Kalluru 	int (*update_drv_state)(struct qed_dev *cdev, bool active);
10720fefbfbaSSudarsana Kalluru 
10730fefbfbaSSudarsana Kalluru /**
10740fefbfbaSSudarsana Kalluru  * @brief update_mac - API to inform the change in the mac address
10750fefbfbaSSudarsana Kalluru  *
10760fefbfbaSSudarsana Kalluru  * @param cdev
10770fefbfbaSSudarsana Kalluru  * @param mac
10780fefbfbaSSudarsana Kalluru  *
10790fefbfbaSSudarsana Kalluru  */
10800fefbfbaSSudarsana Kalluru 	int (*update_mac)(struct qed_dev *cdev, u8 *mac);
10810fefbfbaSSudarsana Kalluru 
10820fefbfbaSSudarsana Kalluru /**
10830fefbfbaSSudarsana Kalluru  * @brief update_mtu - API to inform the change in the mtu
10840fefbfbaSSudarsana Kalluru  *
10850fefbfbaSSudarsana Kalluru  * @param cdev
10860fefbfbaSSudarsana Kalluru  * @param mtu
10870fefbfbaSSudarsana Kalluru  *
10880fefbfbaSSudarsana Kalluru  */
10890fefbfbaSSudarsana Kalluru 	int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
109014d39648SMintz, Yuval 
109114d39648SMintz, Yuval /**
109214d39648SMintz, Yuval  * @brief update_wol - update of changes in the WoL configuration
109314d39648SMintz, Yuval  *
109414d39648SMintz, Yuval  * @param cdev
109514d39648SMintz, Yuval  * @param enabled - true iff WoL should be enabled.
109614d39648SMintz, Yuval  */
109714d39648SMintz, Yuval 	int (*update_wol) (struct qed_dev *cdev, bool enabled);
1098b51dab46SSudarsana Reddy Kalluru 
1099b51dab46SSudarsana Reddy Kalluru /**
1100b51dab46SSudarsana Reddy Kalluru  * @brief read_module_eeprom
1101b51dab46SSudarsana Reddy Kalluru  *
1102b51dab46SSudarsana Reddy Kalluru  * @param cdev
1103b51dab46SSudarsana Reddy Kalluru  * @param buf - buffer
1104b51dab46SSudarsana Reddy Kalluru  * @param dev_addr - PHY device memory region
1105b51dab46SSudarsana Reddy Kalluru  * @param offset - offset into eeprom contents to be read
1106b51dab46SSudarsana Reddy Kalluru  * @param len - buffer length, i.e., max bytes to be read
1107b51dab46SSudarsana Reddy Kalluru  */
1108b51dab46SSudarsana Reddy Kalluru 	int (*read_module_eeprom)(struct qed_dev *cdev,
1109b51dab46SSudarsana Reddy Kalluru 				  char *buf, u8 dev_addr, u32 offset, u32 len);
111008eb1fb0SMichal Kalderon 
111108eb1fb0SMichal Kalderon /**
111208eb1fb0SMichal Kalderon  * @brief get_affin_hwfn_idx
111308eb1fb0SMichal Kalderon  *
111408eb1fb0SMichal Kalderon  * @param cdev
111508eb1fb0SMichal Kalderon  */
111608eb1fb0SMichal Kalderon 	u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev);
11172d4c8495SSudarsana Reddy Kalluru 
11182d4c8495SSudarsana Reddy Kalluru /**
11192d4c8495SSudarsana Reddy Kalluru  * @brief read_nvm_cfg - Read NVM config attribute value.
11202d4c8495SSudarsana Reddy Kalluru  * @param cdev
11212d4c8495SSudarsana Reddy Kalluru  * @param buf - buffer
11222d4c8495SSudarsana Reddy Kalluru  * @param cmd - NVM CFG command id
11232d4c8495SSudarsana Reddy Kalluru  * @param entity_id - Entity id
11242d4c8495SSudarsana Reddy Kalluru  *
11252d4c8495SSudarsana Reddy Kalluru  */
11262d4c8495SSudarsana Reddy Kalluru 	int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd,
11272d4c8495SSudarsana Reddy Kalluru 			    u32 entity_id);
11289e54ba7cSSudarsana Reddy Kalluru /**
11299e54ba7cSSudarsana Reddy Kalluru  * @brief read_nvm_cfg - Read NVM config attribute value.
11309e54ba7cSSudarsana Reddy Kalluru  * @param cdev
11319e54ba7cSSudarsana Reddy Kalluru  * @param cmd - NVM CFG command id
11329e54ba7cSSudarsana Reddy Kalluru  *
11339e54ba7cSSudarsana Reddy Kalluru  * @return config id length, 0 on error.
11349e54ba7cSSudarsana Reddy Kalluru  */
11359e54ba7cSSudarsana Reddy Kalluru 	int (*read_nvm_cfg_len)(struct qed_dev *cdev, u32 cmd);
11363b86bd07SSudarsana Reddy Kalluru 
11373b86bd07SSudarsana Reddy Kalluru /**
11383b86bd07SSudarsana Reddy Kalluru  * @brief set_grc_config - Configure value for grc config id.
11393b86bd07SSudarsana Reddy Kalluru  * @param cdev
11403b86bd07SSudarsana Reddy Kalluru  * @param cfg_id - grc config id
11413b86bd07SSudarsana Reddy Kalluru  * @param val - grc config value
11423b86bd07SSudarsana Reddy Kalluru  *
11433b86bd07SSudarsana Reddy Kalluru  */
11443b86bd07SSudarsana Reddy Kalluru 	int (*set_grc_config)(struct qed_dev *cdev, u32 cfg_id, u32 val);
1145fe56b9e6SYuval Mintz };
1146fe56b9e6SYuval Mintz 
1147fe56b9e6SYuval Mintz #define MASK_FIELD(_name, _value) \
1148fe56b9e6SYuval Mintz 	((_value) &= (_name ## _MASK))
1149fe56b9e6SYuval Mintz 
1150fe56b9e6SYuval Mintz #define FIELD_VALUE(_name, _value) \
1151fe56b9e6SYuval Mintz 	((_value & _name ## _MASK) << _name ## _SHIFT)
1152fe56b9e6SYuval Mintz 
1153fe56b9e6SYuval Mintz #define SET_FIELD(value, name, flag)			       \
1154fe56b9e6SYuval Mintz 	do {						       \
1155fe56b9e6SYuval Mintz 		(value) &= ~(name ## _MASK << name ## _SHIFT); \
1156fe56b9e6SYuval Mintz 		(value) |= (((u64)flag) << (name ## _SHIFT));  \
1157fe56b9e6SYuval Mintz 	} while (0)
1158fe56b9e6SYuval Mintz 
1159fe56b9e6SYuval Mintz #define GET_FIELD(value, name) \
1160fe56b9e6SYuval Mintz 	(((value) >> (name ## _SHIFT)) & name ## _MASK)
1161fe56b9e6SYuval Mintz 
11622d22bc83SMichal Kalderon #define GET_MFW_FIELD(name, field) \
11632d22bc83SMichal Kalderon 	(((name) & (field ## _MASK)) >> (field ## _OFFSET))
11642d22bc83SMichal Kalderon 
11652d22bc83SMichal Kalderon #define SET_MFW_FIELD(name, field, value)				 \
11662d22bc83SMichal Kalderon 	do {								 \
11672d22bc83SMichal Kalderon 		(name) &= ~(field ## _MASK);				 \
11682d22bc83SMichal Kalderon 		(name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK));\
11692d22bc83SMichal Kalderon 	} while (0)
11702d22bc83SMichal Kalderon 
1171997af5dfSMichal Kalderon #define DB_ADDR_SHIFT(addr) ((addr) << DB_PWM_ADDR_OFFSET_SHIFT)
1172997af5dfSMichal Kalderon 
1173fe56b9e6SYuval Mintz /* Debug print definitions */
1174fe56b9e6SYuval Mintz #define DP_ERR(cdev, fmt, ...)					\
11759d7650c2SMintz, Yuval 	do {							\
1176fe56b9e6SYuval Mintz 		pr_err("[%s:%d(%s)]" fmt,			\
1177fe56b9e6SYuval Mintz 		       __func__, __LINE__,			\
1178fe56b9e6SYuval Mintz 		       DP_NAME(cdev) ? DP_NAME(cdev) : "",	\
11799d7650c2SMintz, Yuval 		       ## __VA_ARGS__);				\
11809d7650c2SMintz, Yuval 	} while (0)
1181fe56b9e6SYuval Mintz 
1182fe56b9e6SYuval Mintz #define DP_NOTICE(cdev, fmt, ...)				      \
1183fe56b9e6SYuval Mintz 	do {							      \
1184fe56b9e6SYuval Mintz 		if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
1185fe56b9e6SYuval Mintz 			pr_notice("[%s:%d(%s)]" fmt,		      \
1186fe56b9e6SYuval Mintz 				  __func__, __LINE__,		      \
1187fe56b9e6SYuval Mintz 				  DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1188fe56b9e6SYuval Mintz 				  ## __VA_ARGS__);		      \
1189fe56b9e6SYuval Mintz 								      \
1190fe56b9e6SYuval Mintz 		}						      \
1191fe56b9e6SYuval Mintz 	} while (0)
1192fe56b9e6SYuval Mintz 
1193fe56b9e6SYuval Mintz #define DP_INFO(cdev, fmt, ...)					      \
1194fe56b9e6SYuval Mintz 	do {							      \
1195fe56b9e6SYuval Mintz 		if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) {   \
1196fe56b9e6SYuval Mintz 			pr_notice("[%s:%d(%s)]" fmt,		      \
1197fe56b9e6SYuval Mintz 				  __func__, __LINE__,		      \
1198fe56b9e6SYuval Mintz 				  DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1199fe56b9e6SYuval Mintz 				  ## __VA_ARGS__);		      \
1200fe56b9e6SYuval Mintz 		}						      \
1201fe56b9e6SYuval Mintz 	} while (0)
1202fe56b9e6SYuval Mintz 
1203fe56b9e6SYuval Mintz #define DP_VERBOSE(cdev, module, fmt, ...)				\
1204fe56b9e6SYuval Mintz 	do {								\
1205fe56b9e6SYuval Mintz 		if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) &&	\
1206fe56b9e6SYuval Mintz 			     ((cdev)->dp_module & module))) {		\
1207fe56b9e6SYuval Mintz 			pr_notice("[%s:%d(%s)]" fmt,			\
1208fe56b9e6SYuval Mintz 				  __func__, __LINE__,			\
1209fe56b9e6SYuval Mintz 				  DP_NAME(cdev) ? DP_NAME(cdev) : "",	\
1210fe56b9e6SYuval Mintz 				  ## __VA_ARGS__);			\
1211fe56b9e6SYuval Mintz 		}							\
1212fe56b9e6SYuval Mintz 	} while (0)
1213fe56b9e6SYuval Mintz 
1214fe56b9e6SYuval Mintz enum DP_LEVEL {
1215fe56b9e6SYuval Mintz 	QED_LEVEL_VERBOSE	= 0x0,
1216fe56b9e6SYuval Mintz 	QED_LEVEL_INFO		= 0x1,
1217fe56b9e6SYuval Mintz 	QED_LEVEL_NOTICE	= 0x2,
1218fe56b9e6SYuval Mintz 	QED_LEVEL_ERR		= 0x3,
1219fe56b9e6SYuval Mintz };
1220fe56b9e6SYuval Mintz 
1221fe56b9e6SYuval Mintz #define QED_LOG_LEVEL_SHIFT     (30)
1222fe56b9e6SYuval Mintz #define QED_LOG_VERBOSE_MASK    (0x3fffffff)
1223fe56b9e6SYuval Mintz #define QED_LOG_INFO_MASK       (0x40000000)
1224fe56b9e6SYuval Mintz #define QED_LOG_NOTICE_MASK     (0x80000000)
1225fe56b9e6SYuval Mintz 
1226fe56b9e6SYuval Mintz enum DP_MODULE {
1227fe56b9e6SYuval Mintz 	QED_MSG_SPQ	= 0x10000,
1228fe56b9e6SYuval Mintz 	QED_MSG_STATS	= 0x20000,
1229fe56b9e6SYuval Mintz 	QED_MSG_DCB	= 0x40000,
1230fe56b9e6SYuval Mintz 	QED_MSG_IOV	= 0x80000,
1231fe56b9e6SYuval Mintz 	QED_MSG_SP	= 0x100000,
1232fe56b9e6SYuval Mintz 	QED_MSG_STORAGE = 0x200000,
1233fe56b9e6SYuval Mintz 	QED_MSG_CXT	= 0x800000,
12340a7fb11cSYuval Mintz 	QED_MSG_LL2	= 0x1000000,
1235fe56b9e6SYuval Mintz 	QED_MSG_ILT	= 0x2000000,
123651ff1725SRam Amrani 	QED_MSG_RDMA	= 0x4000000,
1237fe56b9e6SYuval Mintz 	QED_MSG_DEBUG	= 0x8000000,
1238fe56b9e6SYuval Mintz 	/* to be added...up to 0x8000000 */
1239fe56b9e6SYuval Mintz };
1240fe56b9e6SYuval Mintz 
1241fc48b7a6SYuval Mintz enum qed_mf_mode {
1242fc48b7a6SYuval Mintz 	QED_MF_DEFAULT,
1243fc48b7a6SYuval Mintz 	QED_MF_OVLAN,
1244fc48b7a6SYuval Mintz 	QED_MF_NPAR,
1245fc48b7a6SYuval Mintz };
1246fc48b7a6SYuval Mintz 
12479c79ddaaSMintz, Yuval struct qed_eth_stats_common {
1248fe56b9e6SYuval Mintz 	u64	no_buff_discards;
1249fe56b9e6SYuval Mintz 	u64	packet_too_big_discard;
1250fe56b9e6SYuval Mintz 	u64	ttl0_discard;
1251fe56b9e6SYuval Mintz 	u64	rx_ucast_bytes;
1252fe56b9e6SYuval Mintz 	u64	rx_mcast_bytes;
1253fe56b9e6SYuval Mintz 	u64	rx_bcast_bytes;
1254fe56b9e6SYuval Mintz 	u64	rx_ucast_pkts;
1255fe56b9e6SYuval Mintz 	u64	rx_mcast_pkts;
1256fe56b9e6SYuval Mintz 	u64	rx_bcast_pkts;
1257fe56b9e6SYuval Mintz 	u64	mftag_filter_discards;
1258fe56b9e6SYuval Mintz 	u64	mac_filter_discards;
1259608e00d0SManish Chopra 	u64	gft_filter_drop;
1260fe56b9e6SYuval Mintz 	u64	tx_ucast_bytes;
1261fe56b9e6SYuval Mintz 	u64	tx_mcast_bytes;
1262fe56b9e6SYuval Mintz 	u64	tx_bcast_bytes;
1263fe56b9e6SYuval Mintz 	u64	tx_ucast_pkts;
1264fe56b9e6SYuval Mintz 	u64	tx_mcast_pkts;
1265fe56b9e6SYuval Mintz 	u64	tx_bcast_pkts;
1266fe56b9e6SYuval Mintz 	u64	tx_err_drop_pkts;
1267fe56b9e6SYuval Mintz 	u64	tpa_coalesced_pkts;
1268fe56b9e6SYuval Mintz 	u64	tpa_coalesced_events;
1269fe56b9e6SYuval Mintz 	u64	tpa_aborts_num;
1270fe56b9e6SYuval Mintz 	u64	tpa_not_coalesced_pkts;
1271fe56b9e6SYuval Mintz 	u64	tpa_coalesced_bytes;
1272fe56b9e6SYuval Mintz 
1273fe56b9e6SYuval Mintz 	/* port */
1274fe56b9e6SYuval Mintz 	u64	rx_64_byte_packets;
1275d4967cf3SYuval Mintz 	u64	rx_65_to_127_byte_packets;
1276d4967cf3SYuval Mintz 	u64	rx_128_to_255_byte_packets;
1277d4967cf3SYuval Mintz 	u64	rx_256_to_511_byte_packets;
1278d4967cf3SYuval Mintz 	u64	rx_512_to_1023_byte_packets;
1279d4967cf3SYuval Mintz 	u64	rx_1024_to_1518_byte_packets;
1280fe56b9e6SYuval Mintz 	u64	rx_crc_errors;
1281fe56b9e6SYuval Mintz 	u64	rx_mac_crtl_frames;
1282fe56b9e6SYuval Mintz 	u64	rx_pause_frames;
1283fe56b9e6SYuval Mintz 	u64	rx_pfc_frames;
1284fe56b9e6SYuval Mintz 	u64	rx_align_errors;
1285fe56b9e6SYuval Mintz 	u64	rx_carrier_errors;
1286fe56b9e6SYuval Mintz 	u64	rx_oversize_packets;
1287fe56b9e6SYuval Mintz 	u64	rx_jabbers;
1288fe56b9e6SYuval Mintz 	u64	rx_undersize_packets;
1289fe56b9e6SYuval Mintz 	u64	rx_fragments;
1290fe56b9e6SYuval Mintz 	u64	tx_64_byte_packets;
1291fe56b9e6SYuval Mintz 	u64	tx_65_to_127_byte_packets;
1292fe56b9e6SYuval Mintz 	u64	tx_128_to_255_byte_packets;
1293fe56b9e6SYuval Mintz 	u64	tx_256_to_511_byte_packets;
1294fe56b9e6SYuval Mintz 	u64	tx_512_to_1023_byte_packets;
1295fe56b9e6SYuval Mintz 	u64	tx_1024_to_1518_byte_packets;
1296fe56b9e6SYuval Mintz 	u64	tx_pause_frames;
1297fe56b9e6SYuval Mintz 	u64	tx_pfc_frames;
1298fe56b9e6SYuval Mintz 	u64	brb_truncates;
1299fe56b9e6SYuval Mintz 	u64	brb_discards;
1300fe56b9e6SYuval Mintz 	u64	rx_mac_bytes;
1301fe56b9e6SYuval Mintz 	u64	rx_mac_uc_packets;
1302fe56b9e6SYuval Mintz 	u64	rx_mac_mc_packets;
1303fe56b9e6SYuval Mintz 	u64	rx_mac_bc_packets;
1304fe56b9e6SYuval Mintz 	u64	rx_mac_frames_ok;
1305fe56b9e6SYuval Mintz 	u64	tx_mac_bytes;
1306fe56b9e6SYuval Mintz 	u64	tx_mac_uc_packets;
1307fe56b9e6SYuval Mintz 	u64	tx_mac_mc_packets;
1308fe56b9e6SYuval Mintz 	u64	tx_mac_bc_packets;
1309fe56b9e6SYuval Mintz 	u64	tx_mac_ctrl_frames;
131032d26a68SSudarsana Reddy Kalluru 	u64	link_change_count;
1311fe56b9e6SYuval Mintz };
1312fe56b9e6SYuval Mintz 
13139c79ddaaSMintz, Yuval struct qed_eth_stats_bb {
13149c79ddaaSMintz, Yuval 	u64 rx_1519_to_1522_byte_packets;
13159c79ddaaSMintz, Yuval 	u64 rx_1519_to_2047_byte_packets;
13169c79ddaaSMintz, Yuval 	u64 rx_2048_to_4095_byte_packets;
13179c79ddaaSMintz, Yuval 	u64 rx_4096_to_9216_byte_packets;
13189c79ddaaSMintz, Yuval 	u64 rx_9217_to_16383_byte_packets;
13199c79ddaaSMintz, Yuval 	u64 tx_1519_to_2047_byte_packets;
13209c79ddaaSMintz, Yuval 	u64 tx_2048_to_4095_byte_packets;
13219c79ddaaSMintz, Yuval 	u64 tx_4096_to_9216_byte_packets;
13229c79ddaaSMintz, Yuval 	u64 tx_9217_to_16383_byte_packets;
13239c79ddaaSMintz, Yuval 	u64 tx_lpi_entry_count;
13249c79ddaaSMintz, Yuval 	u64 tx_total_collisions;
13259c79ddaaSMintz, Yuval };
13269c79ddaaSMintz, Yuval 
13279c79ddaaSMintz, Yuval struct qed_eth_stats_ah {
13289c79ddaaSMintz, Yuval 	u64 rx_1519_to_max_byte_packets;
13299c79ddaaSMintz, Yuval 	u64 tx_1519_to_max_byte_packets;
13309c79ddaaSMintz, Yuval };
13319c79ddaaSMintz, Yuval 
13329c79ddaaSMintz, Yuval struct qed_eth_stats {
13339c79ddaaSMintz, Yuval 	struct qed_eth_stats_common common;
13349c79ddaaSMintz, Yuval 
13359c79ddaaSMintz, Yuval 	union {
13369c79ddaaSMintz, Yuval 		struct qed_eth_stats_bb bb;
13379c79ddaaSMintz, Yuval 		struct qed_eth_stats_ah ah;
13389c79ddaaSMintz, Yuval 	};
13399c79ddaaSMintz, Yuval };
13409c79ddaaSMintz, Yuval 
1341fe56b9e6SYuval Mintz #define QED_SB_IDX              0x0002
1342fe56b9e6SYuval Mintz 
1343fe56b9e6SYuval Mintz #define RX_PI           0
1344fe56b9e6SYuval Mintz #define TX_PI(tc)       (RX_PI + 1 + tc)
1345fe56b9e6SYuval Mintz 
13464ac801b7SYuval Mintz struct qed_sb_cnt_info {
1347726fdbe9SMintz, Yuval 	/* Original, current, and free SBs for PF */
1348726fdbe9SMintz, Yuval 	int orig;
1349726fdbe9SMintz, Yuval 	int cnt;
1350726fdbe9SMintz, Yuval 	int free_cnt;
1351726fdbe9SMintz, Yuval 
1352726fdbe9SMintz, Yuval 	/* Original, current and free SBS for child VFs */
1353726fdbe9SMintz, Yuval 	int iov_orig;
1354726fdbe9SMintz, Yuval 	int iov_cnt;
1355726fdbe9SMintz, Yuval 	int free_cnt_iov;
13564ac801b7SYuval Mintz };
13574ac801b7SYuval Mintz 
1358fe56b9e6SYuval Mintz static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
1359fe56b9e6SYuval Mintz {
1360fe56b9e6SYuval Mintz 	u32 prod = 0;
1361fe56b9e6SYuval Mintz 	u16 rc = 0;
1362fe56b9e6SYuval Mintz 
1363fe56b9e6SYuval Mintz 	prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
136421dd79e8STomer Tayar 	       STATUS_BLOCK_E4_PROD_INDEX_MASK;
1365fe56b9e6SYuval Mintz 	if (sb_info->sb_ack != prod) {
1366fe56b9e6SYuval Mintz 		sb_info->sb_ack = prod;
1367fe56b9e6SYuval Mintz 		rc |= QED_SB_IDX;
1368fe56b9e6SYuval Mintz 	}
1369fe56b9e6SYuval Mintz 
1370fe56b9e6SYuval Mintz 	/* Let SB update */
1371fe56b9e6SYuval Mintz 	return rc;
1372fe56b9e6SYuval Mintz }
1373fe56b9e6SYuval Mintz 
1374fe56b9e6SYuval Mintz /**
1375fe56b9e6SYuval Mintz  *
1376fe56b9e6SYuval Mintz  * @brief This function creates an update command for interrupts that is
1377fe56b9e6SYuval Mintz  *        written to the IGU.
1378fe56b9e6SYuval Mintz  *
1379fe56b9e6SYuval Mintz  * @param sb_info       - This is the structure allocated and
1380fe56b9e6SYuval Mintz  *                 initialized per status block. Assumption is
1381fe56b9e6SYuval Mintz  *                 that it was initialized using qed_sb_init
1382fe56b9e6SYuval Mintz  * @param int_cmd       - Enable/Disable/Nop
1383fe56b9e6SYuval Mintz  * @param upd_flg       - whether igu consumer should be
1384fe56b9e6SYuval Mintz  *                 updated.
1385fe56b9e6SYuval Mintz  *
1386fe56b9e6SYuval Mintz  * @return inline void
1387fe56b9e6SYuval Mintz  */
1388fe56b9e6SYuval Mintz static inline void qed_sb_ack(struct qed_sb_info *sb_info,
1389fe56b9e6SYuval Mintz 			      enum igu_int_cmd int_cmd,
1390fe56b9e6SYuval Mintz 			      u8 upd_flg)
1391fe56b9e6SYuval Mintz {
13925ab90341SAlexander Lobakin 	u32 igu_ack;
1393fe56b9e6SYuval Mintz 
13945ab90341SAlexander Lobakin 	igu_ack = ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1395fe56b9e6SYuval Mintz 		   (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1396fe56b9e6SYuval Mintz 		   (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1397fe56b9e6SYuval Mintz 		   (IGU_SEG_ACCESS_REG <<
1398fe56b9e6SYuval Mintz 		    IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1399fe56b9e6SYuval Mintz 
14005ab90341SAlexander Lobakin 	DIRECT_REG_WR(sb_info->igu_addr, igu_ack);
1401fe56b9e6SYuval Mintz 
1402fe56b9e6SYuval Mintz 	/* Both segments (interrupts & acks) are written to same place address;
1403fe56b9e6SYuval Mintz 	 * Need to guarantee all commands will be received (in-order) by HW.
1404fe56b9e6SYuval Mintz 	 */
1405fe56b9e6SYuval Mintz 	barrier();
1406fe56b9e6SYuval Mintz }
1407fe56b9e6SYuval Mintz 
1408fe56b9e6SYuval Mintz static inline void __internal_ram_wr(void *p_hwfn,
1409fe56b9e6SYuval Mintz 				     void __iomem *addr,
1410fe56b9e6SYuval Mintz 				     int size,
1411fe56b9e6SYuval Mintz 				     u32 *data)
1412fe56b9e6SYuval Mintz 
1413fe56b9e6SYuval Mintz {
1414fe56b9e6SYuval Mintz 	unsigned int i;
1415fe56b9e6SYuval Mintz 
1416fe56b9e6SYuval Mintz 	for (i = 0; i < size / sizeof(*data); i++)
1417fe56b9e6SYuval Mintz 		DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
1418fe56b9e6SYuval Mintz }
1419fe56b9e6SYuval Mintz 
1420fe56b9e6SYuval Mintz static inline void internal_ram_wr(void __iomem *addr,
1421fe56b9e6SYuval Mintz 				   int size,
1422fe56b9e6SYuval Mintz 				   u32 *data)
1423fe56b9e6SYuval Mintz {
1424fe56b9e6SYuval Mintz 	__internal_ram_wr(NULL, addr, size, data);
1425fe56b9e6SYuval Mintz }
1426fe56b9e6SYuval Mintz 
14278c5ebd0cSSudarsana Reddy Kalluru enum qed_rss_caps {
14288c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV4		= 0x1,
14298c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV6		= 0x2,
14308c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV4_TCP	= 0x4,
14318c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV6_TCP	= 0x8,
14328c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV4_UDP	= 0x10,
14338c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV6_UDP	= 0x20,
14348c5ebd0cSSudarsana Reddy Kalluru };
14358c5ebd0cSSudarsana Reddy Kalluru 
14368c5ebd0cSSudarsana Reddy Kalluru #define QED_RSS_IND_TABLE_SIZE 128
14378c5ebd0cSSudarsana Reddy Kalluru #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
1438fe56b9e6SYuval Mintz #endif
1439