xref: /linux/include/linux/qed/qed_if.h (revision 8f76812e1cc4d561c3efc3b2586c686b5428d31f)
1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver
2e8f1cb50SMintz, Yuval  * Copyright (c) 2015-2017  QLogic Corporation
3fe56b9e6SYuval Mintz  *
4e8f1cb50SMintz, Yuval  * This software is available to you under a choice of one of two
5e8f1cb50SMintz, Yuval  * licenses.  You may choose to be licensed under the terms of the GNU
6e8f1cb50SMintz, Yuval  * General Public License (GPL) Version 2, available from the file
7e8f1cb50SMintz, Yuval  * COPYING in the main directory of this source tree, or the
8e8f1cb50SMintz, Yuval  * OpenIB.org BSD license below:
9fe56b9e6SYuval Mintz  *
10e8f1cb50SMintz, Yuval  *     Redistribution and use in source and binary forms, with or
11e8f1cb50SMintz, Yuval  *     without modification, are permitted provided that the following
12e8f1cb50SMintz, Yuval  *     conditions are met:
13e8f1cb50SMintz, Yuval  *
14e8f1cb50SMintz, Yuval  *      - Redistributions of source code must retain the above
15e8f1cb50SMintz, Yuval  *        copyright notice, this list of conditions and the following
16e8f1cb50SMintz, Yuval  *        disclaimer.
17e8f1cb50SMintz, Yuval  *
18e8f1cb50SMintz, Yuval  *      - Redistributions in binary form must reproduce the above
19e8f1cb50SMintz, Yuval  *        copyright notice, this list of conditions and the following
20e8f1cb50SMintz, Yuval  *        disclaimer in the documentation and /or other materials
21e8f1cb50SMintz, Yuval  *        provided with the distribution.
22e8f1cb50SMintz, Yuval  *
23e8f1cb50SMintz, Yuval  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24e8f1cb50SMintz, Yuval  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25e8f1cb50SMintz, Yuval  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26e8f1cb50SMintz, Yuval  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27e8f1cb50SMintz, Yuval  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28e8f1cb50SMintz, Yuval  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29e8f1cb50SMintz, Yuval  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30e8f1cb50SMintz, Yuval  * SOFTWARE.
31fe56b9e6SYuval Mintz  */
32fe56b9e6SYuval Mintz 
33fe56b9e6SYuval Mintz #ifndef _QED_IF_H
34fe56b9e6SYuval Mintz #define _QED_IF_H
35fe56b9e6SYuval Mintz 
36fe56b9e6SYuval Mintz #include <linux/types.h>
37fe56b9e6SYuval Mintz #include <linux/interrupt.h>
38fe56b9e6SYuval Mintz #include <linux/netdevice.h>
39fe56b9e6SYuval Mintz #include <linux/pci.h>
40fe56b9e6SYuval Mintz #include <linux/skbuff.h>
41fe56b9e6SYuval Mintz #include <asm/byteorder.h>
42fe56b9e6SYuval Mintz #include <linux/io.h>
43fe56b9e6SYuval Mintz #include <linux/compiler.h>
44fe56b9e6SYuval Mintz #include <linux/kernel.h>
45fe56b9e6SYuval Mintz #include <linux/list.h>
46fe56b9e6SYuval Mintz #include <linux/slab.h>
47fe56b9e6SYuval Mintz #include <linux/qed/common_hsi.h>
48fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h>
4936907cd5SAriel Elior #include <linux/io-64-nonatomic-lo-hi.h>
50fe56b9e6SYuval Mintz 
5139651abdSSudarsana Reddy Kalluru enum dcbx_protocol_type {
5239651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_ISCSI,
5339651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_FCOE,
5439651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_ROCE,
5539651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_ROCE_V2,
5639651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_ETH,
5739651abdSSudarsana Reddy Kalluru 	DCBX_MAX_PROTOCOL_TYPE
5839651abdSSudarsana Reddy Kalluru };
5939651abdSSudarsana Reddy Kalluru 
6051ff1725SRam Amrani #define QED_ROCE_PROTOCOL_INDEX (3)
6151ff1725SRam Amrani 
626ad8c632SSudarsana Reddy Kalluru #define QED_LLDP_CHASSIS_ID_STAT_LEN 4
636ad8c632SSudarsana Reddy Kalluru #define QED_LLDP_PORT_ID_STAT_LEN 4
646ad8c632SSudarsana Reddy Kalluru #define QED_DCBX_MAX_APP_PROTOCOL 32
656ad8c632SSudarsana Reddy Kalluru #define QED_MAX_PFC_PRIORITIES 8
666ad8c632SSudarsana Reddy Kalluru #define QED_DCBX_DSCP_SIZE 64
676ad8c632SSudarsana Reddy Kalluru 
686ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_remote {
696ad8c632SSudarsana Reddy Kalluru 	u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
706ad8c632SSudarsana Reddy Kalluru 	u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
716ad8c632SSudarsana Reddy Kalluru 	bool enable_rx;
726ad8c632SSudarsana Reddy Kalluru 	bool enable_tx;
736ad8c632SSudarsana Reddy Kalluru 	u32 tx_interval;
746ad8c632SSudarsana Reddy Kalluru 	u32 max_credit;
756ad8c632SSudarsana Reddy Kalluru };
766ad8c632SSudarsana Reddy Kalluru 
776ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_local {
786ad8c632SSudarsana Reddy Kalluru 	u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
796ad8c632SSudarsana Reddy Kalluru 	u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
806ad8c632SSudarsana Reddy Kalluru };
816ad8c632SSudarsana Reddy Kalluru 
826ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_app_prio {
836ad8c632SSudarsana Reddy Kalluru 	u8 roce;
846ad8c632SSudarsana Reddy Kalluru 	u8 roce_v2;
856ad8c632SSudarsana Reddy Kalluru 	u8 fcoe;
866ad8c632SSudarsana Reddy Kalluru 	u8 iscsi;
876ad8c632SSudarsana Reddy Kalluru 	u8 eth;
886ad8c632SSudarsana Reddy Kalluru };
896ad8c632SSudarsana Reddy Kalluru 
906ad8c632SSudarsana Reddy Kalluru struct qed_dbcx_pfc_params {
916ad8c632SSudarsana Reddy Kalluru 	bool willing;
926ad8c632SSudarsana Reddy Kalluru 	bool enabled;
936ad8c632SSudarsana Reddy Kalluru 	u8 prio[QED_MAX_PFC_PRIORITIES];
946ad8c632SSudarsana Reddy Kalluru 	u8 max_tc;
956ad8c632SSudarsana Reddy Kalluru };
966ad8c632SSudarsana Reddy Kalluru 
9759bcb797SSudarsana Reddy Kalluru enum qed_dcbx_sf_ieee_type {
9859bcb797SSudarsana Reddy Kalluru 	QED_DCBX_SF_IEEE_ETHTYPE,
9959bcb797SSudarsana Reddy Kalluru 	QED_DCBX_SF_IEEE_TCP_PORT,
10059bcb797SSudarsana Reddy Kalluru 	QED_DCBX_SF_IEEE_UDP_PORT,
10159bcb797SSudarsana Reddy Kalluru 	QED_DCBX_SF_IEEE_TCP_UDP_PORT
10259bcb797SSudarsana Reddy Kalluru };
10359bcb797SSudarsana Reddy Kalluru 
1046ad8c632SSudarsana Reddy Kalluru struct qed_app_entry {
1056ad8c632SSudarsana Reddy Kalluru 	bool ethtype;
10659bcb797SSudarsana Reddy Kalluru 	enum qed_dcbx_sf_ieee_type sf_ieee;
1076ad8c632SSudarsana Reddy Kalluru 	bool enabled;
1086ad8c632SSudarsana Reddy Kalluru 	u8 prio;
1096ad8c632SSudarsana Reddy Kalluru 	u16 proto_id;
1106ad8c632SSudarsana Reddy Kalluru 	enum dcbx_protocol_type proto_type;
1116ad8c632SSudarsana Reddy Kalluru };
1126ad8c632SSudarsana Reddy Kalluru 
1136ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params {
1146ad8c632SSudarsana Reddy Kalluru 	struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
1156ad8c632SSudarsana Reddy Kalluru 	u16 num_app_entries;
1166ad8c632SSudarsana Reddy Kalluru 	bool app_willing;
1176ad8c632SSudarsana Reddy Kalluru 	bool app_valid;
1186ad8c632SSudarsana Reddy Kalluru 	bool app_error;
1196ad8c632SSudarsana Reddy Kalluru 	bool ets_willing;
1206ad8c632SSudarsana Reddy Kalluru 	bool ets_enabled;
1216ad8c632SSudarsana Reddy Kalluru 	bool ets_cbs;
1226ad8c632SSudarsana Reddy Kalluru 	bool valid;
1236ad8c632SSudarsana Reddy Kalluru 	u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
1246ad8c632SSudarsana Reddy Kalluru 	u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
1256ad8c632SSudarsana Reddy Kalluru 	u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
1266ad8c632SSudarsana Reddy Kalluru 	struct qed_dbcx_pfc_params pfc;
1276ad8c632SSudarsana Reddy Kalluru 	u8 max_ets_tc;
1286ad8c632SSudarsana Reddy Kalluru };
1296ad8c632SSudarsana Reddy Kalluru 
1306ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_admin_params {
1316ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_params params;
1326ad8c632SSudarsana Reddy Kalluru 	bool valid;
1336ad8c632SSudarsana Reddy Kalluru };
1346ad8c632SSudarsana Reddy Kalluru 
1356ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_remote_params {
1366ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_params params;
1376ad8c632SSudarsana Reddy Kalluru 	bool valid;
1386ad8c632SSudarsana Reddy Kalluru };
1396ad8c632SSudarsana Reddy Kalluru 
1406ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_operational_params {
1416ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_app_prio app_prio;
1426ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_params params;
1436ad8c632SSudarsana Reddy Kalluru 	bool valid;
1446ad8c632SSudarsana Reddy Kalluru 	bool enabled;
1456ad8c632SSudarsana Reddy Kalluru 	bool ieee;
1466ad8c632SSudarsana Reddy Kalluru 	bool cee;
14749632b58Ssudarsana.kalluru@cavium.com 	bool local;
1486ad8c632SSudarsana Reddy Kalluru 	u32 err;
1496ad8c632SSudarsana Reddy Kalluru };
1506ad8c632SSudarsana Reddy Kalluru 
1516ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_get {
1526ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_operational_params operational;
1536ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_lldp_remote lldp_remote;
1546ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_lldp_local lldp_local;
1556ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_remote_params remote;
1566ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_admin_params local;
1576ad8c632SSudarsana Reddy Kalluru };
1586ad8c632SSudarsana Reddy Kalluru 
15920675b37SMintz, Yuval enum qed_nvm_images {
16020675b37SMintz, Yuval 	QED_NVM_IMAGE_ISCSI_CFG,
16120675b37SMintz, Yuval 	QED_NVM_IMAGE_FCOE_CFG,
1628a52bbabSMichal Kalderon 	QED_NVM_IMAGE_MDUMP,
1631ac4329aSDenis Bolotin 	QED_NVM_IMAGE_NVM_CFG1,
1641ac4329aSDenis Bolotin 	QED_NVM_IMAGE_DEFAULT_CFG,
1651ac4329aSDenis Bolotin 	QED_NVM_IMAGE_NVM_META,
16620675b37SMintz, Yuval };
16720675b37SMintz, Yuval 
168645874e5SSudarsana Reddy Kalluru struct qed_link_eee_params {
169645874e5SSudarsana Reddy Kalluru 	u32 tx_lpi_timer;
170645874e5SSudarsana Reddy Kalluru #define QED_EEE_1G_ADV		BIT(0)
171645874e5SSudarsana Reddy Kalluru #define QED_EEE_10G_ADV		BIT(1)
172645874e5SSudarsana Reddy Kalluru 
173645874e5SSudarsana Reddy Kalluru 	/* Capabilities are represented using QED_EEE_*_ADV values */
174645874e5SSudarsana Reddy Kalluru 	u8 adv_caps;
175645874e5SSudarsana Reddy Kalluru 	u8 lp_adv_caps;
176645874e5SSudarsana Reddy Kalluru 	bool enable;
177645874e5SSudarsana Reddy Kalluru 	bool tx_lpi_enable;
178645874e5SSudarsana Reddy Kalluru };
179645874e5SSudarsana Reddy Kalluru 
18091420b83SSudarsana Kalluru enum qed_led_mode {
18191420b83SSudarsana Kalluru 	QED_LED_MODE_OFF,
18291420b83SSudarsana Kalluru 	QED_LED_MODE_ON,
18391420b83SSudarsana Kalluru 	QED_LED_MODE_RESTORE
18491420b83SSudarsana Kalluru };
18591420b83SSudarsana Kalluru 
1862528c389SSudarsana Reddy Kalluru struct qed_mfw_tlv_eth {
1872528c389SSudarsana Reddy Kalluru 	u16 lso_maxoff_size;
1882528c389SSudarsana Reddy Kalluru 	bool lso_maxoff_size_set;
1892528c389SSudarsana Reddy Kalluru 	u16 lso_minseg_size;
1902528c389SSudarsana Reddy Kalluru 	bool lso_minseg_size_set;
1912528c389SSudarsana Reddy Kalluru 	u8 prom_mode;
1922528c389SSudarsana Reddy Kalluru 	bool prom_mode_set;
1932528c389SSudarsana Reddy Kalluru 	u16 tx_descr_size;
1942528c389SSudarsana Reddy Kalluru 	bool tx_descr_size_set;
1952528c389SSudarsana Reddy Kalluru 	u16 rx_descr_size;
1962528c389SSudarsana Reddy Kalluru 	bool rx_descr_size_set;
1972528c389SSudarsana Reddy Kalluru 	u16 netq_count;
1982528c389SSudarsana Reddy Kalluru 	bool netq_count_set;
1992528c389SSudarsana Reddy Kalluru 	u32 tcp4_offloads;
2002528c389SSudarsana Reddy Kalluru 	bool tcp4_offloads_set;
2012528c389SSudarsana Reddy Kalluru 	u32 tcp6_offloads;
2022528c389SSudarsana Reddy Kalluru 	bool tcp6_offloads_set;
2032528c389SSudarsana Reddy Kalluru 	u16 tx_descr_qdepth;
2042528c389SSudarsana Reddy Kalluru 	bool tx_descr_qdepth_set;
2052528c389SSudarsana Reddy Kalluru 	u16 rx_descr_qdepth;
2062528c389SSudarsana Reddy Kalluru 	bool rx_descr_qdepth_set;
2072528c389SSudarsana Reddy Kalluru 	u8 iov_offload;
2082528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_IOV_OFFLOAD_NONE            (0)
2092528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE      (1)
2102528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_IOV_OFFLOAD_VEB             (2)
2112528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_IOV_OFFLOAD_VEPA            (3)
2122528c389SSudarsana Reddy Kalluru 	bool iov_offload_set;
2132528c389SSudarsana Reddy Kalluru 	u8 txqs_empty;
2142528c389SSudarsana Reddy Kalluru 	bool txqs_empty_set;
2152528c389SSudarsana Reddy Kalluru 	u8 rxqs_empty;
2162528c389SSudarsana Reddy Kalluru 	bool rxqs_empty_set;
2172528c389SSudarsana Reddy Kalluru 	u8 num_txqs_full;
2182528c389SSudarsana Reddy Kalluru 	bool num_txqs_full_set;
2192528c389SSudarsana Reddy Kalluru 	u8 num_rxqs_full;
2202528c389SSudarsana Reddy Kalluru 	bool num_rxqs_full_set;
2212528c389SSudarsana Reddy Kalluru };
2222528c389SSudarsana Reddy Kalluru 
223f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_TIME_SIZE	14
224f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_time {
225f240b688SSudarsana Reddy Kalluru 	bool b_set;
226f240b688SSudarsana Reddy Kalluru 	u8 month;
227f240b688SSudarsana Reddy Kalluru 	u8 day;
228f240b688SSudarsana Reddy Kalluru 	u8 hour;
229f240b688SSudarsana Reddy Kalluru 	u8 min;
230f240b688SSudarsana Reddy Kalluru 	u16 msec;
231f240b688SSudarsana Reddy Kalluru 	u16 usec;
232f240b688SSudarsana Reddy Kalluru };
233f240b688SSudarsana Reddy Kalluru 
234f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_fcoe {
235f240b688SSudarsana Reddy Kalluru 	u8 scsi_timeout;
236f240b688SSudarsana Reddy Kalluru 	bool scsi_timeout_set;
237f240b688SSudarsana Reddy Kalluru 	u32 rt_tov;
238f240b688SSudarsana Reddy Kalluru 	bool rt_tov_set;
239f240b688SSudarsana Reddy Kalluru 	u32 ra_tov;
240f240b688SSudarsana Reddy Kalluru 	bool ra_tov_set;
241f240b688SSudarsana Reddy Kalluru 	u32 ed_tov;
242f240b688SSudarsana Reddy Kalluru 	bool ed_tov_set;
243f240b688SSudarsana Reddy Kalluru 	u32 cr_tov;
244f240b688SSudarsana Reddy Kalluru 	bool cr_tov_set;
245f240b688SSudarsana Reddy Kalluru 	u8 boot_type;
246f240b688SSudarsana Reddy Kalluru 	bool boot_type_set;
247f240b688SSudarsana Reddy Kalluru 	u8 npiv_state;
248f240b688SSudarsana Reddy Kalluru 	bool npiv_state_set;
249f240b688SSudarsana Reddy Kalluru 	u32 num_npiv_ids;
250f240b688SSudarsana Reddy Kalluru 	bool num_npiv_ids_set;
251f240b688SSudarsana Reddy Kalluru 	u8 switch_name[8];
252f240b688SSudarsana Reddy Kalluru 	bool switch_name_set;
253f240b688SSudarsana Reddy Kalluru 	u16 switch_portnum;
254f240b688SSudarsana Reddy Kalluru 	bool switch_portnum_set;
255f240b688SSudarsana Reddy Kalluru 	u8 switch_portid[3];
256f240b688SSudarsana Reddy Kalluru 	bool switch_portid_set;
257f240b688SSudarsana Reddy Kalluru 	u8 vendor_name[8];
258f240b688SSudarsana Reddy Kalluru 	bool vendor_name_set;
259f240b688SSudarsana Reddy Kalluru 	u8 switch_model[8];
260f240b688SSudarsana Reddy Kalluru 	bool switch_model_set;
261f240b688SSudarsana Reddy Kalluru 	u8 switch_fw_version[8];
262f240b688SSudarsana Reddy Kalluru 	bool switch_fw_version_set;
263f240b688SSudarsana Reddy Kalluru 	u8 qos_pri;
264f240b688SSudarsana Reddy Kalluru 	bool qos_pri_set;
265f240b688SSudarsana Reddy Kalluru 	u8 port_alias[3];
266f240b688SSudarsana Reddy Kalluru 	bool port_alias_set;
267f240b688SSudarsana Reddy Kalluru 	u8 port_state;
268f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_PORT_STATE_OFFLINE  (0)
269f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_PORT_STATE_LOOP             (1)
270f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_PORT_STATE_P2P              (2)
271f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_PORT_STATE_FABRIC           (3)
272f240b688SSudarsana Reddy Kalluru 	bool port_state_set;
273f240b688SSudarsana Reddy Kalluru 	u16 fip_tx_descr_size;
274f240b688SSudarsana Reddy Kalluru 	bool fip_tx_descr_size_set;
275f240b688SSudarsana Reddy Kalluru 	u16 fip_rx_descr_size;
276f240b688SSudarsana Reddy Kalluru 	bool fip_rx_descr_size_set;
277f240b688SSudarsana Reddy Kalluru 	u16 link_failures;
278f240b688SSudarsana Reddy Kalluru 	bool link_failures_set;
279f240b688SSudarsana Reddy Kalluru 	u8 fcoe_boot_progress;
280f240b688SSudarsana Reddy Kalluru 	bool fcoe_boot_progress_set;
281f240b688SSudarsana Reddy Kalluru 	u64 rx_bcast;
282f240b688SSudarsana Reddy Kalluru 	bool rx_bcast_set;
283f240b688SSudarsana Reddy Kalluru 	u64 tx_bcast;
284f240b688SSudarsana Reddy Kalluru 	bool tx_bcast_set;
285f240b688SSudarsana Reddy Kalluru 	u16 fcoe_txq_depth;
286f240b688SSudarsana Reddy Kalluru 	bool fcoe_txq_depth_set;
287f240b688SSudarsana Reddy Kalluru 	u16 fcoe_rxq_depth;
288f240b688SSudarsana Reddy Kalluru 	bool fcoe_rxq_depth_set;
289f240b688SSudarsana Reddy Kalluru 	u64 fcoe_rx_frames;
290f240b688SSudarsana Reddy Kalluru 	bool fcoe_rx_frames_set;
291f240b688SSudarsana Reddy Kalluru 	u64 fcoe_rx_bytes;
292f240b688SSudarsana Reddy Kalluru 	bool fcoe_rx_bytes_set;
293f240b688SSudarsana Reddy Kalluru 	u64 fcoe_tx_frames;
294f240b688SSudarsana Reddy Kalluru 	bool fcoe_tx_frames_set;
295f240b688SSudarsana Reddy Kalluru 	u64 fcoe_tx_bytes;
296f240b688SSudarsana Reddy Kalluru 	bool fcoe_tx_bytes_set;
297f240b688SSudarsana Reddy Kalluru 	u16 crc_count;
298f240b688SSudarsana Reddy Kalluru 	bool crc_count_set;
299f240b688SSudarsana Reddy Kalluru 	u32 crc_err_src_fcid[5];
300f240b688SSudarsana Reddy Kalluru 	bool crc_err_src_fcid_set[5];
301f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time crc_err[5];
302f240b688SSudarsana Reddy Kalluru 	u16 losync_err;
303f240b688SSudarsana Reddy Kalluru 	bool losync_err_set;
304f240b688SSudarsana Reddy Kalluru 	u16 losig_err;
305f240b688SSudarsana Reddy Kalluru 	bool losig_err_set;
306f240b688SSudarsana Reddy Kalluru 	u16 primtive_err;
307f240b688SSudarsana Reddy Kalluru 	bool primtive_err_set;
308f240b688SSudarsana Reddy Kalluru 	u16 disparity_err;
309f240b688SSudarsana Reddy Kalluru 	bool disparity_err_set;
310f240b688SSudarsana Reddy Kalluru 	u16 code_violation_err;
311f240b688SSudarsana Reddy Kalluru 	bool code_violation_err_set;
312f240b688SSudarsana Reddy Kalluru 	u32 flogi_param[4];
313f240b688SSudarsana Reddy Kalluru 	bool flogi_param_set[4];
314f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time flogi_tstamp;
315f240b688SSudarsana Reddy Kalluru 	u32 flogi_acc_param[4];
316f240b688SSudarsana Reddy Kalluru 	bool flogi_acc_param_set[4];
317f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time flogi_acc_tstamp;
318f240b688SSudarsana Reddy Kalluru 	u32 flogi_rjt;
319f240b688SSudarsana Reddy Kalluru 	bool flogi_rjt_set;
320f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time flogi_rjt_tstamp;
321f240b688SSudarsana Reddy Kalluru 	u32 fdiscs;
322f240b688SSudarsana Reddy Kalluru 	bool fdiscs_set;
323f240b688SSudarsana Reddy Kalluru 	u8 fdisc_acc;
324f240b688SSudarsana Reddy Kalluru 	bool fdisc_acc_set;
325f240b688SSudarsana Reddy Kalluru 	u8 fdisc_rjt;
326f240b688SSudarsana Reddy Kalluru 	bool fdisc_rjt_set;
327f240b688SSudarsana Reddy Kalluru 	u8 plogi;
328f240b688SSudarsana Reddy Kalluru 	bool plogi_set;
329f240b688SSudarsana Reddy Kalluru 	u8 plogi_acc;
330f240b688SSudarsana Reddy Kalluru 	bool plogi_acc_set;
331f240b688SSudarsana Reddy Kalluru 	u8 plogi_rjt;
332f240b688SSudarsana Reddy Kalluru 	bool plogi_rjt_set;
333f240b688SSudarsana Reddy Kalluru 	u32 plogi_dst_fcid[5];
334f240b688SSudarsana Reddy Kalluru 	bool plogi_dst_fcid_set[5];
335f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time plogi_tstamp[5];
336f240b688SSudarsana Reddy Kalluru 	u32 plogi_acc_src_fcid[5];
337f240b688SSudarsana Reddy Kalluru 	bool plogi_acc_src_fcid_set[5];
338f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time plogi_acc_tstamp[5];
339f240b688SSudarsana Reddy Kalluru 	u8 tx_plogos;
340f240b688SSudarsana Reddy Kalluru 	bool tx_plogos_set;
341f240b688SSudarsana Reddy Kalluru 	u8 plogo_acc;
342f240b688SSudarsana Reddy Kalluru 	bool plogo_acc_set;
343f240b688SSudarsana Reddy Kalluru 	u8 plogo_rjt;
344f240b688SSudarsana Reddy Kalluru 	bool plogo_rjt_set;
345f240b688SSudarsana Reddy Kalluru 	u32 plogo_src_fcid[5];
346f240b688SSudarsana Reddy Kalluru 	bool plogo_src_fcid_set[5];
347f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time plogo_tstamp[5];
348f240b688SSudarsana Reddy Kalluru 	u8 rx_logos;
349f240b688SSudarsana Reddy Kalluru 	bool rx_logos_set;
350f240b688SSudarsana Reddy Kalluru 	u8 tx_accs;
351f240b688SSudarsana Reddy Kalluru 	bool tx_accs_set;
352f240b688SSudarsana Reddy Kalluru 	u8 tx_prlis;
353f240b688SSudarsana Reddy Kalluru 	bool tx_prlis_set;
354f240b688SSudarsana Reddy Kalluru 	u8 rx_accs;
355f240b688SSudarsana Reddy Kalluru 	bool rx_accs_set;
356f240b688SSudarsana Reddy Kalluru 	u8 tx_abts;
357f240b688SSudarsana Reddy Kalluru 	bool tx_abts_set;
358f240b688SSudarsana Reddy Kalluru 	u8 rx_abts_acc;
359f240b688SSudarsana Reddy Kalluru 	bool rx_abts_acc_set;
360f240b688SSudarsana Reddy Kalluru 	u8 rx_abts_rjt;
361f240b688SSudarsana Reddy Kalluru 	bool rx_abts_rjt_set;
362f240b688SSudarsana Reddy Kalluru 	u32 abts_dst_fcid[5];
363f240b688SSudarsana Reddy Kalluru 	bool abts_dst_fcid_set[5];
364f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time abts_tstamp[5];
365f240b688SSudarsana Reddy Kalluru 	u8 rx_rscn;
366f240b688SSudarsana Reddy Kalluru 	bool rx_rscn_set;
367f240b688SSudarsana Reddy Kalluru 	u32 rx_rscn_nport[4];
368f240b688SSudarsana Reddy Kalluru 	bool rx_rscn_nport_set[4];
369f240b688SSudarsana Reddy Kalluru 	u8 tx_lun_rst;
370f240b688SSudarsana Reddy Kalluru 	bool tx_lun_rst_set;
371f240b688SSudarsana Reddy Kalluru 	u8 abort_task_sets;
372f240b688SSudarsana Reddy Kalluru 	bool abort_task_sets_set;
373f240b688SSudarsana Reddy Kalluru 	u8 tx_tprlos;
374f240b688SSudarsana Reddy Kalluru 	bool tx_tprlos_set;
375f240b688SSudarsana Reddy Kalluru 	u8 tx_nos;
376f240b688SSudarsana Reddy Kalluru 	bool tx_nos_set;
377f240b688SSudarsana Reddy Kalluru 	u8 rx_nos;
378f240b688SSudarsana Reddy Kalluru 	bool rx_nos_set;
379f240b688SSudarsana Reddy Kalluru 	u8 ols;
380f240b688SSudarsana Reddy Kalluru 	bool ols_set;
381f240b688SSudarsana Reddy Kalluru 	u8 lr;
382f240b688SSudarsana Reddy Kalluru 	bool lr_set;
383f240b688SSudarsana Reddy Kalluru 	u8 lrr;
384f240b688SSudarsana Reddy Kalluru 	bool lrr_set;
385f240b688SSudarsana Reddy Kalluru 	u8 tx_lip;
386f240b688SSudarsana Reddy Kalluru 	bool tx_lip_set;
387f240b688SSudarsana Reddy Kalluru 	u8 rx_lip;
388f240b688SSudarsana Reddy Kalluru 	bool rx_lip_set;
389f240b688SSudarsana Reddy Kalluru 	u8 eofa;
390f240b688SSudarsana Reddy Kalluru 	bool eofa_set;
391f240b688SSudarsana Reddy Kalluru 	u8 eofni;
392f240b688SSudarsana Reddy Kalluru 	bool eofni_set;
393f240b688SSudarsana Reddy Kalluru 	u8 scsi_chks;
394f240b688SSudarsana Reddy Kalluru 	bool scsi_chks_set;
395f240b688SSudarsana Reddy Kalluru 	u8 scsi_cond_met;
396f240b688SSudarsana Reddy Kalluru 	bool scsi_cond_met_set;
397f240b688SSudarsana Reddy Kalluru 	u8 scsi_busy;
398f240b688SSudarsana Reddy Kalluru 	bool scsi_busy_set;
399f240b688SSudarsana Reddy Kalluru 	u8 scsi_inter;
400f240b688SSudarsana Reddy Kalluru 	bool scsi_inter_set;
401f240b688SSudarsana Reddy Kalluru 	u8 scsi_inter_cond_met;
402f240b688SSudarsana Reddy Kalluru 	bool scsi_inter_cond_met_set;
403f240b688SSudarsana Reddy Kalluru 	u8 scsi_rsv_conflicts;
404f240b688SSudarsana Reddy Kalluru 	bool scsi_rsv_conflicts_set;
405f240b688SSudarsana Reddy Kalluru 	u8 scsi_tsk_full;
406f240b688SSudarsana Reddy Kalluru 	bool scsi_tsk_full_set;
407f240b688SSudarsana Reddy Kalluru 	u8 scsi_aca_active;
408f240b688SSudarsana Reddy Kalluru 	bool scsi_aca_active_set;
409f240b688SSudarsana Reddy Kalluru 	u8 scsi_tsk_abort;
410f240b688SSudarsana Reddy Kalluru 	bool scsi_tsk_abort_set;
411f240b688SSudarsana Reddy Kalluru 	u32 scsi_rx_chk[5];
412f240b688SSudarsana Reddy Kalluru 	bool scsi_rx_chk_set[5];
413f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time scsi_chk_tstamp[5];
414f240b688SSudarsana Reddy Kalluru };
415f240b688SSudarsana Reddy Kalluru 
41677a509e4SSudarsana Reddy Kalluru struct qed_mfw_tlv_iscsi {
41777a509e4SSudarsana Reddy Kalluru 	u8 target_llmnr;
41877a509e4SSudarsana Reddy Kalluru 	bool target_llmnr_set;
41977a509e4SSudarsana Reddy Kalluru 	u8 header_digest;
42077a509e4SSudarsana Reddy Kalluru 	bool header_digest_set;
42177a509e4SSudarsana Reddy Kalluru 	u8 data_digest;
42277a509e4SSudarsana Reddy Kalluru 	bool data_digest_set;
42377a509e4SSudarsana Reddy Kalluru 	u8 auth_method;
42477a509e4SSudarsana Reddy Kalluru #define QED_MFW_TLV_AUTH_METHOD_NONE            (1)
42577a509e4SSudarsana Reddy Kalluru #define QED_MFW_TLV_AUTH_METHOD_CHAP            (2)
42677a509e4SSudarsana Reddy Kalluru #define QED_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP     (3)
42777a509e4SSudarsana Reddy Kalluru 	bool auth_method_set;
42877a509e4SSudarsana Reddy Kalluru 	u16 boot_taget_portal;
42977a509e4SSudarsana Reddy Kalluru 	bool boot_taget_portal_set;
43077a509e4SSudarsana Reddy Kalluru 	u16 frame_size;
43177a509e4SSudarsana Reddy Kalluru 	bool frame_size_set;
43277a509e4SSudarsana Reddy Kalluru 	u16 tx_desc_size;
43377a509e4SSudarsana Reddy Kalluru 	bool tx_desc_size_set;
43477a509e4SSudarsana Reddy Kalluru 	u16 rx_desc_size;
43577a509e4SSudarsana Reddy Kalluru 	bool rx_desc_size_set;
43677a509e4SSudarsana Reddy Kalluru 	u8 boot_progress;
43777a509e4SSudarsana Reddy Kalluru 	bool boot_progress_set;
43877a509e4SSudarsana Reddy Kalluru 	u16 tx_desc_qdepth;
43977a509e4SSudarsana Reddy Kalluru 	bool tx_desc_qdepth_set;
44077a509e4SSudarsana Reddy Kalluru 	u16 rx_desc_qdepth;
44177a509e4SSudarsana Reddy Kalluru 	bool rx_desc_qdepth_set;
44277a509e4SSudarsana Reddy Kalluru 	u64 rx_frames;
44377a509e4SSudarsana Reddy Kalluru 	bool rx_frames_set;
44477a509e4SSudarsana Reddy Kalluru 	u64 rx_bytes;
44577a509e4SSudarsana Reddy Kalluru 	bool rx_bytes_set;
44677a509e4SSudarsana Reddy Kalluru 	u64 tx_frames;
44777a509e4SSudarsana Reddy Kalluru 	bool tx_frames_set;
44877a509e4SSudarsana Reddy Kalluru 	u64 tx_bytes;
44977a509e4SSudarsana Reddy Kalluru 	bool tx_bytes_set;
45077a509e4SSudarsana Reddy Kalluru };
45177a509e4SSudarsana Reddy Kalluru 
45236907cd5SAriel Elior enum qed_db_rec_width {
45336907cd5SAriel Elior 	DB_REC_WIDTH_32B,
45436907cd5SAriel Elior 	DB_REC_WIDTH_64B,
45536907cd5SAriel Elior };
45636907cd5SAriel Elior 
45736907cd5SAriel Elior enum qed_db_rec_space {
45836907cd5SAriel Elior 	DB_REC_KERNEL,
45936907cd5SAriel Elior 	DB_REC_USER,
46036907cd5SAriel Elior };
46136907cd5SAriel Elior 
462fe56b9e6SYuval Mintz #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
463fe56b9e6SYuval Mintz 					    (void __iomem *)(reg_addr))
464fe56b9e6SYuval Mintz 
465fe56b9e6SYuval Mintz #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
466fe56b9e6SYuval Mintz 
467997af5dfSMichal Kalderon #define DIRECT_REG_WR64(reg_addr, val) writeq((u64)val,	\
46836907cd5SAriel Elior 					      (void __iomem *)(reg_addr))
46936907cd5SAriel Elior 
47041822878SRahul Verma #define QED_COALESCE_MAX 0x1FF
4710e191827SSudarsana Reddy Kalluru #define QED_DEFAULT_RX_USECS 12
472bf5a94bfSRahul Verma #define QED_DEFAULT_TX_USECS 48
473fe56b9e6SYuval Mintz 
474fe56b9e6SYuval Mintz /* forward */
475fe56b9e6SYuval Mintz struct qed_dev;
476fe56b9e6SYuval Mintz 
477fe56b9e6SYuval Mintz struct qed_eth_pf_params {
478fe56b9e6SYuval Mintz 	/* The following parameters are used during HW-init
479fe56b9e6SYuval Mintz 	 * and these parameters need to be passed as arguments
480fe56b9e6SYuval Mintz 	 * to update_pf_params routine invoked before slowpath start
481fe56b9e6SYuval Mintz 	 */
482fe56b9e6SYuval Mintz 	u16 num_cons;
483d51e4af5SChopra, Manish 
48408bc8f15SMintz, Yuval 	/* per-VF number of CIDs */
48508bc8f15SMintz, Yuval 	u8 num_vf_cons;
48608bc8f15SMintz, Yuval #define ETH_PF_PARAMS_VF_CONS_DEFAULT	(32)
48708bc8f15SMintz, Yuval 
488d51e4af5SChopra, Manish 	/* To enable arfs, previous to HW-init a positive number needs to be
489d51e4af5SChopra, Manish 	 * set [as filters require allocated searcher ILT memory].
490d51e4af5SChopra, Manish 	 * This will set the maximal number of configured steering-filters.
491d51e4af5SChopra, Manish 	 */
492d51e4af5SChopra, Manish 	u32 num_arfs_filters;
493fe56b9e6SYuval Mintz };
494fe56b9e6SYuval Mintz 
4951e128c81SArun Easi struct qed_fcoe_pf_params {
4961e128c81SArun Easi 	/* The following parameters are used during protocol-init */
4971e128c81SArun Easi 	u64 glbl_q_params_addr;
4981e128c81SArun Easi 	u64 bdq_pbl_base_addr[2];
4991e128c81SArun Easi 
5001e128c81SArun Easi 	/* The following parameters are used during HW-init
5011e128c81SArun Easi 	 * and these parameters need to be passed as arguments
5021e128c81SArun Easi 	 * to update_pf_params routine invoked before slowpath start
5031e128c81SArun Easi 	 */
5041e128c81SArun Easi 	u16 num_cons;
5051e128c81SArun Easi 	u16 num_tasks;
5061e128c81SArun Easi 
5071e128c81SArun Easi 	/* The following parameters are used during protocol-init */
5081e128c81SArun Easi 	u16 sq_num_pbl_pages;
5091e128c81SArun Easi 
5101e128c81SArun Easi 	u16 cq_num_entries;
5111e128c81SArun Easi 	u16 cmdq_num_entries;
5121e128c81SArun Easi 	u16 rq_buffer_log_size;
5131e128c81SArun Easi 	u16 mtu;
5141e128c81SArun Easi 	u16 dummy_icid;
5151e128c81SArun Easi 	u16 bdq_xoff_threshold[2];
5161e128c81SArun Easi 	u16 bdq_xon_threshold[2];
5171e128c81SArun Easi 	u16 rq_buffer_size;
5181e128c81SArun Easi 	u8 num_cqs;		/* num of global CQs */
5191e128c81SArun Easi 	u8 log_page_size;
5201e128c81SArun Easi 	u8 gl_rq_pi;
5211e128c81SArun Easi 	u8 gl_cmd_pi;
5221e128c81SArun Easi 	u8 debug_mode;
5231e128c81SArun Easi 	u8 is_target;
5241e128c81SArun Easi 	u8 bdq_pbl_num_entries[2];
5251e128c81SArun Easi };
5261e128c81SArun Easi 
527c5ac9319SYuval Mintz /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
528c5ac9319SYuval Mintz struct qed_iscsi_pf_params {
529c5ac9319SYuval Mintz 	u64 glbl_q_params_addr;
530da090917STomer Tayar 	u64 bdq_pbl_base_addr[3];
531c5ac9319SYuval Mintz 	u16 cq_num_entries;
532c5ac9319SYuval Mintz 	u16 cmdq_num_entries;
533fc831825SYuval Mintz 	u32 two_msl_timer;
534c5ac9319SYuval Mintz 	u16 tx_sws_timer;
535c5ac9319SYuval Mintz 
536c5ac9319SYuval Mintz 	/* The following parameters are used during HW-init
537c5ac9319SYuval Mintz 	 * and these parameters need to be passed as arguments
538c5ac9319SYuval Mintz 	 * to update_pf_params routine invoked before slowpath start
539c5ac9319SYuval Mintz 	 */
540c5ac9319SYuval Mintz 	u16 num_cons;
541c5ac9319SYuval Mintz 	u16 num_tasks;
542c5ac9319SYuval Mintz 
543c5ac9319SYuval Mintz 	/* The following parameters are used during protocol-init */
544c5ac9319SYuval Mintz 	u16 half_way_close_timeout;
545da090917STomer Tayar 	u16 bdq_xoff_threshold[3];
546da090917STomer Tayar 	u16 bdq_xon_threshold[3];
547c5ac9319SYuval Mintz 	u16 cmdq_xoff_threshold;
548c5ac9319SYuval Mintz 	u16 cmdq_xon_threshold;
549c5ac9319SYuval Mintz 	u16 rq_buffer_size;
550c5ac9319SYuval Mintz 
551c5ac9319SYuval Mintz 	u8 num_sq_pages_in_ring;
552c5ac9319SYuval Mintz 	u8 num_r2tq_pages_in_ring;
553c5ac9319SYuval Mintz 	u8 num_uhq_pages_in_ring;
554c5ac9319SYuval Mintz 	u8 num_queues;
555c5ac9319SYuval Mintz 	u8 log_page_size;
556c5ac9319SYuval Mintz 	u8 rqe_log_size;
557c5ac9319SYuval Mintz 	u8 max_fin_rt;
558c5ac9319SYuval Mintz 	u8 gl_rq_pi;
559c5ac9319SYuval Mintz 	u8 gl_cmd_pi;
560c5ac9319SYuval Mintz 	u8 debug_mode;
561c5ac9319SYuval Mintz 	u8 ll2_ooo_queue_id;
562c5ac9319SYuval Mintz 
563c5ac9319SYuval Mintz 	u8 is_target;
564da090917STomer Tayar 	u8 is_soc_en;
565da090917STomer Tayar 	u8 soc_num_of_blocks_log;
566da090917STomer Tayar 	u8 bdq_pbl_num_entries[3];
567c5ac9319SYuval Mintz };
568c5ac9319SYuval Mintz 
569c5ac9319SYuval Mintz struct qed_rdma_pf_params {
570c5ac9319SYuval Mintz 	/* Supplied to QED during resource allocation (may affect the ILT and
571c5ac9319SYuval Mintz 	 * the doorbell BAR).
572c5ac9319SYuval Mintz 	 */
573c5ac9319SYuval Mintz 	u32 min_dpis;		/* number of requested DPIs */
574c5ac9319SYuval Mintz 	u32 num_qps;		/* number of requested Queue Pairs */
575c5ac9319SYuval Mintz 	u32 num_srqs;		/* number of requested SRQ */
576c5ac9319SYuval Mintz 	u8 roce_edpm_mode;	/* see QED_ROCE_EDPM_MODE_ENABLE */
577c5ac9319SYuval Mintz 	u8 gl_pi;		/* protocol index */
578c5ac9319SYuval Mintz 
579c5ac9319SYuval Mintz 	/* Will allocate rate limiters to be used with QPs */
580c5ac9319SYuval Mintz 	u8 enable_dcqcn;
581c5ac9319SYuval Mintz };
582c5ac9319SYuval Mintz 
583fe56b9e6SYuval Mintz struct qed_pf_params {
584fe56b9e6SYuval Mintz 	struct qed_eth_pf_params eth_pf_params;
5851e128c81SArun Easi 	struct qed_fcoe_pf_params fcoe_pf_params;
586c5ac9319SYuval Mintz 	struct qed_iscsi_pf_params iscsi_pf_params;
587c5ac9319SYuval Mintz 	struct qed_rdma_pf_params rdma_pf_params;
588fe56b9e6SYuval Mintz };
589fe56b9e6SYuval Mintz 
590fe56b9e6SYuval Mintz enum qed_int_mode {
591fe56b9e6SYuval Mintz 	QED_INT_MODE_INTA,
592fe56b9e6SYuval Mintz 	QED_INT_MODE_MSIX,
593fe56b9e6SYuval Mintz 	QED_INT_MODE_MSI,
594fe56b9e6SYuval Mintz 	QED_INT_MODE_POLL,
595fe56b9e6SYuval Mintz };
596fe56b9e6SYuval Mintz 
597fe56b9e6SYuval Mintz struct qed_sb_info {
59821dd79e8STomer Tayar 	struct status_block_e4 *sb_virt;
599fe56b9e6SYuval Mintz 	dma_addr_t sb_phys;
600fe56b9e6SYuval Mintz 	u32 sb_ack; /* Last given ack */
601fe56b9e6SYuval Mintz 	u16 igu_sb_id;
602fe56b9e6SYuval Mintz 	void __iomem *igu_addr;
603fe56b9e6SYuval Mintz 	u8 flags;
604fe56b9e6SYuval Mintz #define QED_SB_INFO_INIT	0x1
605fe56b9e6SYuval Mintz #define QED_SB_INFO_SETUP	0x2
606fe56b9e6SYuval Mintz 
607fe56b9e6SYuval Mintz 	struct qed_dev *cdev;
608fe56b9e6SYuval Mintz };
609fe56b9e6SYuval Mintz 
610d639836aSIgor Russkikh enum qed_hw_err_type {
611d639836aSIgor Russkikh 	QED_HW_ERR_FAN_FAIL,
612d639836aSIgor Russkikh 	QED_HW_ERR_MFW_RESP_FAIL,
613d639836aSIgor Russkikh 	QED_HW_ERR_HW_ATTN,
614d639836aSIgor Russkikh 	QED_HW_ERR_DMAE_FAIL,
615d639836aSIgor Russkikh 	QED_HW_ERR_RAMROD_FAIL,
616d639836aSIgor Russkikh 	QED_HW_ERR_FW_ASSERT,
617d639836aSIgor Russkikh 	QED_HW_ERR_LAST,
618d639836aSIgor Russkikh };
619d639836aSIgor Russkikh 
6209c79ddaaSMintz, Yuval enum qed_dev_type {
6219c79ddaaSMintz, Yuval 	QED_DEV_TYPE_BB,
6229c79ddaaSMintz, Yuval 	QED_DEV_TYPE_AH,
6239c79ddaaSMintz, Yuval };
6249c79ddaaSMintz, Yuval 
625fe56b9e6SYuval Mintz struct qed_dev_info {
626fe56b9e6SYuval Mintz 	unsigned long	pci_mem_start;
627fe56b9e6SYuval Mintz 	unsigned long	pci_mem_end;
628fe56b9e6SYuval Mintz 	unsigned int	pci_irq;
629fe56b9e6SYuval Mintz 	u8		num_hwfns;
630fe56b9e6SYuval Mintz 
631fe56b9e6SYuval Mintz 	u8		hw_mac[ETH_ALEN];
632fe56b9e6SYuval Mintz 
633fe56b9e6SYuval Mintz 	/* FW version */
634fe56b9e6SYuval Mintz 	u16		fw_major;
635fe56b9e6SYuval Mintz 	u16		fw_minor;
636fe56b9e6SYuval Mintz 	u16		fw_rev;
637fe56b9e6SYuval Mintz 	u16		fw_eng;
638fe56b9e6SYuval Mintz 
639fe56b9e6SYuval Mintz 	/* MFW version */
640fe56b9e6SYuval Mintz 	u32		mfw_rev;
641ae33666aSTomer Tayar #define QED_MFW_VERSION_0_MASK		0x000000FF
642ae33666aSTomer Tayar #define QED_MFW_VERSION_0_OFFSET	0
643ae33666aSTomer Tayar #define QED_MFW_VERSION_1_MASK		0x0000FF00
644ae33666aSTomer Tayar #define QED_MFW_VERSION_1_OFFSET	8
645ae33666aSTomer Tayar #define QED_MFW_VERSION_2_MASK		0x00FF0000
646ae33666aSTomer Tayar #define QED_MFW_VERSION_2_OFFSET	16
647ae33666aSTomer Tayar #define QED_MFW_VERSION_3_MASK		0xFF000000
648ae33666aSTomer Tayar #define QED_MFW_VERSION_3_OFFSET	24
649fe56b9e6SYuval Mintz 
650fe56b9e6SYuval Mintz 	u32		flash_size;
6510bc5fe85SSudarsana Reddy Kalluru 	bool		b_inter_pf_switch;
652831bfb0eSYuval Mintz 	bool		tx_switching;
653cee9fbd8SRam Amrani 	bool		rdma_supported;
6540fefbfbaSSudarsana Kalluru 	u16		mtu;
65514d39648SMintz, Yuval 
65614d39648SMintz, Yuval 	bool wol_support;
657df9c716dSSudarsana Reddy Kalluru 	bool smart_an;
6589c79ddaaSMintz, Yuval 
659ae33666aSTomer Tayar 	/* MBI version */
660ae33666aSTomer Tayar 	u32 mbi_version;
661ae33666aSTomer Tayar #define QED_MBI_VERSION_0_MASK		0x000000FF
662ae33666aSTomer Tayar #define QED_MBI_VERSION_0_OFFSET	0
663ae33666aSTomer Tayar #define QED_MBI_VERSION_1_MASK		0x0000FF00
664ae33666aSTomer Tayar #define QED_MBI_VERSION_1_OFFSET	8
665ae33666aSTomer Tayar #define QED_MBI_VERSION_2_MASK		0x00FF0000
666ae33666aSTomer Tayar #define QED_MBI_VERSION_2_OFFSET	16
667ae33666aSTomer Tayar 
6689c79ddaaSMintz, Yuval 	enum qed_dev_type dev_type;
66919489c7fSChopra, Manish 
67019489c7fSChopra, Manish 	/* Output parameters for qede */
67119489c7fSChopra, Manish 	bool		vxlan_enable;
67219489c7fSChopra, Manish 	bool		gre_enable;
67319489c7fSChopra, Manish 	bool		geneve_enable;
6743c5da942SMintz, Yuval 
6753c5da942SMintz, Yuval 	u8		abs_pf_id;
676fe56b9e6SYuval Mintz };
677fe56b9e6SYuval Mintz 
678fe56b9e6SYuval Mintz enum qed_sb_type {
679fe56b9e6SYuval Mintz 	QED_SB_TYPE_L2_QUEUE,
68051ff1725SRam Amrani 	QED_SB_TYPE_CNQ,
681fc831825SYuval Mintz 	QED_SB_TYPE_STORAGE,
682fe56b9e6SYuval Mintz };
683fe56b9e6SYuval Mintz 
684fe56b9e6SYuval Mintz enum qed_protocol {
685fe56b9e6SYuval Mintz 	QED_PROTOCOL_ETH,
686c5ac9319SYuval Mintz 	QED_PROTOCOL_ISCSI,
6871e128c81SArun Easi 	QED_PROTOCOL_FCOE,
688fe56b9e6SYuval Mintz };
689fe56b9e6SYuval Mintz 
690054c67d1SSudarsana Reddy Kalluru enum qed_link_mode_bits {
691054c67d1SSudarsana Reddy Kalluru 	QED_LM_FIBRE_BIT = BIT(0),
692054c67d1SSudarsana Reddy Kalluru 	QED_LM_Autoneg_BIT = BIT(1),
693054c67d1SSudarsana Reddy Kalluru 	QED_LM_Asym_Pause_BIT = BIT(2),
694054c67d1SSudarsana Reddy Kalluru 	QED_LM_Pause_BIT = BIT(3),
695c56a8be7SRahul Verma 	QED_LM_1000baseT_Full_BIT = BIT(4),
696c56a8be7SRahul Verma 	QED_LM_10000baseT_Full_BIT = BIT(5),
697054c67d1SSudarsana Reddy Kalluru 	QED_LM_10000baseKR_Full_BIT = BIT(6),
6985bf0961cSSudarsana Reddy Kalluru 	QED_LM_20000baseKR2_Full_BIT = BIT(7),
6995bf0961cSSudarsana Reddy Kalluru 	QED_LM_25000baseKR_Full_BIT = BIT(8),
7005bf0961cSSudarsana Reddy Kalluru 	QED_LM_40000baseLR4_Full_BIT = BIT(9),
7015bf0961cSSudarsana Reddy Kalluru 	QED_LM_50000baseKR2_Full_BIT = BIT(10),
7025bf0961cSSudarsana Reddy Kalluru 	QED_LM_100000baseKR4_Full_BIT = BIT(11),
7035e6d9fc7SRahul Verma 	QED_LM_TP_BIT = BIT(12),
704c56a8be7SRahul Verma 	QED_LM_Backplane_BIT = BIT(13),
705c56a8be7SRahul Verma 	QED_LM_1000baseKX_Full_BIT = BIT(14),
706c56a8be7SRahul Verma 	QED_LM_10000baseKX4_Full_BIT = BIT(15),
707c56a8be7SRahul Verma 	QED_LM_10000baseR_FEC_BIT = BIT(16),
708c56a8be7SRahul Verma 	QED_LM_40000baseKR4_Full_BIT = BIT(17),
709c56a8be7SRahul Verma 	QED_LM_40000baseCR4_Full_BIT = BIT(18),
710c56a8be7SRahul Verma 	QED_LM_40000baseSR4_Full_BIT = BIT(19),
711c56a8be7SRahul Verma 	QED_LM_25000baseCR_Full_BIT = BIT(20),
712c56a8be7SRahul Verma 	QED_LM_25000baseSR_Full_BIT = BIT(21),
713c56a8be7SRahul Verma 	QED_LM_50000baseCR2_Full_BIT = BIT(22),
714c56a8be7SRahul Verma 	QED_LM_100000baseSR4_Full_BIT = BIT(23),
715c56a8be7SRahul Verma 	QED_LM_100000baseCR4_Full_BIT = BIT(24),
716c56a8be7SRahul Verma 	QED_LM_100000baseLR4_ER4_Full_BIT = BIT(25),
717c56a8be7SRahul Verma 	QED_LM_50000baseSR2_Full_BIT = BIT(26),
718c56a8be7SRahul Verma 	QED_LM_1000baseX_Full_BIT = BIT(27),
719c56a8be7SRahul Verma 	QED_LM_10000baseCR_Full_BIT = BIT(28),
720c56a8be7SRahul Verma 	QED_LM_10000baseSR_Full_BIT = BIT(29),
721c56a8be7SRahul Verma 	QED_LM_10000baseLR_Full_BIT = BIT(30),
722c56a8be7SRahul Verma 	QED_LM_10000baseLRM_Full_BIT = BIT(31),
723c56a8be7SRahul Verma 	QED_LM_COUNT = 32
724054c67d1SSudarsana Reddy Kalluru };
725054c67d1SSudarsana Reddy Kalluru 
726fe56b9e6SYuval Mintz struct qed_link_params {
727fe56b9e6SYuval Mintz 	bool	link_up;
728fe56b9e6SYuval Mintz 
729fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_AUTONEG         BIT(0)
730fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS      BIT(1)
731fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED    BIT(2)
732fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_PAUSE_CONFIG          BIT(3)
73303dc76caSSudarsana Reddy Kalluru #define QED_LINK_OVERRIDE_LOOPBACK_MODE         BIT(4)
734645874e5SSudarsana Reddy Kalluru #define QED_LINK_OVERRIDE_EEE_CONFIG            BIT(5)
735fe56b9e6SYuval Mintz 	u32	override_flags;
736fe56b9e6SYuval Mintz 	bool	autoneg;
737fe56b9e6SYuval Mintz 	u32	adv_speeds;
738fe56b9e6SYuval Mintz 	u32	forced_speed;
739fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_AUTONEG_ENABLE           BIT(0)
740fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_RX_ENABLE                BIT(1)
741fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_TX_ENABLE                BIT(2)
742fe56b9e6SYuval Mintz 	u32	pause_config;
74303dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_NONE                  BIT(0)
74403dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_INT_PHY               BIT(1)
74503dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_EXT_PHY               BIT(2)
74603dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_EXT                   BIT(3)
74703dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_MAC                   BIT(4)
74803dc76caSSudarsana Reddy Kalluru 	u32	loopback_mode;
749645874e5SSudarsana Reddy Kalluru 	struct qed_link_eee_params eee;
750fe56b9e6SYuval Mintz };
751fe56b9e6SYuval Mintz 
752fe56b9e6SYuval Mintz struct qed_link_output {
753fe56b9e6SYuval Mintz 	bool	link_up;
754fe56b9e6SYuval Mintz 
755d194fd26SYuval Mintz 	/* In QED_LM_* defs */
756d194fd26SYuval Mintz 	u32	supported_caps;
757d194fd26SYuval Mintz 	u32	advertised_caps;
758d194fd26SYuval Mintz 	u32	lp_caps;
759d194fd26SYuval Mintz 
760fe56b9e6SYuval Mintz 	u32	speed;                  /* In Mb/s */
761fe56b9e6SYuval Mintz 	u8	duplex;                 /* In DUPLEX defs */
762fe56b9e6SYuval Mintz 	u8	port;                   /* In PORT defs */
763fe56b9e6SYuval Mintz 	bool	autoneg;
764fe56b9e6SYuval Mintz 	u32	pause_config;
765645874e5SSudarsana Reddy Kalluru 
766645874e5SSudarsana Reddy Kalluru 	/* EEE - capability & param */
767645874e5SSudarsana Reddy Kalluru 	bool eee_supported;
768645874e5SSudarsana Reddy Kalluru 	bool eee_active;
769645874e5SSudarsana Reddy Kalluru 	u8 sup_caps;
770645874e5SSudarsana Reddy Kalluru 	struct qed_link_eee_params eee;
771fe56b9e6SYuval Mintz };
772fe56b9e6SYuval Mintz 
7731408cc1fSYuval Mintz struct qed_probe_params {
7741408cc1fSYuval Mintz 	enum qed_protocol protocol;
7751408cc1fSYuval Mintz 	u32 dp_module;
7761408cc1fSYuval Mintz 	u8 dp_level;
7771408cc1fSYuval Mintz 	bool is_vf;
77864515dc8STomer Tayar 	bool recov_in_prog;
7791408cc1fSYuval Mintz };
7801408cc1fSYuval Mintz 
781fe56b9e6SYuval Mintz #define QED_DRV_VER_STR_SIZE 12
782fe56b9e6SYuval Mintz struct qed_slowpath_params {
783fe56b9e6SYuval Mintz 	u32	int_mode;
784fe56b9e6SYuval Mintz 	u8	drv_major;
785fe56b9e6SYuval Mintz 	u8	drv_minor;
786fe56b9e6SYuval Mintz 	u8	drv_rev;
787fe56b9e6SYuval Mintz 	u8	drv_eng;
788fe56b9e6SYuval Mintz 	u8	name[QED_DRV_VER_STR_SIZE];
789fe56b9e6SYuval Mintz };
790fe56b9e6SYuval Mintz 
791fe56b9e6SYuval Mintz #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
792fe56b9e6SYuval Mintz 
793fe56b9e6SYuval Mintz struct qed_int_info {
794fe56b9e6SYuval Mintz 	struct msix_entry	*msix;
795fe56b9e6SYuval Mintz 	u8			msix_cnt;
796fe56b9e6SYuval Mintz 
797fe56b9e6SYuval Mintz 	/* This should be updated by the protocol driver */
798fe56b9e6SYuval Mintz 	u8			used_cnt;
799fe56b9e6SYuval Mintz };
800fe56b9e6SYuval Mintz 
80159ccf86fSSudarsana Reddy Kalluru struct qed_generic_tlvs {
80259ccf86fSSudarsana Reddy Kalluru #define QED_TLV_IP_CSUM         BIT(0)
80359ccf86fSSudarsana Reddy Kalluru #define QED_TLV_LSO             BIT(1)
80459ccf86fSSudarsana Reddy Kalluru 	u16 feat_flags;
80559ccf86fSSudarsana Reddy Kalluru #define QED_TLV_MAC_COUNT	3
80659ccf86fSSudarsana Reddy Kalluru 	u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN];
80759ccf86fSSudarsana Reddy Kalluru };
80859ccf86fSSudarsana Reddy Kalluru 
809b51dab46SSudarsana Reddy Kalluru #define QED_I2C_DEV_ADDR_A0 0xA0
810b51dab46SSudarsana Reddy Kalluru #define QED_I2C_DEV_ADDR_A2 0xA2
811b51dab46SSudarsana Reddy Kalluru 
8123a69cae8SSudarsana Reddy Kalluru #define QED_NVM_SIGNATURE 0x12435687
8133a69cae8SSudarsana Reddy Kalluru 
8143a69cae8SSudarsana Reddy Kalluru enum qed_nvm_flash_cmd {
8153a69cae8SSudarsana Reddy Kalluru 	QED_NVM_FLASH_CMD_FILE_DATA = 0x2,
8163a69cae8SSudarsana Reddy Kalluru 	QED_NVM_FLASH_CMD_FILE_START = 0x3,
8173a69cae8SSudarsana Reddy Kalluru 	QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4,
8180dabbe1bSSudarsana Reddy Kalluru 	QED_NVM_FLASH_CMD_NVM_CFG_ID = 0x5,
8193a69cae8SSudarsana Reddy Kalluru 	QED_NVM_FLASH_CMD_NVM_MAX,
8203a69cae8SSudarsana Reddy Kalluru };
8213a69cae8SSudarsana Reddy Kalluru 
822fe56b9e6SYuval Mintz struct qed_common_cb_ops {
823d51e4af5SChopra, Manish 	void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc);
824*8f76812eSIgor Russkikh 	void (*link_update)(void *dev, struct qed_link_output *link);
82564515dc8STomer Tayar 	void (*schedule_recovery_handler)(void *dev);
826d639836aSIgor Russkikh 	void (*schedule_hw_err_handler)(void *dev,
827d639836aSIgor Russkikh 					enum qed_hw_err_type err_type);
8281e128c81SArun Easi 	void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
82959ccf86fSSudarsana Reddy Kalluru 	void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data);
83059ccf86fSSudarsana Reddy Kalluru 	void (*get_protocol_tlv_data)(void *dev, void *data);
831fe56b9e6SYuval Mintz };
832fe56b9e6SYuval Mintz 
83303dc76caSSudarsana Reddy Kalluru struct qed_selftest_ops {
83403dc76caSSudarsana Reddy Kalluru /**
83503dc76caSSudarsana Reddy Kalluru  * @brief selftest_interrupt - Perform interrupt test
83603dc76caSSudarsana Reddy Kalluru  *
83703dc76caSSudarsana Reddy Kalluru  * @param cdev
83803dc76caSSudarsana Reddy Kalluru  *
83903dc76caSSudarsana Reddy Kalluru  * @return 0 on success, error otherwise.
84003dc76caSSudarsana Reddy Kalluru  */
84103dc76caSSudarsana Reddy Kalluru 	int (*selftest_interrupt)(struct qed_dev *cdev);
84203dc76caSSudarsana Reddy Kalluru 
84303dc76caSSudarsana Reddy Kalluru /**
84403dc76caSSudarsana Reddy Kalluru  * @brief selftest_memory - Perform memory test
84503dc76caSSudarsana Reddy Kalluru  *
84603dc76caSSudarsana Reddy Kalluru  * @param cdev
84703dc76caSSudarsana Reddy Kalluru  *
84803dc76caSSudarsana Reddy Kalluru  * @return 0 on success, error otherwise.
84903dc76caSSudarsana Reddy Kalluru  */
85003dc76caSSudarsana Reddy Kalluru 	int (*selftest_memory)(struct qed_dev *cdev);
85103dc76caSSudarsana Reddy Kalluru 
85203dc76caSSudarsana Reddy Kalluru /**
85303dc76caSSudarsana Reddy Kalluru  * @brief selftest_register - Perform register test
85403dc76caSSudarsana Reddy Kalluru  *
85503dc76caSSudarsana Reddy Kalluru  * @param cdev
85603dc76caSSudarsana Reddy Kalluru  *
85703dc76caSSudarsana Reddy Kalluru  * @return 0 on success, error otherwise.
85803dc76caSSudarsana Reddy Kalluru  */
85903dc76caSSudarsana Reddy Kalluru 	int (*selftest_register)(struct qed_dev *cdev);
86003dc76caSSudarsana Reddy Kalluru 
86103dc76caSSudarsana Reddy Kalluru /**
86203dc76caSSudarsana Reddy Kalluru  * @brief selftest_clock - Perform clock test
86303dc76caSSudarsana Reddy Kalluru  *
86403dc76caSSudarsana Reddy Kalluru  * @param cdev
86503dc76caSSudarsana Reddy Kalluru  *
86603dc76caSSudarsana Reddy Kalluru  * @return 0 on success, error otherwise.
86703dc76caSSudarsana Reddy Kalluru  */
86803dc76caSSudarsana Reddy Kalluru 	int (*selftest_clock)(struct qed_dev *cdev);
8697a4b21b7SMintz, Yuval 
8707a4b21b7SMintz, Yuval /**
8717a4b21b7SMintz, Yuval  * @brief selftest_nvram - Perform nvram test
8727a4b21b7SMintz, Yuval  *
8737a4b21b7SMintz, Yuval  * @param cdev
8747a4b21b7SMintz, Yuval  *
8757a4b21b7SMintz, Yuval  * @return 0 on success, error otherwise.
8767a4b21b7SMintz, Yuval  */
8777a4b21b7SMintz, Yuval 	int (*selftest_nvram) (struct qed_dev *cdev);
87803dc76caSSudarsana Reddy Kalluru };
87903dc76caSSudarsana Reddy Kalluru 
880fe56b9e6SYuval Mintz struct qed_common_ops {
88103dc76caSSudarsana Reddy Kalluru 	struct qed_selftest_ops *selftest;
88203dc76caSSudarsana Reddy Kalluru 
883fe56b9e6SYuval Mintz 	struct qed_dev*	(*probe)(struct pci_dev *dev,
8841408cc1fSYuval Mintz 				 struct qed_probe_params *params);
885fe56b9e6SYuval Mintz 
886fe56b9e6SYuval Mintz 	void		(*remove)(struct qed_dev *cdev);
887fe56b9e6SYuval Mintz 
888fe56b9e6SYuval Mintz 	int		(*set_power_state)(struct qed_dev *cdev,
889fe56b9e6SYuval Mintz 					   pci_power_t state);
890fe56b9e6SYuval Mintz 
891712c3cbfSMintz, Yuval 	void (*set_name) (struct qed_dev *cdev, char name[]);
892fe56b9e6SYuval Mintz 
893fe56b9e6SYuval Mintz 	/* Client drivers need to make this call before slowpath_start.
894fe56b9e6SYuval Mintz 	 * PF params required for the call before slowpath_start is
895fe56b9e6SYuval Mintz 	 * documented within the qed_pf_params structure definition.
896fe56b9e6SYuval Mintz 	 */
897fe56b9e6SYuval Mintz 	void		(*update_pf_params)(struct qed_dev *cdev,
898fe56b9e6SYuval Mintz 					    struct qed_pf_params *params);
899fe56b9e6SYuval Mintz 	int		(*slowpath_start)(struct qed_dev *cdev,
900fe56b9e6SYuval Mintz 					  struct qed_slowpath_params *params);
901fe56b9e6SYuval Mintz 
902fe56b9e6SYuval Mintz 	int		(*slowpath_stop)(struct qed_dev *cdev);
903fe56b9e6SYuval Mintz 
904fe56b9e6SYuval Mintz 	/* Requests to use `cnt' interrupts for fastpath.
905fe56b9e6SYuval Mintz 	 * upon success, returns number of interrupts allocated for fastpath.
906fe56b9e6SYuval Mintz 	 */
907fe56b9e6SYuval Mintz 	int		(*set_fp_int)(struct qed_dev *cdev,
908fe56b9e6SYuval Mintz 				      u16 cnt);
909fe56b9e6SYuval Mintz 
910fe56b9e6SYuval Mintz 	/* Fills `info' with pointers required for utilizing interrupts */
911fe56b9e6SYuval Mintz 	int		(*get_fp_int)(struct qed_dev *cdev,
912fe56b9e6SYuval Mintz 				      struct qed_int_info *info);
913fe56b9e6SYuval Mintz 
914fe56b9e6SYuval Mintz 	u32		(*sb_init)(struct qed_dev *cdev,
915fe56b9e6SYuval Mintz 				   struct qed_sb_info *sb_info,
916fe56b9e6SYuval Mintz 				   void *sb_virt_addr,
917fe56b9e6SYuval Mintz 				   dma_addr_t sb_phy_addr,
918fe56b9e6SYuval Mintz 				   u16 sb_id,
919fe56b9e6SYuval Mintz 				   enum qed_sb_type type);
920fe56b9e6SYuval Mintz 
921fe56b9e6SYuval Mintz 	u32		(*sb_release)(struct qed_dev *cdev,
922fe56b9e6SYuval Mintz 				      struct qed_sb_info *sb_info,
92308eb1fb0SMichal Kalderon 				      u16 sb_id,
92408eb1fb0SMichal Kalderon 				      enum qed_sb_type type);
925fe56b9e6SYuval Mintz 
926fe56b9e6SYuval Mintz 	void		(*simd_handler_config)(struct qed_dev *cdev,
927fe56b9e6SYuval Mintz 					       void *token,
928fe56b9e6SYuval Mintz 					       int index,
929fe56b9e6SYuval Mintz 					       void (*handler)(void *));
930fe56b9e6SYuval Mintz 
931fe56b9e6SYuval Mintz 	void		(*simd_handler_clean)(struct qed_dev *cdev,
932fe56b9e6SYuval Mintz 					      int index);
9331e128c81SArun Easi 	int (*dbg_grc)(struct qed_dev *cdev,
9341e128c81SArun Easi 		       void *buffer, u32 *num_dumped_bytes);
9351e128c81SArun Easi 
9361e128c81SArun Easi 	int (*dbg_grc_size)(struct qed_dev *cdev);
937fe7cd2bfSYuval Mintz 
938e0971c83STomer Tayar 	int (*dbg_all_data) (struct qed_dev *cdev, void *buffer);
939e0971c83STomer Tayar 
940e0971c83STomer Tayar 	int (*dbg_all_data_size) (struct qed_dev *cdev);
941e0971c83STomer Tayar 
942fe7cd2bfSYuval Mintz /**
943fe7cd2bfSYuval Mintz  * @brief can_link_change - can the instance change the link or not
944fe7cd2bfSYuval Mintz  *
945fe7cd2bfSYuval Mintz  * @param cdev
946fe7cd2bfSYuval Mintz  *
947fe7cd2bfSYuval Mintz  * @return true if link-change is allowed, false otherwise.
948fe7cd2bfSYuval Mintz  */
949fe7cd2bfSYuval Mintz 	bool (*can_link_change)(struct qed_dev *cdev);
950fe7cd2bfSYuval Mintz 
951fe56b9e6SYuval Mintz /**
952fe56b9e6SYuval Mintz  * @brief set_link - set links according to params
953fe56b9e6SYuval Mintz  *
954fe56b9e6SYuval Mintz  * @param cdev
955fe56b9e6SYuval Mintz  * @param params - values used to override the default link configuration
956fe56b9e6SYuval Mintz  *
957fe56b9e6SYuval Mintz  * @return 0 on success, error otherwise.
958fe56b9e6SYuval Mintz  */
959fe56b9e6SYuval Mintz 	int		(*set_link)(struct qed_dev *cdev,
960fe56b9e6SYuval Mintz 				    struct qed_link_params *params);
961fe56b9e6SYuval Mintz 
962fe56b9e6SYuval Mintz /**
963fe56b9e6SYuval Mintz  * @brief get_link - returns the current link state.
964fe56b9e6SYuval Mintz  *
965fe56b9e6SYuval Mintz  * @param cdev
966fe56b9e6SYuval Mintz  * @param if_link - structure to be filled with current link configuration.
967fe56b9e6SYuval Mintz  */
968fe56b9e6SYuval Mintz 	void		(*get_link)(struct qed_dev *cdev,
969fe56b9e6SYuval Mintz 				    struct qed_link_output *if_link);
970fe56b9e6SYuval Mintz 
971fe56b9e6SYuval Mintz /**
972fe56b9e6SYuval Mintz  * @brief - drains chip in case Tx completions fail to arrive due to pause.
973fe56b9e6SYuval Mintz  *
974fe56b9e6SYuval Mintz  * @param cdev
975fe56b9e6SYuval Mintz  */
976fe56b9e6SYuval Mintz 	int		(*drain)(struct qed_dev *cdev);
977fe56b9e6SYuval Mintz 
978fe56b9e6SYuval Mintz /**
979fe56b9e6SYuval Mintz  * @brief update_msglvl - update module debug level
980fe56b9e6SYuval Mintz  *
981fe56b9e6SYuval Mintz  * @param cdev
982fe56b9e6SYuval Mintz  * @param dp_module
983fe56b9e6SYuval Mintz  * @param dp_level
984fe56b9e6SYuval Mintz  */
985fe56b9e6SYuval Mintz 	void		(*update_msglvl)(struct qed_dev *cdev,
986fe56b9e6SYuval Mintz 					 u32 dp_module,
987fe56b9e6SYuval Mintz 					 u8 dp_level);
988fe56b9e6SYuval Mintz 
989fe56b9e6SYuval Mintz 	int		(*chain_alloc)(struct qed_dev *cdev,
990fe56b9e6SYuval Mintz 				       enum qed_chain_use_mode intended_use,
991fe56b9e6SYuval Mintz 				       enum qed_chain_mode mode,
992a91eb52aSYuval Mintz 				       enum qed_chain_cnt_type cnt_type,
993a91eb52aSYuval Mintz 				       u32 num_elems,
994fe56b9e6SYuval Mintz 				       size_t elem_size,
9951a4a6975SMintz, Yuval 				       struct qed_chain *p_chain,
9961a4a6975SMintz, Yuval 				       struct qed_chain_ext_pbl *ext_pbl);
997fe56b9e6SYuval Mintz 
998fe56b9e6SYuval Mintz 	void		(*chain_free)(struct qed_dev *cdev,
999fe56b9e6SYuval Mintz 				      struct qed_chain *p_chain);
100091420b83SSudarsana Kalluru 
100191420b83SSudarsana Kalluru /**
10023a69cae8SSudarsana Reddy Kalluru  * @brief nvm_flash - Flash nvm data.
10033a69cae8SSudarsana Reddy Kalluru  *
10043a69cae8SSudarsana Reddy Kalluru  * @param cdev
10053a69cae8SSudarsana Reddy Kalluru  * @param name - file containing the data
10063a69cae8SSudarsana Reddy Kalluru  *
10073a69cae8SSudarsana Reddy Kalluru  * @return 0 on success, error otherwise.
10083a69cae8SSudarsana Reddy Kalluru  */
10093a69cae8SSudarsana Reddy Kalluru 	int (*nvm_flash)(struct qed_dev *cdev, const char *name);
10103a69cae8SSudarsana Reddy Kalluru 
10113a69cae8SSudarsana Reddy Kalluru /**
101220675b37SMintz, Yuval  * @brief nvm_get_image - reads an entire image from nvram
101320675b37SMintz, Yuval  *
101420675b37SMintz, Yuval  * @param cdev
101520675b37SMintz, Yuval  * @param type - type of the request nvram image
101620675b37SMintz, Yuval  * @param buf - preallocated buffer to fill with the image
101720675b37SMintz, Yuval  * @param len - length of the allocated buffer
101820675b37SMintz, Yuval  *
101920675b37SMintz, Yuval  * @return 0 on success, error otherwise
102020675b37SMintz, Yuval  */
102120675b37SMintz, Yuval 	int (*nvm_get_image)(struct qed_dev *cdev,
102220675b37SMintz, Yuval 			     enum qed_nvm_images type, u8 *buf, u16 len);
102320675b37SMintz, Yuval 
102420675b37SMintz, Yuval /**
1025722003acSSudarsana Reddy Kalluru  * @brief set_coalesce - Configure Rx coalesce value in usec
1026722003acSSudarsana Reddy Kalluru  *
1027722003acSSudarsana Reddy Kalluru  * @param cdev
1028722003acSSudarsana Reddy Kalluru  * @param rx_coal - Rx coalesce value in usec
1029722003acSSudarsana Reddy Kalluru  * @param tx_coal - Tx coalesce value in usec
1030722003acSSudarsana Reddy Kalluru  * @param qid - Queue index
1031722003acSSudarsana Reddy Kalluru  * @param sb_id - Status Block Id
1032722003acSSudarsana Reddy Kalluru  *
1033722003acSSudarsana Reddy Kalluru  * @return 0 on success, error otherwise.
1034722003acSSudarsana Reddy Kalluru  */
1035477f2d14SRahul Verma 	int (*set_coalesce)(struct qed_dev *cdev,
1036477f2d14SRahul Verma 			    u16 rx_coal, u16 tx_coal, void *handle);
1037722003acSSudarsana Reddy Kalluru 
1038722003acSSudarsana Reddy Kalluru /**
103991420b83SSudarsana Kalluru  * @brief set_led - Configure LED mode
104091420b83SSudarsana Kalluru  *
104191420b83SSudarsana Kalluru  * @param cdev
104291420b83SSudarsana Kalluru  * @param mode - LED mode
104391420b83SSudarsana Kalluru  *
104491420b83SSudarsana Kalluru  * @return 0 on success, error otherwise.
104591420b83SSudarsana Kalluru  */
104691420b83SSudarsana Kalluru 	int (*set_led)(struct qed_dev *cdev,
104791420b83SSudarsana Kalluru 		       enum qed_led_mode mode);
1048936c7ba4SIgor Russkikh 
1049936c7ba4SIgor Russkikh /**
1050936c7ba4SIgor Russkikh  * @brief attn_clr_enable - Prevent attentions from being reasserted
1051936c7ba4SIgor Russkikh  *
1052936c7ba4SIgor Russkikh  * @param cdev
1053936c7ba4SIgor Russkikh  * @param clr_enable
1054936c7ba4SIgor Russkikh  */
1055936c7ba4SIgor Russkikh 	void (*attn_clr_enable)(struct qed_dev *cdev, bool clr_enable);
1056936c7ba4SIgor Russkikh 
10570e1f1044SAriel Elior /**
10580e1f1044SAriel Elior  * @brief db_recovery_add - add doorbell information to the doorbell
10590e1f1044SAriel Elior  * recovery mechanism.
10600e1f1044SAriel Elior  *
10610e1f1044SAriel Elior  * @param cdev
10620e1f1044SAriel Elior  * @param db_addr - doorbell address
10630e1f1044SAriel Elior  * @param db_data - address of where db_data is stored
10640e1f1044SAriel Elior  * @param db_is_32b - doorbell is 32b pr 64b
10650e1f1044SAriel Elior  * @param db_is_user - doorbell recovery addresses are user or kernel space
10660e1f1044SAriel Elior  */
10670e1f1044SAriel Elior 	int (*db_recovery_add)(struct qed_dev *cdev,
10680e1f1044SAriel Elior 			       void __iomem *db_addr,
10690e1f1044SAriel Elior 			       void *db_data,
10700e1f1044SAriel Elior 			       enum qed_db_rec_width db_width,
10710e1f1044SAriel Elior 			       enum qed_db_rec_space db_space);
10720e1f1044SAriel Elior 
10730e1f1044SAriel Elior /**
10740e1f1044SAriel Elior  * @brief db_recovery_del - remove doorbell information from the doorbell
10750e1f1044SAriel Elior  * recovery mechanism. db_data serves as key (db_addr is not unique).
10760e1f1044SAriel Elior  *
10770e1f1044SAriel Elior  * @param cdev
10780e1f1044SAriel Elior  * @param db_addr - doorbell address
10790e1f1044SAriel Elior  * @param db_data - address where db_data is stored. Serves as key for the
10800e1f1044SAriel Elior  *		    entry to delete.
10810e1f1044SAriel Elior  */
10820e1f1044SAriel Elior 	int (*db_recovery_del)(struct qed_dev *cdev,
10830e1f1044SAriel Elior 			       void __iomem *db_addr, void *db_data);
10840fefbfbaSSudarsana Kalluru 
10850fefbfbaSSudarsana Kalluru /**
108664515dc8STomer Tayar  * @brief recovery_process - Trigger a recovery process
108764515dc8STomer Tayar  *
108864515dc8STomer Tayar  * @param cdev
108964515dc8STomer Tayar  *
109064515dc8STomer Tayar  * @return 0 on success, error otherwise.
109164515dc8STomer Tayar  */
109264515dc8STomer Tayar 	int (*recovery_process)(struct qed_dev *cdev);
109364515dc8STomer Tayar 
109464515dc8STomer Tayar /**
109564515dc8STomer Tayar  * @brief recovery_prolog - Execute the prolog operations of a recovery process
109664515dc8STomer Tayar  *
109764515dc8STomer Tayar  * @param cdev
109864515dc8STomer Tayar  *
109964515dc8STomer Tayar  * @return 0 on success, error otherwise.
110064515dc8STomer Tayar  */
110164515dc8STomer Tayar 	int (*recovery_prolog)(struct qed_dev *cdev);
110264515dc8STomer Tayar 
110364515dc8STomer Tayar /**
11040fefbfbaSSudarsana Kalluru  * @brief update_drv_state - API to inform the change in the driver state.
11050fefbfbaSSudarsana Kalluru  *
11060fefbfbaSSudarsana Kalluru  * @param cdev
11070fefbfbaSSudarsana Kalluru  * @param active
11080fefbfbaSSudarsana Kalluru  *
11090fefbfbaSSudarsana Kalluru  */
11100fefbfbaSSudarsana Kalluru 	int (*update_drv_state)(struct qed_dev *cdev, bool active);
11110fefbfbaSSudarsana Kalluru 
11120fefbfbaSSudarsana Kalluru /**
11130fefbfbaSSudarsana Kalluru  * @brief update_mac - API to inform the change in the mac address
11140fefbfbaSSudarsana Kalluru  *
11150fefbfbaSSudarsana Kalluru  * @param cdev
11160fefbfbaSSudarsana Kalluru  * @param mac
11170fefbfbaSSudarsana Kalluru  *
11180fefbfbaSSudarsana Kalluru  */
11190fefbfbaSSudarsana Kalluru 	int (*update_mac)(struct qed_dev *cdev, u8 *mac);
11200fefbfbaSSudarsana Kalluru 
11210fefbfbaSSudarsana Kalluru /**
11220fefbfbaSSudarsana Kalluru  * @brief update_mtu - API to inform the change in the mtu
11230fefbfbaSSudarsana Kalluru  *
11240fefbfbaSSudarsana Kalluru  * @param cdev
11250fefbfbaSSudarsana Kalluru  * @param mtu
11260fefbfbaSSudarsana Kalluru  *
11270fefbfbaSSudarsana Kalluru  */
11280fefbfbaSSudarsana Kalluru 	int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
112914d39648SMintz, Yuval 
113014d39648SMintz, Yuval /**
113114d39648SMintz, Yuval  * @brief update_wol - update of changes in the WoL configuration
113214d39648SMintz, Yuval  *
113314d39648SMintz, Yuval  * @param cdev
113414d39648SMintz, Yuval  * @param enabled - true iff WoL should be enabled.
113514d39648SMintz, Yuval  */
113614d39648SMintz, Yuval 	int (*update_wol) (struct qed_dev *cdev, bool enabled);
1137b51dab46SSudarsana Reddy Kalluru 
1138b51dab46SSudarsana Reddy Kalluru /**
1139b51dab46SSudarsana Reddy Kalluru  * @brief read_module_eeprom
1140b51dab46SSudarsana Reddy Kalluru  *
1141b51dab46SSudarsana Reddy Kalluru  * @param cdev
1142b51dab46SSudarsana Reddy Kalluru  * @param buf - buffer
1143b51dab46SSudarsana Reddy Kalluru  * @param dev_addr - PHY device memory region
1144b51dab46SSudarsana Reddy Kalluru  * @param offset - offset into eeprom contents to be read
1145b51dab46SSudarsana Reddy Kalluru  * @param len - buffer length, i.e., max bytes to be read
1146b51dab46SSudarsana Reddy Kalluru  */
1147b51dab46SSudarsana Reddy Kalluru 	int (*read_module_eeprom)(struct qed_dev *cdev,
1148b51dab46SSudarsana Reddy Kalluru 				  char *buf, u8 dev_addr, u32 offset, u32 len);
114908eb1fb0SMichal Kalderon 
115008eb1fb0SMichal Kalderon /**
115108eb1fb0SMichal Kalderon  * @brief get_affin_hwfn_idx
115208eb1fb0SMichal Kalderon  *
115308eb1fb0SMichal Kalderon  * @param cdev
115408eb1fb0SMichal Kalderon  */
115508eb1fb0SMichal Kalderon 	u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev);
11562d4c8495SSudarsana Reddy Kalluru 
11572d4c8495SSudarsana Reddy Kalluru /**
11582d4c8495SSudarsana Reddy Kalluru  * @brief read_nvm_cfg - Read NVM config attribute value.
11592d4c8495SSudarsana Reddy Kalluru  * @param cdev
11602d4c8495SSudarsana Reddy Kalluru  * @param buf - buffer
11612d4c8495SSudarsana Reddy Kalluru  * @param cmd - NVM CFG command id
11622d4c8495SSudarsana Reddy Kalluru  * @param entity_id - Entity id
11632d4c8495SSudarsana Reddy Kalluru  *
11642d4c8495SSudarsana Reddy Kalluru  */
11652d4c8495SSudarsana Reddy Kalluru 	int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd,
11662d4c8495SSudarsana Reddy Kalluru 			    u32 entity_id);
11679e54ba7cSSudarsana Reddy Kalluru /**
11689e54ba7cSSudarsana Reddy Kalluru  * @brief read_nvm_cfg - Read NVM config attribute value.
11699e54ba7cSSudarsana Reddy Kalluru  * @param cdev
11709e54ba7cSSudarsana Reddy Kalluru  * @param cmd - NVM CFG command id
11719e54ba7cSSudarsana Reddy Kalluru  *
11729e54ba7cSSudarsana Reddy Kalluru  * @return config id length, 0 on error.
11739e54ba7cSSudarsana Reddy Kalluru  */
11749e54ba7cSSudarsana Reddy Kalluru 	int (*read_nvm_cfg_len)(struct qed_dev *cdev, u32 cmd);
11753b86bd07SSudarsana Reddy Kalluru 
11763b86bd07SSudarsana Reddy Kalluru /**
11773b86bd07SSudarsana Reddy Kalluru  * @brief set_grc_config - Configure value for grc config id.
11783b86bd07SSudarsana Reddy Kalluru  * @param cdev
11793b86bd07SSudarsana Reddy Kalluru  * @param cfg_id - grc config id
11803b86bd07SSudarsana Reddy Kalluru  * @param val - grc config value
11813b86bd07SSudarsana Reddy Kalluru  *
11823b86bd07SSudarsana Reddy Kalluru  */
11833b86bd07SSudarsana Reddy Kalluru 	int (*set_grc_config)(struct qed_dev *cdev, u32 cfg_id, u32 val);
1184fe56b9e6SYuval Mintz };
1185fe56b9e6SYuval Mintz 
1186fe56b9e6SYuval Mintz #define MASK_FIELD(_name, _value) \
1187fe56b9e6SYuval Mintz 	((_value) &= (_name ## _MASK))
1188fe56b9e6SYuval Mintz 
1189fe56b9e6SYuval Mintz #define FIELD_VALUE(_name, _value) \
1190fe56b9e6SYuval Mintz 	((_value & _name ## _MASK) << _name ## _SHIFT)
1191fe56b9e6SYuval Mintz 
1192fe56b9e6SYuval Mintz #define SET_FIELD(value, name, flag)			       \
1193fe56b9e6SYuval Mintz 	do {						       \
1194fe56b9e6SYuval Mintz 		(value) &= ~(name ## _MASK << name ## _SHIFT); \
1195fe56b9e6SYuval Mintz 		(value) |= (((u64)flag) << (name ## _SHIFT));  \
1196fe56b9e6SYuval Mintz 	} while (0)
1197fe56b9e6SYuval Mintz 
1198fe56b9e6SYuval Mintz #define GET_FIELD(value, name) \
1199fe56b9e6SYuval Mintz 	(((value) >> (name ## _SHIFT)) & name ## _MASK)
1200fe56b9e6SYuval Mintz 
12012d22bc83SMichal Kalderon #define GET_MFW_FIELD(name, field) \
12022d22bc83SMichal Kalderon 	(((name) & (field ## _MASK)) >> (field ## _OFFSET))
12032d22bc83SMichal Kalderon 
12042d22bc83SMichal Kalderon #define SET_MFW_FIELD(name, field, value)				 \
12052d22bc83SMichal Kalderon 	do {								 \
12062d22bc83SMichal Kalderon 		(name) &= ~(field ## _MASK);				 \
12072d22bc83SMichal Kalderon 		(name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK));\
12082d22bc83SMichal Kalderon 	} while (0)
12092d22bc83SMichal Kalderon 
1210997af5dfSMichal Kalderon #define DB_ADDR_SHIFT(addr) ((addr) << DB_PWM_ADDR_OFFSET_SHIFT)
1211997af5dfSMichal Kalderon 
1212fe56b9e6SYuval Mintz /* Debug print definitions */
1213fe56b9e6SYuval Mintz #define DP_ERR(cdev, fmt, ...)					\
12149d7650c2SMintz, Yuval 	do {							\
1215fe56b9e6SYuval Mintz 		pr_err("[%s:%d(%s)]" fmt,			\
1216fe56b9e6SYuval Mintz 		       __func__, __LINE__,			\
1217fe56b9e6SYuval Mintz 		       DP_NAME(cdev) ? DP_NAME(cdev) : "",	\
12189d7650c2SMintz, Yuval 		       ## __VA_ARGS__);				\
12199d7650c2SMintz, Yuval 	} while (0)
1220fe56b9e6SYuval Mintz 
1221fe56b9e6SYuval Mintz #define DP_NOTICE(cdev, fmt, ...)				      \
1222fe56b9e6SYuval Mintz 	do {							      \
1223fe56b9e6SYuval Mintz 		if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
1224fe56b9e6SYuval Mintz 			pr_notice("[%s:%d(%s)]" fmt,		      \
1225fe56b9e6SYuval Mintz 				  __func__, __LINE__,		      \
1226fe56b9e6SYuval Mintz 				  DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1227fe56b9e6SYuval Mintz 				  ## __VA_ARGS__);		      \
1228fe56b9e6SYuval Mintz 								      \
1229fe56b9e6SYuval Mintz 		}						      \
1230fe56b9e6SYuval Mintz 	} while (0)
1231fe56b9e6SYuval Mintz 
1232fe56b9e6SYuval Mintz #define DP_INFO(cdev, fmt, ...)					      \
1233fe56b9e6SYuval Mintz 	do {							      \
1234fe56b9e6SYuval Mintz 		if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) {   \
1235fe56b9e6SYuval Mintz 			pr_notice("[%s:%d(%s)]" fmt,		      \
1236fe56b9e6SYuval Mintz 				  __func__, __LINE__,		      \
1237fe56b9e6SYuval Mintz 				  DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1238fe56b9e6SYuval Mintz 				  ## __VA_ARGS__);		      \
1239fe56b9e6SYuval Mintz 		}						      \
1240fe56b9e6SYuval Mintz 	} while (0)
1241fe56b9e6SYuval Mintz 
1242fe56b9e6SYuval Mintz #define DP_VERBOSE(cdev, module, fmt, ...)				\
1243fe56b9e6SYuval Mintz 	do {								\
1244fe56b9e6SYuval Mintz 		if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) &&	\
1245fe56b9e6SYuval Mintz 			     ((cdev)->dp_module & module))) {		\
1246fe56b9e6SYuval Mintz 			pr_notice("[%s:%d(%s)]" fmt,			\
1247fe56b9e6SYuval Mintz 				  __func__, __LINE__,			\
1248fe56b9e6SYuval Mintz 				  DP_NAME(cdev) ? DP_NAME(cdev) : "",	\
1249fe56b9e6SYuval Mintz 				  ## __VA_ARGS__);			\
1250fe56b9e6SYuval Mintz 		}							\
1251fe56b9e6SYuval Mintz 	} while (0)
1252fe56b9e6SYuval Mintz 
1253fe56b9e6SYuval Mintz enum DP_LEVEL {
1254fe56b9e6SYuval Mintz 	QED_LEVEL_VERBOSE	= 0x0,
1255fe56b9e6SYuval Mintz 	QED_LEVEL_INFO		= 0x1,
1256fe56b9e6SYuval Mintz 	QED_LEVEL_NOTICE	= 0x2,
1257fe56b9e6SYuval Mintz 	QED_LEVEL_ERR		= 0x3,
1258fe56b9e6SYuval Mintz };
1259fe56b9e6SYuval Mintz 
1260fe56b9e6SYuval Mintz #define QED_LOG_LEVEL_SHIFT     (30)
1261fe56b9e6SYuval Mintz #define QED_LOG_VERBOSE_MASK    (0x3fffffff)
1262fe56b9e6SYuval Mintz #define QED_LOG_INFO_MASK       (0x40000000)
1263fe56b9e6SYuval Mintz #define QED_LOG_NOTICE_MASK     (0x80000000)
1264fe56b9e6SYuval Mintz 
1265fe56b9e6SYuval Mintz enum DP_MODULE {
1266fe56b9e6SYuval Mintz 	QED_MSG_SPQ	= 0x10000,
1267fe56b9e6SYuval Mintz 	QED_MSG_STATS	= 0x20000,
1268fe56b9e6SYuval Mintz 	QED_MSG_DCB	= 0x40000,
1269fe56b9e6SYuval Mintz 	QED_MSG_IOV	= 0x80000,
1270fe56b9e6SYuval Mintz 	QED_MSG_SP	= 0x100000,
1271fe56b9e6SYuval Mintz 	QED_MSG_STORAGE = 0x200000,
1272fe56b9e6SYuval Mintz 	QED_MSG_CXT	= 0x800000,
12730a7fb11cSYuval Mintz 	QED_MSG_LL2	= 0x1000000,
1274fe56b9e6SYuval Mintz 	QED_MSG_ILT	= 0x2000000,
127551ff1725SRam Amrani 	QED_MSG_RDMA	= 0x4000000,
1276fe56b9e6SYuval Mintz 	QED_MSG_DEBUG	= 0x8000000,
1277fe56b9e6SYuval Mintz 	/* to be added...up to 0x8000000 */
1278fe56b9e6SYuval Mintz };
1279fe56b9e6SYuval Mintz 
1280fc48b7a6SYuval Mintz enum qed_mf_mode {
1281fc48b7a6SYuval Mintz 	QED_MF_DEFAULT,
1282fc48b7a6SYuval Mintz 	QED_MF_OVLAN,
1283fc48b7a6SYuval Mintz 	QED_MF_NPAR,
1284fc48b7a6SYuval Mintz };
1285fc48b7a6SYuval Mintz 
12869c79ddaaSMintz, Yuval struct qed_eth_stats_common {
1287fe56b9e6SYuval Mintz 	u64	no_buff_discards;
1288fe56b9e6SYuval Mintz 	u64	packet_too_big_discard;
1289fe56b9e6SYuval Mintz 	u64	ttl0_discard;
1290fe56b9e6SYuval Mintz 	u64	rx_ucast_bytes;
1291fe56b9e6SYuval Mintz 	u64	rx_mcast_bytes;
1292fe56b9e6SYuval Mintz 	u64	rx_bcast_bytes;
1293fe56b9e6SYuval Mintz 	u64	rx_ucast_pkts;
1294fe56b9e6SYuval Mintz 	u64	rx_mcast_pkts;
1295fe56b9e6SYuval Mintz 	u64	rx_bcast_pkts;
1296fe56b9e6SYuval Mintz 	u64	mftag_filter_discards;
1297fe56b9e6SYuval Mintz 	u64	mac_filter_discards;
1298608e00d0SManish Chopra 	u64	gft_filter_drop;
1299fe56b9e6SYuval Mintz 	u64	tx_ucast_bytes;
1300fe56b9e6SYuval Mintz 	u64	tx_mcast_bytes;
1301fe56b9e6SYuval Mintz 	u64	tx_bcast_bytes;
1302fe56b9e6SYuval Mintz 	u64	tx_ucast_pkts;
1303fe56b9e6SYuval Mintz 	u64	tx_mcast_pkts;
1304fe56b9e6SYuval Mintz 	u64	tx_bcast_pkts;
1305fe56b9e6SYuval Mintz 	u64	tx_err_drop_pkts;
1306fe56b9e6SYuval Mintz 	u64	tpa_coalesced_pkts;
1307fe56b9e6SYuval Mintz 	u64	tpa_coalesced_events;
1308fe56b9e6SYuval Mintz 	u64	tpa_aborts_num;
1309fe56b9e6SYuval Mintz 	u64	tpa_not_coalesced_pkts;
1310fe56b9e6SYuval Mintz 	u64	tpa_coalesced_bytes;
1311fe56b9e6SYuval Mintz 
1312fe56b9e6SYuval Mintz 	/* port */
1313fe56b9e6SYuval Mintz 	u64	rx_64_byte_packets;
1314d4967cf3SYuval Mintz 	u64	rx_65_to_127_byte_packets;
1315d4967cf3SYuval Mintz 	u64	rx_128_to_255_byte_packets;
1316d4967cf3SYuval Mintz 	u64	rx_256_to_511_byte_packets;
1317d4967cf3SYuval Mintz 	u64	rx_512_to_1023_byte_packets;
1318d4967cf3SYuval Mintz 	u64	rx_1024_to_1518_byte_packets;
1319fe56b9e6SYuval Mintz 	u64	rx_crc_errors;
1320fe56b9e6SYuval Mintz 	u64	rx_mac_crtl_frames;
1321fe56b9e6SYuval Mintz 	u64	rx_pause_frames;
1322fe56b9e6SYuval Mintz 	u64	rx_pfc_frames;
1323fe56b9e6SYuval Mintz 	u64	rx_align_errors;
1324fe56b9e6SYuval Mintz 	u64	rx_carrier_errors;
1325fe56b9e6SYuval Mintz 	u64	rx_oversize_packets;
1326fe56b9e6SYuval Mintz 	u64	rx_jabbers;
1327fe56b9e6SYuval Mintz 	u64	rx_undersize_packets;
1328fe56b9e6SYuval Mintz 	u64	rx_fragments;
1329fe56b9e6SYuval Mintz 	u64	tx_64_byte_packets;
1330fe56b9e6SYuval Mintz 	u64	tx_65_to_127_byte_packets;
1331fe56b9e6SYuval Mintz 	u64	tx_128_to_255_byte_packets;
1332fe56b9e6SYuval Mintz 	u64	tx_256_to_511_byte_packets;
1333fe56b9e6SYuval Mintz 	u64	tx_512_to_1023_byte_packets;
1334fe56b9e6SYuval Mintz 	u64	tx_1024_to_1518_byte_packets;
1335fe56b9e6SYuval Mintz 	u64	tx_pause_frames;
1336fe56b9e6SYuval Mintz 	u64	tx_pfc_frames;
1337fe56b9e6SYuval Mintz 	u64	brb_truncates;
1338fe56b9e6SYuval Mintz 	u64	brb_discards;
1339fe56b9e6SYuval Mintz 	u64	rx_mac_bytes;
1340fe56b9e6SYuval Mintz 	u64	rx_mac_uc_packets;
1341fe56b9e6SYuval Mintz 	u64	rx_mac_mc_packets;
1342fe56b9e6SYuval Mintz 	u64	rx_mac_bc_packets;
1343fe56b9e6SYuval Mintz 	u64	rx_mac_frames_ok;
1344fe56b9e6SYuval Mintz 	u64	tx_mac_bytes;
1345fe56b9e6SYuval Mintz 	u64	tx_mac_uc_packets;
1346fe56b9e6SYuval Mintz 	u64	tx_mac_mc_packets;
1347fe56b9e6SYuval Mintz 	u64	tx_mac_bc_packets;
1348fe56b9e6SYuval Mintz 	u64	tx_mac_ctrl_frames;
134932d26a68SSudarsana Reddy Kalluru 	u64	link_change_count;
1350fe56b9e6SYuval Mintz };
1351fe56b9e6SYuval Mintz 
13529c79ddaaSMintz, Yuval struct qed_eth_stats_bb {
13539c79ddaaSMintz, Yuval 	u64 rx_1519_to_1522_byte_packets;
13549c79ddaaSMintz, Yuval 	u64 rx_1519_to_2047_byte_packets;
13559c79ddaaSMintz, Yuval 	u64 rx_2048_to_4095_byte_packets;
13569c79ddaaSMintz, Yuval 	u64 rx_4096_to_9216_byte_packets;
13579c79ddaaSMintz, Yuval 	u64 rx_9217_to_16383_byte_packets;
13589c79ddaaSMintz, Yuval 	u64 tx_1519_to_2047_byte_packets;
13599c79ddaaSMintz, Yuval 	u64 tx_2048_to_4095_byte_packets;
13609c79ddaaSMintz, Yuval 	u64 tx_4096_to_9216_byte_packets;
13619c79ddaaSMintz, Yuval 	u64 tx_9217_to_16383_byte_packets;
13629c79ddaaSMintz, Yuval 	u64 tx_lpi_entry_count;
13639c79ddaaSMintz, Yuval 	u64 tx_total_collisions;
13649c79ddaaSMintz, Yuval };
13659c79ddaaSMintz, Yuval 
13669c79ddaaSMintz, Yuval struct qed_eth_stats_ah {
13679c79ddaaSMintz, Yuval 	u64 rx_1519_to_max_byte_packets;
13689c79ddaaSMintz, Yuval 	u64 tx_1519_to_max_byte_packets;
13699c79ddaaSMintz, Yuval };
13709c79ddaaSMintz, Yuval 
13719c79ddaaSMintz, Yuval struct qed_eth_stats {
13729c79ddaaSMintz, Yuval 	struct qed_eth_stats_common common;
13739c79ddaaSMintz, Yuval 
13749c79ddaaSMintz, Yuval 	union {
13759c79ddaaSMintz, Yuval 		struct qed_eth_stats_bb bb;
13769c79ddaaSMintz, Yuval 		struct qed_eth_stats_ah ah;
13779c79ddaaSMintz, Yuval 	};
13789c79ddaaSMintz, Yuval };
13799c79ddaaSMintz, Yuval 
1380fe56b9e6SYuval Mintz #define QED_SB_IDX              0x0002
1381fe56b9e6SYuval Mintz 
1382fe56b9e6SYuval Mintz #define RX_PI           0
1383fe56b9e6SYuval Mintz #define TX_PI(tc)       (RX_PI + 1 + tc)
1384fe56b9e6SYuval Mintz 
13854ac801b7SYuval Mintz struct qed_sb_cnt_info {
1386726fdbe9SMintz, Yuval 	/* Original, current, and free SBs for PF */
1387726fdbe9SMintz, Yuval 	int orig;
1388726fdbe9SMintz, Yuval 	int cnt;
1389726fdbe9SMintz, Yuval 	int free_cnt;
1390726fdbe9SMintz, Yuval 
1391726fdbe9SMintz, Yuval 	/* Original, current and free SBS for child VFs */
1392726fdbe9SMintz, Yuval 	int iov_orig;
1393726fdbe9SMintz, Yuval 	int iov_cnt;
1394726fdbe9SMintz, Yuval 	int free_cnt_iov;
13954ac801b7SYuval Mintz };
13964ac801b7SYuval Mintz 
1397fe56b9e6SYuval Mintz static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
1398fe56b9e6SYuval Mintz {
1399fe56b9e6SYuval Mintz 	u32 prod = 0;
1400fe56b9e6SYuval Mintz 	u16 rc = 0;
1401fe56b9e6SYuval Mintz 
1402fe56b9e6SYuval Mintz 	prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
140321dd79e8STomer Tayar 	       STATUS_BLOCK_E4_PROD_INDEX_MASK;
1404fe56b9e6SYuval Mintz 	if (sb_info->sb_ack != prod) {
1405fe56b9e6SYuval Mintz 		sb_info->sb_ack = prod;
1406fe56b9e6SYuval Mintz 		rc |= QED_SB_IDX;
1407fe56b9e6SYuval Mintz 	}
1408fe56b9e6SYuval Mintz 
1409fe56b9e6SYuval Mintz 	/* Let SB update */
1410fe56b9e6SYuval Mintz 	return rc;
1411fe56b9e6SYuval Mintz }
1412fe56b9e6SYuval Mintz 
1413fe56b9e6SYuval Mintz /**
1414fe56b9e6SYuval Mintz  *
1415fe56b9e6SYuval Mintz  * @brief This function creates an update command for interrupts that is
1416fe56b9e6SYuval Mintz  *        written to the IGU.
1417fe56b9e6SYuval Mintz  *
1418fe56b9e6SYuval Mintz  * @param sb_info       - This is the structure allocated and
1419fe56b9e6SYuval Mintz  *                 initialized per status block. Assumption is
1420fe56b9e6SYuval Mintz  *                 that it was initialized using qed_sb_init
1421fe56b9e6SYuval Mintz  * @param int_cmd       - Enable/Disable/Nop
1422fe56b9e6SYuval Mintz  * @param upd_flg       - whether igu consumer should be
1423fe56b9e6SYuval Mintz  *                 updated.
1424fe56b9e6SYuval Mintz  *
1425fe56b9e6SYuval Mintz  * @return inline void
1426fe56b9e6SYuval Mintz  */
1427fe56b9e6SYuval Mintz static inline void qed_sb_ack(struct qed_sb_info *sb_info,
1428fe56b9e6SYuval Mintz 			      enum igu_int_cmd int_cmd,
1429fe56b9e6SYuval Mintz 			      u8 upd_flg)
1430fe56b9e6SYuval Mintz {
1431fe56b9e6SYuval Mintz 	struct igu_prod_cons_update igu_ack = { 0 };
1432fe56b9e6SYuval Mintz 
1433fe56b9e6SYuval Mintz 	igu_ack.sb_id_and_flags =
1434fe56b9e6SYuval Mintz 		((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1435fe56b9e6SYuval Mintz 		 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1436fe56b9e6SYuval Mintz 		 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1437fe56b9e6SYuval Mintz 		 (IGU_SEG_ACCESS_REG <<
1438fe56b9e6SYuval Mintz 		  IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1439fe56b9e6SYuval Mintz 
1440fe56b9e6SYuval Mintz 	DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
1441fe56b9e6SYuval Mintz 
1442fe56b9e6SYuval Mintz 	/* Both segments (interrupts & acks) are written to same place address;
1443fe56b9e6SYuval Mintz 	 * Need to guarantee all commands will be received (in-order) by HW.
1444fe56b9e6SYuval Mintz 	 */
1445fe56b9e6SYuval Mintz 	barrier();
1446fe56b9e6SYuval Mintz }
1447fe56b9e6SYuval Mintz 
1448fe56b9e6SYuval Mintz static inline void __internal_ram_wr(void *p_hwfn,
1449fe56b9e6SYuval Mintz 				     void __iomem *addr,
1450fe56b9e6SYuval Mintz 				     int size,
1451fe56b9e6SYuval Mintz 				     u32 *data)
1452fe56b9e6SYuval Mintz 
1453fe56b9e6SYuval Mintz {
1454fe56b9e6SYuval Mintz 	unsigned int i;
1455fe56b9e6SYuval Mintz 
1456fe56b9e6SYuval Mintz 	for (i = 0; i < size / sizeof(*data); i++)
1457fe56b9e6SYuval Mintz 		DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
1458fe56b9e6SYuval Mintz }
1459fe56b9e6SYuval Mintz 
1460fe56b9e6SYuval Mintz static inline void internal_ram_wr(void __iomem *addr,
1461fe56b9e6SYuval Mintz 				   int size,
1462fe56b9e6SYuval Mintz 				   u32 *data)
1463fe56b9e6SYuval Mintz {
1464fe56b9e6SYuval Mintz 	__internal_ram_wr(NULL, addr, size, data);
1465fe56b9e6SYuval Mintz }
1466fe56b9e6SYuval Mintz 
14678c5ebd0cSSudarsana Reddy Kalluru enum qed_rss_caps {
14688c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV4		= 0x1,
14698c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV6		= 0x2,
14708c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV4_TCP	= 0x4,
14718c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV6_TCP	= 0x8,
14728c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV4_UDP	= 0x10,
14738c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV6_UDP	= 0x20,
14748c5ebd0cSSudarsana Reddy Kalluru };
14758c5ebd0cSSudarsana Reddy Kalluru 
14768c5ebd0cSSudarsana Reddy Kalluru #define QED_RSS_IND_TABLE_SIZE 128
14778c5ebd0cSSudarsana Reddy Kalluru #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
1478fe56b9e6SYuval Mintz #endif
1479