1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9fe56b9e6SYuval Mintz * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #ifndef _QED_IF_H 34fe56b9e6SYuval Mintz #define _QED_IF_H 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz #include <linux/types.h> 37fe56b9e6SYuval Mintz #include <linux/interrupt.h> 38fe56b9e6SYuval Mintz #include <linux/netdevice.h> 39fe56b9e6SYuval Mintz #include <linux/pci.h> 40fe56b9e6SYuval Mintz #include <linux/skbuff.h> 41fe56b9e6SYuval Mintz #include <linux/types.h> 42fe56b9e6SYuval Mintz #include <asm/byteorder.h> 43fe56b9e6SYuval Mintz #include <linux/io.h> 44fe56b9e6SYuval Mintz #include <linux/compiler.h> 45fe56b9e6SYuval Mintz #include <linux/kernel.h> 46fe56b9e6SYuval Mintz #include <linux/list.h> 47fe56b9e6SYuval Mintz #include <linux/slab.h> 48fe56b9e6SYuval Mintz #include <linux/qed/common_hsi.h> 49fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 50fe56b9e6SYuval Mintz 5139651abdSSudarsana Reddy Kalluru enum dcbx_protocol_type { 5239651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_ISCSI, 5339651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_FCOE, 5439651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_ROCE, 5539651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_ROCE_V2, 5639651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_ETH, 5739651abdSSudarsana Reddy Kalluru DCBX_MAX_PROTOCOL_TYPE 5839651abdSSudarsana Reddy Kalluru }; 5939651abdSSudarsana Reddy Kalluru 6051ff1725SRam Amrani #define QED_ROCE_PROTOCOL_INDEX (3) 6151ff1725SRam Amrani 626ad8c632SSudarsana Reddy Kalluru #define QED_LLDP_CHASSIS_ID_STAT_LEN 4 636ad8c632SSudarsana Reddy Kalluru #define QED_LLDP_PORT_ID_STAT_LEN 4 646ad8c632SSudarsana Reddy Kalluru #define QED_DCBX_MAX_APP_PROTOCOL 32 656ad8c632SSudarsana Reddy Kalluru #define QED_MAX_PFC_PRIORITIES 8 666ad8c632SSudarsana Reddy Kalluru #define QED_DCBX_DSCP_SIZE 64 676ad8c632SSudarsana Reddy Kalluru 686ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_remote { 696ad8c632SSudarsana Reddy Kalluru u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 706ad8c632SSudarsana Reddy Kalluru u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 716ad8c632SSudarsana Reddy Kalluru bool enable_rx; 726ad8c632SSudarsana Reddy Kalluru bool enable_tx; 736ad8c632SSudarsana Reddy Kalluru u32 tx_interval; 746ad8c632SSudarsana Reddy Kalluru u32 max_credit; 756ad8c632SSudarsana Reddy Kalluru }; 766ad8c632SSudarsana Reddy Kalluru 776ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_local { 786ad8c632SSudarsana Reddy Kalluru u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 796ad8c632SSudarsana Reddy Kalluru u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 806ad8c632SSudarsana Reddy Kalluru }; 816ad8c632SSudarsana Reddy Kalluru 826ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_app_prio { 836ad8c632SSudarsana Reddy Kalluru u8 roce; 846ad8c632SSudarsana Reddy Kalluru u8 roce_v2; 856ad8c632SSudarsana Reddy Kalluru u8 fcoe; 866ad8c632SSudarsana Reddy Kalluru u8 iscsi; 876ad8c632SSudarsana Reddy Kalluru u8 eth; 886ad8c632SSudarsana Reddy Kalluru }; 896ad8c632SSudarsana Reddy Kalluru 906ad8c632SSudarsana Reddy Kalluru struct qed_dbcx_pfc_params { 916ad8c632SSudarsana Reddy Kalluru bool willing; 926ad8c632SSudarsana Reddy Kalluru bool enabled; 936ad8c632SSudarsana Reddy Kalluru u8 prio[QED_MAX_PFC_PRIORITIES]; 946ad8c632SSudarsana Reddy Kalluru u8 max_tc; 956ad8c632SSudarsana Reddy Kalluru }; 966ad8c632SSudarsana Reddy Kalluru 9759bcb797SSudarsana Reddy Kalluru enum qed_dcbx_sf_ieee_type { 9859bcb797SSudarsana Reddy Kalluru QED_DCBX_SF_IEEE_ETHTYPE, 9959bcb797SSudarsana Reddy Kalluru QED_DCBX_SF_IEEE_TCP_PORT, 10059bcb797SSudarsana Reddy Kalluru QED_DCBX_SF_IEEE_UDP_PORT, 10159bcb797SSudarsana Reddy Kalluru QED_DCBX_SF_IEEE_TCP_UDP_PORT 10259bcb797SSudarsana Reddy Kalluru }; 10359bcb797SSudarsana Reddy Kalluru 1046ad8c632SSudarsana Reddy Kalluru struct qed_app_entry { 1056ad8c632SSudarsana Reddy Kalluru bool ethtype; 10659bcb797SSudarsana Reddy Kalluru enum qed_dcbx_sf_ieee_type sf_ieee; 1076ad8c632SSudarsana Reddy Kalluru bool enabled; 1086ad8c632SSudarsana Reddy Kalluru u8 prio; 1096ad8c632SSudarsana Reddy Kalluru u16 proto_id; 1106ad8c632SSudarsana Reddy Kalluru enum dcbx_protocol_type proto_type; 1116ad8c632SSudarsana Reddy Kalluru }; 1126ad8c632SSudarsana Reddy Kalluru 1136ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params { 1146ad8c632SSudarsana Reddy Kalluru struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL]; 1156ad8c632SSudarsana Reddy Kalluru u16 num_app_entries; 1166ad8c632SSudarsana Reddy Kalluru bool app_willing; 1176ad8c632SSudarsana Reddy Kalluru bool app_valid; 1186ad8c632SSudarsana Reddy Kalluru bool app_error; 1196ad8c632SSudarsana Reddy Kalluru bool ets_willing; 1206ad8c632SSudarsana Reddy Kalluru bool ets_enabled; 1216ad8c632SSudarsana Reddy Kalluru bool ets_cbs; 1226ad8c632SSudarsana Reddy Kalluru bool valid; 1236ad8c632SSudarsana Reddy Kalluru u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES]; 1246ad8c632SSudarsana Reddy Kalluru u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES]; 1256ad8c632SSudarsana Reddy Kalluru u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES]; 1266ad8c632SSudarsana Reddy Kalluru struct qed_dbcx_pfc_params pfc; 1276ad8c632SSudarsana Reddy Kalluru u8 max_ets_tc; 1286ad8c632SSudarsana Reddy Kalluru }; 1296ad8c632SSudarsana Reddy Kalluru 1306ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_admin_params { 1316ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params params; 1326ad8c632SSudarsana Reddy Kalluru bool valid; 1336ad8c632SSudarsana Reddy Kalluru }; 1346ad8c632SSudarsana Reddy Kalluru 1356ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_remote_params { 1366ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params params; 1376ad8c632SSudarsana Reddy Kalluru bool valid; 1386ad8c632SSudarsana Reddy Kalluru }; 1396ad8c632SSudarsana Reddy Kalluru 1406ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_operational_params { 1416ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_app_prio app_prio; 1426ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params params; 1436ad8c632SSudarsana Reddy Kalluru bool valid; 1446ad8c632SSudarsana Reddy Kalluru bool enabled; 1456ad8c632SSudarsana Reddy Kalluru bool ieee; 1466ad8c632SSudarsana Reddy Kalluru bool cee; 14749632b58Ssudarsana.kalluru@cavium.com bool local; 1486ad8c632SSudarsana Reddy Kalluru u32 err; 1496ad8c632SSudarsana Reddy Kalluru }; 1506ad8c632SSudarsana Reddy Kalluru 1516ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_get { 1526ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_operational_params operational; 1536ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_remote lldp_remote; 1546ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_local lldp_local; 1556ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_remote_params remote; 1566ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_admin_params local; 1576ad8c632SSudarsana Reddy Kalluru }; 1586ad8c632SSudarsana Reddy Kalluru 15920675b37SMintz, Yuval enum qed_nvm_images { 16020675b37SMintz, Yuval QED_NVM_IMAGE_ISCSI_CFG, 16120675b37SMintz, Yuval QED_NVM_IMAGE_FCOE_CFG, 16220675b37SMintz, Yuval }; 16320675b37SMintz, Yuval 164*645874e5SSudarsana Reddy Kalluru struct qed_link_eee_params { 165*645874e5SSudarsana Reddy Kalluru u32 tx_lpi_timer; 166*645874e5SSudarsana Reddy Kalluru #define QED_EEE_1G_ADV BIT(0) 167*645874e5SSudarsana Reddy Kalluru #define QED_EEE_10G_ADV BIT(1) 168*645874e5SSudarsana Reddy Kalluru 169*645874e5SSudarsana Reddy Kalluru /* Capabilities are represented using QED_EEE_*_ADV values */ 170*645874e5SSudarsana Reddy Kalluru u8 adv_caps; 171*645874e5SSudarsana Reddy Kalluru u8 lp_adv_caps; 172*645874e5SSudarsana Reddy Kalluru bool enable; 173*645874e5SSudarsana Reddy Kalluru bool tx_lpi_enable; 174*645874e5SSudarsana Reddy Kalluru }; 175*645874e5SSudarsana Reddy Kalluru 17691420b83SSudarsana Kalluru enum qed_led_mode { 17791420b83SSudarsana Kalluru QED_LED_MODE_OFF, 17891420b83SSudarsana Kalluru QED_LED_MODE_ON, 17991420b83SSudarsana Kalluru QED_LED_MODE_RESTORE 18091420b83SSudarsana Kalluru }; 18191420b83SSudarsana Kalluru 182fe56b9e6SYuval Mintz #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \ 183fe56b9e6SYuval Mintz (void __iomem *)(reg_addr)) 184fe56b9e6SYuval Mintz 185fe56b9e6SYuval Mintz #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr)) 186fe56b9e6SYuval Mintz 187fe56b9e6SYuval Mintz #define QED_COALESCE_MAX 0xFF 1880e191827SSudarsana Reddy Kalluru #define QED_DEFAULT_RX_USECS 12 189fe56b9e6SYuval Mintz 190fe56b9e6SYuval Mintz /* forward */ 191fe56b9e6SYuval Mintz struct qed_dev; 192fe56b9e6SYuval Mintz 193fe56b9e6SYuval Mintz struct qed_eth_pf_params { 194fe56b9e6SYuval Mintz /* The following parameters are used during HW-init 195fe56b9e6SYuval Mintz * and these parameters need to be passed as arguments 196fe56b9e6SYuval Mintz * to update_pf_params routine invoked before slowpath start 197fe56b9e6SYuval Mintz */ 198fe56b9e6SYuval Mintz u16 num_cons; 199d51e4af5SChopra, Manish 20008bc8f15SMintz, Yuval /* per-VF number of CIDs */ 20108bc8f15SMintz, Yuval u8 num_vf_cons; 20208bc8f15SMintz, Yuval #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32) 20308bc8f15SMintz, Yuval 204d51e4af5SChopra, Manish /* To enable arfs, previous to HW-init a positive number needs to be 205d51e4af5SChopra, Manish * set [as filters require allocated searcher ILT memory]. 206d51e4af5SChopra, Manish * This will set the maximal number of configured steering-filters. 207d51e4af5SChopra, Manish */ 208d51e4af5SChopra, Manish u32 num_arfs_filters; 209fe56b9e6SYuval Mintz }; 210fe56b9e6SYuval Mintz 2111e128c81SArun Easi struct qed_fcoe_pf_params { 2121e128c81SArun Easi /* The following parameters are used during protocol-init */ 2131e128c81SArun Easi u64 glbl_q_params_addr; 2141e128c81SArun Easi u64 bdq_pbl_base_addr[2]; 2151e128c81SArun Easi 2161e128c81SArun Easi /* The following parameters are used during HW-init 2171e128c81SArun Easi * and these parameters need to be passed as arguments 2181e128c81SArun Easi * to update_pf_params routine invoked before slowpath start 2191e128c81SArun Easi */ 2201e128c81SArun Easi u16 num_cons; 2211e128c81SArun Easi u16 num_tasks; 2221e128c81SArun Easi 2231e128c81SArun Easi /* The following parameters are used during protocol-init */ 2241e128c81SArun Easi u16 sq_num_pbl_pages; 2251e128c81SArun Easi 2261e128c81SArun Easi u16 cq_num_entries; 2271e128c81SArun Easi u16 cmdq_num_entries; 2281e128c81SArun Easi u16 rq_buffer_log_size; 2291e128c81SArun Easi u16 mtu; 2301e128c81SArun Easi u16 dummy_icid; 2311e128c81SArun Easi u16 bdq_xoff_threshold[2]; 2321e128c81SArun Easi u16 bdq_xon_threshold[2]; 2331e128c81SArun Easi u16 rq_buffer_size; 2341e128c81SArun Easi u8 num_cqs; /* num of global CQs */ 2351e128c81SArun Easi u8 log_page_size; 2361e128c81SArun Easi u8 gl_rq_pi; 2371e128c81SArun Easi u8 gl_cmd_pi; 2381e128c81SArun Easi u8 debug_mode; 2391e128c81SArun Easi u8 is_target; 2401e128c81SArun Easi u8 bdq_pbl_num_entries[2]; 2411e128c81SArun Easi }; 2421e128c81SArun Easi 243c5ac9319SYuval Mintz /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */ 244c5ac9319SYuval Mintz struct qed_iscsi_pf_params { 245c5ac9319SYuval Mintz u64 glbl_q_params_addr; 246c5ac9319SYuval Mintz u64 bdq_pbl_base_addr[2]; 247c5ac9319SYuval Mintz u32 max_cwnd; 248c5ac9319SYuval Mintz u16 cq_num_entries; 249c5ac9319SYuval Mintz u16 cmdq_num_entries; 250fc831825SYuval Mintz u32 two_msl_timer; 251c5ac9319SYuval Mintz u16 dup_ack_threshold; 252c5ac9319SYuval Mintz u16 tx_sws_timer; 253c5ac9319SYuval Mintz u16 min_rto; 254c5ac9319SYuval Mintz u16 min_rto_rt; 255c5ac9319SYuval Mintz u16 max_rto; 256c5ac9319SYuval Mintz 257c5ac9319SYuval Mintz /* The following parameters are used during HW-init 258c5ac9319SYuval Mintz * and these parameters need to be passed as arguments 259c5ac9319SYuval Mintz * to update_pf_params routine invoked before slowpath start 260c5ac9319SYuval Mintz */ 261c5ac9319SYuval Mintz u16 num_cons; 262c5ac9319SYuval Mintz u16 num_tasks; 263c5ac9319SYuval Mintz 264c5ac9319SYuval Mintz /* The following parameters are used during protocol-init */ 265c5ac9319SYuval Mintz u16 half_way_close_timeout; 266c5ac9319SYuval Mintz u16 bdq_xoff_threshold[2]; 267c5ac9319SYuval Mintz u16 bdq_xon_threshold[2]; 268c5ac9319SYuval Mintz u16 cmdq_xoff_threshold; 269c5ac9319SYuval Mintz u16 cmdq_xon_threshold; 270c5ac9319SYuval Mintz u16 rq_buffer_size; 271c5ac9319SYuval Mintz 272c5ac9319SYuval Mintz u8 num_sq_pages_in_ring; 273c5ac9319SYuval Mintz u8 num_r2tq_pages_in_ring; 274c5ac9319SYuval Mintz u8 num_uhq_pages_in_ring; 275c5ac9319SYuval Mintz u8 num_queues; 276c5ac9319SYuval Mintz u8 log_page_size; 277c5ac9319SYuval Mintz u8 rqe_log_size; 278c5ac9319SYuval Mintz u8 max_fin_rt; 279c5ac9319SYuval Mintz u8 gl_rq_pi; 280c5ac9319SYuval Mintz u8 gl_cmd_pi; 281c5ac9319SYuval Mintz u8 debug_mode; 282c5ac9319SYuval Mintz u8 ll2_ooo_queue_id; 283c5ac9319SYuval Mintz u8 ooo_enable; 284c5ac9319SYuval Mintz 285c5ac9319SYuval Mintz u8 is_target; 286c5ac9319SYuval Mintz u8 bdq_pbl_num_entries[2]; 287c5ac9319SYuval Mintz }; 288c5ac9319SYuval Mintz 289c5ac9319SYuval Mintz struct qed_rdma_pf_params { 290c5ac9319SYuval Mintz /* Supplied to QED during resource allocation (may affect the ILT and 291c5ac9319SYuval Mintz * the doorbell BAR). 292c5ac9319SYuval Mintz */ 293c5ac9319SYuval Mintz u32 min_dpis; /* number of requested DPIs */ 294c5ac9319SYuval Mintz u32 num_qps; /* number of requested Queue Pairs */ 295c5ac9319SYuval Mintz u32 num_srqs; /* number of requested SRQ */ 296c5ac9319SYuval Mintz u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */ 297c5ac9319SYuval Mintz u8 gl_pi; /* protocol index */ 298c5ac9319SYuval Mintz 299c5ac9319SYuval Mintz /* Will allocate rate limiters to be used with QPs */ 300c5ac9319SYuval Mintz u8 enable_dcqcn; 301c5ac9319SYuval Mintz }; 302c5ac9319SYuval Mintz 303fe56b9e6SYuval Mintz struct qed_pf_params { 304fe56b9e6SYuval Mintz struct qed_eth_pf_params eth_pf_params; 3051e128c81SArun Easi struct qed_fcoe_pf_params fcoe_pf_params; 306c5ac9319SYuval Mintz struct qed_iscsi_pf_params iscsi_pf_params; 307c5ac9319SYuval Mintz struct qed_rdma_pf_params rdma_pf_params; 308fe56b9e6SYuval Mintz }; 309fe56b9e6SYuval Mintz 310fe56b9e6SYuval Mintz enum qed_int_mode { 311fe56b9e6SYuval Mintz QED_INT_MODE_INTA, 312fe56b9e6SYuval Mintz QED_INT_MODE_MSIX, 313fe56b9e6SYuval Mintz QED_INT_MODE_MSI, 314fe56b9e6SYuval Mintz QED_INT_MODE_POLL, 315fe56b9e6SYuval Mintz }; 316fe56b9e6SYuval Mintz 317fe56b9e6SYuval Mintz struct qed_sb_info { 318fe56b9e6SYuval Mintz struct status_block *sb_virt; 319fe56b9e6SYuval Mintz dma_addr_t sb_phys; 320fe56b9e6SYuval Mintz u32 sb_ack; /* Last given ack */ 321fe56b9e6SYuval Mintz u16 igu_sb_id; 322fe56b9e6SYuval Mintz void __iomem *igu_addr; 323fe56b9e6SYuval Mintz u8 flags; 324fe56b9e6SYuval Mintz #define QED_SB_INFO_INIT 0x1 325fe56b9e6SYuval Mintz #define QED_SB_INFO_SETUP 0x2 326fe56b9e6SYuval Mintz 327fe56b9e6SYuval Mintz struct qed_dev *cdev; 328fe56b9e6SYuval Mintz }; 329fe56b9e6SYuval Mintz 3309c79ddaaSMintz, Yuval enum qed_dev_type { 3319c79ddaaSMintz, Yuval QED_DEV_TYPE_BB, 3329c79ddaaSMintz, Yuval QED_DEV_TYPE_AH, 3339c79ddaaSMintz, Yuval }; 3349c79ddaaSMintz, Yuval 335fe56b9e6SYuval Mintz struct qed_dev_info { 336fe56b9e6SYuval Mintz unsigned long pci_mem_start; 337fe56b9e6SYuval Mintz unsigned long pci_mem_end; 338fe56b9e6SYuval Mintz unsigned int pci_irq; 339fe56b9e6SYuval Mintz u8 num_hwfns; 340fe56b9e6SYuval Mintz 341fe56b9e6SYuval Mintz u8 hw_mac[ETH_ALEN]; 342fc48b7a6SYuval Mintz bool is_mf_default; 343fe56b9e6SYuval Mintz 344fe56b9e6SYuval Mintz /* FW version */ 345fe56b9e6SYuval Mintz u16 fw_major; 346fe56b9e6SYuval Mintz u16 fw_minor; 347fe56b9e6SYuval Mintz u16 fw_rev; 348fe56b9e6SYuval Mintz u16 fw_eng; 349fe56b9e6SYuval Mintz 350fe56b9e6SYuval Mintz /* MFW version */ 351fe56b9e6SYuval Mintz u32 mfw_rev; 352ae33666aSTomer Tayar #define QED_MFW_VERSION_0_MASK 0x000000FF 353ae33666aSTomer Tayar #define QED_MFW_VERSION_0_OFFSET 0 354ae33666aSTomer Tayar #define QED_MFW_VERSION_1_MASK 0x0000FF00 355ae33666aSTomer Tayar #define QED_MFW_VERSION_1_OFFSET 8 356ae33666aSTomer Tayar #define QED_MFW_VERSION_2_MASK 0x00FF0000 357ae33666aSTomer Tayar #define QED_MFW_VERSION_2_OFFSET 16 358ae33666aSTomer Tayar #define QED_MFW_VERSION_3_MASK 0xFF000000 359ae33666aSTomer Tayar #define QED_MFW_VERSION_3_OFFSET 24 360fe56b9e6SYuval Mintz 361fe56b9e6SYuval Mintz u32 flash_size; 362fe56b9e6SYuval Mintz u8 mf_mode; 363831bfb0eSYuval Mintz bool tx_switching; 364cee9fbd8SRam Amrani bool rdma_supported; 3650fefbfbaSSudarsana Kalluru u16 mtu; 36614d39648SMintz, Yuval 36714d39648SMintz, Yuval bool wol_support; 3689c79ddaaSMintz, Yuval 369ae33666aSTomer Tayar /* MBI version */ 370ae33666aSTomer Tayar u32 mbi_version; 371ae33666aSTomer Tayar #define QED_MBI_VERSION_0_MASK 0x000000FF 372ae33666aSTomer Tayar #define QED_MBI_VERSION_0_OFFSET 0 373ae33666aSTomer Tayar #define QED_MBI_VERSION_1_MASK 0x0000FF00 374ae33666aSTomer Tayar #define QED_MBI_VERSION_1_OFFSET 8 375ae33666aSTomer Tayar #define QED_MBI_VERSION_2_MASK 0x00FF0000 376ae33666aSTomer Tayar #define QED_MBI_VERSION_2_OFFSET 16 377ae33666aSTomer Tayar 3789c79ddaaSMintz, Yuval enum qed_dev_type dev_type; 37919489c7fSChopra, Manish 38019489c7fSChopra, Manish /* Output parameters for qede */ 38119489c7fSChopra, Manish bool vxlan_enable; 38219489c7fSChopra, Manish bool gre_enable; 38319489c7fSChopra, Manish bool geneve_enable; 3843c5da942SMintz, Yuval 3853c5da942SMintz, Yuval u8 abs_pf_id; 386fe56b9e6SYuval Mintz }; 387fe56b9e6SYuval Mintz 388fe56b9e6SYuval Mintz enum qed_sb_type { 389fe56b9e6SYuval Mintz QED_SB_TYPE_L2_QUEUE, 39051ff1725SRam Amrani QED_SB_TYPE_CNQ, 391fc831825SYuval Mintz QED_SB_TYPE_STORAGE, 392fe56b9e6SYuval Mintz }; 393fe56b9e6SYuval Mintz 394fe56b9e6SYuval Mintz enum qed_protocol { 395fe56b9e6SYuval Mintz QED_PROTOCOL_ETH, 396c5ac9319SYuval Mintz QED_PROTOCOL_ISCSI, 3971e128c81SArun Easi QED_PROTOCOL_FCOE, 398fe56b9e6SYuval Mintz }; 399fe56b9e6SYuval Mintz 400054c67d1SSudarsana Reddy Kalluru enum qed_link_mode_bits { 401054c67d1SSudarsana Reddy Kalluru QED_LM_FIBRE_BIT = BIT(0), 402054c67d1SSudarsana Reddy Kalluru QED_LM_Autoneg_BIT = BIT(1), 403054c67d1SSudarsana Reddy Kalluru QED_LM_Asym_Pause_BIT = BIT(2), 404054c67d1SSudarsana Reddy Kalluru QED_LM_Pause_BIT = BIT(3), 405054c67d1SSudarsana Reddy Kalluru QED_LM_1000baseT_Half_BIT = BIT(4), 406054c67d1SSudarsana Reddy Kalluru QED_LM_1000baseT_Full_BIT = BIT(5), 407054c67d1SSudarsana Reddy Kalluru QED_LM_10000baseKR_Full_BIT = BIT(6), 408054c67d1SSudarsana Reddy Kalluru QED_LM_25000baseKR_Full_BIT = BIT(7), 409054c67d1SSudarsana Reddy Kalluru QED_LM_40000baseLR4_Full_BIT = BIT(8), 410054c67d1SSudarsana Reddy Kalluru QED_LM_50000baseKR2_Full_BIT = BIT(9), 411054c67d1SSudarsana Reddy Kalluru QED_LM_100000baseKR4_Full_BIT = BIT(10), 412054c67d1SSudarsana Reddy Kalluru QED_LM_COUNT = 11 413054c67d1SSudarsana Reddy Kalluru }; 414054c67d1SSudarsana Reddy Kalluru 415fe56b9e6SYuval Mintz struct qed_link_params { 416fe56b9e6SYuval Mintz bool link_up; 417fe56b9e6SYuval Mintz 418fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0) 419fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1) 420fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2) 421fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3) 42203dc76caSSudarsana Reddy Kalluru #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4) 423*645874e5SSudarsana Reddy Kalluru #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5) 424fe56b9e6SYuval Mintz u32 override_flags; 425fe56b9e6SYuval Mintz bool autoneg; 426fe56b9e6SYuval Mintz u32 adv_speeds; 427fe56b9e6SYuval Mintz u32 forced_speed; 428fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0) 429fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_RX_ENABLE BIT(1) 430fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_TX_ENABLE BIT(2) 431fe56b9e6SYuval Mintz u32 pause_config; 43203dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_NONE BIT(0) 43303dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_INT_PHY BIT(1) 43403dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_EXT_PHY BIT(2) 43503dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_EXT BIT(3) 43603dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_MAC BIT(4) 43703dc76caSSudarsana Reddy Kalluru u32 loopback_mode; 438*645874e5SSudarsana Reddy Kalluru struct qed_link_eee_params eee; 439fe56b9e6SYuval Mintz }; 440fe56b9e6SYuval Mintz 441fe56b9e6SYuval Mintz struct qed_link_output { 442fe56b9e6SYuval Mintz bool link_up; 443fe56b9e6SYuval Mintz 444d194fd26SYuval Mintz /* In QED_LM_* defs */ 445d194fd26SYuval Mintz u32 supported_caps; 446d194fd26SYuval Mintz u32 advertised_caps; 447d194fd26SYuval Mintz u32 lp_caps; 448d194fd26SYuval Mintz 449fe56b9e6SYuval Mintz u32 speed; /* In Mb/s */ 450fe56b9e6SYuval Mintz u8 duplex; /* In DUPLEX defs */ 451fe56b9e6SYuval Mintz u8 port; /* In PORT defs */ 452fe56b9e6SYuval Mintz bool autoneg; 453fe56b9e6SYuval Mintz u32 pause_config; 454*645874e5SSudarsana Reddy Kalluru 455*645874e5SSudarsana Reddy Kalluru /* EEE - capability & param */ 456*645874e5SSudarsana Reddy Kalluru bool eee_supported; 457*645874e5SSudarsana Reddy Kalluru bool eee_active; 458*645874e5SSudarsana Reddy Kalluru u8 sup_caps; 459*645874e5SSudarsana Reddy Kalluru struct qed_link_eee_params eee; 460fe56b9e6SYuval Mintz }; 461fe56b9e6SYuval Mintz 4621408cc1fSYuval Mintz struct qed_probe_params { 4631408cc1fSYuval Mintz enum qed_protocol protocol; 4641408cc1fSYuval Mintz u32 dp_module; 4651408cc1fSYuval Mintz u8 dp_level; 4661408cc1fSYuval Mintz bool is_vf; 4671408cc1fSYuval Mintz }; 4681408cc1fSYuval Mintz 469fe56b9e6SYuval Mintz #define QED_DRV_VER_STR_SIZE 12 470fe56b9e6SYuval Mintz struct qed_slowpath_params { 471fe56b9e6SYuval Mintz u32 int_mode; 472fe56b9e6SYuval Mintz u8 drv_major; 473fe56b9e6SYuval Mintz u8 drv_minor; 474fe56b9e6SYuval Mintz u8 drv_rev; 475fe56b9e6SYuval Mintz u8 drv_eng; 476fe56b9e6SYuval Mintz u8 name[QED_DRV_VER_STR_SIZE]; 477fe56b9e6SYuval Mintz }; 478fe56b9e6SYuval Mintz 479fe56b9e6SYuval Mintz #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */ 480fe56b9e6SYuval Mintz 481fe56b9e6SYuval Mintz struct qed_int_info { 482fe56b9e6SYuval Mintz struct msix_entry *msix; 483fe56b9e6SYuval Mintz u8 msix_cnt; 484fe56b9e6SYuval Mintz 485fe56b9e6SYuval Mintz /* This should be updated by the protocol driver */ 486fe56b9e6SYuval Mintz u8 used_cnt; 487fe56b9e6SYuval Mintz }; 488fe56b9e6SYuval Mintz 489fe56b9e6SYuval Mintz struct qed_common_cb_ops { 490d51e4af5SChopra, Manish void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc); 491fe56b9e6SYuval Mintz void (*link_update)(void *dev, 492fe56b9e6SYuval Mintz struct qed_link_output *link); 4931e128c81SArun Easi void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type); 494fe56b9e6SYuval Mintz }; 495fe56b9e6SYuval Mintz 49603dc76caSSudarsana Reddy Kalluru struct qed_selftest_ops { 49703dc76caSSudarsana Reddy Kalluru /** 49803dc76caSSudarsana Reddy Kalluru * @brief selftest_interrupt - Perform interrupt test 49903dc76caSSudarsana Reddy Kalluru * 50003dc76caSSudarsana Reddy Kalluru * @param cdev 50103dc76caSSudarsana Reddy Kalluru * 50203dc76caSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 50303dc76caSSudarsana Reddy Kalluru */ 50403dc76caSSudarsana Reddy Kalluru int (*selftest_interrupt)(struct qed_dev *cdev); 50503dc76caSSudarsana Reddy Kalluru 50603dc76caSSudarsana Reddy Kalluru /** 50703dc76caSSudarsana Reddy Kalluru * @brief selftest_memory - Perform memory test 50803dc76caSSudarsana Reddy Kalluru * 50903dc76caSSudarsana Reddy Kalluru * @param cdev 51003dc76caSSudarsana Reddy Kalluru * 51103dc76caSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 51203dc76caSSudarsana Reddy Kalluru */ 51303dc76caSSudarsana Reddy Kalluru int (*selftest_memory)(struct qed_dev *cdev); 51403dc76caSSudarsana Reddy Kalluru 51503dc76caSSudarsana Reddy Kalluru /** 51603dc76caSSudarsana Reddy Kalluru * @brief selftest_register - Perform register test 51703dc76caSSudarsana Reddy Kalluru * 51803dc76caSSudarsana Reddy Kalluru * @param cdev 51903dc76caSSudarsana Reddy Kalluru * 52003dc76caSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 52103dc76caSSudarsana Reddy Kalluru */ 52203dc76caSSudarsana Reddy Kalluru int (*selftest_register)(struct qed_dev *cdev); 52303dc76caSSudarsana Reddy Kalluru 52403dc76caSSudarsana Reddy Kalluru /** 52503dc76caSSudarsana Reddy Kalluru * @brief selftest_clock - Perform clock test 52603dc76caSSudarsana Reddy Kalluru * 52703dc76caSSudarsana Reddy Kalluru * @param cdev 52803dc76caSSudarsana Reddy Kalluru * 52903dc76caSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 53003dc76caSSudarsana Reddy Kalluru */ 53103dc76caSSudarsana Reddy Kalluru int (*selftest_clock)(struct qed_dev *cdev); 5327a4b21b7SMintz, Yuval 5337a4b21b7SMintz, Yuval /** 5347a4b21b7SMintz, Yuval * @brief selftest_nvram - Perform nvram test 5357a4b21b7SMintz, Yuval * 5367a4b21b7SMintz, Yuval * @param cdev 5377a4b21b7SMintz, Yuval * 5387a4b21b7SMintz, Yuval * @return 0 on success, error otherwise. 5397a4b21b7SMintz, Yuval */ 5407a4b21b7SMintz, Yuval int (*selftest_nvram) (struct qed_dev *cdev); 54103dc76caSSudarsana Reddy Kalluru }; 54203dc76caSSudarsana Reddy Kalluru 543fe56b9e6SYuval Mintz struct qed_common_ops { 54403dc76caSSudarsana Reddy Kalluru struct qed_selftest_ops *selftest; 54503dc76caSSudarsana Reddy Kalluru 546fe56b9e6SYuval Mintz struct qed_dev* (*probe)(struct pci_dev *dev, 5471408cc1fSYuval Mintz struct qed_probe_params *params); 548fe56b9e6SYuval Mintz 549fe56b9e6SYuval Mintz void (*remove)(struct qed_dev *cdev); 550fe56b9e6SYuval Mintz 551fe56b9e6SYuval Mintz int (*set_power_state)(struct qed_dev *cdev, 552fe56b9e6SYuval Mintz pci_power_t state); 553fe56b9e6SYuval Mintz 554712c3cbfSMintz, Yuval void (*set_name) (struct qed_dev *cdev, char name[]); 555fe56b9e6SYuval Mintz 556fe56b9e6SYuval Mintz /* Client drivers need to make this call before slowpath_start. 557fe56b9e6SYuval Mintz * PF params required for the call before slowpath_start is 558fe56b9e6SYuval Mintz * documented within the qed_pf_params structure definition. 559fe56b9e6SYuval Mintz */ 560fe56b9e6SYuval Mintz void (*update_pf_params)(struct qed_dev *cdev, 561fe56b9e6SYuval Mintz struct qed_pf_params *params); 562fe56b9e6SYuval Mintz int (*slowpath_start)(struct qed_dev *cdev, 563fe56b9e6SYuval Mintz struct qed_slowpath_params *params); 564fe56b9e6SYuval Mintz 565fe56b9e6SYuval Mintz int (*slowpath_stop)(struct qed_dev *cdev); 566fe56b9e6SYuval Mintz 567fe56b9e6SYuval Mintz /* Requests to use `cnt' interrupts for fastpath. 568fe56b9e6SYuval Mintz * upon success, returns number of interrupts allocated for fastpath. 569fe56b9e6SYuval Mintz */ 570fe56b9e6SYuval Mintz int (*set_fp_int)(struct qed_dev *cdev, 571fe56b9e6SYuval Mintz u16 cnt); 572fe56b9e6SYuval Mintz 573fe56b9e6SYuval Mintz /* Fills `info' with pointers required for utilizing interrupts */ 574fe56b9e6SYuval Mintz int (*get_fp_int)(struct qed_dev *cdev, 575fe56b9e6SYuval Mintz struct qed_int_info *info); 576fe56b9e6SYuval Mintz 577fe56b9e6SYuval Mintz u32 (*sb_init)(struct qed_dev *cdev, 578fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 579fe56b9e6SYuval Mintz void *sb_virt_addr, 580fe56b9e6SYuval Mintz dma_addr_t sb_phy_addr, 581fe56b9e6SYuval Mintz u16 sb_id, 582fe56b9e6SYuval Mintz enum qed_sb_type type); 583fe56b9e6SYuval Mintz 584fe56b9e6SYuval Mintz u32 (*sb_release)(struct qed_dev *cdev, 585fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 586fe56b9e6SYuval Mintz u16 sb_id); 587fe56b9e6SYuval Mintz 588fe56b9e6SYuval Mintz void (*simd_handler_config)(struct qed_dev *cdev, 589fe56b9e6SYuval Mintz void *token, 590fe56b9e6SYuval Mintz int index, 591fe56b9e6SYuval Mintz void (*handler)(void *)); 592fe56b9e6SYuval Mintz 593fe56b9e6SYuval Mintz void (*simd_handler_clean)(struct qed_dev *cdev, 594fe56b9e6SYuval Mintz int index); 5951e128c81SArun Easi int (*dbg_grc)(struct qed_dev *cdev, 5961e128c81SArun Easi void *buffer, u32 *num_dumped_bytes); 5971e128c81SArun Easi 5981e128c81SArun Easi int (*dbg_grc_size)(struct qed_dev *cdev); 599fe7cd2bfSYuval Mintz 600e0971c83STomer Tayar int (*dbg_all_data) (struct qed_dev *cdev, void *buffer); 601e0971c83STomer Tayar 602e0971c83STomer Tayar int (*dbg_all_data_size) (struct qed_dev *cdev); 603e0971c83STomer Tayar 604fe7cd2bfSYuval Mintz /** 605fe7cd2bfSYuval Mintz * @brief can_link_change - can the instance change the link or not 606fe7cd2bfSYuval Mintz * 607fe7cd2bfSYuval Mintz * @param cdev 608fe7cd2bfSYuval Mintz * 609fe7cd2bfSYuval Mintz * @return true if link-change is allowed, false otherwise. 610fe7cd2bfSYuval Mintz */ 611fe7cd2bfSYuval Mintz bool (*can_link_change)(struct qed_dev *cdev); 612fe7cd2bfSYuval Mintz 613fe56b9e6SYuval Mintz /** 614fe56b9e6SYuval Mintz * @brief set_link - set links according to params 615fe56b9e6SYuval Mintz * 616fe56b9e6SYuval Mintz * @param cdev 617fe56b9e6SYuval Mintz * @param params - values used to override the default link configuration 618fe56b9e6SYuval Mintz * 619fe56b9e6SYuval Mintz * @return 0 on success, error otherwise. 620fe56b9e6SYuval Mintz */ 621fe56b9e6SYuval Mintz int (*set_link)(struct qed_dev *cdev, 622fe56b9e6SYuval Mintz struct qed_link_params *params); 623fe56b9e6SYuval Mintz 624fe56b9e6SYuval Mintz /** 625fe56b9e6SYuval Mintz * @brief get_link - returns the current link state. 626fe56b9e6SYuval Mintz * 627fe56b9e6SYuval Mintz * @param cdev 628fe56b9e6SYuval Mintz * @param if_link - structure to be filled with current link configuration. 629fe56b9e6SYuval Mintz */ 630fe56b9e6SYuval Mintz void (*get_link)(struct qed_dev *cdev, 631fe56b9e6SYuval Mintz struct qed_link_output *if_link); 632fe56b9e6SYuval Mintz 633fe56b9e6SYuval Mintz /** 634fe56b9e6SYuval Mintz * @brief - drains chip in case Tx completions fail to arrive due to pause. 635fe56b9e6SYuval Mintz * 636fe56b9e6SYuval Mintz * @param cdev 637fe56b9e6SYuval Mintz */ 638fe56b9e6SYuval Mintz int (*drain)(struct qed_dev *cdev); 639fe56b9e6SYuval Mintz 640fe56b9e6SYuval Mintz /** 641fe56b9e6SYuval Mintz * @brief update_msglvl - update module debug level 642fe56b9e6SYuval Mintz * 643fe56b9e6SYuval Mintz * @param cdev 644fe56b9e6SYuval Mintz * @param dp_module 645fe56b9e6SYuval Mintz * @param dp_level 646fe56b9e6SYuval Mintz */ 647fe56b9e6SYuval Mintz void (*update_msglvl)(struct qed_dev *cdev, 648fe56b9e6SYuval Mintz u32 dp_module, 649fe56b9e6SYuval Mintz u8 dp_level); 650fe56b9e6SYuval Mintz 651fe56b9e6SYuval Mintz int (*chain_alloc)(struct qed_dev *cdev, 652fe56b9e6SYuval Mintz enum qed_chain_use_mode intended_use, 653fe56b9e6SYuval Mintz enum qed_chain_mode mode, 654a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 655a91eb52aSYuval Mintz u32 num_elems, 656fe56b9e6SYuval Mintz size_t elem_size, 6571a4a6975SMintz, Yuval struct qed_chain *p_chain, 6581a4a6975SMintz, Yuval struct qed_chain_ext_pbl *ext_pbl); 659fe56b9e6SYuval Mintz 660fe56b9e6SYuval Mintz void (*chain_free)(struct qed_dev *cdev, 661fe56b9e6SYuval Mintz struct qed_chain *p_chain); 66291420b83SSudarsana Kalluru 66391420b83SSudarsana Kalluru /** 66420675b37SMintz, Yuval * @brief nvm_get_image - reads an entire image from nvram 66520675b37SMintz, Yuval * 66620675b37SMintz, Yuval * @param cdev 66720675b37SMintz, Yuval * @param type - type of the request nvram image 66820675b37SMintz, Yuval * @param buf - preallocated buffer to fill with the image 66920675b37SMintz, Yuval * @param len - length of the allocated buffer 67020675b37SMintz, Yuval * 67120675b37SMintz, Yuval * @return 0 on success, error otherwise 67220675b37SMintz, Yuval */ 67320675b37SMintz, Yuval int (*nvm_get_image)(struct qed_dev *cdev, 67420675b37SMintz, Yuval enum qed_nvm_images type, u8 *buf, u16 len); 67520675b37SMintz, Yuval 67620675b37SMintz, Yuval /** 677722003acSSudarsana Reddy Kalluru * @brief get_coalesce - Get coalesce parameters in usec 678722003acSSudarsana Reddy Kalluru * 679722003acSSudarsana Reddy Kalluru * @param cdev 680722003acSSudarsana Reddy Kalluru * @param rx_coal - Rx coalesce value in usec 681722003acSSudarsana Reddy Kalluru * @param tx_coal - Tx coalesce value in usec 682722003acSSudarsana Reddy Kalluru * 683722003acSSudarsana Reddy Kalluru */ 684722003acSSudarsana Reddy Kalluru void (*get_coalesce)(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal); 685722003acSSudarsana Reddy Kalluru 686722003acSSudarsana Reddy Kalluru /** 687722003acSSudarsana Reddy Kalluru * @brief set_coalesce - Configure Rx coalesce value in usec 688722003acSSudarsana Reddy Kalluru * 689722003acSSudarsana Reddy Kalluru * @param cdev 690722003acSSudarsana Reddy Kalluru * @param rx_coal - Rx coalesce value in usec 691722003acSSudarsana Reddy Kalluru * @param tx_coal - Tx coalesce value in usec 692722003acSSudarsana Reddy Kalluru * @param qid - Queue index 693722003acSSudarsana Reddy Kalluru * @param sb_id - Status Block Id 694722003acSSudarsana Reddy Kalluru * 695722003acSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 696722003acSSudarsana Reddy Kalluru */ 697722003acSSudarsana Reddy Kalluru int (*set_coalesce)(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, 698f870a3c6Ssudarsana.kalluru@cavium.com u16 qid, u16 sb_id); 699722003acSSudarsana Reddy Kalluru 700722003acSSudarsana Reddy Kalluru /** 70191420b83SSudarsana Kalluru * @brief set_led - Configure LED mode 70291420b83SSudarsana Kalluru * 70391420b83SSudarsana Kalluru * @param cdev 70491420b83SSudarsana Kalluru * @param mode - LED mode 70591420b83SSudarsana Kalluru * 70691420b83SSudarsana Kalluru * @return 0 on success, error otherwise. 70791420b83SSudarsana Kalluru */ 70891420b83SSudarsana Kalluru int (*set_led)(struct qed_dev *cdev, 70991420b83SSudarsana Kalluru enum qed_led_mode mode); 7100fefbfbaSSudarsana Kalluru 7110fefbfbaSSudarsana Kalluru /** 7120fefbfbaSSudarsana Kalluru * @brief update_drv_state - API to inform the change in the driver state. 7130fefbfbaSSudarsana Kalluru * 7140fefbfbaSSudarsana Kalluru * @param cdev 7150fefbfbaSSudarsana Kalluru * @param active 7160fefbfbaSSudarsana Kalluru * 7170fefbfbaSSudarsana Kalluru */ 7180fefbfbaSSudarsana Kalluru int (*update_drv_state)(struct qed_dev *cdev, bool active); 7190fefbfbaSSudarsana Kalluru 7200fefbfbaSSudarsana Kalluru /** 7210fefbfbaSSudarsana Kalluru * @brief update_mac - API to inform the change in the mac address 7220fefbfbaSSudarsana Kalluru * 7230fefbfbaSSudarsana Kalluru * @param cdev 7240fefbfbaSSudarsana Kalluru * @param mac 7250fefbfbaSSudarsana Kalluru * 7260fefbfbaSSudarsana Kalluru */ 7270fefbfbaSSudarsana Kalluru int (*update_mac)(struct qed_dev *cdev, u8 *mac); 7280fefbfbaSSudarsana Kalluru 7290fefbfbaSSudarsana Kalluru /** 7300fefbfbaSSudarsana Kalluru * @brief update_mtu - API to inform the change in the mtu 7310fefbfbaSSudarsana Kalluru * 7320fefbfbaSSudarsana Kalluru * @param cdev 7330fefbfbaSSudarsana Kalluru * @param mtu 7340fefbfbaSSudarsana Kalluru * 7350fefbfbaSSudarsana Kalluru */ 7360fefbfbaSSudarsana Kalluru int (*update_mtu)(struct qed_dev *cdev, u16 mtu); 73714d39648SMintz, Yuval 73814d39648SMintz, Yuval /** 73914d39648SMintz, Yuval * @brief update_wol - update of changes in the WoL configuration 74014d39648SMintz, Yuval * 74114d39648SMintz, Yuval * @param cdev 74214d39648SMintz, Yuval * @param enabled - true iff WoL should be enabled. 74314d39648SMintz, Yuval */ 74414d39648SMintz, Yuval int (*update_wol) (struct qed_dev *cdev, bool enabled); 745fe56b9e6SYuval Mintz }; 746fe56b9e6SYuval Mintz 747fe56b9e6SYuval Mintz #define MASK_FIELD(_name, _value) \ 748fe56b9e6SYuval Mintz ((_value) &= (_name ## _MASK)) 749fe56b9e6SYuval Mintz 750fe56b9e6SYuval Mintz #define FIELD_VALUE(_name, _value) \ 751fe56b9e6SYuval Mintz ((_value & _name ## _MASK) << _name ## _SHIFT) 752fe56b9e6SYuval Mintz 753fe56b9e6SYuval Mintz #define SET_FIELD(value, name, flag) \ 754fe56b9e6SYuval Mintz do { \ 755fe56b9e6SYuval Mintz (value) &= ~(name ## _MASK << name ## _SHIFT); \ 756fe56b9e6SYuval Mintz (value) |= (((u64)flag) << (name ## _SHIFT)); \ 757fe56b9e6SYuval Mintz } while (0) 758fe56b9e6SYuval Mintz 759fe56b9e6SYuval Mintz #define GET_FIELD(value, name) \ 760fe56b9e6SYuval Mintz (((value) >> (name ## _SHIFT)) & name ## _MASK) 761fe56b9e6SYuval Mintz 762fe56b9e6SYuval Mintz /* Debug print definitions */ 763fe56b9e6SYuval Mintz #define DP_ERR(cdev, fmt, ...) \ 7649d7650c2SMintz, Yuval do { \ 765fe56b9e6SYuval Mintz pr_err("[%s:%d(%s)]" fmt, \ 766fe56b9e6SYuval Mintz __func__, __LINE__, \ 767fe56b9e6SYuval Mintz DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 7689d7650c2SMintz, Yuval ## __VA_ARGS__); \ 7699d7650c2SMintz, Yuval } while (0) 770fe56b9e6SYuval Mintz 771fe56b9e6SYuval Mintz #define DP_NOTICE(cdev, fmt, ...) \ 772fe56b9e6SYuval Mintz do { \ 773fe56b9e6SYuval Mintz if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \ 774fe56b9e6SYuval Mintz pr_notice("[%s:%d(%s)]" fmt, \ 775fe56b9e6SYuval Mintz __func__, __LINE__, \ 776fe56b9e6SYuval Mintz DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 777fe56b9e6SYuval Mintz ## __VA_ARGS__); \ 778fe56b9e6SYuval Mintz \ 779fe56b9e6SYuval Mintz } \ 780fe56b9e6SYuval Mintz } while (0) 781fe56b9e6SYuval Mintz 782fe56b9e6SYuval Mintz #define DP_INFO(cdev, fmt, ...) \ 783fe56b9e6SYuval Mintz do { \ 784fe56b9e6SYuval Mintz if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \ 785fe56b9e6SYuval Mintz pr_notice("[%s:%d(%s)]" fmt, \ 786fe56b9e6SYuval Mintz __func__, __LINE__, \ 787fe56b9e6SYuval Mintz DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 788fe56b9e6SYuval Mintz ## __VA_ARGS__); \ 789fe56b9e6SYuval Mintz } \ 790fe56b9e6SYuval Mintz } while (0) 791fe56b9e6SYuval Mintz 792fe56b9e6SYuval Mintz #define DP_VERBOSE(cdev, module, fmt, ...) \ 793fe56b9e6SYuval Mintz do { \ 794fe56b9e6SYuval Mintz if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \ 795fe56b9e6SYuval Mintz ((cdev)->dp_module & module))) { \ 796fe56b9e6SYuval Mintz pr_notice("[%s:%d(%s)]" fmt, \ 797fe56b9e6SYuval Mintz __func__, __LINE__, \ 798fe56b9e6SYuval Mintz DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 799fe56b9e6SYuval Mintz ## __VA_ARGS__); \ 800fe56b9e6SYuval Mintz } \ 801fe56b9e6SYuval Mintz } while (0) 802fe56b9e6SYuval Mintz 803fe56b9e6SYuval Mintz enum DP_LEVEL { 804fe56b9e6SYuval Mintz QED_LEVEL_VERBOSE = 0x0, 805fe56b9e6SYuval Mintz QED_LEVEL_INFO = 0x1, 806fe56b9e6SYuval Mintz QED_LEVEL_NOTICE = 0x2, 807fe56b9e6SYuval Mintz QED_LEVEL_ERR = 0x3, 808fe56b9e6SYuval Mintz }; 809fe56b9e6SYuval Mintz 810fe56b9e6SYuval Mintz #define QED_LOG_LEVEL_SHIFT (30) 811fe56b9e6SYuval Mintz #define QED_LOG_VERBOSE_MASK (0x3fffffff) 812fe56b9e6SYuval Mintz #define QED_LOG_INFO_MASK (0x40000000) 813fe56b9e6SYuval Mintz #define QED_LOG_NOTICE_MASK (0x80000000) 814fe56b9e6SYuval Mintz 815fe56b9e6SYuval Mintz enum DP_MODULE { 816fe56b9e6SYuval Mintz QED_MSG_SPQ = 0x10000, 817fe56b9e6SYuval Mintz QED_MSG_STATS = 0x20000, 818fe56b9e6SYuval Mintz QED_MSG_DCB = 0x40000, 819fe56b9e6SYuval Mintz QED_MSG_IOV = 0x80000, 820fe56b9e6SYuval Mintz QED_MSG_SP = 0x100000, 821fe56b9e6SYuval Mintz QED_MSG_STORAGE = 0x200000, 822fe56b9e6SYuval Mintz QED_MSG_CXT = 0x800000, 8230a7fb11cSYuval Mintz QED_MSG_LL2 = 0x1000000, 824fe56b9e6SYuval Mintz QED_MSG_ILT = 0x2000000, 82551ff1725SRam Amrani QED_MSG_RDMA = 0x4000000, 826fe56b9e6SYuval Mintz QED_MSG_DEBUG = 0x8000000, 827fe56b9e6SYuval Mintz /* to be added...up to 0x8000000 */ 828fe56b9e6SYuval Mintz }; 829fe56b9e6SYuval Mintz 830fc48b7a6SYuval Mintz enum qed_mf_mode { 831fc48b7a6SYuval Mintz QED_MF_DEFAULT, 832fc48b7a6SYuval Mintz QED_MF_OVLAN, 833fc48b7a6SYuval Mintz QED_MF_NPAR, 834fc48b7a6SYuval Mintz }; 835fc48b7a6SYuval Mintz 8369c79ddaaSMintz, Yuval struct qed_eth_stats_common { 837fe56b9e6SYuval Mintz u64 no_buff_discards; 838fe56b9e6SYuval Mintz u64 packet_too_big_discard; 839fe56b9e6SYuval Mintz u64 ttl0_discard; 840fe56b9e6SYuval Mintz u64 rx_ucast_bytes; 841fe56b9e6SYuval Mintz u64 rx_mcast_bytes; 842fe56b9e6SYuval Mintz u64 rx_bcast_bytes; 843fe56b9e6SYuval Mintz u64 rx_ucast_pkts; 844fe56b9e6SYuval Mintz u64 rx_mcast_pkts; 845fe56b9e6SYuval Mintz u64 rx_bcast_pkts; 846fe56b9e6SYuval Mintz u64 mftag_filter_discards; 847fe56b9e6SYuval Mintz u64 mac_filter_discards; 848fe56b9e6SYuval Mintz u64 tx_ucast_bytes; 849fe56b9e6SYuval Mintz u64 tx_mcast_bytes; 850fe56b9e6SYuval Mintz u64 tx_bcast_bytes; 851fe56b9e6SYuval Mintz u64 tx_ucast_pkts; 852fe56b9e6SYuval Mintz u64 tx_mcast_pkts; 853fe56b9e6SYuval Mintz u64 tx_bcast_pkts; 854fe56b9e6SYuval Mintz u64 tx_err_drop_pkts; 855fe56b9e6SYuval Mintz u64 tpa_coalesced_pkts; 856fe56b9e6SYuval Mintz u64 tpa_coalesced_events; 857fe56b9e6SYuval Mintz u64 tpa_aborts_num; 858fe56b9e6SYuval Mintz u64 tpa_not_coalesced_pkts; 859fe56b9e6SYuval Mintz u64 tpa_coalesced_bytes; 860fe56b9e6SYuval Mintz 861fe56b9e6SYuval Mintz /* port */ 862fe56b9e6SYuval Mintz u64 rx_64_byte_packets; 863d4967cf3SYuval Mintz u64 rx_65_to_127_byte_packets; 864d4967cf3SYuval Mintz u64 rx_128_to_255_byte_packets; 865d4967cf3SYuval Mintz u64 rx_256_to_511_byte_packets; 866d4967cf3SYuval Mintz u64 rx_512_to_1023_byte_packets; 867d4967cf3SYuval Mintz u64 rx_1024_to_1518_byte_packets; 868fe56b9e6SYuval Mintz u64 rx_crc_errors; 869fe56b9e6SYuval Mintz u64 rx_mac_crtl_frames; 870fe56b9e6SYuval Mintz u64 rx_pause_frames; 871fe56b9e6SYuval Mintz u64 rx_pfc_frames; 872fe56b9e6SYuval Mintz u64 rx_align_errors; 873fe56b9e6SYuval Mintz u64 rx_carrier_errors; 874fe56b9e6SYuval Mintz u64 rx_oversize_packets; 875fe56b9e6SYuval Mintz u64 rx_jabbers; 876fe56b9e6SYuval Mintz u64 rx_undersize_packets; 877fe56b9e6SYuval Mintz u64 rx_fragments; 878fe56b9e6SYuval Mintz u64 tx_64_byte_packets; 879fe56b9e6SYuval Mintz u64 tx_65_to_127_byte_packets; 880fe56b9e6SYuval Mintz u64 tx_128_to_255_byte_packets; 881fe56b9e6SYuval Mintz u64 tx_256_to_511_byte_packets; 882fe56b9e6SYuval Mintz u64 tx_512_to_1023_byte_packets; 883fe56b9e6SYuval Mintz u64 tx_1024_to_1518_byte_packets; 884fe56b9e6SYuval Mintz u64 tx_pause_frames; 885fe56b9e6SYuval Mintz u64 tx_pfc_frames; 886fe56b9e6SYuval Mintz u64 brb_truncates; 887fe56b9e6SYuval Mintz u64 brb_discards; 888fe56b9e6SYuval Mintz u64 rx_mac_bytes; 889fe56b9e6SYuval Mintz u64 rx_mac_uc_packets; 890fe56b9e6SYuval Mintz u64 rx_mac_mc_packets; 891fe56b9e6SYuval Mintz u64 rx_mac_bc_packets; 892fe56b9e6SYuval Mintz u64 rx_mac_frames_ok; 893fe56b9e6SYuval Mintz u64 tx_mac_bytes; 894fe56b9e6SYuval Mintz u64 tx_mac_uc_packets; 895fe56b9e6SYuval Mintz u64 tx_mac_mc_packets; 896fe56b9e6SYuval Mintz u64 tx_mac_bc_packets; 897fe56b9e6SYuval Mintz u64 tx_mac_ctrl_frames; 898fe56b9e6SYuval Mintz }; 899fe56b9e6SYuval Mintz 9009c79ddaaSMintz, Yuval struct qed_eth_stats_bb { 9019c79ddaaSMintz, Yuval u64 rx_1519_to_1522_byte_packets; 9029c79ddaaSMintz, Yuval u64 rx_1519_to_2047_byte_packets; 9039c79ddaaSMintz, Yuval u64 rx_2048_to_4095_byte_packets; 9049c79ddaaSMintz, Yuval u64 rx_4096_to_9216_byte_packets; 9059c79ddaaSMintz, Yuval u64 rx_9217_to_16383_byte_packets; 9069c79ddaaSMintz, Yuval u64 tx_1519_to_2047_byte_packets; 9079c79ddaaSMintz, Yuval u64 tx_2048_to_4095_byte_packets; 9089c79ddaaSMintz, Yuval u64 tx_4096_to_9216_byte_packets; 9099c79ddaaSMintz, Yuval u64 tx_9217_to_16383_byte_packets; 9109c79ddaaSMintz, Yuval u64 tx_lpi_entry_count; 9119c79ddaaSMintz, Yuval u64 tx_total_collisions; 9129c79ddaaSMintz, Yuval }; 9139c79ddaaSMintz, Yuval 9149c79ddaaSMintz, Yuval struct qed_eth_stats_ah { 9159c79ddaaSMintz, Yuval u64 rx_1519_to_max_byte_packets; 9169c79ddaaSMintz, Yuval u64 tx_1519_to_max_byte_packets; 9179c79ddaaSMintz, Yuval }; 9189c79ddaaSMintz, Yuval 9199c79ddaaSMintz, Yuval struct qed_eth_stats { 9209c79ddaaSMintz, Yuval struct qed_eth_stats_common common; 9219c79ddaaSMintz, Yuval 9229c79ddaaSMintz, Yuval union { 9239c79ddaaSMintz, Yuval struct qed_eth_stats_bb bb; 9249c79ddaaSMintz, Yuval struct qed_eth_stats_ah ah; 9259c79ddaaSMintz, Yuval }; 9269c79ddaaSMintz, Yuval }; 9279c79ddaaSMintz, Yuval 928fe56b9e6SYuval Mintz #define QED_SB_IDX 0x0002 929fe56b9e6SYuval Mintz 930fe56b9e6SYuval Mintz #define RX_PI 0 931fe56b9e6SYuval Mintz #define TX_PI(tc) (RX_PI + 1 + tc) 932fe56b9e6SYuval Mintz 9334ac801b7SYuval Mintz struct qed_sb_cnt_info { 934726fdbe9SMintz, Yuval /* Original, current, and free SBs for PF */ 935726fdbe9SMintz, Yuval int orig; 936726fdbe9SMintz, Yuval int cnt; 937726fdbe9SMintz, Yuval int free_cnt; 938726fdbe9SMintz, Yuval 939726fdbe9SMintz, Yuval /* Original, current and free SBS for child VFs */ 940726fdbe9SMintz, Yuval int iov_orig; 941726fdbe9SMintz, Yuval int iov_cnt; 942726fdbe9SMintz, Yuval int free_cnt_iov; 9434ac801b7SYuval Mintz }; 9444ac801b7SYuval Mintz 945fe56b9e6SYuval Mintz static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info) 946fe56b9e6SYuval Mintz { 947fe56b9e6SYuval Mintz u32 prod = 0; 948fe56b9e6SYuval Mintz u16 rc = 0; 949fe56b9e6SYuval Mintz 950fe56b9e6SYuval Mintz prod = le32_to_cpu(sb_info->sb_virt->prod_index) & 951fe56b9e6SYuval Mintz STATUS_BLOCK_PROD_INDEX_MASK; 952fe56b9e6SYuval Mintz if (sb_info->sb_ack != prod) { 953fe56b9e6SYuval Mintz sb_info->sb_ack = prod; 954fe56b9e6SYuval Mintz rc |= QED_SB_IDX; 955fe56b9e6SYuval Mintz } 956fe56b9e6SYuval Mintz 957fe56b9e6SYuval Mintz /* Let SB update */ 958fe56b9e6SYuval Mintz mmiowb(); 959fe56b9e6SYuval Mintz return rc; 960fe56b9e6SYuval Mintz } 961fe56b9e6SYuval Mintz 962fe56b9e6SYuval Mintz /** 963fe56b9e6SYuval Mintz * 964fe56b9e6SYuval Mintz * @brief This function creates an update command for interrupts that is 965fe56b9e6SYuval Mintz * written to the IGU. 966fe56b9e6SYuval Mintz * 967fe56b9e6SYuval Mintz * @param sb_info - This is the structure allocated and 968fe56b9e6SYuval Mintz * initialized per status block. Assumption is 969fe56b9e6SYuval Mintz * that it was initialized using qed_sb_init 970fe56b9e6SYuval Mintz * @param int_cmd - Enable/Disable/Nop 971fe56b9e6SYuval Mintz * @param upd_flg - whether igu consumer should be 972fe56b9e6SYuval Mintz * updated. 973fe56b9e6SYuval Mintz * 974fe56b9e6SYuval Mintz * @return inline void 975fe56b9e6SYuval Mintz */ 976fe56b9e6SYuval Mintz static inline void qed_sb_ack(struct qed_sb_info *sb_info, 977fe56b9e6SYuval Mintz enum igu_int_cmd int_cmd, 978fe56b9e6SYuval Mintz u8 upd_flg) 979fe56b9e6SYuval Mintz { 980fe56b9e6SYuval Mintz struct igu_prod_cons_update igu_ack = { 0 }; 981fe56b9e6SYuval Mintz 982fe56b9e6SYuval Mintz igu_ack.sb_id_and_flags = 983fe56b9e6SYuval Mintz ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 984fe56b9e6SYuval Mintz (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 985fe56b9e6SYuval Mintz (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 986fe56b9e6SYuval Mintz (IGU_SEG_ACCESS_REG << 987fe56b9e6SYuval Mintz IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 988fe56b9e6SYuval Mintz 989fe56b9e6SYuval Mintz DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags); 990fe56b9e6SYuval Mintz 991fe56b9e6SYuval Mintz /* Both segments (interrupts & acks) are written to same place address; 992fe56b9e6SYuval Mintz * Need to guarantee all commands will be received (in-order) by HW. 993fe56b9e6SYuval Mintz */ 994fe56b9e6SYuval Mintz mmiowb(); 995fe56b9e6SYuval Mintz barrier(); 996fe56b9e6SYuval Mintz } 997fe56b9e6SYuval Mintz 998fe56b9e6SYuval Mintz static inline void __internal_ram_wr(void *p_hwfn, 999fe56b9e6SYuval Mintz void __iomem *addr, 1000fe56b9e6SYuval Mintz int size, 1001fe56b9e6SYuval Mintz u32 *data) 1002fe56b9e6SYuval Mintz 1003fe56b9e6SYuval Mintz { 1004fe56b9e6SYuval Mintz unsigned int i; 1005fe56b9e6SYuval Mintz 1006fe56b9e6SYuval Mintz for (i = 0; i < size / sizeof(*data); i++) 1007fe56b9e6SYuval Mintz DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]); 1008fe56b9e6SYuval Mintz } 1009fe56b9e6SYuval Mintz 1010fe56b9e6SYuval Mintz static inline void internal_ram_wr(void __iomem *addr, 1011fe56b9e6SYuval Mintz int size, 1012fe56b9e6SYuval Mintz u32 *data) 1013fe56b9e6SYuval Mintz { 1014fe56b9e6SYuval Mintz __internal_ram_wr(NULL, addr, size, data); 1015fe56b9e6SYuval Mintz } 1016fe56b9e6SYuval Mintz 10178c5ebd0cSSudarsana Reddy Kalluru enum qed_rss_caps { 10188c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV4 = 0x1, 10198c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV6 = 0x2, 10208c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV4_TCP = 0x4, 10218c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV6_TCP = 0x8, 10228c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV4_UDP = 0x10, 10238c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV6_UDP = 0x20, 10248c5ebd0cSSudarsana Reddy Kalluru }; 10258c5ebd0cSSudarsana Reddy Kalluru 10268c5ebd0cSSudarsana Reddy Kalluru #define QED_RSS_IND_TABLE_SIZE 128 10278c5ebd0cSSudarsana Reddy Kalluru #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */ 1028fe56b9e6SYuval Mintz #endif 1029