1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9fe56b9e6SYuval Mintz * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #ifndef _QED_IF_H 34fe56b9e6SYuval Mintz #define _QED_IF_H 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz #include <linux/types.h> 37fe56b9e6SYuval Mintz #include <linux/interrupt.h> 38fe56b9e6SYuval Mintz #include <linux/netdevice.h> 39fe56b9e6SYuval Mintz #include <linux/pci.h> 40fe56b9e6SYuval Mintz #include <linux/skbuff.h> 41fe56b9e6SYuval Mintz #include <linux/types.h> 42fe56b9e6SYuval Mintz #include <asm/byteorder.h> 43fe56b9e6SYuval Mintz #include <linux/io.h> 44fe56b9e6SYuval Mintz #include <linux/compiler.h> 45fe56b9e6SYuval Mintz #include <linux/kernel.h> 46fe56b9e6SYuval Mintz #include <linux/list.h> 47fe56b9e6SYuval Mintz #include <linux/slab.h> 48fe56b9e6SYuval Mintz #include <linux/qed/common_hsi.h> 49fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 50fe56b9e6SYuval Mintz 5139651abdSSudarsana Reddy Kalluru enum dcbx_protocol_type { 5239651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_ISCSI, 5339651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_FCOE, 5439651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_ROCE, 5539651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_ROCE_V2, 5639651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_ETH, 5739651abdSSudarsana Reddy Kalluru DCBX_MAX_PROTOCOL_TYPE 5839651abdSSudarsana Reddy Kalluru }; 5939651abdSSudarsana Reddy Kalluru 6051ff1725SRam Amrani #define QED_ROCE_PROTOCOL_INDEX (3) 6151ff1725SRam Amrani 626ad8c632SSudarsana Reddy Kalluru #define QED_LLDP_CHASSIS_ID_STAT_LEN 4 636ad8c632SSudarsana Reddy Kalluru #define QED_LLDP_PORT_ID_STAT_LEN 4 646ad8c632SSudarsana Reddy Kalluru #define QED_DCBX_MAX_APP_PROTOCOL 32 656ad8c632SSudarsana Reddy Kalluru #define QED_MAX_PFC_PRIORITIES 8 666ad8c632SSudarsana Reddy Kalluru #define QED_DCBX_DSCP_SIZE 64 676ad8c632SSudarsana Reddy Kalluru 686ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_remote { 696ad8c632SSudarsana Reddy Kalluru u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 706ad8c632SSudarsana Reddy Kalluru u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 716ad8c632SSudarsana Reddy Kalluru bool enable_rx; 726ad8c632SSudarsana Reddy Kalluru bool enable_tx; 736ad8c632SSudarsana Reddy Kalluru u32 tx_interval; 746ad8c632SSudarsana Reddy Kalluru u32 max_credit; 756ad8c632SSudarsana Reddy Kalluru }; 766ad8c632SSudarsana Reddy Kalluru 776ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_local { 786ad8c632SSudarsana Reddy Kalluru u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 796ad8c632SSudarsana Reddy Kalluru u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 806ad8c632SSudarsana Reddy Kalluru }; 816ad8c632SSudarsana Reddy Kalluru 826ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_app_prio { 836ad8c632SSudarsana Reddy Kalluru u8 roce; 846ad8c632SSudarsana Reddy Kalluru u8 roce_v2; 856ad8c632SSudarsana Reddy Kalluru u8 fcoe; 866ad8c632SSudarsana Reddy Kalluru u8 iscsi; 876ad8c632SSudarsana Reddy Kalluru u8 eth; 886ad8c632SSudarsana Reddy Kalluru }; 896ad8c632SSudarsana Reddy Kalluru 906ad8c632SSudarsana Reddy Kalluru struct qed_dbcx_pfc_params { 916ad8c632SSudarsana Reddy Kalluru bool willing; 926ad8c632SSudarsana Reddy Kalluru bool enabled; 936ad8c632SSudarsana Reddy Kalluru u8 prio[QED_MAX_PFC_PRIORITIES]; 946ad8c632SSudarsana Reddy Kalluru u8 max_tc; 956ad8c632SSudarsana Reddy Kalluru }; 966ad8c632SSudarsana Reddy Kalluru 9759bcb797SSudarsana Reddy Kalluru enum qed_dcbx_sf_ieee_type { 9859bcb797SSudarsana Reddy Kalluru QED_DCBX_SF_IEEE_ETHTYPE, 9959bcb797SSudarsana Reddy Kalluru QED_DCBX_SF_IEEE_TCP_PORT, 10059bcb797SSudarsana Reddy Kalluru QED_DCBX_SF_IEEE_UDP_PORT, 10159bcb797SSudarsana Reddy Kalluru QED_DCBX_SF_IEEE_TCP_UDP_PORT 10259bcb797SSudarsana Reddy Kalluru }; 10359bcb797SSudarsana Reddy Kalluru 1046ad8c632SSudarsana Reddy Kalluru struct qed_app_entry { 1056ad8c632SSudarsana Reddy Kalluru bool ethtype; 10659bcb797SSudarsana Reddy Kalluru enum qed_dcbx_sf_ieee_type sf_ieee; 1076ad8c632SSudarsana Reddy Kalluru bool enabled; 1086ad8c632SSudarsana Reddy Kalluru u8 prio; 1096ad8c632SSudarsana Reddy Kalluru u16 proto_id; 1106ad8c632SSudarsana Reddy Kalluru enum dcbx_protocol_type proto_type; 1116ad8c632SSudarsana Reddy Kalluru }; 1126ad8c632SSudarsana Reddy Kalluru 1136ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params { 1146ad8c632SSudarsana Reddy Kalluru struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL]; 1156ad8c632SSudarsana Reddy Kalluru u16 num_app_entries; 1166ad8c632SSudarsana Reddy Kalluru bool app_willing; 1176ad8c632SSudarsana Reddy Kalluru bool app_valid; 1186ad8c632SSudarsana Reddy Kalluru bool app_error; 1196ad8c632SSudarsana Reddy Kalluru bool ets_willing; 1206ad8c632SSudarsana Reddy Kalluru bool ets_enabled; 1216ad8c632SSudarsana Reddy Kalluru bool ets_cbs; 1226ad8c632SSudarsana Reddy Kalluru bool valid; 1236ad8c632SSudarsana Reddy Kalluru u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES]; 1246ad8c632SSudarsana Reddy Kalluru u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES]; 1256ad8c632SSudarsana Reddy Kalluru u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES]; 1266ad8c632SSudarsana Reddy Kalluru struct qed_dbcx_pfc_params pfc; 1276ad8c632SSudarsana Reddy Kalluru u8 max_ets_tc; 1286ad8c632SSudarsana Reddy Kalluru }; 1296ad8c632SSudarsana Reddy Kalluru 1306ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_admin_params { 1316ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params params; 1326ad8c632SSudarsana Reddy Kalluru bool valid; 1336ad8c632SSudarsana Reddy Kalluru }; 1346ad8c632SSudarsana Reddy Kalluru 1356ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_remote_params { 1366ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params params; 1376ad8c632SSudarsana Reddy Kalluru bool valid; 1386ad8c632SSudarsana Reddy Kalluru }; 1396ad8c632SSudarsana Reddy Kalluru 1406ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_operational_params { 1416ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_app_prio app_prio; 1426ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params params; 1436ad8c632SSudarsana Reddy Kalluru bool valid; 1446ad8c632SSudarsana Reddy Kalluru bool enabled; 1456ad8c632SSudarsana Reddy Kalluru bool ieee; 1466ad8c632SSudarsana Reddy Kalluru bool cee; 14749632b58Ssudarsana.kalluru@cavium.com bool local; 1486ad8c632SSudarsana Reddy Kalluru u32 err; 1496ad8c632SSudarsana Reddy Kalluru }; 1506ad8c632SSudarsana Reddy Kalluru 1516ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_get { 1526ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_operational_params operational; 1536ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_remote lldp_remote; 1546ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_local lldp_local; 1556ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_remote_params remote; 1566ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_admin_params local; 1576ad8c632SSudarsana Reddy Kalluru }; 1586ad8c632SSudarsana Reddy Kalluru 15920675b37SMintz, Yuval enum qed_nvm_images { 16020675b37SMintz, Yuval QED_NVM_IMAGE_ISCSI_CFG, 16120675b37SMintz, Yuval QED_NVM_IMAGE_FCOE_CFG, 1621ac4329aSDenis Bolotin QED_NVM_IMAGE_NVM_CFG1, 1631ac4329aSDenis Bolotin QED_NVM_IMAGE_DEFAULT_CFG, 1641ac4329aSDenis Bolotin QED_NVM_IMAGE_NVM_META, 16520675b37SMintz, Yuval }; 16620675b37SMintz, Yuval 167645874e5SSudarsana Reddy Kalluru struct qed_link_eee_params { 168645874e5SSudarsana Reddy Kalluru u32 tx_lpi_timer; 169645874e5SSudarsana Reddy Kalluru #define QED_EEE_1G_ADV BIT(0) 170645874e5SSudarsana Reddy Kalluru #define QED_EEE_10G_ADV BIT(1) 171645874e5SSudarsana Reddy Kalluru 172645874e5SSudarsana Reddy Kalluru /* Capabilities are represented using QED_EEE_*_ADV values */ 173645874e5SSudarsana Reddy Kalluru u8 adv_caps; 174645874e5SSudarsana Reddy Kalluru u8 lp_adv_caps; 175645874e5SSudarsana Reddy Kalluru bool enable; 176645874e5SSudarsana Reddy Kalluru bool tx_lpi_enable; 177645874e5SSudarsana Reddy Kalluru }; 178645874e5SSudarsana Reddy Kalluru 17991420b83SSudarsana Kalluru enum qed_led_mode { 18091420b83SSudarsana Kalluru QED_LED_MODE_OFF, 18191420b83SSudarsana Kalluru QED_LED_MODE_ON, 18291420b83SSudarsana Kalluru QED_LED_MODE_RESTORE 18391420b83SSudarsana Kalluru }; 18491420b83SSudarsana Kalluru 1852528c389SSudarsana Reddy Kalluru struct qed_mfw_tlv_eth { 1862528c389SSudarsana Reddy Kalluru u16 lso_maxoff_size; 1872528c389SSudarsana Reddy Kalluru bool lso_maxoff_size_set; 1882528c389SSudarsana Reddy Kalluru u16 lso_minseg_size; 1892528c389SSudarsana Reddy Kalluru bool lso_minseg_size_set; 1902528c389SSudarsana Reddy Kalluru u8 prom_mode; 1912528c389SSudarsana Reddy Kalluru bool prom_mode_set; 1922528c389SSudarsana Reddy Kalluru u16 tx_descr_size; 1932528c389SSudarsana Reddy Kalluru bool tx_descr_size_set; 1942528c389SSudarsana Reddy Kalluru u16 rx_descr_size; 1952528c389SSudarsana Reddy Kalluru bool rx_descr_size_set; 1962528c389SSudarsana Reddy Kalluru u16 netq_count; 1972528c389SSudarsana Reddy Kalluru bool netq_count_set; 1982528c389SSudarsana Reddy Kalluru u32 tcp4_offloads; 1992528c389SSudarsana Reddy Kalluru bool tcp4_offloads_set; 2002528c389SSudarsana Reddy Kalluru u32 tcp6_offloads; 2012528c389SSudarsana Reddy Kalluru bool tcp6_offloads_set; 2022528c389SSudarsana Reddy Kalluru u16 tx_descr_qdepth; 2032528c389SSudarsana Reddy Kalluru bool tx_descr_qdepth_set; 2042528c389SSudarsana Reddy Kalluru u16 rx_descr_qdepth; 2052528c389SSudarsana Reddy Kalluru bool rx_descr_qdepth_set; 2062528c389SSudarsana Reddy Kalluru u8 iov_offload; 2072528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_IOV_OFFLOAD_NONE (0) 2082528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE (1) 2092528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_IOV_OFFLOAD_VEB (2) 2102528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_IOV_OFFLOAD_VEPA (3) 2112528c389SSudarsana Reddy Kalluru bool iov_offload_set; 2122528c389SSudarsana Reddy Kalluru u8 txqs_empty; 2132528c389SSudarsana Reddy Kalluru bool txqs_empty_set; 2142528c389SSudarsana Reddy Kalluru u8 rxqs_empty; 2152528c389SSudarsana Reddy Kalluru bool rxqs_empty_set; 2162528c389SSudarsana Reddy Kalluru u8 num_txqs_full; 2172528c389SSudarsana Reddy Kalluru bool num_txqs_full_set; 2182528c389SSudarsana Reddy Kalluru u8 num_rxqs_full; 2192528c389SSudarsana Reddy Kalluru bool num_rxqs_full_set; 2202528c389SSudarsana Reddy Kalluru }; 2212528c389SSudarsana Reddy Kalluru 222f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_TIME_SIZE 14 223f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_time { 224f240b688SSudarsana Reddy Kalluru bool b_set; 225f240b688SSudarsana Reddy Kalluru u8 month; 226f240b688SSudarsana Reddy Kalluru u8 day; 227f240b688SSudarsana Reddy Kalluru u8 hour; 228f240b688SSudarsana Reddy Kalluru u8 min; 229f240b688SSudarsana Reddy Kalluru u16 msec; 230f240b688SSudarsana Reddy Kalluru u16 usec; 231f240b688SSudarsana Reddy Kalluru }; 232f240b688SSudarsana Reddy Kalluru 233f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_fcoe { 234f240b688SSudarsana Reddy Kalluru u8 scsi_timeout; 235f240b688SSudarsana Reddy Kalluru bool scsi_timeout_set; 236f240b688SSudarsana Reddy Kalluru u32 rt_tov; 237f240b688SSudarsana Reddy Kalluru bool rt_tov_set; 238f240b688SSudarsana Reddy Kalluru u32 ra_tov; 239f240b688SSudarsana Reddy Kalluru bool ra_tov_set; 240f240b688SSudarsana Reddy Kalluru u32 ed_tov; 241f240b688SSudarsana Reddy Kalluru bool ed_tov_set; 242f240b688SSudarsana Reddy Kalluru u32 cr_tov; 243f240b688SSudarsana Reddy Kalluru bool cr_tov_set; 244f240b688SSudarsana Reddy Kalluru u8 boot_type; 245f240b688SSudarsana Reddy Kalluru bool boot_type_set; 246f240b688SSudarsana Reddy Kalluru u8 npiv_state; 247f240b688SSudarsana Reddy Kalluru bool npiv_state_set; 248f240b688SSudarsana Reddy Kalluru u32 num_npiv_ids; 249f240b688SSudarsana Reddy Kalluru bool num_npiv_ids_set; 250f240b688SSudarsana Reddy Kalluru u8 switch_name[8]; 251f240b688SSudarsana Reddy Kalluru bool switch_name_set; 252f240b688SSudarsana Reddy Kalluru u16 switch_portnum; 253f240b688SSudarsana Reddy Kalluru bool switch_portnum_set; 254f240b688SSudarsana Reddy Kalluru u8 switch_portid[3]; 255f240b688SSudarsana Reddy Kalluru bool switch_portid_set; 256f240b688SSudarsana Reddy Kalluru u8 vendor_name[8]; 257f240b688SSudarsana Reddy Kalluru bool vendor_name_set; 258f240b688SSudarsana Reddy Kalluru u8 switch_model[8]; 259f240b688SSudarsana Reddy Kalluru bool switch_model_set; 260f240b688SSudarsana Reddy Kalluru u8 switch_fw_version[8]; 261f240b688SSudarsana Reddy Kalluru bool switch_fw_version_set; 262f240b688SSudarsana Reddy Kalluru u8 qos_pri; 263f240b688SSudarsana Reddy Kalluru bool qos_pri_set; 264f240b688SSudarsana Reddy Kalluru u8 port_alias[3]; 265f240b688SSudarsana Reddy Kalluru bool port_alias_set; 266f240b688SSudarsana Reddy Kalluru u8 port_state; 267f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_PORT_STATE_OFFLINE (0) 268f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_PORT_STATE_LOOP (1) 269f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_PORT_STATE_P2P (2) 270f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_PORT_STATE_FABRIC (3) 271f240b688SSudarsana Reddy Kalluru bool port_state_set; 272f240b688SSudarsana Reddy Kalluru u16 fip_tx_descr_size; 273f240b688SSudarsana Reddy Kalluru bool fip_tx_descr_size_set; 274f240b688SSudarsana Reddy Kalluru u16 fip_rx_descr_size; 275f240b688SSudarsana Reddy Kalluru bool fip_rx_descr_size_set; 276f240b688SSudarsana Reddy Kalluru u16 link_failures; 277f240b688SSudarsana Reddy Kalluru bool link_failures_set; 278f240b688SSudarsana Reddy Kalluru u8 fcoe_boot_progress; 279f240b688SSudarsana Reddy Kalluru bool fcoe_boot_progress_set; 280f240b688SSudarsana Reddy Kalluru u64 rx_bcast; 281f240b688SSudarsana Reddy Kalluru bool rx_bcast_set; 282f240b688SSudarsana Reddy Kalluru u64 tx_bcast; 283f240b688SSudarsana Reddy Kalluru bool tx_bcast_set; 284f240b688SSudarsana Reddy Kalluru u16 fcoe_txq_depth; 285f240b688SSudarsana Reddy Kalluru bool fcoe_txq_depth_set; 286f240b688SSudarsana Reddy Kalluru u16 fcoe_rxq_depth; 287f240b688SSudarsana Reddy Kalluru bool fcoe_rxq_depth_set; 288f240b688SSudarsana Reddy Kalluru u64 fcoe_rx_frames; 289f240b688SSudarsana Reddy Kalluru bool fcoe_rx_frames_set; 290f240b688SSudarsana Reddy Kalluru u64 fcoe_rx_bytes; 291f240b688SSudarsana Reddy Kalluru bool fcoe_rx_bytes_set; 292f240b688SSudarsana Reddy Kalluru u64 fcoe_tx_frames; 293f240b688SSudarsana Reddy Kalluru bool fcoe_tx_frames_set; 294f240b688SSudarsana Reddy Kalluru u64 fcoe_tx_bytes; 295f240b688SSudarsana Reddy Kalluru bool fcoe_tx_bytes_set; 296f240b688SSudarsana Reddy Kalluru u16 crc_count; 297f240b688SSudarsana Reddy Kalluru bool crc_count_set; 298f240b688SSudarsana Reddy Kalluru u32 crc_err_src_fcid[5]; 299f240b688SSudarsana Reddy Kalluru bool crc_err_src_fcid_set[5]; 300f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_time crc_err[5]; 301f240b688SSudarsana Reddy Kalluru u16 losync_err; 302f240b688SSudarsana Reddy Kalluru bool losync_err_set; 303f240b688SSudarsana Reddy Kalluru u16 losig_err; 304f240b688SSudarsana Reddy Kalluru bool losig_err_set; 305f240b688SSudarsana Reddy Kalluru u16 primtive_err; 306f240b688SSudarsana Reddy Kalluru bool primtive_err_set; 307f240b688SSudarsana Reddy Kalluru u16 disparity_err; 308f240b688SSudarsana Reddy Kalluru bool disparity_err_set; 309f240b688SSudarsana Reddy Kalluru u16 code_violation_err; 310f240b688SSudarsana Reddy Kalluru bool code_violation_err_set; 311f240b688SSudarsana Reddy Kalluru u32 flogi_param[4]; 312f240b688SSudarsana Reddy Kalluru bool flogi_param_set[4]; 313f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_time flogi_tstamp; 314f240b688SSudarsana Reddy Kalluru u32 flogi_acc_param[4]; 315f240b688SSudarsana Reddy Kalluru bool flogi_acc_param_set[4]; 316f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_time flogi_acc_tstamp; 317f240b688SSudarsana Reddy Kalluru u32 flogi_rjt; 318f240b688SSudarsana Reddy Kalluru bool flogi_rjt_set; 319f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_time flogi_rjt_tstamp; 320f240b688SSudarsana Reddy Kalluru u32 fdiscs; 321f240b688SSudarsana Reddy Kalluru bool fdiscs_set; 322f240b688SSudarsana Reddy Kalluru u8 fdisc_acc; 323f240b688SSudarsana Reddy Kalluru bool fdisc_acc_set; 324f240b688SSudarsana Reddy Kalluru u8 fdisc_rjt; 325f240b688SSudarsana Reddy Kalluru bool fdisc_rjt_set; 326f240b688SSudarsana Reddy Kalluru u8 plogi; 327f240b688SSudarsana Reddy Kalluru bool plogi_set; 328f240b688SSudarsana Reddy Kalluru u8 plogi_acc; 329f240b688SSudarsana Reddy Kalluru bool plogi_acc_set; 330f240b688SSudarsana Reddy Kalluru u8 plogi_rjt; 331f240b688SSudarsana Reddy Kalluru bool plogi_rjt_set; 332f240b688SSudarsana Reddy Kalluru u32 plogi_dst_fcid[5]; 333f240b688SSudarsana Reddy Kalluru bool plogi_dst_fcid_set[5]; 334f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_time plogi_tstamp[5]; 335f240b688SSudarsana Reddy Kalluru u32 plogi_acc_src_fcid[5]; 336f240b688SSudarsana Reddy Kalluru bool plogi_acc_src_fcid_set[5]; 337f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_time plogi_acc_tstamp[5]; 338f240b688SSudarsana Reddy Kalluru u8 tx_plogos; 339f240b688SSudarsana Reddy Kalluru bool tx_plogos_set; 340f240b688SSudarsana Reddy Kalluru u8 plogo_acc; 341f240b688SSudarsana Reddy Kalluru bool plogo_acc_set; 342f240b688SSudarsana Reddy Kalluru u8 plogo_rjt; 343f240b688SSudarsana Reddy Kalluru bool plogo_rjt_set; 344f240b688SSudarsana Reddy Kalluru u32 plogo_src_fcid[5]; 345f240b688SSudarsana Reddy Kalluru bool plogo_src_fcid_set[5]; 346f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_time plogo_tstamp[5]; 347f240b688SSudarsana Reddy Kalluru u8 rx_logos; 348f240b688SSudarsana Reddy Kalluru bool rx_logos_set; 349f240b688SSudarsana Reddy Kalluru u8 tx_accs; 350f240b688SSudarsana Reddy Kalluru bool tx_accs_set; 351f240b688SSudarsana Reddy Kalluru u8 tx_prlis; 352f240b688SSudarsana Reddy Kalluru bool tx_prlis_set; 353f240b688SSudarsana Reddy Kalluru u8 rx_accs; 354f240b688SSudarsana Reddy Kalluru bool rx_accs_set; 355f240b688SSudarsana Reddy Kalluru u8 tx_abts; 356f240b688SSudarsana Reddy Kalluru bool tx_abts_set; 357f240b688SSudarsana Reddy Kalluru u8 rx_abts_acc; 358f240b688SSudarsana Reddy Kalluru bool rx_abts_acc_set; 359f240b688SSudarsana Reddy Kalluru u8 rx_abts_rjt; 360f240b688SSudarsana Reddy Kalluru bool rx_abts_rjt_set; 361f240b688SSudarsana Reddy Kalluru u32 abts_dst_fcid[5]; 362f240b688SSudarsana Reddy Kalluru bool abts_dst_fcid_set[5]; 363f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_time abts_tstamp[5]; 364f240b688SSudarsana Reddy Kalluru u8 rx_rscn; 365f240b688SSudarsana Reddy Kalluru bool rx_rscn_set; 366f240b688SSudarsana Reddy Kalluru u32 rx_rscn_nport[4]; 367f240b688SSudarsana Reddy Kalluru bool rx_rscn_nport_set[4]; 368f240b688SSudarsana Reddy Kalluru u8 tx_lun_rst; 369f240b688SSudarsana Reddy Kalluru bool tx_lun_rst_set; 370f240b688SSudarsana Reddy Kalluru u8 abort_task_sets; 371f240b688SSudarsana Reddy Kalluru bool abort_task_sets_set; 372f240b688SSudarsana Reddy Kalluru u8 tx_tprlos; 373f240b688SSudarsana Reddy Kalluru bool tx_tprlos_set; 374f240b688SSudarsana Reddy Kalluru u8 tx_nos; 375f240b688SSudarsana Reddy Kalluru bool tx_nos_set; 376f240b688SSudarsana Reddy Kalluru u8 rx_nos; 377f240b688SSudarsana Reddy Kalluru bool rx_nos_set; 378f240b688SSudarsana Reddy Kalluru u8 ols; 379f240b688SSudarsana Reddy Kalluru bool ols_set; 380f240b688SSudarsana Reddy Kalluru u8 lr; 381f240b688SSudarsana Reddy Kalluru bool lr_set; 382f240b688SSudarsana Reddy Kalluru u8 lrr; 383f240b688SSudarsana Reddy Kalluru bool lrr_set; 384f240b688SSudarsana Reddy Kalluru u8 tx_lip; 385f240b688SSudarsana Reddy Kalluru bool tx_lip_set; 386f240b688SSudarsana Reddy Kalluru u8 rx_lip; 387f240b688SSudarsana Reddy Kalluru bool rx_lip_set; 388f240b688SSudarsana Reddy Kalluru u8 eofa; 389f240b688SSudarsana Reddy Kalluru bool eofa_set; 390f240b688SSudarsana Reddy Kalluru u8 eofni; 391f240b688SSudarsana Reddy Kalluru bool eofni_set; 392f240b688SSudarsana Reddy Kalluru u8 scsi_chks; 393f240b688SSudarsana Reddy Kalluru bool scsi_chks_set; 394f240b688SSudarsana Reddy Kalluru u8 scsi_cond_met; 395f240b688SSudarsana Reddy Kalluru bool scsi_cond_met_set; 396f240b688SSudarsana Reddy Kalluru u8 scsi_busy; 397f240b688SSudarsana Reddy Kalluru bool scsi_busy_set; 398f240b688SSudarsana Reddy Kalluru u8 scsi_inter; 399f240b688SSudarsana Reddy Kalluru bool scsi_inter_set; 400f240b688SSudarsana Reddy Kalluru u8 scsi_inter_cond_met; 401f240b688SSudarsana Reddy Kalluru bool scsi_inter_cond_met_set; 402f240b688SSudarsana Reddy Kalluru u8 scsi_rsv_conflicts; 403f240b688SSudarsana Reddy Kalluru bool scsi_rsv_conflicts_set; 404f240b688SSudarsana Reddy Kalluru u8 scsi_tsk_full; 405f240b688SSudarsana Reddy Kalluru bool scsi_tsk_full_set; 406f240b688SSudarsana Reddy Kalluru u8 scsi_aca_active; 407f240b688SSudarsana Reddy Kalluru bool scsi_aca_active_set; 408f240b688SSudarsana Reddy Kalluru u8 scsi_tsk_abort; 409f240b688SSudarsana Reddy Kalluru bool scsi_tsk_abort_set; 410f240b688SSudarsana Reddy Kalluru u32 scsi_rx_chk[5]; 411f240b688SSudarsana Reddy Kalluru bool scsi_rx_chk_set[5]; 412f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_time scsi_chk_tstamp[5]; 413f240b688SSudarsana Reddy Kalluru }; 414f240b688SSudarsana Reddy Kalluru 41577a509e4SSudarsana Reddy Kalluru struct qed_mfw_tlv_iscsi { 41677a509e4SSudarsana Reddy Kalluru u8 target_llmnr; 41777a509e4SSudarsana Reddy Kalluru bool target_llmnr_set; 41877a509e4SSudarsana Reddy Kalluru u8 header_digest; 41977a509e4SSudarsana Reddy Kalluru bool header_digest_set; 42077a509e4SSudarsana Reddy Kalluru u8 data_digest; 42177a509e4SSudarsana Reddy Kalluru bool data_digest_set; 42277a509e4SSudarsana Reddy Kalluru u8 auth_method; 42377a509e4SSudarsana Reddy Kalluru #define QED_MFW_TLV_AUTH_METHOD_NONE (1) 42477a509e4SSudarsana Reddy Kalluru #define QED_MFW_TLV_AUTH_METHOD_CHAP (2) 42577a509e4SSudarsana Reddy Kalluru #define QED_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP (3) 42677a509e4SSudarsana Reddy Kalluru bool auth_method_set; 42777a509e4SSudarsana Reddy Kalluru u16 boot_taget_portal; 42877a509e4SSudarsana Reddy Kalluru bool boot_taget_portal_set; 42977a509e4SSudarsana Reddy Kalluru u16 frame_size; 43077a509e4SSudarsana Reddy Kalluru bool frame_size_set; 43177a509e4SSudarsana Reddy Kalluru u16 tx_desc_size; 43277a509e4SSudarsana Reddy Kalluru bool tx_desc_size_set; 43377a509e4SSudarsana Reddy Kalluru u16 rx_desc_size; 43477a509e4SSudarsana Reddy Kalluru bool rx_desc_size_set; 43577a509e4SSudarsana Reddy Kalluru u8 boot_progress; 43677a509e4SSudarsana Reddy Kalluru bool boot_progress_set; 43777a509e4SSudarsana Reddy Kalluru u16 tx_desc_qdepth; 43877a509e4SSudarsana Reddy Kalluru bool tx_desc_qdepth_set; 43977a509e4SSudarsana Reddy Kalluru u16 rx_desc_qdepth; 44077a509e4SSudarsana Reddy Kalluru bool rx_desc_qdepth_set; 44177a509e4SSudarsana Reddy Kalluru u64 rx_frames; 44277a509e4SSudarsana Reddy Kalluru bool rx_frames_set; 44377a509e4SSudarsana Reddy Kalluru u64 rx_bytes; 44477a509e4SSudarsana Reddy Kalluru bool rx_bytes_set; 44577a509e4SSudarsana Reddy Kalluru u64 tx_frames; 44677a509e4SSudarsana Reddy Kalluru bool tx_frames_set; 44777a509e4SSudarsana Reddy Kalluru u64 tx_bytes; 44877a509e4SSudarsana Reddy Kalluru bool tx_bytes_set; 44977a509e4SSudarsana Reddy Kalluru }; 45077a509e4SSudarsana Reddy Kalluru 451fe56b9e6SYuval Mintz #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \ 452fe56b9e6SYuval Mintz (void __iomem *)(reg_addr)) 453fe56b9e6SYuval Mintz 454fe56b9e6SYuval Mintz #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr)) 455fe56b9e6SYuval Mintz 45641822878SRahul Verma #define QED_COALESCE_MAX 0x1FF 4570e191827SSudarsana Reddy Kalluru #define QED_DEFAULT_RX_USECS 12 458bf5a94bfSRahul Verma #define QED_DEFAULT_TX_USECS 48 459fe56b9e6SYuval Mintz 460fe56b9e6SYuval Mintz /* forward */ 461fe56b9e6SYuval Mintz struct qed_dev; 462fe56b9e6SYuval Mintz 463fe56b9e6SYuval Mintz struct qed_eth_pf_params { 464fe56b9e6SYuval Mintz /* The following parameters are used during HW-init 465fe56b9e6SYuval Mintz * and these parameters need to be passed as arguments 466fe56b9e6SYuval Mintz * to update_pf_params routine invoked before slowpath start 467fe56b9e6SYuval Mintz */ 468fe56b9e6SYuval Mintz u16 num_cons; 469d51e4af5SChopra, Manish 47008bc8f15SMintz, Yuval /* per-VF number of CIDs */ 47108bc8f15SMintz, Yuval u8 num_vf_cons; 47208bc8f15SMintz, Yuval #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32) 47308bc8f15SMintz, Yuval 474d51e4af5SChopra, Manish /* To enable arfs, previous to HW-init a positive number needs to be 475d51e4af5SChopra, Manish * set [as filters require allocated searcher ILT memory]. 476d51e4af5SChopra, Manish * This will set the maximal number of configured steering-filters. 477d51e4af5SChopra, Manish */ 478d51e4af5SChopra, Manish u32 num_arfs_filters; 479fe56b9e6SYuval Mintz }; 480fe56b9e6SYuval Mintz 4811e128c81SArun Easi struct qed_fcoe_pf_params { 4821e128c81SArun Easi /* The following parameters are used during protocol-init */ 4831e128c81SArun Easi u64 glbl_q_params_addr; 4841e128c81SArun Easi u64 bdq_pbl_base_addr[2]; 4851e128c81SArun Easi 4861e128c81SArun Easi /* The following parameters are used during HW-init 4871e128c81SArun Easi * and these parameters need to be passed as arguments 4881e128c81SArun Easi * to update_pf_params routine invoked before slowpath start 4891e128c81SArun Easi */ 4901e128c81SArun Easi u16 num_cons; 4911e128c81SArun Easi u16 num_tasks; 4921e128c81SArun Easi 4931e128c81SArun Easi /* The following parameters are used during protocol-init */ 4941e128c81SArun Easi u16 sq_num_pbl_pages; 4951e128c81SArun Easi 4961e128c81SArun Easi u16 cq_num_entries; 4971e128c81SArun Easi u16 cmdq_num_entries; 4981e128c81SArun Easi u16 rq_buffer_log_size; 4991e128c81SArun Easi u16 mtu; 5001e128c81SArun Easi u16 dummy_icid; 5011e128c81SArun Easi u16 bdq_xoff_threshold[2]; 5021e128c81SArun Easi u16 bdq_xon_threshold[2]; 5031e128c81SArun Easi u16 rq_buffer_size; 5041e128c81SArun Easi u8 num_cqs; /* num of global CQs */ 5051e128c81SArun Easi u8 log_page_size; 5061e128c81SArun Easi u8 gl_rq_pi; 5071e128c81SArun Easi u8 gl_cmd_pi; 5081e128c81SArun Easi u8 debug_mode; 5091e128c81SArun Easi u8 is_target; 5101e128c81SArun Easi u8 bdq_pbl_num_entries[2]; 5111e128c81SArun Easi }; 5121e128c81SArun Easi 513c5ac9319SYuval Mintz /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */ 514c5ac9319SYuval Mintz struct qed_iscsi_pf_params { 515c5ac9319SYuval Mintz u64 glbl_q_params_addr; 516da090917STomer Tayar u64 bdq_pbl_base_addr[3]; 517c5ac9319SYuval Mintz u16 cq_num_entries; 518c5ac9319SYuval Mintz u16 cmdq_num_entries; 519fc831825SYuval Mintz u32 two_msl_timer; 520c5ac9319SYuval Mintz u16 tx_sws_timer; 521c5ac9319SYuval Mintz 522c5ac9319SYuval Mintz /* The following parameters are used during HW-init 523c5ac9319SYuval Mintz * and these parameters need to be passed as arguments 524c5ac9319SYuval Mintz * to update_pf_params routine invoked before slowpath start 525c5ac9319SYuval Mintz */ 526c5ac9319SYuval Mintz u16 num_cons; 527c5ac9319SYuval Mintz u16 num_tasks; 528c5ac9319SYuval Mintz 529c5ac9319SYuval Mintz /* The following parameters are used during protocol-init */ 530c5ac9319SYuval Mintz u16 half_way_close_timeout; 531da090917STomer Tayar u16 bdq_xoff_threshold[3]; 532da090917STomer Tayar u16 bdq_xon_threshold[3]; 533c5ac9319SYuval Mintz u16 cmdq_xoff_threshold; 534c5ac9319SYuval Mintz u16 cmdq_xon_threshold; 535c5ac9319SYuval Mintz u16 rq_buffer_size; 536c5ac9319SYuval Mintz 537c5ac9319SYuval Mintz u8 num_sq_pages_in_ring; 538c5ac9319SYuval Mintz u8 num_r2tq_pages_in_ring; 539c5ac9319SYuval Mintz u8 num_uhq_pages_in_ring; 540c5ac9319SYuval Mintz u8 num_queues; 541c5ac9319SYuval Mintz u8 log_page_size; 542c5ac9319SYuval Mintz u8 rqe_log_size; 543c5ac9319SYuval Mintz u8 max_fin_rt; 544c5ac9319SYuval Mintz u8 gl_rq_pi; 545c5ac9319SYuval Mintz u8 gl_cmd_pi; 546c5ac9319SYuval Mintz u8 debug_mode; 547c5ac9319SYuval Mintz u8 ll2_ooo_queue_id; 548c5ac9319SYuval Mintz 549c5ac9319SYuval Mintz u8 is_target; 550da090917STomer Tayar u8 is_soc_en; 551da090917STomer Tayar u8 soc_num_of_blocks_log; 552da090917STomer Tayar u8 bdq_pbl_num_entries[3]; 553c5ac9319SYuval Mintz }; 554c5ac9319SYuval Mintz 555c5ac9319SYuval Mintz struct qed_rdma_pf_params { 556c5ac9319SYuval Mintz /* Supplied to QED during resource allocation (may affect the ILT and 557c5ac9319SYuval Mintz * the doorbell BAR). 558c5ac9319SYuval Mintz */ 559c5ac9319SYuval Mintz u32 min_dpis; /* number of requested DPIs */ 560c5ac9319SYuval Mintz u32 num_qps; /* number of requested Queue Pairs */ 561c5ac9319SYuval Mintz u32 num_srqs; /* number of requested SRQ */ 562c5ac9319SYuval Mintz u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */ 563c5ac9319SYuval Mintz u8 gl_pi; /* protocol index */ 564c5ac9319SYuval Mintz 565c5ac9319SYuval Mintz /* Will allocate rate limiters to be used with QPs */ 566c5ac9319SYuval Mintz u8 enable_dcqcn; 567c5ac9319SYuval Mintz }; 568c5ac9319SYuval Mintz 569fe56b9e6SYuval Mintz struct qed_pf_params { 570fe56b9e6SYuval Mintz struct qed_eth_pf_params eth_pf_params; 5711e128c81SArun Easi struct qed_fcoe_pf_params fcoe_pf_params; 572c5ac9319SYuval Mintz struct qed_iscsi_pf_params iscsi_pf_params; 573c5ac9319SYuval Mintz struct qed_rdma_pf_params rdma_pf_params; 574fe56b9e6SYuval Mintz }; 575fe56b9e6SYuval Mintz 576fe56b9e6SYuval Mintz enum qed_int_mode { 577fe56b9e6SYuval Mintz QED_INT_MODE_INTA, 578fe56b9e6SYuval Mintz QED_INT_MODE_MSIX, 579fe56b9e6SYuval Mintz QED_INT_MODE_MSI, 580fe56b9e6SYuval Mintz QED_INT_MODE_POLL, 581fe56b9e6SYuval Mintz }; 582fe56b9e6SYuval Mintz 583fe56b9e6SYuval Mintz struct qed_sb_info { 58421dd79e8STomer Tayar struct status_block_e4 *sb_virt; 585fe56b9e6SYuval Mintz dma_addr_t sb_phys; 586fe56b9e6SYuval Mintz u32 sb_ack; /* Last given ack */ 587fe56b9e6SYuval Mintz u16 igu_sb_id; 588fe56b9e6SYuval Mintz void __iomem *igu_addr; 589fe56b9e6SYuval Mintz u8 flags; 590fe56b9e6SYuval Mintz #define QED_SB_INFO_INIT 0x1 591fe56b9e6SYuval Mintz #define QED_SB_INFO_SETUP 0x2 592fe56b9e6SYuval Mintz 593fe56b9e6SYuval Mintz struct qed_dev *cdev; 594fe56b9e6SYuval Mintz }; 595fe56b9e6SYuval Mintz 5969c79ddaaSMintz, Yuval enum qed_dev_type { 5979c79ddaaSMintz, Yuval QED_DEV_TYPE_BB, 5989c79ddaaSMintz, Yuval QED_DEV_TYPE_AH, 5999c79ddaaSMintz, Yuval }; 6009c79ddaaSMintz, Yuval 601fe56b9e6SYuval Mintz struct qed_dev_info { 602fe56b9e6SYuval Mintz unsigned long pci_mem_start; 603fe56b9e6SYuval Mintz unsigned long pci_mem_end; 604fe56b9e6SYuval Mintz unsigned int pci_irq; 605fe56b9e6SYuval Mintz u8 num_hwfns; 606fe56b9e6SYuval Mintz 607fe56b9e6SYuval Mintz u8 hw_mac[ETH_ALEN]; 608fe56b9e6SYuval Mintz 609fe56b9e6SYuval Mintz /* FW version */ 610fe56b9e6SYuval Mintz u16 fw_major; 611fe56b9e6SYuval Mintz u16 fw_minor; 612fe56b9e6SYuval Mintz u16 fw_rev; 613fe56b9e6SYuval Mintz u16 fw_eng; 614fe56b9e6SYuval Mintz 615fe56b9e6SYuval Mintz /* MFW version */ 616fe56b9e6SYuval Mintz u32 mfw_rev; 617ae33666aSTomer Tayar #define QED_MFW_VERSION_0_MASK 0x000000FF 618ae33666aSTomer Tayar #define QED_MFW_VERSION_0_OFFSET 0 619ae33666aSTomer Tayar #define QED_MFW_VERSION_1_MASK 0x0000FF00 620ae33666aSTomer Tayar #define QED_MFW_VERSION_1_OFFSET 8 621ae33666aSTomer Tayar #define QED_MFW_VERSION_2_MASK 0x00FF0000 622ae33666aSTomer Tayar #define QED_MFW_VERSION_2_OFFSET 16 623ae33666aSTomer Tayar #define QED_MFW_VERSION_3_MASK 0xFF000000 624ae33666aSTomer Tayar #define QED_MFW_VERSION_3_OFFSET 24 625fe56b9e6SYuval Mintz 626fe56b9e6SYuval Mintz u32 flash_size; 6270bc5fe85SSudarsana Reddy Kalluru bool b_inter_pf_switch; 628831bfb0eSYuval Mintz bool tx_switching; 629cee9fbd8SRam Amrani bool rdma_supported; 6300fefbfbaSSudarsana Kalluru u16 mtu; 63114d39648SMintz, Yuval 63214d39648SMintz, Yuval bool wol_support; 6339c79ddaaSMintz, Yuval 634ae33666aSTomer Tayar /* MBI version */ 635ae33666aSTomer Tayar u32 mbi_version; 636ae33666aSTomer Tayar #define QED_MBI_VERSION_0_MASK 0x000000FF 637ae33666aSTomer Tayar #define QED_MBI_VERSION_0_OFFSET 0 638ae33666aSTomer Tayar #define QED_MBI_VERSION_1_MASK 0x0000FF00 639ae33666aSTomer Tayar #define QED_MBI_VERSION_1_OFFSET 8 640ae33666aSTomer Tayar #define QED_MBI_VERSION_2_MASK 0x00FF0000 641ae33666aSTomer Tayar #define QED_MBI_VERSION_2_OFFSET 16 642ae33666aSTomer Tayar 6439c79ddaaSMintz, Yuval enum qed_dev_type dev_type; 64419489c7fSChopra, Manish 64519489c7fSChopra, Manish /* Output parameters for qede */ 64619489c7fSChopra, Manish bool vxlan_enable; 64719489c7fSChopra, Manish bool gre_enable; 64819489c7fSChopra, Manish bool geneve_enable; 6493c5da942SMintz, Yuval 6503c5da942SMintz, Yuval u8 abs_pf_id; 651fe56b9e6SYuval Mintz }; 652fe56b9e6SYuval Mintz 653fe56b9e6SYuval Mintz enum qed_sb_type { 654fe56b9e6SYuval Mintz QED_SB_TYPE_L2_QUEUE, 65551ff1725SRam Amrani QED_SB_TYPE_CNQ, 656fc831825SYuval Mintz QED_SB_TYPE_STORAGE, 657fe56b9e6SYuval Mintz }; 658fe56b9e6SYuval Mintz 659fe56b9e6SYuval Mintz enum qed_protocol { 660fe56b9e6SYuval Mintz QED_PROTOCOL_ETH, 661c5ac9319SYuval Mintz QED_PROTOCOL_ISCSI, 6621e128c81SArun Easi QED_PROTOCOL_FCOE, 663fe56b9e6SYuval Mintz }; 664fe56b9e6SYuval Mintz 665054c67d1SSudarsana Reddy Kalluru enum qed_link_mode_bits { 666054c67d1SSudarsana Reddy Kalluru QED_LM_FIBRE_BIT = BIT(0), 667054c67d1SSudarsana Reddy Kalluru QED_LM_Autoneg_BIT = BIT(1), 668054c67d1SSudarsana Reddy Kalluru QED_LM_Asym_Pause_BIT = BIT(2), 669054c67d1SSudarsana Reddy Kalluru QED_LM_Pause_BIT = BIT(3), 670054c67d1SSudarsana Reddy Kalluru QED_LM_1000baseT_Half_BIT = BIT(4), 671054c67d1SSudarsana Reddy Kalluru QED_LM_1000baseT_Full_BIT = BIT(5), 672054c67d1SSudarsana Reddy Kalluru QED_LM_10000baseKR_Full_BIT = BIT(6), 673054c67d1SSudarsana Reddy Kalluru QED_LM_25000baseKR_Full_BIT = BIT(7), 674054c67d1SSudarsana Reddy Kalluru QED_LM_40000baseLR4_Full_BIT = BIT(8), 675054c67d1SSudarsana Reddy Kalluru QED_LM_50000baseKR2_Full_BIT = BIT(9), 676054c67d1SSudarsana Reddy Kalluru QED_LM_100000baseKR4_Full_BIT = BIT(10), 677054c67d1SSudarsana Reddy Kalluru QED_LM_COUNT = 11 678054c67d1SSudarsana Reddy Kalluru }; 679054c67d1SSudarsana Reddy Kalluru 680fe56b9e6SYuval Mintz struct qed_link_params { 681fe56b9e6SYuval Mintz bool link_up; 682fe56b9e6SYuval Mintz 683fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0) 684fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1) 685fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2) 686fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3) 68703dc76caSSudarsana Reddy Kalluru #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4) 688645874e5SSudarsana Reddy Kalluru #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5) 689fe56b9e6SYuval Mintz u32 override_flags; 690fe56b9e6SYuval Mintz bool autoneg; 691fe56b9e6SYuval Mintz u32 adv_speeds; 692fe56b9e6SYuval Mintz u32 forced_speed; 693fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0) 694fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_RX_ENABLE BIT(1) 695fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_TX_ENABLE BIT(2) 696fe56b9e6SYuval Mintz u32 pause_config; 69703dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_NONE BIT(0) 69803dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_INT_PHY BIT(1) 69903dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_EXT_PHY BIT(2) 70003dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_EXT BIT(3) 70103dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_MAC BIT(4) 70203dc76caSSudarsana Reddy Kalluru u32 loopback_mode; 703645874e5SSudarsana Reddy Kalluru struct qed_link_eee_params eee; 704fe56b9e6SYuval Mintz }; 705fe56b9e6SYuval Mintz 706fe56b9e6SYuval Mintz struct qed_link_output { 707fe56b9e6SYuval Mintz bool link_up; 708fe56b9e6SYuval Mintz 709d194fd26SYuval Mintz /* In QED_LM_* defs */ 710d194fd26SYuval Mintz u32 supported_caps; 711d194fd26SYuval Mintz u32 advertised_caps; 712d194fd26SYuval Mintz u32 lp_caps; 713d194fd26SYuval Mintz 714fe56b9e6SYuval Mintz u32 speed; /* In Mb/s */ 715fe56b9e6SYuval Mintz u8 duplex; /* In DUPLEX defs */ 716fe56b9e6SYuval Mintz u8 port; /* In PORT defs */ 717fe56b9e6SYuval Mintz bool autoneg; 718fe56b9e6SYuval Mintz u32 pause_config; 719645874e5SSudarsana Reddy Kalluru 720645874e5SSudarsana Reddy Kalluru /* EEE - capability & param */ 721645874e5SSudarsana Reddy Kalluru bool eee_supported; 722645874e5SSudarsana Reddy Kalluru bool eee_active; 723645874e5SSudarsana Reddy Kalluru u8 sup_caps; 724645874e5SSudarsana Reddy Kalluru struct qed_link_eee_params eee; 725fe56b9e6SYuval Mintz }; 726fe56b9e6SYuval Mintz 7271408cc1fSYuval Mintz struct qed_probe_params { 7281408cc1fSYuval Mintz enum qed_protocol protocol; 7291408cc1fSYuval Mintz u32 dp_module; 7301408cc1fSYuval Mintz u8 dp_level; 7311408cc1fSYuval Mintz bool is_vf; 7321408cc1fSYuval Mintz }; 7331408cc1fSYuval Mintz 734fe56b9e6SYuval Mintz #define QED_DRV_VER_STR_SIZE 12 735fe56b9e6SYuval Mintz struct qed_slowpath_params { 736fe56b9e6SYuval Mintz u32 int_mode; 737fe56b9e6SYuval Mintz u8 drv_major; 738fe56b9e6SYuval Mintz u8 drv_minor; 739fe56b9e6SYuval Mintz u8 drv_rev; 740fe56b9e6SYuval Mintz u8 drv_eng; 741fe56b9e6SYuval Mintz u8 name[QED_DRV_VER_STR_SIZE]; 742fe56b9e6SYuval Mintz }; 743fe56b9e6SYuval Mintz 744fe56b9e6SYuval Mintz #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */ 745fe56b9e6SYuval Mintz 746fe56b9e6SYuval Mintz struct qed_int_info { 747fe56b9e6SYuval Mintz struct msix_entry *msix; 748fe56b9e6SYuval Mintz u8 msix_cnt; 749fe56b9e6SYuval Mintz 750fe56b9e6SYuval Mintz /* This should be updated by the protocol driver */ 751fe56b9e6SYuval Mintz u8 used_cnt; 752fe56b9e6SYuval Mintz }; 753fe56b9e6SYuval Mintz 75459ccf86fSSudarsana Reddy Kalluru struct qed_generic_tlvs { 75559ccf86fSSudarsana Reddy Kalluru #define QED_TLV_IP_CSUM BIT(0) 75659ccf86fSSudarsana Reddy Kalluru #define QED_TLV_LSO BIT(1) 75759ccf86fSSudarsana Reddy Kalluru u16 feat_flags; 75859ccf86fSSudarsana Reddy Kalluru #define QED_TLV_MAC_COUNT 3 75959ccf86fSSudarsana Reddy Kalluru u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN]; 76059ccf86fSSudarsana Reddy Kalluru }; 76159ccf86fSSudarsana Reddy Kalluru 7623a69cae8SSudarsana Reddy Kalluru #define QED_NVM_SIGNATURE 0x12435687 7633a69cae8SSudarsana Reddy Kalluru 7643a69cae8SSudarsana Reddy Kalluru enum qed_nvm_flash_cmd { 7653a69cae8SSudarsana Reddy Kalluru QED_NVM_FLASH_CMD_FILE_DATA = 0x2, 7663a69cae8SSudarsana Reddy Kalluru QED_NVM_FLASH_CMD_FILE_START = 0x3, 7673a69cae8SSudarsana Reddy Kalluru QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4, 7683a69cae8SSudarsana Reddy Kalluru QED_NVM_FLASH_CMD_NVM_MAX, 7693a69cae8SSudarsana Reddy Kalluru }; 7703a69cae8SSudarsana Reddy Kalluru 771fe56b9e6SYuval Mintz struct qed_common_cb_ops { 772d51e4af5SChopra, Manish void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc); 773fe56b9e6SYuval Mintz void (*link_update)(void *dev, 774fe56b9e6SYuval Mintz struct qed_link_output *link); 7751e128c81SArun Easi void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type); 77659ccf86fSSudarsana Reddy Kalluru void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data); 77759ccf86fSSudarsana Reddy Kalluru void (*get_protocol_tlv_data)(void *dev, void *data); 778fe56b9e6SYuval Mintz }; 779fe56b9e6SYuval Mintz 78003dc76caSSudarsana Reddy Kalluru struct qed_selftest_ops { 78103dc76caSSudarsana Reddy Kalluru /** 78203dc76caSSudarsana Reddy Kalluru * @brief selftest_interrupt - Perform interrupt test 78303dc76caSSudarsana Reddy Kalluru * 78403dc76caSSudarsana Reddy Kalluru * @param cdev 78503dc76caSSudarsana Reddy Kalluru * 78603dc76caSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 78703dc76caSSudarsana Reddy Kalluru */ 78803dc76caSSudarsana Reddy Kalluru int (*selftest_interrupt)(struct qed_dev *cdev); 78903dc76caSSudarsana Reddy Kalluru 79003dc76caSSudarsana Reddy Kalluru /** 79103dc76caSSudarsana Reddy Kalluru * @brief selftest_memory - Perform memory test 79203dc76caSSudarsana Reddy Kalluru * 79303dc76caSSudarsana Reddy Kalluru * @param cdev 79403dc76caSSudarsana Reddy Kalluru * 79503dc76caSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 79603dc76caSSudarsana Reddy Kalluru */ 79703dc76caSSudarsana Reddy Kalluru int (*selftest_memory)(struct qed_dev *cdev); 79803dc76caSSudarsana Reddy Kalluru 79903dc76caSSudarsana Reddy Kalluru /** 80003dc76caSSudarsana Reddy Kalluru * @brief selftest_register - Perform register test 80103dc76caSSudarsana Reddy Kalluru * 80203dc76caSSudarsana Reddy Kalluru * @param cdev 80303dc76caSSudarsana Reddy Kalluru * 80403dc76caSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 80503dc76caSSudarsana Reddy Kalluru */ 80603dc76caSSudarsana Reddy Kalluru int (*selftest_register)(struct qed_dev *cdev); 80703dc76caSSudarsana Reddy Kalluru 80803dc76caSSudarsana Reddy Kalluru /** 80903dc76caSSudarsana Reddy Kalluru * @brief selftest_clock - Perform clock test 81003dc76caSSudarsana Reddy Kalluru * 81103dc76caSSudarsana Reddy Kalluru * @param cdev 81203dc76caSSudarsana Reddy Kalluru * 81303dc76caSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 81403dc76caSSudarsana Reddy Kalluru */ 81503dc76caSSudarsana Reddy Kalluru int (*selftest_clock)(struct qed_dev *cdev); 8167a4b21b7SMintz, Yuval 8177a4b21b7SMintz, Yuval /** 8187a4b21b7SMintz, Yuval * @brief selftest_nvram - Perform nvram test 8197a4b21b7SMintz, Yuval * 8207a4b21b7SMintz, Yuval * @param cdev 8217a4b21b7SMintz, Yuval * 8227a4b21b7SMintz, Yuval * @return 0 on success, error otherwise. 8237a4b21b7SMintz, Yuval */ 8247a4b21b7SMintz, Yuval int (*selftest_nvram) (struct qed_dev *cdev); 82503dc76caSSudarsana Reddy Kalluru }; 82603dc76caSSudarsana Reddy Kalluru 827fe56b9e6SYuval Mintz struct qed_common_ops { 82803dc76caSSudarsana Reddy Kalluru struct qed_selftest_ops *selftest; 82903dc76caSSudarsana Reddy Kalluru 830fe56b9e6SYuval Mintz struct qed_dev* (*probe)(struct pci_dev *dev, 8311408cc1fSYuval Mintz struct qed_probe_params *params); 832fe56b9e6SYuval Mintz 833fe56b9e6SYuval Mintz void (*remove)(struct qed_dev *cdev); 834fe56b9e6SYuval Mintz 835fe56b9e6SYuval Mintz int (*set_power_state)(struct qed_dev *cdev, 836fe56b9e6SYuval Mintz pci_power_t state); 837fe56b9e6SYuval Mintz 838712c3cbfSMintz, Yuval void (*set_name) (struct qed_dev *cdev, char name[]); 839fe56b9e6SYuval Mintz 840fe56b9e6SYuval Mintz /* Client drivers need to make this call before slowpath_start. 841fe56b9e6SYuval Mintz * PF params required for the call before slowpath_start is 842fe56b9e6SYuval Mintz * documented within the qed_pf_params structure definition. 843fe56b9e6SYuval Mintz */ 844fe56b9e6SYuval Mintz void (*update_pf_params)(struct qed_dev *cdev, 845fe56b9e6SYuval Mintz struct qed_pf_params *params); 846fe56b9e6SYuval Mintz int (*slowpath_start)(struct qed_dev *cdev, 847fe56b9e6SYuval Mintz struct qed_slowpath_params *params); 848fe56b9e6SYuval Mintz 849fe56b9e6SYuval Mintz int (*slowpath_stop)(struct qed_dev *cdev); 850fe56b9e6SYuval Mintz 851fe56b9e6SYuval Mintz /* Requests to use `cnt' interrupts for fastpath. 852fe56b9e6SYuval Mintz * upon success, returns number of interrupts allocated for fastpath. 853fe56b9e6SYuval Mintz */ 854fe56b9e6SYuval Mintz int (*set_fp_int)(struct qed_dev *cdev, 855fe56b9e6SYuval Mintz u16 cnt); 856fe56b9e6SYuval Mintz 857fe56b9e6SYuval Mintz /* Fills `info' with pointers required for utilizing interrupts */ 858fe56b9e6SYuval Mintz int (*get_fp_int)(struct qed_dev *cdev, 859fe56b9e6SYuval Mintz struct qed_int_info *info); 860fe56b9e6SYuval Mintz 861fe56b9e6SYuval Mintz u32 (*sb_init)(struct qed_dev *cdev, 862fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 863fe56b9e6SYuval Mintz void *sb_virt_addr, 864fe56b9e6SYuval Mintz dma_addr_t sb_phy_addr, 865fe56b9e6SYuval Mintz u16 sb_id, 866fe56b9e6SYuval Mintz enum qed_sb_type type); 867fe56b9e6SYuval Mintz 868fe56b9e6SYuval Mintz u32 (*sb_release)(struct qed_dev *cdev, 869fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 870fe56b9e6SYuval Mintz u16 sb_id); 871fe56b9e6SYuval Mintz 872fe56b9e6SYuval Mintz void (*simd_handler_config)(struct qed_dev *cdev, 873fe56b9e6SYuval Mintz void *token, 874fe56b9e6SYuval Mintz int index, 875fe56b9e6SYuval Mintz void (*handler)(void *)); 876fe56b9e6SYuval Mintz 877fe56b9e6SYuval Mintz void (*simd_handler_clean)(struct qed_dev *cdev, 878fe56b9e6SYuval Mintz int index); 8791e128c81SArun Easi int (*dbg_grc)(struct qed_dev *cdev, 8801e128c81SArun Easi void *buffer, u32 *num_dumped_bytes); 8811e128c81SArun Easi 8821e128c81SArun Easi int (*dbg_grc_size)(struct qed_dev *cdev); 883fe7cd2bfSYuval Mintz 884e0971c83STomer Tayar int (*dbg_all_data) (struct qed_dev *cdev, void *buffer); 885e0971c83STomer Tayar 886e0971c83STomer Tayar int (*dbg_all_data_size) (struct qed_dev *cdev); 887e0971c83STomer Tayar 888fe7cd2bfSYuval Mintz /** 889fe7cd2bfSYuval Mintz * @brief can_link_change - can the instance change the link or not 890fe7cd2bfSYuval Mintz * 891fe7cd2bfSYuval Mintz * @param cdev 892fe7cd2bfSYuval Mintz * 893fe7cd2bfSYuval Mintz * @return true if link-change is allowed, false otherwise. 894fe7cd2bfSYuval Mintz */ 895fe7cd2bfSYuval Mintz bool (*can_link_change)(struct qed_dev *cdev); 896fe7cd2bfSYuval Mintz 897fe56b9e6SYuval Mintz /** 898fe56b9e6SYuval Mintz * @brief set_link - set links according to params 899fe56b9e6SYuval Mintz * 900fe56b9e6SYuval Mintz * @param cdev 901fe56b9e6SYuval Mintz * @param params - values used to override the default link configuration 902fe56b9e6SYuval Mintz * 903fe56b9e6SYuval Mintz * @return 0 on success, error otherwise. 904fe56b9e6SYuval Mintz */ 905fe56b9e6SYuval Mintz int (*set_link)(struct qed_dev *cdev, 906fe56b9e6SYuval Mintz struct qed_link_params *params); 907fe56b9e6SYuval Mintz 908fe56b9e6SYuval Mintz /** 909fe56b9e6SYuval Mintz * @brief get_link - returns the current link state. 910fe56b9e6SYuval Mintz * 911fe56b9e6SYuval Mintz * @param cdev 912fe56b9e6SYuval Mintz * @param if_link - structure to be filled with current link configuration. 913fe56b9e6SYuval Mintz */ 914fe56b9e6SYuval Mintz void (*get_link)(struct qed_dev *cdev, 915fe56b9e6SYuval Mintz struct qed_link_output *if_link); 916fe56b9e6SYuval Mintz 917fe56b9e6SYuval Mintz /** 918fe56b9e6SYuval Mintz * @brief - drains chip in case Tx completions fail to arrive due to pause. 919fe56b9e6SYuval Mintz * 920fe56b9e6SYuval Mintz * @param cdev 921fe56b9e6SYuval Mintz */ 922fe56b9e6SYuval Mintz int (*drain)(struct qed_dev *cdev); 923fe56b9e6SYuval Mintz 924fe56b9e6SYuval Mintz /** 925fe56b9e6SYuval Mintz * @brief update_msglvl - update module debug level 926fe56b9e6SYuval Mintz * 927fe56b9e6SYuval Mintz * @param cdev 928fe56b9e6SYuval Mintz * @param dp_module 929fe56b9e6SYuval Mintz * @param dp_level 930fe56b9e6SYuval Mintz */ 931fe56b9e6SYuval Mintz void (*update_msglvl)(struct qed_dev *cdev, 932fe56b9e6SYuval Mintz u32 dp_module, 933fe56b9e6SYuval Mintz u8 dp_level); 934fe56b9e6SYuval Mintz 935fe56b9e6SYuval Mintz int (*chain_alloc)(struct qed_dev *cdev, 936fe56b9e6SYuval Mintz enum qed_chain_use_mode intended_use, 937fe56b9e6SYuval Mintz enum qed_chain_mode mode, 938a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 939a91eb52aSYuval Mintz u32 num_elems, 940fe56b9e6SYuval Mintz size_t elem_size, 9411a4a6975SMintz, Yuval struct qed_chain *p_chain, 9421a4a6975SMintz, Yuval struct qed_chain_ext_pbl *ext_pbl); 943fe56b9e6SYuval Mintz 944fe56b9e6SYuval Mintz void (*chain_free)(struct qed_dev *cdev, 945fe56b9e6SYuval Mintz struct qed_chain *p_chain); 94691420b83SSudarsana Kalluru 94791420b83SSudarsana Kalluru /** 9483a69cae8SSudarsana Reddy Kalluru * @brief nvm_flash - Flash nvm data. 9493a69cae8SSudarsana Reddy Kalluru * 9503a69cae8SSudarsana Reddy Kalluru * @param cdev 9513a69cae8SSudarsana Reddy Kalluru * @param name - file containing the data 9523a69cae8SSudarsana Reddy Kalluru * 9533a69cae8SSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 9543a69cae8SSudarsana Reddy Kalluru */ 9553a69cae8SSudarsana Reddy Kalluru int (*nvm_flash)(struct qed_dev *cdev, const char *name); 9563a69cae8SSudarsana Reddy Kalluru 9573a69cae8SSudarsana Reddy Kalluru /** 95820675b37SMintz, Yuval * @brief nvm_get_image - reads an entire image from nvram 95920675b37SMintz, Yuval * 96020675b37SMintz, Yuval * @param cdev 96120675b37SMintz, Yuval * @param type - type of the request nvram image 96220675b37SMintz, Yuval * @param buf - preallocated buffer to fill with the image 96320675b37SMintz, Yuval * @param len - length of the allocated buffer 96420675b37SMintz, Yuval * 96520675b37SMintz, Yuval * @return 0 on success, error otherwise 96620675b37SMintz, Yuval */ 96720675b37SMintz, Yuval int (*nvm_get_image)(struct qed_dev *cdev, 96820675b37SMintz, Yuval enum qed_nvm_images type, u8 *buf, u16 len); 96920675b37SMintz, Yuval 97020675b37SMintz, Yuval /** 971722003acSSudarsana Reddy Kalluru * @brief set_coalesce - Configure Rx coalesce value in usec 972722003acSSudarsana Reddy Kalluru * 973722003acSSudarsana Reddy Kalluru * @param cdev 974722003acSSudarsana Reddy Kalluru * @param rx_coal - Rx coalesce value in usec 975722003acSSudarsana Reddy Kalluru * @param tx_coal - Tx coalesce value in usec 976722003acSSudarsana Reddy Kalluru * @param qid - Queue index 977722003acSSudarsana Reddy Kalluru * @param sb_id - Status Block Id 978722003acSSudarsana Reddy Kalluru * 979722003acSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 980722003acSSudarsana Reddy Kalluru */ 981477f2d14SRahul Verma int (*set_coalesce)(struct qed_dev *cdev, 982477f2d14SRahul Verma u16 rx_coal, u16 tx_coal, void *handle); 983722003acSSudarsana Reddy Kalluru 984722003acSSudarsana Reddy Kalluru /** 98591420b83SSudarsana Kalluru * @brief set_led - Configure LED mode 98691420b83SSudarsana Kalluru * 98791420b83SSudarsana Kalluru * @param cdev 98891420b83SSudarsana Kalluru * @param mode - LED mode 98991420b83SSudarsana Kalluru * 99091420b83SSudarsana Kalluru * @return 0 on success, error otherwise. 99191420b83SSudarsana Kalluru */ 99291420b83SSudarsana Kalluru int (*set_led)(struct qed_dev *cdev, 99391420b83SSudarsana Kalluru enum qed_led_mode mode); 9940fefbfbaSSudarsana Kalluru 9950fefbfbaSSudarsana Kalluru /** 9960fefbfbaSSudarsana Kalluru * @brief update_drv_state - API to inform the change in the driver state. 9970fefbfbaSSudarsana Kalluru * 9980fefbfbaSSudarsana Kalluru * @param cdev 9990fefbfbaSSudarsana Kalluru * @param active 10000fefbfbaSSudarsana Kalluru * 10010fefbfbaSSudarsana Kalluru */ 10020fefbfbaSSudarsana Kalluru int (*update_drv_state)(struct qed_dev *cdev, bool active); 10030fefbfbaSSudarsana Kalluru 10040fefbfbaSSudarsana Kalluru /** 10050fefbfbaSSudarsana Kalluru * @brief update_mac - API to inform the change in the mac address 10060fefbfbaSSudarsana Kalluru * 10070fefbfbaSSudarsana Kalluru * @param cdev 10080fefbfbaSSudarsana Kalluru * @param mac 10090fefbfbaSSudarsana Kalluru * 10100fefbfbaSSudarsana Kalluru */ 10110fefbfbaSSudarsana Kalluru int (*update_mac)(struct qed_dev *cdev, u8 *mac); 10120fefbfbaSSudarsana Kalluru 10130fefbfbaSSudarsana Kalluru /** 10140fefbfbaSSudarsana Kalluru * @brief update_mtu - API to inform the change in the mtu 10150fefbfbaSSudarsana Kalluru * 10160fefbfbaSSudarsana Kalluru * @param cdev 10170fefbfbaSSudarsana Kalluru * @param mtu 10180fefbfbaSSudarsana Kalluru * 10190fefbfbaSSudarsana Kalluru */ 10200fefbfbaSSudarsana Kalluru int (*update_mtu)(struct qed_dev *cdev, u16 mtu); 102114d39648SMintz, Yuval 102214d39648SMintz, Yuval /** 102314d39648SMintz, Yuval * @brief update_wol - update of changes in the WoL configuration 102414d39648SMintz, Yuval * 102514d39648SMintz, Yuval * @param cdev 102614d39648SMintz, Yuval * @param enabled - true iff WoL should be enabled. 102714d39648SMintz, Yuval */ 102814d39648SMintz, Yuval int (*update_wol) (struct qed_dev *cdev, bool enabled); 1029fe56b9e6SYuval Mintz }; 1030fe56b9e6SYuval Mintz 1031fe56b9e6SYuval Mintz #define MASK_FIELD(_name, _value) \ 1032fe56b9e6SYuval Mintz ((_value) &= (_name ## _MASK)) 1033fe56b9e6SYuval Mintz 1034fe56b9e6SYuval Mintz #define FIELD_VALUE(_name, _value) \ 1035fe56b9e6SYuval Mintz ((_value & _name ## _MASK) << _name ## _SHIFT) 1036fe56b9e6SYuval Mintz 1037fe56b9e6SYuval Mintz #define SET_FIELD(value, name, flag) \ 1038fe56b9e6SYuval Mintz do { \ 1039fe56b9e6SYuval Mintz (value) &= ~(name ## _MASK << name ## _SHIFT); \ 1040fe56b9e6SYuval Mintz (value) |= (((u64)flag) << (name ## _SHIFT)); \ 1041fe56b9e6SYuval Mintz } while (0) 1042fe56b9e6SYuval Mintz 1043fe56b9e6SYuval Mintz #define GET_FIELD(value, name) \ 1044fe56b9e6SYuval Mintz (((value) >> (name ## _SHIFT)) & name ## _MASK) 1045fe56b9e6SYuval Mintz 1046fe56b9e6SYuval Mintz /* Debug print definitions */ 1047fe56b9e6SYuval Mintz #define DP_ERR(cdev, fmt, ...) \ 10489d7650c2SMintz, Yuval do { \ 1049fe56b9e6SYuval Mintz pr_err("[%s:%d(%s)]" fmt, \ 1050fe56b9e6SYuval Mintz __func__, __LINE__, \ 1051fe56b9e6SYuval Mintz DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 10529d7650c2SMintz, Yuval ## __VA_ARGS__); \ 10539d7650c2SMintz, Yuval } while (0) 1054fe56b9e6SYuval Mintz 1055fe56b9e6SYuval Mintz #define DP_NOTICE(cdev, fmt, ...) \ 1056fe56b9e6SYuval Mintz do { \ 1057fe56b9e6SYuval Mintz if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \ 1058fe56b9e6SYuval Mintz pr_notice("[%s:%d(%s)]" fmt, \ 1059fe56b9e6SYuval Mintz __func__, __LINE__, \ 1060fe56b9e6SYuval Mintz DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 1061fe56b9e6SYuval Mintz ## __VA_ARGS__); \ 1062fe56b9e6SYuval Mintz \ 1063fe56b9e6SYuval Mintz } \ 1064fe56b9e6SYuval Mintz } while (0) 1065fe56b9e6SYuval Mintz 1066fe56b9e6SYuval Mintz #define DP_INFO(cdev, fmt, ...) \ 1067fe56b9e6SYuval Mintz do { \ 1068fe56b9e6SYuval Mintz if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \ 1069fe56b9e6SYuval Mintz pr_notice("[%s:%d(%s)]" fmt, \ 1070fe56b9e6SYuval Mintz __func__, __LINE__, \ 1071fe56b9e6SYuval Mintz DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 1072fe56b9e6SYuval Mintz ## __VA_ARGS__); \ 1073fe56b9e6SYuval Mintz } \ 1074fe56b9e6SYuval Mintz } while (0) 1075fe56b9e6SYuval Mintz 1076fe56b9e6SYuval Mintz #define DP_VERBOSE(cdev, module, fmt, ...) \ 1077fe56b9e6SYuval Mintz do { \ 1078fe56b9e6SYuval Mintz if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \ 1079fe56b9e6SYuval Mintz ((cdev)->dp_module & module))) { \ 1080fe56b9e6SYuval Mintz pr_notice("[%s:%d(%s)]" fmt, \ 1081fe56b9e6SYuval Mintz __func__, __LINE__, \ 1082fe56b9e6SYuval Mintz DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 1083fe56b9e6SYuval Mintz ## __VA_ARGS__); \ 1084fe56b9e6SYuval Mintz } \ 1085fe56b9e6SYuval Mintz } while (0) 1086fe56b9e6SYuval Mintz 1087fe56b9e6SYuval Mintz enum DP_LEVEL { 1088fe56b9e6SYuval Mintz QED_LEVEL_VERBOSE = 0x0, 1089fe56b9e6SYuval Mintz QED_LEVEL_INFO = 0x1, 1090fe56b9e6SYuval Mintz QED_LEVEL_NOTICE = 0x2, 1091fe56b9e6SYuval Mintz QED_LEVEL_ERR = 0x3, 1092fe56b9e6SYuval Mintz }; 1093fe56b9e6SYuval Mintz 1094fe56b9e6SYuval Mintz #define QED_LOG_LEVEL_SHIFT (30) 1095fe56b9e6SYuval Mintz #define QED_LOG_VERBOSE_MASK (0x3fffffff) 1096fe56b9e6SYuval Mintz #define QED_LOG_INFO_MASK (0x40000000) 1097fe56b9e6SYuval Mintz #define QED_LOG_NOTICE_MASK (0x80000000) 1098fe56b9e6SYuval Mintz 1099fe56b9e6SYuval Mintz enum DP_MODULE { 1100fe56b9e6SYuval Mintz QED_MSG_SPQ = 0x10000, 1101fe56b9e6SYuval Mintz QED_MSG_STATS = 0x20000, 1102fe56b9e6SYuval Mintz QED_MSG_DCB = 0x40000, 1103fe56b9e6SYuval Mintz QED_MSG_IOV = 0x80000, 1104fe56b9e6SYuval Mintz QED_MSG_SP = 0x100000, 1105fe56b9e6SYuval Mintz QED_MSG_STORAGE = 0x200000, 1106fe56b9e6SYuval Mintz QED_MSG_CXT = 0x800000, 11070a7fb11cSYuval Mintz QED_MSG_LL2 = 0x1000000, 1108fe56b9e6SYuval Mintz QED_MSG_ILT = 0x2000000, 110951ff1725SRam Amrani QED_MSG_RDMA = 0x4000000, 1110fe56b9e6SYuval Mintz QED_MSG_DEBUG = 0x8000000, 1111fe56b9e6SYuval Mintz /* to be added...up to 0x8000000 */ 1112fe56b9e6SYuval Mintz }; 1113fe56b9e6SYuval Mintz 1114fc48b7a6SYuval Mintz enum qed_mf_mode { 1115fc48b7a6SYuval Mintz QED_MF_DEFAULT, 1116fc48b7a6SYuval Mintz QED_MF_OVLAN, 1117fc48b7a6SYuval Mintz QED_MF_NPAR, 1118fc48b7a6SYuval Mintz }; 1119fc48b7a6SYuval Mintz 11209c79ddaaSMintz, Yuval struct qed_eth_stats_common { 1121fe56b9e6SYuval Mintz u64 no_buff_discards; 1122fe56b9e6SYuval Mintz u64 packet_too_big_discard; 1123fe56b9e6SYuval Mintz u64 ttl0_discard; 1124fe56b9e6SYuval Mintz u64 rx_ucast_bytes; 1125fe56b9e6SYuval Mintz u64 rx_mcast_bytes; 1126fe56b9e6SYuval Mintz u64 rx_bcast_bytes; 1127fe56b9e6SYuval Mintz u64 rx_ucast_pkts; 1128fe56b9e6SYuval Mintz u64 rx_mcast_pkts; 1129fe56b9e6SYuval Mintz u64 rx_bcast_pkts; 1130fe56b9e6SYuval Mintz u64 mftag_filter_discards; 1131fe56b9e6SYuval Mintz u64 mac_filter_discards; 1132608e00d0SManish Chopra u64 gft_filter_drop; 1133fe56b9e6SYuval Mintz u64 tx_ucast_bytes; 1134fe56b9e6SYuval Mintz u64 tx_mcast_bytes; 1135fe56b9e6SYuval Mintz u64 tx_bcast_bytes; 1136fe56b9e6SYuval Mintz u64 tx_ucast_pkts; 1137fe56b9e6SYuval Mintz u64 tx_mcast_pkts; 1138fe56b9e6SYuval Mintz u64 tx_bcast_pkts; 1139fe56b9e6SYuval Mintz u64 tx_err_drop_pkts; 1140fe56b9e6SYuval Mintz u64 tpa_coalesced_pkts; 1141fe56b9e6SYuval Mintz u64 tpa_coalesced_events; 1142fe56b9e6SYuval Mintz u64 tpa_aborts_num; 1143fe56b9e6SYuval Mintz u64 tpa_not_coalesced_pkts; 1144fe56b9e6SYuval Mintz u64 tpa_coalesced_bytes; 1145fe56b9e6SYuval Mintz 1146fe56b9e6SYuval Mintz /* port */ 1147fe56b9e6SYuval Mintz u64 rx_64_byte_packets; 1148d4967cf3SYuval Mintz u64 rx_65_to_127_byte_packets; 1149d4967cf3SYuval Mintz u64 rx_128_to_255_byte_packets; 1150d4967cf3SYuval Mintz u64 rx_256_to_511_byte_packets; 1151d4967cf3SYuval Mintz u64 rx_512_to_1023_byte_packets; 1152d4967cf3SYuval Mintz u64 rx_1024_to_1518_byte_packets; 1153fe56b9e6SYuval Mintz u64 rx_crc_errors; 1154fe56b9e6SYuval Mintz u64 rx_mac_crtl_frames; 1155fe56b9e6SYuval Mintz u64 rx_pause_frames; 1156fe56b9e6SYuval Mintz u64 rx_pfc_frames; 1157fe56b9e6SYuval Mintz u64 rx_align_errors; 1158fe56b9e6SYuval Mintz u64 rx_carrier_errors; 1159fe56b9e6SYuval Mintz u64 rx_oversize_packets; 1160fe56b9e6SYuval Mintz u64 rx_jabbers; 1161fe56b9e6SYuval Mintz u64 rx_undersize_packets; 1162fe56b9e6SYuval Mintz u64 rx_fragments; 1163fe56b9e6SYuval Mintz u64 tx_64_byte_packets; 1164fe56b9e6SYuval Mintz u64 tx_65_to_127_byte_packets; 1165fe56b9e6SYuval Mintz u64 tx_128_to_255_byte_packets; 1166fe56b9e6SYuval Mintz u64 tx_256_to_511_byte_packets; 1167fe56b9e6SYuval Mintz u64 tx_512_to_1023_byte_packets; 1168fe56b9e6SYuval Mintz u64 tx_1024_to_1518_byte_packets; 1169fe56b9e6SYuval Mintz u64 tx_pause_frames; 1170fe56b9e6SYuval Mintz u64 tx_pfc_frames; 1171fe56b9e6SYuval Mintz u64 brb_truncates; 1172fe56b9e6SYuval Mintz u64 brb_discards; 1173fe56b9e6SYuval Mintz u64 rx_mac_bytes; 1174fe56b9e6SYuval Mintz u64 rx_mac_uc_packets; 1175fe56b9e6SYuval Mintz u64 rx_mac_mc_packets; 1176fe56b9e6SYuval Mintz u64 rx_mac_bc_packets; 1177fe56b9e6SYuval Mintz u64 rx_mac_frames_ok; 1178fe56b9e6SYuval Mintz u64 tx_mac_bytes; 1179fe56b9e6SYuval Mintz u64 tx_mac_uc_packets; 1180fe56b9e6SYuval Mintz u64 tx_mac_mc_packets; 1181fe56b9e6SYuval Mintz u64 tx_mac_bc_packets; 1182fe56b9e6SYuval Mintz u64 tx_mac_ctrl_frames; 1183*32d26a68SSudarsana Reddy Kalluru u64 link_change_count; 1184fe56b9e6SYuval Mintz }; 1185fe56b9e6SYuval Mintz 11869c79ddaaSMintz, Yuval struct qed_eth_stats_bb { 11879c79ddaaSMintz, Yuval u64 rx_1519_to_1522_byte_packets; 11889c79ddaaSMintz, Yuval u64 rx_1519_to_2047_byte_packets; 11899c79ddaaSMintz, Yuval u64 rx_2048_to_4095_byte_packets; 11909c79ddaaSMintz, Yuval u64 rx_4096_to_9216_byte_packets; 11919c79ddaaSMintz, Yuval u64 rx_9217_to_16383_byte_packets; 11929c79ddaaSMintz, Yuval u64 tx_1519_to_2047_byte_packets; 11939c79ddaaSMintz, Yuval u64 tx_2048_to_4095_byte_packets; 11949c79ddaaSMintz, Yuval u64 tx_4096_to_9216_byte_packets; 11959c79ddaaSMintz, Yuval u64 tx_9217_to_16383_byte_packets; 11969c79ddaaSMintz, Yuval u64 tx_lpi_entry_count; 11979c79ddaaSMintz, Yuval u64 tx_total_collisions; 11989c79ddaaSMintz, Yuval }; 11999c79ddaaSMintz, Yuval 12009c79ddaaSMintz, Yuval struct qed_eth_stats_ah { 12019c79ddaaSMintz, Yuval u64 rx_1519_to_max_byte_packets; 12029c79ddaaSMintz, Yuval u64 tx_1519_to_max_byte_packets; 12039c79ddaaSMintz, Yuval }; 12049c79ddaaSMintz, Yuval 12059c79ddaaSMintz, Yuval struct qed_eth_stats { 12069c79ddaaSMintz, Yuval struct qed_eth_stats_common common; 12079c79ddaaSMintz, Yuval 12089c79ddaaSMintz, Yuval union { 12099c79ddaaSMintz, Yuval struct qed_eth_stats_bb bb; 12109c79ddaaSMintz, Yuval struct qed_eth_stats_ah ah; 12119c79ddaaSMintz, Yuval }; 12129c79ddaaSMintz, Yuval }; 12139c79ddaaSMintz, Yuval 1214fe56b9e6SYuval Mintz #define QED_SB_IDX 0x0002 1215fe56b9e6SYuval Mintz 1216fe56b9e6SYuval Mintz #define RX_PI 0 1217fe56b9e6SYuval Mintz #define TX_PI(tc) (RX_PI + 1 + tc) 1218fe56b9e6SYuval Mintz 12194ac801b7SYuval Mintz struct qed_sb_cnt_info { 1220726fdbe9SMintz, Yuval /* Original, current, and free SBs for PF */ 1221726fdbe9SMintz, Yuval int orig; 1222726fdbe9SMintz, Yuval int cnt; 1223726fdbe9SMintz, Yuval int free_cnt; 1224726fdbe9SMintz, Yuval 1225726fdbe9SMintz, Yuval /* Original, current and free SBS for child VFs */ 1226726fdbe9SMintz, Yuval int iov_orig; 1227726fdbe9SMintz, Yuval int iov_cnt; 1228726fdbe9SMintz, Yuval int free_cnt_iov; 12294ac801b7SYuval Mintz }; 12304ac801b7SYuval Mintz 1231fe56b9e6SYuval Mintz static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info) 1232fe56b9e6SYuval Mintz { 1233fe56b9e6SYuval Mintz u32 prod = 0; 1234fe56b9e6SYuval Mintz u16 rc = 0; 1235fe56b9e6SYuval Mintz 1236fe56b9e6SYuval Mintz prod = le32_to_cpu(sb_info->sb_virt->prod_index) & 123721dd79e8STomer Tayar STATUS_BLOCK_E4_PROD_INDEX_MASK; 1238fe56b9e6SYuval Mintz if (sb_info->sb_ack != prod) { 1239fe56b9e6SYuval Mintz sb_info->sb_ack = prod; 1240fe56b9e6SYuval Mintz rc |= QED_SB_IDX; 1241fe56b9e6SYuval Mintz } 1242fe56b9e6SYuval Mintz 1243fe56b9e6SYuval Mintz /* Let SB update */ 1244fe56b9e6SYuval Mintz mmiowb(); 1245fe56b9e6SYuval Mintz return rc; 1246fe56b9e6SYuval Mintz } 1247fe56b9e6SYuval Mintz 1248fe56b9e6SYuval Mintz /** 1249fe56b9e6SYuval Mintz * 1250fe56b9e6SYuval Mintz * @brief This function creates an update command for interrupts that is 1251fe56b9e6SYuval Mintz * written to the IGU. 1252fe56b9e6SYuval Mintz * 1253fe56b9e6SYuval Mintz * @param sb_info - This is the structure allocated and 1254fe56b9e6SYuval Mintz * initialized per status block. Assumption is 1255fe56b9e6SYuval Mintz * that it was initialized using qed_sb_init 1256fe56b9e6SYuval Mintz * @param int_cmd - Enable/Disable/Nop 1257fe56b9e6SYuval Mintz * @param upd_flg - whether igu consumer should be 1258fe56b9e6SYuval Mintz * updated. 1259fe56b9e6SYuval Mintz * 1260fe56b9e6SYuval Mintz * @return inline void 1261fe56b9e6SYuval Mintz */ 1262fe56b9e6SYuval Mintz static inline void qed_sb_ack(struct qed_sb_info *sb_info, 1263fe56b9e6SYuval Mintz enum igu_int_cmd int_cmd, 1264fe56b9e6SYuval Mintz u8 upd_flg) 1265fe56b9e6SYuval Mintz { 1266fe56b9e6SYuval Mintz struct igu_prod_cons_update igu_ack = { 0 }; 1267fe56b9e6SYuval Mintz 1268fe56b9e6SYuval Mintz igu_ack.sb_id_and_flags = 1269fe56b9e6SYuval Mintz ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 1270fe56b9e6SYuval Mintz (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 1271fe56b9e6SYuval Mintz (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 1272fe56b9e6SYuval Mintz (IGU_SEG_ACCESS_REG << 1273fe56b9e6SYuval Mintz IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 1274fe56b9e6SYuval Mintz 1275fe56b9e6SYuval Mintz DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags); 1276fe56b9e6SYuval Mintz 1277fe56b9e6SYuval Mintz /* Both segments (interrupts & acks) are written to same place address; 1278fe56b9e6SYuval Mintz * Need to guarantee all commands will be received (in-order) by HW. 1279fe56b9e6SYuval Mintz */ 1280fe56b9e6SYuval Mintz mmiowb(); 1281fe56b9e6SYuval Mintz barrier(); 1282fe56b9e6SYuval Mintz } 1283fe56b9e6SYuval Mintz 1284fe56b9e6SYuval Mintz static inline void __internal_ram_wr(void *p_hwfn, 1285fe56b9e6SYuval Mintz void __iomem *addr, 1286fe56b9e6SYuval Mintz int size, 1287fe56b9e6SYuval Mintz u32 *data) 1288fe56b9e6SYuval Mintz 1289fe56b9e6SYuval Mintz { 1290fe56b9e6SYuval Mintz unsigned int i; 1291fe56b9e6SYuval Mintz 1292fe56b9e6SYuval Mintz for (i = 0; i < size / sizeof(*data); i++) 1293fe56b9e6SYuval Mintz DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]); 1294fe56b9e6SYuval Mintz } 1295fe56b9e6SYuval Mintz 1296fe56b9e6SYuval Mintz static inline void internal_ram_wr(void __iomem *addr, 1297fe56b9e6SYuval Mintz int size, 1298fe56b9e6SYuval Mintz u32 *data) 1299fe56b9e6SYuval Mintz { 1300fe56b9e6SYuval Mintz __internal_ram_wr(NULL, addr, size, data); 1301fe56b9e6SYuval Mintz } 1302fe56b9e6SYuval Mintz 13038c5ebd0cSSudarsana Reddy Kalluru enum qed_rss_caps { 13048c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV4 = 0x1, 13058c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV6 = 0x2, 13068c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV4_TCP = 0x4, 13078c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV6_TCP = 0x8, 13088c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV4_UDP = 0x10, 13098c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV6_UDP = 0x20, 13108c5ebd0cSSudarsana Reddy Kalluru }; 13118c5ebd0cSSudarsana Reddy Kalluru 13128c5ebd0cSSudarsana Reddy Kalluru #define QED_RSS_IND_TABLE_SIZE 128 13138c5ebd0cSSudarsana Reddy Kalluru #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */ 1314fe56b9e6SYuval Mintz #endif 1315