1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9fe56b9e6SYuval Mintz * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #ifndef _QED_IF_H 34fe56b9e6SYuval Mintz #define _QED_IF_H 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz #include <linux/types.h> 37fe56b9e6SYuval Mintz #include <linux/interrupt.h> 38fe56b9e6SYuval Mintz #include <linux/netdevice.h> 39fe56b9e6SYuval Mintz #include <linux/pci.h> 40fe56b9e6SYuval Mintz #include <linux/skbuff.h> 41fe56b9e6SYuval Mintz #include <linux/types.h> 42fe56b9e6SYuval Mintz #include <asm/byteorder.h> 43fe56b9e6SYuval Mintz #include <linux/io.h> 44fe56b9e6SYuval Mintz #include <linux/compiler.h> 45fe56b9e6SYuval Mintz #include <linux/kernel.h> 46fe56b9e6SYuval Mintz #include <linux/list.h> 47fe56b9e6SYuval Mintz #include <linux/slab.h> 48fe56b9e6SYuval Mintz #include <linux/qed/common_hsi.h> 49fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 50fe56b9e6SYuval Mintz 5139651abdSSudarsana Reddy Kalluru enum dcbx_protocol_type { 5239651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_ISCSI, 5339651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_FCOE, 5439651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_ROCE, 5539651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_ROCE_V2, 5639651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_ETH, 5739651abdSSudarsana Reddy Kalluru DCBX_MAX_PROTOCOL_TYPE 5839651abdSSudarsana Reddy Kalluru }; 5939651abdSSudarsana Reddy Kalluru 6051ff1725SRam Amrani #define QED_ROCE_PROTOCOL_INDEX (3) 6151ff1725SRam Amrani 626ad8c632SSudarsana Reddy Kalluru #define QED_LLDP_CHASSIS_ID_STAT_LEN 4 636ad8c632SSudarsana Reddy Kalluru #define QED_LLDP_PORT_ID_STAT_LEN 4 646ad8c632SSudarsana Reddy Kalluru #define QED_DCBX_MAX_APP_PROTOCOL 32 656ad8c632SSudarsana Reddy Kalluru #define QED_MAX_PFC_PRIORITIES 8 666ad8c632SSudarsana Reddy Kalluru #define QED_DCBX_DSCP_SIZE 64 676ad8c632SSudarsana Reddy Kalluru 686ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_remote { 696ad8c632SSudarsana Reddy Kalluru u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 706ad8c632SSudarsana Reddy Kalluru u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 716ad8c632SSudarsana Reddy Kalluru bool enable_rx; 726ad8c632SSudarsana Reddy Kalluru bool enable_tx; 736ad8c632SSudarsana Reddy Kalluru u32 tx_interval; 746ad8c632SSudarsana Reddy Kalluru u32 max_credit; 756ad8c632SSudarsana Reddy Kalluru }; 766ad8c632SSudarsana Reddy Kalluru 776ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_local { 786ad8c632SSudarsana Reddy Kalluru u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 796ad8c632SSudarsana Reddy Kalluru u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 806ad8c632SSudarsana Reddy Kalluru }; 816ad8c632SSudarsana Reddy Kalluru 826ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_app_prio { 836ad8c632SSudarsana Reddy Kalluru u8 roce; 846ad8c632SSudarsana Reddy Kalluru u8 roce_v2; 856ad8c632SSudarsana Reddy Kalluru u8 fcoe; 866ad8c632SSudarsana Reddy Kalluru u8 iscsi; 876ad8c632SSudarsana Reddy Kalluru u8 eth; 886ad8c632SSudarsana Reddy Kalluru }; 896ad8c632SSudarsana Reddy Kalluru 906ad8c632SSudarsana Reddy Kalluru struct qed_dbcx_pfc_params { 916ad8c632SSudarsana Reddy Kalluru bool willing; 926ad8c632SSudarsana Reddy Kalluru bool enabled; 936ad8c632SSudarsana Reddy Kalluru u8 prio[QED_MAX_PFC_PRIORITIES]; 946ad8c632SSudarsana Reddy Kalluru u8 max_tc; 956ad8c632SSudarsana Reddy Kalluru }; 966ad8c632SSudarsana Reddy Kalluru 9759bcb797SSudarsana Reddy Kalluru enum qed_dcbx_sf_ieee_type { 9859bcb797SSudarsana Reddy Kalluru QED_DCBX_SF_IEEE_ETHTYPE, 9959bcb797SSudarsana Reddy Kalluru QED_DCBX_SF_IEEE_TCP_PORT, 10059bcb797SSudarsana Reddy Kalluru QED_DCBX_SF_IEEE_UDP_PORT, 10159bcb797SSudarsana Reddy Kalluru QED_DCBX_SF_IEEE_TCP_UDP_PORT 10259bcb797SSudarsana Reddy Kalluru }; 10359bcb797SSudarsana Reddy Kalluru 1046ad8c632SSudarsana Reddy Kalluru struct qed_app_entry { 1056ad8c632SSudarsana Reddy Kalluru bool ethtype; 10659bcb797SSudarsana Reddy Kalluru enum qed_dcbx_sf_ieee_type sf_ieee; 1076ad8c632SSudarsana Reddy Kalluru bool enabled; 1086ad8c632SSudarsana Reddy Kalluru u8 prio; 1096ad8c632SSudarsana Reddy Kalluru u16 proto_id; 1106ad8c632SSudarsana Reddy Kalluru enum dcbx_protocol_type proto_type; 1116ad8c632SSudarsana Reddy Kalluru }; 1126ad8c632SSudarsana Reddy Kalluru 1136ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params { 1146ad8c632SSudarsana Reddy Kalluru struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL]; 1156ad8c632SSudarsana Reddy Kalluru u16 num_app_entries; 1166ad8c632SSudarsana Reddy Kalluru bool app_willing; 1176ad8c632SSudarsana Reddy Kalluru bool app_valid; 1186ad8c632SSudarsana Reddy Kalluru bool app_error; 1196ad8c632SSudarsana Reddy Kalluru bool ets_willing; 1206ad8c632SSudarsana Reddy Kalluru bool ets_enabled; 1216ad8c632SSudarsana Reddy Kalluru bool ets_cbs; 1226ad8c632SSudarsana Reddy Kalluru bool valid; 1236ad8c632SSudarsana Reddy Kalluru u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES]; 1246ad8c632SSudarsana Reddy Kalluru u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES]; 1256ad8c632SSudarsana Reddy Kalluru u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES]; 1266ad8c632SSudarsana Reddy Kalluru struct qed_dbcx_pfc_params pfc; 1276ad8c632SSudarsana Reddy Kalluru u8 max_ets_tc; 1286ad8c632SSudarsana Reddy Kalluru }; 1296ad8c632SSudarsana Reddy Kalluru 1306ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_admin_params { 1316ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params params; 1326ad8c632SSudarsana Reddy Kalluru bool valid; 1336ad8c632SSudarsana Reddy Kalluru }; 1346ad8c632SSudarsana Reddy Kalluru 1356ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_remote_params { 1366ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params params; 1376ad8c632SSudarsana Reddy Kalluru bool valid; 1386ad8c632SSudarsana Reddy Kalluru }; 1396ad8c632SSudarsana Reddy Kalluru 1406ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_operational_params { 1416ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_app_prio app_prio; 1426ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params params; 1436ad8c632SSudarsana Reddy Kalluru bool valid; 1446ad8c632SSudarsana Reddy Kalluru bool enabled; 1456ad8c632SSudarsana Reddy Kalluru bool ieee; 1466ad8c632SSudarsana Reddy Kalluru bool cee; 14749632b58Ssudarsana.kalluru@cavium.com bool local; 1486ad8c632SSudarsana Reddy Kalluru u32 err; 1496ad8c632SSudarsana Reddy Kalluru }; 1506ad8c632SSudarsana Reddy Kalluru 1516ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_get { 1526ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_operational_params operational; 1536ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_remote lldp_remote; 1546ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_local lldp_local; 1556ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_remote_params remote; 1566ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_admin_params local; 1576ad8c632SSudarsana Reddy Kalluru }; 1586ad8c632SSudarsana Reddy Kalluru 15920675b37SMintz, Yuval enum qed_nvm_images { 16020675b37SMintz, Yuval QED_NVM_IMAGE_ISCSI_CFG, 16120675b37SMintz, Yuval QED_NVM_IMAGE_FCOE_CFG, 16220675b37SMintz, Yuval }; 16320675b37SMintz, Yuval 16491420b83SSudarsana Kalluru enum qed_led_mode { 16591420b83SSudarsana Kalluru QED_LED_MODE_OFF, 16691420b83SSudarsana Kalluru QED_LED_MODE_ON, 16791420b83SSudarsana Kalluru QED_LED_MODE_RESTORE 16891420b83SSudarsana Kalluru }; 16991420b83SSudarsana Kalluru 170fe56b9e6SYuval Mintz #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \ 171fe56b9e6SYuval Mintz (void __iomem *)(reg_addr)) 172fe56b9e6SYuval Mintz 173fe56b9e6SYuval Mintz #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr)) 174fe56b9e6SYuval Mintz 175fe56b9e6SYuval Mintz #define QED_COALESCE_MAX 0xFF 1760e191827SSudarsana Reddy Kalluru #define QED_DEFAULT_RX_USECS 12 177fe56b9e6SYuval Mintz 178fe56b9e6SYuval Mintz /* forward */ 179fe56b9e6SYuval Mintz struct qed_dev; 180fe56b9e6SYuval Mintz 181fe56b9e6SYuval Mintz struct qed_eth_pf_params { 182fe56b9e6SYuval Mintz /* The following parameters are used during HW-init 183fe56b9e6SYuval Mintz * and these parameters need to be passed as arguments 184fe56b9e6SYuval Mintz * to update_pf_params routine invoked before slowpath start 185fe56b9e6SYuval Mintz */ 186fe56b9e6SYuval Mintz u16 num_cons; 187d51e4af5SChopra, Manish 188*08bc8f15SMintz, Yuval /* per-VF number of CIDs */ 189*08bc8f15SMintz, Yuval u8 num_vf_cons; 190*08bc8f15SMintz, Yuval #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32) 191*08bc8f15SMintz, Yuval 192d51e4af5SChopra, Manish /* To enable arfs, previous to HW-init a positive number needs to be 193d51e4af5SChopra, Manish * set [as filters require allocated searcher ILT memory]. 194d51e4af5SChopra, Manish * This will set the maximal number of configured steering-filters. 195d51e4af5SChopra, Manish */ 196d51e4af5SChopra, Manish u32 num_arfs_filters; 197fe56b9e6SYuval Mintz }; 198fe56b9e6SYuval Mintz 1991e128c81SArun Easi struct qed_fcoe_pf_params { 2001e128c81SArun Easi /* The following parameters are used during protocol-init */ 2011e128c81SArun Easi u64 glbl_q_params_addr; 2021e128c81SArun Easi u64 bdq_pbl_base_addr[2]; 2031e128c81SArun Easi 2041e128c81SArun Easi /* The following parameters are used during HW-init 2051e128c81SArun Easi * and these parameters need to be passed as arguments 2061e128c81SArun Easi * to update_pf_params routine invoked before slowpath start 2071e128c81SArun Easi */ 2081e128c81SArun Easi u16 num_cons; 2091e128c81SArun Easi u16 num_tasks; 2101e128c81SArun Easi 2111e128c81SArun Easi /* The following parameters are used during protocol-init */ 2121e128c81SArun Easi u16 sq_num_pbl_pages; 2131e128c81SArun Easi 2141e128c81SArun Easi u16 cq_num_entries; 2151e128c81SArun Easi u16 cmdq_num_entries; 2161e128c81SArun Easi u16 rq_buffer_log_size; 2171e128c81SArun Easi u16 mtu; 2181e128c81SArun Easi u16 dummy_icid; 2191e128c81SArun Easi u16 bdq_xoff_threshold[2]; 2201e128c81SArun Easi u16 bdq_xon_threshold[2]; 2211e128c81SArun Easi u16 rq_buffer_size; 2221e128c81SArun Easi u8 num_cqs; /* num of global CQs */ 2231e128c81SArun Easi u8 log_page_size; 2241e128c81SArun Easi u8 gl_rq_pi; 2251e128c81SArun Easi u8 gl_cmd_pi; 2261e128c81SArun Easi u8 debug_mode; 2271e128c81SArun Easi u8 is_target; 2281e128c81SArun Easi u8 bdq_pbl_num_entries[2]; 2291e128c81SArun Easi }; 2301e128c81SArun Easi 231c5ac9319SYuval Mintz /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */ 232c5ac9319SYuval Mintz struct qed_iscsi_pf_params { 233c5ac9319SYuval Mintz u64 glbl_q_params_addr; 234c5ac9319SYuval Mintz u64 bdq_pbl_base_addr[2]; 235c5ac9319SYuval Mintz u32 max_cwnd; 236c5ac9319SYuval Mintz u16 cq_num_entries; 237c5ac9319SYuval Mintz u16 cmdq_num_entries; 238fc831825SYuval Mintz u32 two_msl_timer; 239c5ac9319SYuval Mintz u16 dup_ack_threshold; 240c5ac9319SYuval Mintz u16 tx_sws_timer; 241c5ac9319SYuval Mintz u16 min_rto; 242c5ac9319SYuval Mintz u16 min_rto_rt; 243c5ac9319SYuval Mintz u16 max_rto; 244c5ac9319SYuval Mintz 245c5ac9319SYuval Mintz /* The following parameters are used during HW-init 246c5ac9319SYuval Mintz * and these parameters need to be passed as arguments 247c5ac9319SYuval Mintz * to update_pf_params routine invoked before slowpath start 248c5ac9319SYuval Mintz */ 249c5ac9319SYuval Mintz u16 num_cons; 250c5ac9319SYuval Mintz u16 num_tasks; 251c5ac9319SYuval Mintz 252c5ac9319SYuval Mintz /* The following parameters are used during protocol-init */ 253c5ac9319SYuval Mintz u16 half_way_close_timeout; 254c5ac9319SYuval Mintz u16 bdq_xoff_threshold[2]; 255c5ac9319SYuval Mintz u16 bdq_xon_threshold[2]; 256c5ac9319SYuval Mintz u16 cmdq_xoff_threshold; 257c5ac9319SYuval Mintz u16 cmdq_xon_threshold; 258c5ac9319SYuval Mintz u16 rq_buffer_size; 259c5ac9319SYuval Mintz 260c5ac9319SYuval Mintz u8 num_sq_pages_in_ring; 261c5ac9319SYuval Mintz u8 num_r2tq_pages_in_ring; 262c5ac9319SYuval Mintz u8 num_uhq_pages_in_ring; 263c5ac9319SYuval Mintz u8 num_queues; 264c5ac9319SYuval Mintz u8 log_page_size; 265c5ac9319SYuval Mintz u8 rqe_log_size; 266c5ac9319SYuval Mintz u8 max_fin_rt; 267c5ac9319SYuval Mintz u8 gl_rq_pi; 268c5ac9319SYuval Mintz u8 gl_cmd_pi; 269c5ac9319SYuval Mintz u8 debug_mode; 270c5ac9319SYuval Mintz u8 ll2_ooo_queue_id; 271c5ac9319SYuval Mintz u8 ooo_enable; 272c5ac9319SYuval Mintz 273c5ac9319SYuval Mintz u8 is_target; 274c5ac9319SYuval Mintz u8 bdq_pbl_num_entries[2]; 275c5ac9319SYuval Mintz }; 276c5ac9319SYuval Mintz 277c5ac9319SYuval Mintz struct qed_rdma_pf_params { 278c5ac9319SYuval Mintz /* Supplied to QED during resource allocation (may affect the ILT and 279c5ac9319SYuval Mintz * the doorbell BAR). 280c5ac9319SYuval Mintz */ 281c5ac9319SYuval Mintz u32 min_dpis; /* number of requested DPIs */ 282c5ac9319SYuval Mintz u32 num_qps; /* number of requested Queue Pairs */ 283c5ac9319SYuval Mintz u32 num_srqs; /* number of requested SRQ */ 284c5ac9319SYuval Mintz u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */ 285c5ac9319SYuval Mintz u8 gl_pi; /* protocol index */ 286c5ac9319SYuval Mintz 287c5ac9319SYuval Mintz /* Will allocate rate limiters to be used with QPs */ 288c5ac9319SYuval Mintz u8 enable_dcqcn; 289c5ac9319SYuval Mintz }; 290c5ac9319SYuval Mintz 291fe56b9e6SYuval Mintz struct qed_pf_params { 292fe56b9e6SYuval Mintz struct qed_eth_pf_params eth_pf_params; 2931e128c81SArun Easi struct qed_fcoe_pf_params fcoe_pf_params; 294c5ac9319SYuval Mintz struct qed_iscsi_pf_params iscsi_pf_params; 295c5ac9319SYuval Mintz struct qed_rdma_pf_params rdma_pf_params; 296fe56b9e6SYuval Mintz }; 297fe56b9e6SYuval Mintz 298fe56b9e6SYuval Mintz enum qed_int_mode { 299fe56b9e6SYuval Mintz QED_INT_MODE_INTA, 300fe56b9e6SYuval Mintz QED_INT_MODE_MSIX, 301fe56b9e6SYuval Mintz QED_INT_MODE_MSI, 302fe56b9e6SYuval Mintz QED_INT_MODE_POLL, 303fe56b9e6SYuval Mintz }; 304fe56b9e6SYuval Mintz 305fe56b9e6SYuval Mintz struct qed_sb_info { 306fe56b9e6SYuval Mintz struct status_block *sb_virt; 307fe56b9e6SYuval Mintz dma_addr_t sb_phys; 308fe56b9e6SYuval Mintz u32 sb_ack; /* Last given ack */ 309fe56b9e6SYuval Mintz u16 igu_sb_id; 310fe56b9e6SYuval Mintz void __iomem *igu_addr; 311fe56b9e6SYuval Mintz u8 flags; 312fe56b9e6SYuval Mintz #define QED_SB_INFO_INIT 0x1 313fe56b9e6SYuval Mintz #define QED_SB_INFO_SETUP 0x2 314fe56b9e6SYuval Mintz 315fe56b9e6SYuval Mintz struct qed_dev *cdev; 316fe56b9e6SYuval Mintz }; 317fe56b9e6SYuval Mintz 3189c79ddaaSMintz, Yuval enum qed_dev_type { 3199c79ddaaSMintz, Yuval QED_DEV_TYPE_BB, 3209c79ddaaSMintz, Yuval QED_DEV_TYPE_AH, 3219c79ddaaSMintz, Yuval }; 3229c79ddaaSMintz, Yuval 323fe56b9e6SYuval Mintz struct qed_dev_info { 324fe56b9e6SYuval Mintz unsigned long pci_mem_start; 325fe56b9e6SYuval Mintz unsigned long pci_mem_end; 326fe56b9e6SYuval Mintz unsigned int pci_irq; 327fe56b9e6SYuval Mintz u8 num_hwfns; 328fe56b9e6SYuval Mintz 329fe56b9e6SYuval Mintz u8 hw_mac[ETH_ALEN]; 330fc48b7a6SYuval Mintz bool is_mf_default; 331fe56b9e6SYuval Mintz 332fe56b9e6SYuval Mintz /* FW version */ 333fe56b9e6SYuval Mintz u16 fw_major; 334fe56b9e6SYuval Mintz u16 fw_minor; 335fe56b9e6SYuval Mintz u16 fw_rev; 336fe56b9e6SYuval Mintz u16 fw_eng; 337fe56b9e6SYuval Mintz 338fe56b9e6SYuval Mintz /* MFW version */ 339fe56b9e6SYuval Mintz u32 mfw_rev; 340ae33666aSTomer Tayar #define QED_MFW_VERSION_0_MASK 0x000000FF 341ae33666aSTomer Tayar #define QED_MFW_VERSION_0_OFFSET 0 342ae33666aSTomer Tayar #define QED_MFW_VERSION_1_MASK 0x0000FF00 343ae33666aSTomer Tayar #define QED_MFW_VERSION_1_OFFSET 8 344ae33666aSTomer Tayar #define QED_MFW_VERSION_2_MASK 0x00FF0000 345ae33666aSTomer Tayar #define QED_MFW_VERSION_2_OFFSET 16 346ae33666aSTomer Tayar #define QED_MFW_VERSION_3_MASK 0xFF000000 347ae33666aSTomer Tayar #define QED_MFW_VERSION_3_OFFSET 24 348fe56b9e6SYuval Mintz 349fe56b9e6SYuval Mintz u32 flash_size; 350fe56b9e6SYuval Mintz u8 mf_mode; 351831bfb0eSYuval Mintz bool tx_switching; 352cee9fbd8SRam Amrani bool rdma_supported; 3530fefbfbaSSudarsana Kalluru u16 mtu; 35414d39648SMintz, Yuval 35514d39648SMintz, Yuval bool wol_support; 3569c79ddaaSMintz, Yuval 357ae33666aSTomer Tayar /* MBI version */ 358ae33666aSTomer Tayar u32 mbi_version; 359ae33666aSTomer Tayar #define QED_MBI_VERSION_0_MASK 0x000000FF 360ae33666aSTomer Tayar #define QED_MBI_VERSION_0_OFFSET 0 361ae33666aSTomer Tayar #define QED_MBI_VERSION_1_MASK 0x0000FF00 362ae33666aSTomer Tayar #define QED_MBI_VERSION_1_OFFSET 8 363ae33666aSTomer Tayar #define QED_MBI_VERSION_2_MASK 0x00FF0000 364ae33666aSTomer Tayar #define QED_MBI_VERSION_2_OFFSET 16 365ae33666aSTomer Tayar 3669c79ddaaSMintz, Yuval enum qed_dev_type dev_type; 36719489c7fSChopra, Manish 36819489c7fSChopra, Manish /* Output parameters for qede */ 36919489c7fSChopra, Manish bool vxlan_enable; 37019489c7fSChopra, Manish bool gre_enable; 37119489c7fSChopra, Manish bool geneve_enable; 3723c5da942SMintz, Yuval 3733c5da942SMintz, Yuval u8 abs_pf_id; 374fe56b9e6SYuval Mintz }; 375fe56b9e6SYuval Mintz 376fe56b9e6SYuval Mintz enum qed_sb_type { 377fe56b9e6SYuval Mintz QED_SB_TYPE_L2_QUEUE, 37851ff1725SRam Amrani QED_SB_TYPE_CNQ, 379fc831825SYuval Mintz QED_SB_TYPE_STORAGE, 380fe56b9e6SYuval Mintz }; 381fe56b9e6SYuval Mintz 382fe56b9e6SYuval Mintz enum qed_protocol { 383fe56b9e6SYuval Mintz QED_PROTOCOL_ETH, 384c5ac9319SYuval Mintz QED_PROTOCOL_ISCSI, 3851e128c81SArun Easi QED_PROTOCOL_FCOE, 386fe56b9e6SYuval Mintz }; 387fe56b9e6SYuval Mintz 388054c67d1SSudarsana Reddy Kalluru enum qed_link_mode_bits { 389054c67d1SSudarsana Reddy Kalluru QED_LM_FIBRE_BIT = BIT(0), 390054c67d1SSudarsana Reddy Kalluru QED_LM_Autoneg_BIT = BIT(1), 391054c67d1SSudarsana Reddy Kalluru QED_LM_Asym_Pause_BIT = BIT(2), 392054c67d1SSudarsana Reddy Kalluru QED_LM_Pause_BIT = BIT(3), 393054c67d1SSudarsana Reddy Kalluru QED_LM_1000baseT_Half_BIT = BIT(4), 394054c67d1SSudarsana Reddy Kalluru QED_LM_1000baseT_Full_BIT = BIT(5), 395054c67d1SSudarsana Reddy Kalluru QED_LM_10000baseKR_Full_BIT = BIT(6), 396054c67d1SSudarsana Reddy Kalluru QED_LM_25000baseKR_Full_BIT = BIT(7), 397054c67d1SSudarsana Reddy Kalluru QED_LM_40000baseLR4_Full_BIT = BIT(8), 398054c67d1SSudarsana Reddy Kalluru QED_LM_50000baseKR2_Full_BIT = BIT(9), 399054c67d1SSudarsana Reddy Kalluru QED_LM_100000baseKR4_Full_BIT = BIT(10), 400054c67d1SSudarsana Reddy Kalluru QED_LM_COUNT = 11 401054c67d1SSudarsana Reddy Kalluru }; 402054c67d1SSudarsana Reddy Kalluru 403fe56b9e6SYuval Mintz struct qed_link_params { 404fe56b9e6SYuval Mintz bool link_up; 405fe56b9e6SYuval Mintz 406fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0) 407fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1) 408fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2) 409fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3) 41003dc76caSSudarsana Reddy Kalluru #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4) 411fe56b9e6SYuval Mintz u32 override_flags; 412fe56b9e6SYuval Mintz bool autoneg; 413fe56b9e6SYuval Mintz u32 adv_speeds; 414fe56b9e6SYuval Mintz u32 forced_speed; 415fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0) 416fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_RX_ENABLE BIT(1) 417fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_TX_ENABLE BIT(2) 418fe56b9e6SYuval Mintz u32 pause_config; 41903dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_NONE BIT(0) 42003dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_INT_PHY BIT(1) 42103dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_EXT_PHY BIT(2) 42203dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_EXT BIT(3) 42303dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_MAC BIT(4) 42403dc76caSSudarsana Reddy Kalluru u32 loopback_mode; 425fe56b9e6SYuval Mintz }; 426fe56b9e6SYuval Mintz 427fe56b9e6SYuval Mintz struct qed_link_output { 428fe56b9e6SYuval Mintz bool link_up; 429fe56b9e6SYuval Mintz 430d194fd26SYuval Mintz /* In QED_LM_* defs */ 431d194fd26SYuval Mintz u32 supported_caps; 432d194fd26SYuval Mintz u32 advertised_caps; 433d194fd26SYuval Mintz u32 lp_caps; 434d194fd26SYuval Mintz 435fe56b9e6SYuval Mintz u32 speed; /* In Mb/s */ 436fe56b9e6SYuval Mintz u8 duplex; /* In DUPLEX defs */ 437fe56b9e6SYuval Mintz u8 port; /* In PORT defs */ 438fe56b9e6SYuval Mintz bool autoneg; 439fe56b9e6SYuval Mintz u32 pause_config; 440fe56b9e6SYuval Mintz }; 441fe56b9e6SYuval Mintz 4421408cc1fSYuval Mintz struct qed_probe_params { 4431408cc1fSYuval Mintz enum qed_protocol protocol; 4441408cc1fSYuval Mintz u32 dp_module; 4451408cc1fSYuval Mintz u8 dp_level; 4461408cc1fSYuval Mintz bool is_vf; 4471408cc1fSYuval Mintz }; 4481408cc1fSYuval Mintz 449fe56b9e6SYuval Mintz #define QED_DRV_VER_STR_SIZE 12 450fe56b9e6SYuval Mintz struct qed_slowpath_params { 451fe56b9e6SYuval Mintz u32 int_mode; 452fe56b9e6SYuval Mintz u8 drv_major; 453fe56b9e6SYuval Mintz u8 drv_minor; 454fe56b9e6SYuval Mintz u8 drv_rev; 455fe56b9e6SYuval Mintz u8 drv_eng; 456fe56b9e6SYuval Mintz u8 name[QED_DRV_VER_STR_SIZE]; 457fe56b9e6SYuval Mintz }; 458fe56b9e6SYuval Mintz 459fe56b9e6SYuval Mintz #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */ 460fe56b9e6SYuval Mintz 461fe56b9e6SYuval Mintz struct qed_int_info { 462fe56b9e6SYuval Mintz struct msix_entry *msix; 463fe56b9e6SYuval Mintz u8 msix_cnt; 464fe56b9e6SYuval Mintz 465fe56b9e6SYuval Mintz /* This should be updated by the protocol driver */ 466fe56b9e6SYuval Mintz u8 used_cnt; 467fe56b9e6SYuval Mintz }; 468fe56b9e6SYuval Mintz 469fe56b9e6SYuval Mintz struct qed_common_cb_ops { 470d51e4af5SChopra, Manish void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc); 471fe56b9e6SYuval Mintz void (*link_update)(void *dev, 472fe56b9e6SYuval Mintz struct qed_link_output *link); 4731e128c81SArun Easi void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type); 474fe56b9e6SYuval Mintz }; 475fe56b9e6SYuval Mintz 47603dc76caSSudarsana Reddy Kalluru struct qed_selftest_ops { 47703dc76caSSudarsana Reddy Kalluru /** 47803dc76caSSudarsana Reddy Kalluru * @brief selftest_interrupt - Perform interrupt test 47903dc76caSSudarsana Reddy Kalluru * 48003dc76caSSudarsana Reddy Kalluru * @param cdev 48103dc76caSSudarsana Reddy Kalluru * 48203dc76caSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 48303dc76caSSudarsana Reddy Kalluru */ 48403dc76caSSudarsana Reddy Kalluru int (*selftest_interrupt)(struct qed_dev *cdev); 48503dc76caSSudarsana Reddy Kalluru 48603dc76caSSudarsana Reddy Kalluru /** 48703dc76caSSudarsana Reddy Kalluru * @brief selftest_memory - Perform memory test 48803dc76caSSudarsana Reddy Kalluru * 48903dc76caSSudarsana Reddy Kalluru * @param cdev 49003dc76caSSudarsana Reddy Kalluru * 49103dc76caSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 49203dc76caSSudarsana Reddy Kalluru */ 49303dc76caSSudarsana Reddy Kalluru int (*selftest_memory)(struct qed_dev *cdev); 49403dc76caSSudarsana Reddy Kalluru 49503dc76caSSudarsana Reddy Kalluru /** 49603dc76caSSudarsana Reddy Kalluru * @brief selftest_register - Perform register test 49703dc76caSSudarsana Reddy Kalluru * 49803dc76caSSudarsana Reddy Kalluru * @param cdev 49903dc76caSSudarsana Reddy Kalluru * 50003dc76caSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 50103dc76caSSudarsana Reddy Kalluru */ 50203dc76caSSudarsana Reddy Kalluru int (*selftest_register)(struct qed_dev *cdev); 50303dc76caSSudarsana Reddy Kalluru 50403dc76caSSudarsana Reddy Kalluru /** 50503dc76caSSudarsana Reddy Kalluru * @brief selftest_clock - Perform clock test 50603dc76caSSudarsana Reddy Kalluru * 50703dc76caSSudarsana Reddy Kalluru * @param cdev 50803dc76caSSudarsana Reddy Kalluru * 50903dc76caSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 51003dc76caSSudarsana Reddy Kalluru */ 51103dc76caSSudarsana Reddy Kalluru int (*selftest_clock)(struct qed_dev *cdev); 5127a4b21b7SMintz, Yuval 5137a4b21b7SMintz, Yuval /** 5147a4b21b7SMintz, Yuval * @brief selftest_nvram - Perform nvram test 5157a4b21b7SMintz, Yuval * 5167a4b21b7SMintz, Yuval * @param cdev 5177a4b21b7SMintz, Yuval * 5187a4b21b7SMintz, Yuval * @return 0 on success, error otherwise. 5197a4b21b7SMintz, Yuval */ 5207a4b21b7SMintz, Yuval int (*selftest_nvram) (struct qed_dev *cdev); 52103dc76caSSudarsana Reddy Kalluru }; 52203dc76caSSudarsana Reddy Kalluru 523fe56b9e6SYuval Mintz struct qed_common_ops { 52403dc76caSSudarsana Reddy Kalluru struct qed_selftest_ops *selftest; 52503dc76caSSudarsana Reddy Kalluru 526fe56b9e6SYuval Mintz struct qed_dev* (*probe)(struct pci_dev *dev, 5271408cc1fSYuval Mintz struct qed_probe_params *params); 528fe56b9e6SYuval Mintz 529fe56b9e6SYuval Mintz void (*remove)(struct qed_dev *cdev); 530fe56b9e6SYuval Mintz 531fe56b9e6SYuval Mintz int (*set_power_state)(struct qed_dev *cdev, 532fe56b9e6SYuval Mintz pci_power_t state); 533fe56b9e6SYuval Mintz 534712c3cbfSMintz, Yuval void (*set_name) (struct qed_dev *cdev, char name[]); 535fe56b9e6SYuval Mintz 536fe56b9e6SYuval Mintz /* Client drivers need to make this call before slowpath_start. 537fe56b9e6SYuval Mintz * PF params required for the call before slowpath_start is 538fe56b9e6SYuval Mintz * documented within the qed_pf_params structure definition. 539fe56b9e6SYuval Mintz */ 540fe56b9e6SYuval Mintz void (*update_pf_params)(struct qed_dev *cdev, 541fe56b9e6SYuval Mintz struct qed_pf_params *params); 542fe56b9e6SYuval Mintz int (*slowpath_start)(struct qed_dev *cdev, 543fe56b9e6SYuval Mintz struct qed_slowpath_params *params); 544fe56b9e6SYuval Mintz 545fe56b9e6SYuval Mintz int (*slowpath_stop)(struct qed_dev *cdev); 546fe56b9e6SYuval Mintz 547fe56b9e6SYuval Mintz /* Requests to use `cnt' interrupts for fastpath. 548fe56b9e6SYuval Mintz * upon success, returns number of interrupts allocated for fastpath. 549fe56b9e6SYuval Mintz */ 550fe56b9e6SYuval Mintz int (*set_fp_int)(struct qed_dev *cdev, 551fe56b9e6SYuval Mintz u16 cnt); 552fe56b9e6SYuval Mintz 553fe56b9e6SYuval Mintz /* Fills `info' with pointers required for utilizing interrupts */ 554fe56b9e6SYuval Mintz int (*get_fp_int)(struct qed_dev *cdev, 555fe56b9e6SYuval Mintz struct qed_int_info *info); 556fe56b9e6SYuval Mintz 557fe56b9e6SYuval Mintz u32 (*sb_init)(struct qed_dev *cdev, 558fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 559fe56b9e6SYuval Mintz void *sb_virt_addr, 560fe56b9e6SYuval Mintz dma_addr_t sb_phy_addr, 561fe56b9e6SYuval Mintz u16 sb_id, 562fe56b9e6SYuval Mintz enum qed_sb_type type); 563fe56b9e6SYuval Mintz 564fe56b9e6SYuval Mintz u32 (*sb_release)(struct qed_dev *cdev, 565fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 566fe56b9e6SYuval Mintz u16 sb_id); 567fe56b9e6SYuval Mintz 568fe56b9e6SYuval Mintz void (*simd_handler_config)(struct qed_dev *cdev, 569fe56b9e6SYuval Mintz void *token, 570fe56b9e6SYuval Mintz int index, 571fe56b9e6SYuval Mintz void (*handler)(void *)); 572fe56b9e6SYuval Mintz 573fe56b9e6SYuval Mintz void (*simd_handler_clean)(struct qed_dev *cdev, 574fe56b9e6SYuval Mintz int index); 5751e128c81SArun Easi int (*dbg_grc)(struct qed_dev *cdev, 5761e128c81SArun Easi void *buffer, u32 *num_dumped_bytes); 5771e128c81SArun Easi 5781e128c81SArun Easi int (*dbg_grc_size)(struct qed_dev *cdev); 579fe7cd2bfSYuval Mintz 580e0971c83STomer Tayar int (*dbg_all_data) (struct qed_dev *cdev, void *buffer); 581e0971c83STomer Tayar 582e0971c83STomer Tayar int (*dbg_all_data_size) (struct qed_dev *cdev); 583e0971c83STomer Tayar 584fe7cd2bfSYuval Mintz /** 585fe7cd2bfSYuval Mintz * @brief can_link_change - can the instance change the link or not 586fe7cd2bfSYuval Mintz * 587fe7cd2bfSYuval Mintz * @param cdev 588fe7cd2bfSYuval Mintz * 589fe7cd2bfSYuval Mintz * @return true if link-change is allowed, false otherwise. 590fe7cd2bfSYuval Mintz */ 591fe7cd2bfSYuval Mintz bool (*can_link_change)(struct qed_dev *cdev); 592fe7cd2bfSYuval Mintz 593fe56b9e6SYuval Mintz /** 594fe56b9e6SYuval Mintz * @brief set_link - set links according to params 595fe56b9e6SYuval Mintz * 596fe56b9e6SYuval Mintz * @param cdev 597fe56b9e6SYuval Mintz * @param params - values used to override the default link configuration 598fe56b9e6SYuval Mintz * 599fe56b9e6SYuval Mintz * @return 0 on success, error otherwise. 600fe56b9e6SYuval Mintz */ 601fe56b9e6SYuval Mintz int (*set_link)(struct qed_dev *cdev, 602fe56b9e6SYuval Mintz struct qed_link_params *params); 603fe56b9e6SYuval Mintz 604fe56b9e6SYuval Mintz /** 605fe56b9e6SYuval Mintz * @brief get_link - returns the current link state. 606fe56b9e6SYuval Mintz * 607fe56b9e6SYuval Mintz * @param cdev 608fe56b9e6SYuval Mintz * @param if_link - structure to be filled with current link configuration. 609fe56b9e6SYuval Mintz */ 610fe56b9e6SYuval Mintz void (*get_link)(struct qed_dev *cdev, 611fe56b9e6SYuval Mintz struct qed_link_output *if_link); 612fe56b9e6SYuval Mintz 613fe56b9e6SYuval Mintz /** 614fe56b9e6SYuval Mintz * @brief - drains chip in case Tx completions fail to arrive due to pause. 615fe56b9e6SYuval Mintz * 616fe56b9e6SYuval Mintz * @param cdev 617fe56b9e6SYuval Mintz */ 618fe56b9e6SYuval Mintz int (*drain)(struct qed_dev *cdev); 619fe56b9e6SYuval Mintz 620fe56b9e6SYuval Mintz /** 621fe56b9e6SYuval Mintz * @brief update_msglvl - update module debug level 622fe56b9e6SYuval Mintz * 623fe56b9e6SYuval Mintz * @param cdev 624fe56b9e6SYuval Mintz * @param dp_module 625fe56b9e6SYuval Mintz * @param dp_level 626fe56b9e6SYuval Mintz */ 627fe56b9e6SYuval Mintz void (*update_msglvl)(struct qed_dev *cdev, 628fe56b9e6SYuval Mintz u32 dp_module, 629fe56b9e6SYuval Mintz u8 dp_level); 630fe56b9e6SYuval Mintz 631fe56b9e6SYuval Mintz int (*chain_alloc)(struct qed_dev *cdev, 632fe56b9e6SYuval Mintz enum qed_chain_use_mode intended_use, 633fe56b9e6SYuval Mintz enum qed_chain_mode mode, 634a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 635a91eb52aSYuval Mintz u32 num_elems, 636fe56b9e6SYuval Mintz size_t elem_size, 637fe56b9e6SYuval Mintz struct qed_chain *p_chain); 638fe56b9e6SYuval Mintz 639fe56b9e6SYuval Mintz void (*chain_free)(struct qed_dev *cdev, 640fe56b9e6SYuval Mintz struct qed_chain *p_chain); 64191420b83SSudarsana Kalluru 64291420b83SSudarsana Kalluru /** 64320675b37SMintz, Yuval * @brief nvm_get_image - reads an entire image from nvram 64420675b37SMintz, Yuval * 64520675b37SMintz, Yuval * @param cdev 64620675b37SMintz, Yuval * @param type - type of the request nvram image 64720675b37SMintz, Yuval * @param buf - preallocated buffer to fill with the image 64820675b37SMintz, Yuval * @param len - length of the allocated buffer 64920675b37SMintz, Yuval * 65020675b37SMintz, Yuval * @return 0 on success, error otherwise 65120675b37SMintz, Yuval */ 65220675b37SMintz, Yuval int (*nvm_get_image)(struct qed_dev *cdev, 65320675b37SMintz, Yuval enum qed_nvm_images type, u8 *buf, u16 len); 65420675b37SMintz, Yuval 65520675b37SMintz, Yuval /** 656722003acSSudarsana Reddy Kalluru * @brief get_coalesce - Get coalesce parameters in usec 657722003acSSudarsana Reddy Kalluru * 658722003acSSudarsana Reddy Kalluru * @param cdev 659722003acSSudarsana Reddy Kalluru * @param rx_coal - Rx coalesce value in usec 660722003acSSudarsana Reddy Kalluru * @param tx_coal - Tx coalesce value in usec 661722003acSSudarsana Reddy Kalluru * 662722003acSSudarsana Reddy Kalluru */ 663722003acSSudarsana Reddy Kalluru void (*get_coalesce)(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal); 664722003acSSudarsana Reddy Kalluru 665722003acSSudarsana Reddy Kalluru /** 666722003acSSudarsana Reddy Kalluru * @brief set_coalesce - Configure Rx coalesce value in usec 667722003acSSudarsana Reddy Kalluru * 668722003acSSudarsana Reddy Kalluru * @param cdev 669722003acSSudarsana Reddy Kalluru * @param rx_coal - Rx coalesce value in usec 670722003acSSudarsana Reddy Kalluru * @param tx_coal - Tx coalesce value in usec 671722003acSSudarsana Reddy Kalluru * @param qid - Queue index 672722003acSSudarsana Reddy Kalluru * @param sb_id - Status Block Id 673722003acSSudarsana Reddy Kalluru * 674722003acSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 675722003acSSudarsana Reddy Kalluru */ 676722003acSSudarsana Reddy Kalluru int (*set_coalesce)(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, 677f870a3c6Ssudarsana.kalluru@cavium.com u16 qid, u16 sb_id); 678722003acSSudarsana Reddy Kalluru 679722003acSSudarsana Reddy Kalluru /** 68091420b83SSudarsana Kalluru * @brief set_led - Configure LED mode 68191420b83SSudarsana Kalluru * 68291420b83SSudarsana Kalluru * @param cdev 68391420b83SSudarsana Kalluru * @param mode - LED mode 68491420b83SSudarsana Kalluru * 68591420b83SSudarsana Kalluru * @return 0 on success, error otherwise. 68691420b83SSudarsana Kalluru */ 68791420b83SSudarsana Kalluru int (*set_led)(struct qed_dev *cdev, 68891420b83SSudarsana Kalluru enum qed_led_mode mode); 6890fefbfbaSSudarsana Kalluru 6900fefbfbaSSudarsana Kalluru /** 6910fefbfbaSSudarsana Kalluru * @brief update_drv_state - API to inform the change in the driver state. 6920fefbfbaSSudarsana Kalluru * 6930fefbfbaSSudarsana Kalluru * @param cdev 6940fefbfbaSSudarsana Kalluru * @param active 6950fefbfbaSSudarsana Kalluru * 6960fefbfbaSSudarsana Kalluru */ 6970fefbfbaSSudarsana Kalluru int (*update_drv_state)(struct qed_dev *cdev, bool active); 6980fefbfbaSSudarsana Kalluru 6990fefbfbaSSudarsana Kalluru /** 7000fefbfbaSSudarsana Kalluru * @brief update_mac - API to inform the change in the mac address 7010fefbfbaSSudarsana Kalluru * 7020fefbfbaSSudarsana Kalluru * @param cdev 7030fefbfbaSSudarsana Kalluru * @param mac 7040fefbfbaSSudarsana Kalluru * 7050fefbfbaSSudarsana Kalluru */ 7060fefbfbaSSudarsana Kalluru int (*update_mac)(struct qed_dev *cdev, u8 *mac); 7070fefbfbaSSudarsana Kalluru 7080fefbfbaSSudarsana Kalluru /** 7090fefbfbaSSudarsana Kalluru * @brief update_mtu - API to inform the change in the mtu 7100fefbfbaSSudarsana Kalluru * 7110fefbfbaSSudarsana Kalluru * @param cdev 7120fefbfbaSSudarsana Kalluru * @param mtu 7130fefbfbaSSudarsana Kalluru * 7140fefbfbaSSudarsana Kalluru */ 7150fefbfbaSSudarsana Kalluru int (*update_mtu)(struct qed_dev *cdev, u16 mtu); 71614d39648SMintz, Yuval 71714d39648SMintz, Yuval /** 71814d39648SMintz, Yuval * @brief update_wol - update of changes in the WoL configuration 71914d39648SMintz, Yuval * 72014d39648SMintz, Yuval * @param cdev 72114d39648SMintz, Yuval * @param enabled - true iff WoL should be enabled. 72214d39648SMintz, Yuval */ 72314d39648SMintz, Yuval int (*update_wol) (struct qed_dev *cdev, bool enabled); 724fe56b9e6SYuval Mintz }; 725fe56b9e6SYuval Mintz 726fe56b9e6SYuval Mintz #define MASK_FIELD(_name, _value) \ 727fe56b9e6SYuval Mintz ((_value) &= (_name ## _MASK)) 728fe56b9e6SYuval Mintz 729fe56b9e6SYuval Mintz #define FIELD_VALUE(_name, _value) \ 730fe56b9e6SYuval Mintz ((_value & _name ## _MASK) << _name ## _SHIFT) 731fe56b9e6SYuval Mintz 732fe56b9e6SYuval Mintz #define SET_FIELD(value, name, flag) \ 733fe56b9e6SYuval Mintz do { \ 734fe56b9e6SYuval Mintz (value) &= ~(name ## _MASK << name ## _SHIFT); \ 735fe56b9e6SYuval Mintz (value) |= (((u64)flag) << (name ## _SHIFT)); \ 736fe56b9e6SYuval Mintz } while (0) 737fe56b9e6SYuval Mintz 738fe56b9e6SYuval Mintz #define GET_FIELD(value, name) \ 739fe56b9e6SYuval Mintz (((value) >> (name ## _SHIFT)) & name ## _MASK) 740fe56b9e6SYuval Mintz 741fe56b9e6SYuval Mintz /* Debug print definitions */ 742fe56b9e6SYuval Mintz #define DP_ERR(cdev, fmt, ...) \ 7439d7650c2SMintz, Yuval do { \ 744fe56b9e6SYuval Mintz pr_err("[%s:%d(%s)]" fmt, \ 745fe56b9e6SYuval Mintz __func__, __LINE__, \ 746fe56b9e6SYuval Mintz DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 7479d7650c2SMintz, Yuval ## __VA_ARGS__); \ 7489d7650c2SMintz, Yuval } while (0) 749fe56b9e6SYuval Mintz 750fe56b9e6SYuval Mintz #define DP_NOTICE(cdev, fmt, ...) \ 751fe56b9e6SYuval Mintz do { \ 752fe56b9e6SYuval Mintz if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \ 753fe56b9e6SYuval Mintz pr_notice("[%s:%d(%s)]" fmt, \ 754fe56b9e6SYuval Mintz __func__, __LINE__, \ 755fe56b9e6SYuval Mintz DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 756fe56b9e6SYuval Mintz ## __VA_ARGS__); \ 757fe56b9e6SYuval Mintz \ 758fe56b9e6SYuval Mintz } \ 759fe56b9e6SYuval Mintz } while (0) 760fe56b9e6SYuval Mintz 761fe56b9e6SYuval Mintz #define DP_INFO(cdev, fmt, ...) \ 762fe56b9e6SYuval Mintz do { \ 763fe56b9e6SYuval Mintz if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \ 764fe56b9e6SYuval Mintz pr_notice("[%s:%d(%s)]" fmt, \ 765fe56b9e6SYuval Mintz __func__, __LINE__, \ 766fe56b9e6SYuval Mintz DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 767fe56b9e6SYuval Mintz ## __VA_ARGS__); \ 768fe56b9e6SYuval Mintz } \ 769fe56b9e6SYuval Mintz } while (0) 770fe56b9e6SYuval Mintz 771fe56b9e6SYuval Mintz #define DP_VERBOSE(cdev, module, fmt, ...) \ 772fe56b9e6SYuval Mintz do { \ 773fe56b9e6SYuval Mintz if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \ 774fe56b9e6SYuval Mintz ((cdev)->dp_module & module))) { \ 775fe56b9e6SYuval Mintz pr_notice("[%s:%d(%s)]" fmt, \ 776fe56b9e6SYuval Mintz __func__, __LINE__, \ 777fe56b9e6SYuval Mintz DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 778fe56b9e6SYuval Mintz ## __VA_ARGS__); \ 779fe56b9e6SYuval Mintz } \ 780fe56b9e6SYuval Mintz } while (0) 781fe56b9e6SYuval Mintz 782fe56b9e6SYuval Mintz enum DP_LEVEL { 783fe56b9e6SYuval Mintz QED_LEVEL_VERBOSE = 0x0, 784fe56b9e6SYuval Mintz QED_LEVEL_INFO = 0x1, 785fe56b9e6SYuval Mintz QED_LEVEL_NOTICE = 0x2, 786fe56b9e6SYuval Mintz QED_LEVEL_ERR = 0x3, 787fe56b9e6SYuval Mintz }; 788fe56b9e6SYuval Mintz 789fe56b9e6SYuval Mintz #define QED_LOG_LEVEL_SHIFT (30) 790fe56b9e6SYuval Mintz #define QED_LOG_VERBOSE_MASK (0x3fffffff) 791fe56b9e6SYuval Mintz #define QED_LOG_INFO_MASK (0x40000000) 792fe56b9e6SYuval Mintz #define QED_LOG_NOTICE_MASK (0x80000000) 793fe56b9e6SYuval Mintz 794fe56b9e6SYuval Mintz enum DP_MODULE { 795fe56b9e6SYuval Mintz QED_MSG_SPQ = 0x10000, 796fe56b9e6SYuval Mintz QED_MSG_STATS = 0x20000, 797fe56b9e6SYuval Mintz QED_MSG_DCB = 0x40000, 798fe56b9e6SYuval Mintz QED_MSG_IOV = 0x80000, 799fe56b9e6SYuval Mintz QED_MSG_SP = 0x100000, 800fe56b9e6SYuval Mintz QED_MSG_STORAGE = 0x200000, 801fe56b9e6SYuval Mintz QED_MSG_CXT = 0x800000, 8020a7fb11cSYuval Mintz QED_MSG_LL2 = 0x1000000, 803fe56b9e6SYuval Mintz QED_MSG_ILT = 0x2000000, 80451ff1725SRam Amrani QED_MSG_RDMA = 0x4000000, 805fe56b9e6SYuval Mintz QED_MSG_DEBUG = 0x8000000, 806fe56b9e6SYuval Mintz /* to be added...up to 0x8000000 */ 807fe56b9e6SYuval Mintz }; 808fe56b9e6SYuval Mintz 809fc48b7a6SYuval Mintz enum qed_mf_mode { 810fc48b7a6SYuval Mintz QED_MF_DEFAULT, 811fc48b7a6SYuval Mintz QED_MF_OVLAN, 812fc48b7a6SYuval Mintz QED_MF_NPAR, 813fc48b7a6SYuval Mintz }; 814fc48b7a6SYuval Mintz 8159c79ddaaSMintz, Yuval struct qed_eth_stats_common { 816fe56b9e6SYuval Mintz u64 no_buff_discards; 817fe56b9e6SYuval Mintz u64 packet_too_big_discard; 818fe56b9e6SYuval Mintz u64 ttl0_discard; 819fe56b9e6SYuval Mintz u64 rx_ucast_bytes; 820fe56b9e6SYuval Mintz u64 rx_mcast_bytes; 821fe56b9e6SYuval Mintz u64 rx_bcast_bytes; 822fe56b9e6SYuval Mintz u64 rx_ucast_pkts; 823fe56b9e6SYuval Mintz u64 rx_mcast_pkts; 824fe56b9e6SYuval Mintz u64 rx_bcast_pkts; 825fe56b9e6SYuval Mintz u64 mftag_filter_discards; 826fe56b9e6SYuval Mintz u64 mac_filter_discards; 827fe56b9e6SYuval Mintz u64 tx_ucast_bytes; 828fe56b9e6SYuval Mintz u64 tx_mcast_bytes; 829fe56b9e6SYuval Mintz u64 tx_bcast_bytes; 830fe56b9e6SYuval Mintz u64 tx_ucast_pkts; 831fe56b9e6SYuval Mintz u64 tx_mcast_pkts; 832fe56b9e6SYuval Mintz u64 tx_bcast_pkts; 833fe56b9e6SYuval Mintz u64 tx_err_drop_pkts; 834fe56b9e6SYuval Mintz u64 tpa_coalesced_pkts; 835fe56b9e6SYuval Mintz u64 tpa_coalesced_events; 836fe56b9e6SYuval Mintz u64 tpa_aborts_num; 837fe56b9e6SYuval Mintz u64 tpa_not_coalesced_pkts; 838fe56b9e6SYuval Mintz u64 tpa_coalesced_bytes; 839fe56b9e6SYuval Mintz 840fe56b9e6SYuval Mintz /* port */ 841fe56b9e6SYuval Mintz u64 rx_64_byte_packets; 842d4967cf3SYuval Mintz u64 rx_65_to_127_byte_packets; 843d4967cf3SYuval Mintz u64 rx_128_to_255_byte_packets; 844d4967cf3SYuval Mintz u64 rx_256_to_511_byte_packets; 845d4967cf3SYuval Mintz u64 rx_512_to_1023_byte_packets; 846d4967cf3SYuval Mintz u64 rx_1024_to_1518_byte_packets; 847fe56b9e6SYuval Mintz u64 rx_crc_errors; 848fe56b9e6SYuval Mintz u64 rx_mac_crtl_frames; 849fe56b9e6SYuval Mintz u64 rx_pause_frames; 850fe56b9e6SYuval Mintz u64 rx_pfc_frames; 851fe56b9e6SYuval Mintz u64 rx_align_errors; 852fe56b9e6SYuval Mintz u64 rx_carrier_errors; 853fe56b9e6SYuval Mintz u64 rx_oversize_packets; 854fe56b9e6SYuval Mintz u64 rx_jabbers; 855fe56b9e6SYuval Mintz u64 rx_undersize_packets; 856fe56b9e6SYuval Mintz u64 rx_fragments; 857fe56b9e6SYuval Mintz u64 tx_64_byte_packets; 858fe56b9e6SYuval Mintz u64 tx_65_to_127_byte_packets; 859fe56b9e6SYuval Mintz u64 tx_128_to_255_byte_packets; 860fe56b9e6SYuval Mintz u64 tx_256_to_511_byte_packets; 861fe56b9e6SYuval Mintz u64 tx_512_to_1023_byte_packets; 862fe56b9e6SYuval Mintz u64 tx_1024_to_1518_byte_packets; 863fe56b9e6SYuval Mintz u64 tx_pause_frames; 864fe56b9e6SYuval Mintz u64 tx_pfc_frames; 865fe56b9e6SYuval Mintz u64 brb_truncates; 866fe56b9e6SYuval Mintz u64 brb_discards; 867fe56b9e6SYuval Mintz u64 rx_mac_bytes; 868fe56b9e6SYuval Mintz u64 rx_mac_uc_packets; 869fe56b9e6SYuval Mintz u64 rx_mac_mc_packets; 870fe56b9e6SYuval Mintz u64 rx_mac_bc_packets; 871fe56b9e6SYuval Mintz u64 rx_mac_frames_ok; 872fe56b9e6SYuval Mintz u64 tx_mac_bytes; 873fe56b9e6SYuval Mintz u64 tx_mac_uc_packets; 874fe56b9e6SYuval Mintz u64 tx_mac_mc_packets; 875fe56b9e6SYuval Mintz u64 tx_mac_bc_packets; 876fe56b9e6SYuval Mintz u64 tx_mac_ctrl_frames; 877fe56b9e6SYuval Mintz }; 878fe56b9e6SYuval Mintz 8799c79ddaaSMintz, Yuval struct qed_eth_stats_bb { 8809c79ddaaSMintz, Yuval u64 rx_1519_to_1522_byte_packets; 8819c79ddaaSMintz, Yuval u64 rx_1519_to_2047_byte_packets; 8829c79ddaaSMintz, Yuval u64 rx_2048_to_4095_byte_packets; 8839c79ddaaSMintz, Yuval u64 rx_4096_to_9216_byte_packets; 8849c79ddaaSMintz, Yuval u64 rx_9217_to_16383_byte_packets; 8859c79ddaaSMintz, Yuval u64 tx_1519_to_2047_byte_packets; 8869c79ddaaSMintz, Yuval u64 tx_2048_to_4095_byte_packets; 8879c79ddaaSMintz, Yuval u64 tx_4096_to_9216_byte_packets; 8889c79ddaaSMintz, Yuval u64 tx_9217_to_16383_byte_packets; 8899c79ddaaSMintz, Yuval u64 tx_lpi_entry_count; 8909c79ddaaSMintz, Yuval u64 tx_total_collisions; 8919c79ddaaSMintz, Yuval }; 8929c79ddaaSMintz, Yuval 8939c79ddaaSMintz, Yuval struct qed_eth_stats_ah { 8949c79ddaaSMintz, Yuval u64 rx_1519_to_max_byte_packets; 8959c79ddaaSMintz, Yuval u64 tx_1519_to_max_byte_packets; 8969c79ddaaSMintz, Yuval }; 8979c79ddaaSMintz, Yuval 8989c79ddaaSMintz, Yuval struct qed_eth_stats { 8999c79ddaaSMintz, Yuval struct qed_eth_stats_common common; 9009c79ddaaSMintz, Yuval 9019c79ddaaSMintz, Yuval union { 9029c79ddaaSMintz, Yuval struct qed_eth_stats_bb bb; 9039c79ddaaSMintz, Yuval struct qed_eth_stats_ah ah; 9049c79ddaaSMintz, Yuval }; 9059c79ddaaSMintz, Yuval }; 9069c79ddaaSMintz, Yuval 907fe56b9e6SYuval Mintz #define QED_SB_IDX 0x0002 908fe56b9e6SYuval Mintz 909fe56b9e6SYuval Mintz #define RX_PI 0 910fe56b9e6SYuval Mintz #define TX_PI(tc) (RX_PI + 1 + tc) 911fe56b9e6SYuval Mintz 9124ac801b7SYuval Mintz struct qed_sb_cnt_info { 913726fdbe9SMintz, Yuval /* Original, current, and free SBs for PF */ 914726fdbe9SMintz, Yuval int orig; 915726fdbe9SMintz, Yuval int cnt; 916726fdbe9SMintz, Yuval int free_cnt; 917726fdbe9SMintz, Yuval 918726fdbe9SMintz, Yuval /* Original, current and free SBS for child VFs */ 919726fdbe9SMintz, Yuval int iov_orig; 920726fdbe9SMintz, Yuval int iov_cnt; 921726fdbe9SMintz, Yuval int free_cnt_iov; 9224ac801b7SYuval Mintz }; 9234ac801b7SYuval Mintz 924fe56b9e6SYuval Mintz static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info) 925fe56b9e6SYuval Mintz { 926fe56b9e6SYuval Mintz u32 prod = 0; 927fe56b9e6SYuval Mintz u16 rc = 0; 928fe56b9e6SYuval Mintz 929fe56b9e6SYuval Mintz prod = le32_to_cpu(sb_info->sb_virt->prod_index) & 930fe56b9e6SYuval Mintz STATUS_BLOCK_PROD_INDEX_MASK; 931fe56b9e6SYuval Mintz if (sb_info->sb_ack != prod) { 932fe56b9e6SYuval Mintz sb_info->sb_ack = prod; 933fe56b9e6SYuval Mintz rc |= QED_SB_IDX; 934fe56b9e6SYuval Mintz } 935fe56b9e6SYuval Mintz 936fe56b9e6SYuval Mintz /* Let SB update */ 937fe56b9e6SYuval Mintz mmiowb(); 938fe56b9e6SYuval Mintz return rc; 939fe56b9e6SYuval Mintz } 940fe56b9e6SYuval Mintz 941fe56b9e6SYuval Mintz /** 942fe56b9e6SYuval Mintz * 943fe56b9e6SYuval Mintz * @brief This function creates an update command for interrupts that is 944fe56b9e6SYuval Mintz * written to the IGU. 945fe56b9e6SYuval Mintz * 946fe56b9e6SYuval Mintz * @param sb_info - This is the structure allocated and 947fe56b9e6SYuval Mintz * initialized per status block. Assumption is 948fe56b9e6SYuval Mintz * that it was initialized using qed_sb_init 949fe56b9e6SYuval Mintz * @param int_cmd - Enable/Disable/Nop 950fe56b9e6SYuval Mintz * @param upd_flg - whether igu consumer should be 951fe56b9e6SYuval Mintz * updated. 952fe56b9e6SYuval Mintz * 953fe56b9e6SYuval Mintz * @return inline void 954fe56b9e6SYuval Mintz */ 955fe56b9e6SYuval Mintz static inline void qed_sb_ack(struct qed_sb_info *sb_info, 956fe56b9e6SYuval Mintz enum igu_int_cmd int_cmd, 957fe56b9e6SYuval Mintz u8 upd_flg) 958fe56b9e6SYuval Mintz { 959fe56b9e6SYuval Mintz struct igu_prod_cons_update igu_ack = { 0 }; 960fe56b9e6SYuval Mintz 961fe56b9e6SYuval Mintz igu_ack.sb_id_and_flags = 962fe56b9e6SYuval Mintz ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 963fe56b9e6SYuval Mintz (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 964fe56b9e6SYuval Mintz (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 965fe56b9e6SYuval Mintz (IGU_SEG_ACCESS_REG << 966fe56b9e6SYuval Mintz IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 967fe56b9e6SYuval Mintz 968fe56b9e6SYuval Mintz DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags); 969fe56b9e6SYuval Mintz 970fe56b9e6SYuval Mintz /* Both segments (interrupts & acks) are written to same place address; 971fe56b9e6SYuval Mintz * Need to guarantee all commands will be received (in-order) by HW. 972fe56b9e6SYuval Mintz */ 973fe56b9e6SYuval Mintz mmiowb(); 974fe56b9e6SYuval Mintz barrier(); 975fe56b9e6SYuval Mintz } 976fe56b9e6SYuval Mintz 977fe56b9e6SYuval Mintz static inline void __internal_ram_wr(void *p_hwfn, 978fe56b9e6SYuval Mintz void __iomem *addr, 979fe56b9e6SYuval Mintz int size, 980fe56b9e6SYuval Mintz u32 *data) 981fe56b9e6SYuval Mintz 982fe56b9e6SYuval Mintz { 983fe56b9e6SYuval Mintz unsigned int i; 984fe56b9e6SYuval Mintz 985fe56b9e6SYuval Mintz for (i = 0; i < size / sizeof(*data); i++) 986fe56b9e6SYuval Mintz DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]); 987fe56b9e6SYuval Mintz } 988fe56b9e6SYuval Mintz 989fe56b9e6SYuval Mintz static inline void internal_ram_wr(void __iomem *addr, 990fe56b9e6SYuval Mintz int size, 991fe56b9e6SYuval Mintz u32 *data) 992fe56b9e6SYuval Mintz { 993fe56b9e6SYuval Mintz __internal_ram_wr(NULL, addr, size, data); 994fe56b9e6SYuval Mintz } 995fe56b9e6SYuval Mintz 9968c5ebd0cSSudarsana Reddy Kalluru enum qed_rss_caps { 9978c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV4 = 0x1, 9988c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV6 = 0x2, 9998c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV4_TCP = 0x4, 10008c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV6_TCP = 0x8, 10018c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV4_UDP = 0x10, 10028c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV6_UDP = 0x20, 10038c5ebd0cSSudarsana Reddy Kalluru }; 10048c5ebd0cSSudarsana Reddy Kalluru 10058c5ebd0cSSudarsana Reddy Kalluru #define QED_RSS_IND_TABLE_SIZE 128 10068c5ebd0cSSudarsana Reddy Kalluru #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */ 1007fe56b9e6SYuval Mintz #endif 1008