1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * 3fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 4fe56b9e6SYuval Mintz * 5fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 6fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 7fe56b9e6SYuval Mintz * this source tree. 8fe56b9e6SYuval Mintz */ 9fe56b9e6SYuval Mintz 10fe56b9e6SYuval Mintz #ifndef _QED_IF_H 11fe56b9e6SYuval Mintz #define _QED_IF_H 12fe56b9e6SYuval Mintz 13fe56b9e6SYuval Mintz #include <linux/types.h> 14fe56b9e6SYuval Mintz #include <linux/interrupt.h> 15fe56b9e6SYuval Mintz #include <linux/netdevice.h> 16fe56b9e6SYuval Mintz #include <linux/pci.h> 17fe56b9e6SYuval Mintz #include <linux/skbuff.h> 18fe56b9e6SYuval Mintz #include <linux/types.h> 19fe56b9e6SYuval Mintz #include <asm/byteorder.h> 20fe56b9e6SYuval Mintz #include <linux/io.h> 21fe56b9e6SYuval Mintz #include <linux/compiler.h> 22fe56b9e6SYuval Mintz #include <linux/kernel.h> 23fe56b9e6SYuval Mintz #include <linux/list.h> 24fe56b9e6SYuval Mintz #include <linux/slab.h> 25fe56b9e6SYuval Mintz #include <linux/qed/common_hsi.h> 26fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 27fe56b9e6SYuval Mintz 2839651abdSSudarsana Reddy Kalluru enum dcbx_protocol_type { 2939651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_ISCSI, 3039651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_FCOE, 3139651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_ROCE, 3239651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_ROCE_V2, 3339651abdSSudarsana Reddy Kalluru DCBX_PROTOCOL_ETH, 3439651abdSSudarsana Reddy Kalluru DCBX_MAX_PROTOCOL_TYPE 3539651abdSSudarsana Reddy Kalluru }; 3639651abdSSudarsana Reddy Kalluru 376ad8c632SSudarsana Reddy Kalluru #ifdef CONFIG_DCB 386ad8c632SSudarsana Reddy Kalluru #define QED_LLDP_CHASSIS_ID_STAT_LEN 4 396ad8c632SSudarsana Reddy Kalluru #define QED_LLDP_PORT_ID_STAT_LEN 4 406ad8c632SSudarsana Reddy Kalluru #define QED_DCBX_MAX_APP_PROTOCOL 32 416ad8c632SSudarsana Reddy Kalluru #define QED_MAX_PFC_PRIORITIES 8 426ad8c632SSudarsana Reddy Kalluru #define QED_DCBX_DSCP_SIZE 64 436ad8c632SSudarsana Reddy Kalluru 446ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_remote { 456ad8c632SSudarsana Reddy Kalluru u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 466ad8c632SSudarsana Reddy Kalluru u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 476ad8c632SSudarsana Reddy Kalluru bool enable_rx; 486ad8c632SSudarsana Reddy Kalluru bool enable_tx; 496ad8c632SSudarsana Reddy Kalluru u32 tx_interval; 506ad8c632SSudarsana Reddy Kalluru u32 max_credit; 516ad8c632SSudarsana Reddy Kalluru }; 526ad8c632SSudarsana Reddy Kalluru 536ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_local { 546ad8c632SSudarsana Reddy Kalluru u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; 556ad8c632SSudarsana Reddy Kalluru u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN]; 566ad8c632SSudarsana Reddy Kalluru }; 576ad8c632SSudarsana Reddy Kalluru 586ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_app_prio { 596ad8c632SSudarsana Reddy Kalluru u8 roce; 606ad8c632SSudarsana Reddy Kalluru u8 roce_v2; 616ad8c632SSudarsana Reddy Kalluru u8 fcoe; 626ad8c632SSudarsana Reddy Kalluru u8 iscsi; 636ad8c632SSudarsana Reddy Kalluru u8 eth; 646ad8c632SSudarsana Reddy Kalluru }; 656ad8c632SSudarsana Reddy Kalluru 666ad8c632SSudarsana Reddy Kalluru struct qed_dbcx_pfc_params { 676ad8c632SSudarsana Reddy Kalluru bool willing; 686ad8c632SSudarsana Reddy Kalluru bool enabled; 696ad8c632SSudarsana Reddy Kalluru u8 prio[QED_MAX_PFC_PRIORITIES]; 706ad8c632SSudarsana Reddy Kalluru u8 max_tc; 716ad8c632SSudarsana Reddy Kalluru }; 726ad8c632SSudarsana Reddy Kalluru 736ad8c632SSudarsana Reddy Kalluru struct qed_app_entry { 746ad8c632SSudarsana Reddy Kalluru bool ethtype; 756ad8c632SSudarsana Reddy Kalluru bool enabled; 766ad8c632SSudarsana Reddy Kalluru u8 prio; 776ad8c632SSudarsana Reddy Kalluru u16 proto_id; 786ad8c632SSudarsana Reddy Kalluru enum dcbx_protocol_type proto_type; 796ad8c632SSudarsana Reddy Kalluru }; 806ad8c632SSudarsana Reddy Kalluru 816ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params { 826ad8c632SSudarsana Reddy Kalluru struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL]; 836ad8c632SSudarsana Reddy Kalluru u16 num_app_entries; 846ad8c632SSudarsana Reddy Kalluru bool app_willing; 856ad8c632SSudarsana Reddy Kalluru bool app_valid; 866ad8c632SSudarsana Reddy Kalluru bool app_error; 876ad8c632SSudarsana Reddy Kalluru bool ets_willing; 886ad8c632SSudarsana Reddy Kalluru bool ets_enabled; 896ad8c632SSudarsana Reddy Kalluru bool ets_cbs; 906ad8c632SSudarsana Reddy Kalluru bool valid; 916ad8c632SSudarsana Reddy Kalluru u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES]; 926ad8c632SSudarsana Reddy Kalluru u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES]; 936ad8c632SSudarsana Reddy Kalluru u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES]; 946ad8c632SSudarsana Reddy Kalluru struct qed_dbcx_pfc_params pfc; 956ad8c632SSudarsana Reddy Kalluru u8 max_ets_tc; 966ad8c632SSudarsana Reddy Kalluru }; 976ad8c632SSudarsana Reddy Kalluru 986ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_admin_params { 996ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params params; 1006ad8c632SSudarsana Reddy Kalluru bool valid; 1016ad8c632SSudarsana Reddy Kalluru }; 1026ad8c632SSudarsana Reddy Kalluru 1036ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_remote_params { 1046ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params params; 1056ad8c632SSudarsana Reddy Kalluru bool valid; 1066ad8c632SSudarsana Reddy Kalluru }; 1076ad8c632SSudarsana Reddy Kalluru 1086ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_operational_params { 1096ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_app_prio app_prio; 1106ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params params; 1116ad8c632SSudarsana Reddy Kalluru bool valid; 1126ad8c632SSudarsana Reddy Kalluru bool enabled; 1136ad8c632SSudarsana Reddy Kalluru bool ieee; 1146ad8c632SSudarsana Reddy Kalluru bool cee; 1156ad8c632SSudarsana Reddy Kalluru u32 err; 1166ad8c632SSudarsana Reddy Kalluru }; 1176ad8c632SSudarsana Reddy Kalluru 1186ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_get { 1196ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_operational_params operational; 1206ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_remote lldp_remote; 1216ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_local lldp_local; 1226ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_remote_params remote; 1236ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_admin_params local; 1246ad8c632SSudarsana Reddy Kalluru }; 1256ad8c632SSudarsana Reddy Kalluru #endif 1266ad8c632SSudarsana Reddy Kalluru 12791420b83SSudarsana Kalluru enum qed_led_mode { 12891420b83SSudarsana Kalluru QED_LED_MODE_OFF, 12991420b83SSudarsana Kalluru QED_LED_MODE_ON, 13091420b83SSudarsana Kalluru QED_LED_MODE_RESTORE 13191420b83SSudarsana Kalluru }; 13291420b83SSudarsana Kalluru 133fe56b9e6SYuval Mintz #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \ 134fe56b9e6SYuval Mintz (void __iomem *)(reg_addr)) 135fe56b9e6SYuval Mintz 136fe56b9e6SYuval Mintz #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr)) 137fe56b9e6SYuval Mintz 138fe56b9e6SYuval Mintz #define QED_COALESCE_MAX 0xFF 139fe56b9e6SYuval Mintz 140fe56b9e6SYuval Mintz /* forward */ 141fe56b9e6SYuval Mintz struct qed_dev; 142fe56b9e6SYuval Mintz 143fe56b9e6SYuval Mintz struct qed_eth_pf_params { 144fe56b9e6SYuval Mintz /* The following parameters are used during HW-init 145fe56b9e6SYuval Mintz * and these parameters need to be passed as arguments 146fe56b9e6SYuval Mintz * to update_pf_params routine invoked before slowpath start 147fe56b9e6SYuval Mintz */ 148fe56b9e6SYuval Mintz u16 num_cons; 149fe56b9e6SYuval Mintz }; 150fe56b9e6SYuval Mintz 151c5ac9319SYuval Mintz /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */ 152c5ac9319SYuval Mintz struct qed_iscsi_pf_params { 153c5ac9319SYuval Mintz u64 glbl_q_params_addr; 154c5ac9319SYuval Mintz u64 bdq_pbl_base_addr[2]; 155c5ac9319SYuval Mintz u32 max_cwnd; 156c5ac9319SYuval Mintz u16 cq_num_entries; 157c5ac9319SYuval Mintz u16 cmdq_num_entries; 158c5ac9319SYuval Mintz u16 dup_ack_threshold; 159c5ac9319SYuval Mintz u16 tx_sws_timer; 160c5ac9319SYuval Mintz u16 min_rto; 161c5ac9319SYuval Mintz u16 min_rto_rt; 162c5ac9319SYuval Mintz u16 max_rto; 163c5ac9319SYuval Mintz 164c5ac9319SYuval Mintz /* The following parameters are used during HW-init 165c5ac9319SYuval Mintz * and these parameters need to be passed as arguments 166c5ac9319SYuval Mintz * to update_pf_params routine invoked before slowpath start 167c5ac9319SYuval Mintz */ 168c5ac9319SYuval Mintz u16 num_cons; 169c5ac9319SYuval Mintz u16 num_tasks; 170c5ac9319SYuval Mintz 171c5ac9319SYuval Mintz /* The following parameters are used during protocol-init */ 172c5ac9319SYuval Mintz u16 half_way_close_timeout; 173c5ac9319SYuval Mintz u16 bdq_xoff_threshold[2]; 174c5ac9319SYuval Mintz u16 bdq_xon_threshold[2]; 175c5ac9319SYuval Mintz u16 cmdq_xoff_threshold; 176c5ac9319SYuval Mintz u16 cmdq_xon_threshold; 177c5ac9319SYuval Mintz u16 rq_buffer_size; 178c5ac9319SYuval Mintz 179c5ac9319SYuval Mintz u8 num_sq_pages_in_ring; 180c5ac9319SYuval Mintz u8 num_r2tq_pages_in_ring; 181c5ac9319SYuval Mintz u8 num_uhq_pages_in_ring; 182c5ac9319SYuval Mintz u8 num_queues; 183c5ac9319SYuval Mintz u8 log_page_size; 184c5ac9319SYuval Mintz u8 rqe_log_size; 185c5ac9319SYuval Mintz u8 max_fin_rt; 186c5ac9319SYuval Mintz u8 gl_rq_pi; 187c5ac9319SYuval Mintz u8 gl_cmd_pi; 188c5ac9319SYuval Mintz u8 debug_mode; 189c5ac9319SYuval Mintz u8 ll2_ooo_queue_id; 190c5ac9319SYuval Mintz u8 ooo_enable; 191c5ac9319SYuval Mintz 192c5ac9319SYuval Mintz u8 is_target; 193c5ac9319SYuval Mintz u8 bdq_pbl_num_entries[2]; 194c5ac9319SYuval Mintz }; 195c5ac9319SYuval Mintz 196c5ac9319SYuval Mintz struct qed_rdma_pf_params { 197c5ac9319SYuval Mintz /* Supplied to QED during resource allocation (may affect the ILT and 198c5ac9319SYuval Mintz * the doorbell BAR). 199c5ac9319SYuval Mintz */ 200c5ac9319SYuval Mintz u32 min_dpis; /* number of requested DPIs */ 201c5ac9319SYuval Mintz u32 num_mrs; /* number of requested memory regions */ 202c5ac9319SYuval Mintz u32 num_qps; /* number of requested Queue Pairs */ 203c5ac9319SYuval Mintz u32 num_srqs; /* number of requested SRQ */ 204c5ac9319SYuval Mintz u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */ 205c5ac9319SYuval Mintz u8 gl_pi; /* protocol index */ 206c5ac9319SYuval Mintz 207c5ac9319SYuval Mintz /* Will allocate rate limiters to be used with QPs */ 208c5ac9319SYuval Mintz u8 enable_dcqcn; 209c5ac9319SYuval Mintz }; 210c5ac9319SYuval Mintz 211fe56b9e6SYuval Mintz struct qed_pf_params { 212fe56b9e6SYuval Mintz struct qed_eth_pf_params eth_pf_params; 213c5ac9319SYuval Mintz struct qed_iscsi_pf_params iscsi_pf_params; 214c5ac9319SYuval Mintz struct qed_rdma_pf_params rdma_pf_params; 215fe56b9e6SYuval Mintz }; 216fe56b9e6SYuval Mintz 217fe56b9e6SYuval Mintz enum qed_int_mode { 218fe56b9e6SYuval Mintz QED_INT_MODE_INTA, 219fe56b9e6SYuval Mintz QED_INT_MODE_MSIX, 220fe56b9e6SYuval Mintz QED_INT_MODE_MSI, 221fe56b9e6SYuval Mintz QED_INT_MODE_POLL, 222fe56b9e6SYuval Mintz }; 223fe56b9e6SYuval Mintz 224fe56b9e6SYuval Mintz struct qed_sb_info { 225fe56b9e6SYuval Mintz struct status_block *sb_virt; 226fe56b9e6SYuval Mintz dma_addr_t sb_phys; 227fe56b9e6SYuval Mintz u32 sb_ack; /* Last given ack */ 228fe56b9e6SYuval Mintz u16 igu_sb_id; 229fe56b9e6SYuval Mintz void __iomem *igu_addr; 230fe56b9e6SYuval Mintz u8 flags; 231fe56b9e6SYuval Mintz #define QED_SB_INFO_INIT 0x1 232fe56b9e6SYuval Mintz #define QED_SB_INFO_SETUP 0x2 233fe56b9e6SYuval Mintz 234fe56b9e6SYuval Mintz struct qed_dev *cdev; 235fe56b9e6SYuval Mintz }; 236fe56b9e6SYuval Mintz 237fe56b9e6SYuval Mintz struct qed_dev_info { 238fe56b9e6SYuval Mintz unsigned long pci_mem_start; 239fe56b9e6SYuval Mintz unsigned long pci_mem_end; 240fe56b9e6SYuval Mintz unsigned int pci_irq; 241fe56b9e6SYuval Mintz u8 num_hwfns; 242fe56b9e6SYuval Mintz 243fe56b9e6SYuval Mintz u8 hw_mac[ETH_ALEN]; 244fc48b7a6SYuval Mintz bool is_mf_default; 245fe56b9e6SYuval Mintz 246fe56b9e6SYuval Mintz /* FW version */ 247fe56b9e6SYuval Mintz u16 fw_major; 248fe56b9e6SYuval Mintz u16 fw_minor; 249fe56b9e6SYuval Mintz u16 fw_rev; 250fe56b9e6SYuval Mintz u16 fw_eng; 251fe56b9e6SYuval Mintz 252fe56b9e6SYuval Mintz /* MFW version */ 253fe56b9e6SYuval Mintz u32 mfw_rev; 254fe56b9e6SYuval Mintz 255c5ac9319SYuval Mintz bool rdma_supported; 256c5ac9319SYuval Mintz 257fe56b9e6SYuval Mintz u32 flash_size; 258fe56b9e6SYuval Mintz u8 mf_mode; 259831bfb0eSYuval Mintz bool tx_switching; 260fe56b9e6SYuval Mintz }; 261fe56b9e6SYuval Mintz 262fe56b9e6SYuval Mintz enum qed_sb_type { 263fe56b9e6SYuval Mintz QED_SB_TYPE_L2_QUEUE, 264fe56b9e6SYuval Mintz }; 265fe56b9e6SYuval Mintz 266fe56b9e6SYuval Mintz enum qed_protocol { 267fe56b9e6SYuval Mintz QED_PROTOCOL_ETH, 268c5ac9319SYuval Mintz QED_PROTOCOL_ISCSI, 269fe56b9e6SYuval Mintz }; 270fe56b9e6SYuval Mintz 271*054c67d1SSudarsana Reddy Kalluru enum qed_link_mode_bits { 272*054c67d1SSudarsana Reddy Kalluru QED_LM_FIBRE_BIT = BIT(0), 273*054c67d1SSudarsana Reddy Kalluru QED_LM_Autoneg_BIT = BIT(1), 274*054c67d1SSudarsana Reddy Kalluru QED_LM_Asym_Pause_BIT = BIT(2), 275*054c67d1SSudarsana Reddy Kalluru QED_LM_Pause_BIT = BIT(3), 276*054c67d1SSudarsana Reddy Kalluru QED_LM_1000baseT_Half_BIT = BIT(4), 277*054c67d1SSudarsana Reddy Kalluru QED_LM_1000baseT_Full_BIT = BIT(5), 278*054c67d1SSudarsana Reddy Kalluru QED_LM_10000baseKR_Full_BIT = BIT(6), 279*054c67d1SSudarsana Reddy Kalluru QED_LM_25000baseKR_Full_BIT = BIT(7), 280*054c67d1SSudarsana Reddy Kalluru QED_LM_40000baseLR4_Full_BIT = BIT(8), 281*054c67d1SSudarsana Reddy Kalluru QED_LM_50000baseKR2_Full_BIT = BIT(9), 282*054c67d1SSudarsana Reddy Kalluru QED_LM_100000baseKR4_Full_BIT = BIT(10), 283*054c67d1SSudarsana Reddy Kalluru QED_LM_COUNT = 11 284*054c67d1SSudarsana Reddy Kalluru }; 285*054c67d1SSudarsana Reddy Kalluru 286fe56b9e6SYuval Mintz struct qed_link_params { 287fe56b9e6SYuval Mintz bool link_up; 288fe56b9e6SYuval Mintz 289fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0) 290fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1) 291fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2) 292fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3) 29303dc76caSSudarsana Reddy Kalluru #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4) 294fe56b9e6SYuval Mintz u32 override_flags; 295fe56b9e6SYuval Mintz bool autoneg; 296fe56b9e6SYuval Mintz u32 adv_speeds; 297fe56b9e6SYuval Mintz u32 forced_speed; 298fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0) 299fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_RX_ENABLE BIT(1) 300fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_TX_ENABLE BIT(2) 301fe56b9e6SYuval Mintz u32 pause_config; 30203dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_NONE BIT(0) 30303dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_INT_PHY BIT(1) 30403dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_EXT_PHY BIT(2) 30503dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_EXT BIT(3) 30603dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_MAC BIT(4) 30703dc76caSSudarsana Reddy Kalluru u32 loopback_mode; 308fe56b9e6SYuval Mintz }; 309fe56b9e6SYuval Mintz 310fe56b9e6SYuval Mintz struct qed_link_output { 311fe56b9e6SYuval Mintz bool link_up; 312fe56b9e6SYuval Mintz 313fe56b9e6SYuval Mintz u32 supported_caps; /* In SUPPORTED defs */ 314fe56b9e6SYuval Mintz u32 advertised_caps; /* In ADVERTISED defs */ 315fe56b9e6SYuval Mintz u32 lp_caps; /* In ADVERTISED defs */ 316fe56b9e6SYuval Mintz u32 speed; /* In Mb/s */ 317fe56b9e6SYuval Mintz u8 duplex; /* In DUPLEX defs */ 318fe56b9e6SYuval Mintz u8 port; /* In PORT defs */ 319fe56b9e6SYuval Mintz bool autoneg; 320fe56b9e6SYuval Mintz u32 pause_config; 321fe56b9e6SYuval Mintz }; 322fe56b9e6SYuval Mintz 3231408cc1fSYuval Mintz struct qed_probe_params { 3241408cc1fSYuval Mintz enum qed_protocol protocol; 3251408cc1fSYuval Mintz u32 dp_module; 3261408cc1fSYuval Mintz u8 dp_level; 3271408cc1fSYuval Mintz bool is_vf; 3281408cc1fSYuval Mintz }; 3291408cc1fSYuval Mintz 330fe56b9e6SYuval Mintz #define QED_DRV_VER_STR_SIZE 12 331fe56b9e6SYuval Mintz struct qed_slowpath_params { 332fe56b9e6SYuval Mintz u32 int_mode; 333fe56b9e6SYuval Mintz u8 drv_major; 334fe56b9e6SYuval Mintz u8 drv_minor; 335fe56b9e6SYuval Mintz u8 drv_rev; 336fe56b9e6SYuval Mintz u8 drv_eng; 337fe56b9e6SYuval Mintz u8 name[QED_DRV_VER_STR_SIZE]; 338fe56b9e6SYuval Mintz }; 339fe56b9e6SYuval Mintz 340fe56b9e6SYuval Mintz #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */ 341fe56b9e6SYuval Mintz 342fe56b9e6SYuval Mintz struct qed_int_info { 343fe56b9e6SYuval Mintz struct msix_entry *msix; 344fe56b9e6SYuval Mintz u8 msix_cnt; 345fe56b9e6SYuval Mintz 346fe56b9e6SYuval Mintz /* This should be updated by the protocol driver */ 347fe56b9e6SYuval Mintz u8 used_cnt; 348fe56b9e6SYuval Mintz }; 349fe56b9e6SYuval Mintz 350fe56b9e6SYuval Mintz struct qed_common_cb_ops { 351fe56b9e6SYuval Mintz void (*link_update)(void *dev, 352fe56b9e6SYuval Mintz struct qed_link_output *link); 353fe56b9e6SYuval Mintz }; 354fe56b9e6SYuval Mintz 35503dc76caSSudarsana Reddy Kalluru struct qed_selftest_ops { 35603dc76caSSudarsana Reddy Kalluru /** 35703dc76caSSudarsana Reddy Kalluru * @brief selftest_interrupt - Perform interrupt test 35803dc76caSSudarsana Reddy Kalluru * 35903dc76caSSudarsana Reddy Kalluru * @param cdev 36003dc76caSSudarsana Reddy Kalluru * 36103dc76caSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 36203dc76caSSudarsana Reddy Kalluru */ 36303dc76caSSudarsana Reddy Kalluru int (*selftest_interrupt)(struct qed_dev *cdev); 36403dc76caSSudarsana Reddy Kalluru 36503dc76caSSudarsana Reddy Kalluru /** 36603dc76caSSudarsana Reddy Kalluru * @brief selftest_memory - Perform memory test 36703dc76caSSudarsana Reddy Kalluru * 36803dc76caSSudarsana Reddy Kalluru * @param cdev 36903dc76caSSudarsana Reddy Kalluru * 37003dc76caSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 37103dc76caSSudarsana Reddy Kalluru */ 37203dc76caSSudarsana Reddy Kalluru int (*selftest_memory)(struct qed_dev *cdev); 37303dc76caSSudarsana Reddy Kalluru 37403dc76caSSudarsana Reddy Kalluru /** 37503dc76caSSudarsana Reddy Kalluru * @brief selftest_register - Perform register test 37603dc76caSSudarsana Reddy Kalluru * 37703dc76caSSudarsana Reddy Kalluru * @param cdev 37803dc76caSSudarsana Reddy Kalluru * 37903dc76caSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 38003dc76caSSudarsana Reddy Kalluru */ 38103dc76caSSudarsana Reddy Kalluru int (*selftest_register)(struct qed_dev *cdev); 38203dc76caSSudarsana Reddy Kalluru 38303dc76caSSudarsana Reddy Kalluru /** 38403dc76caSSudarsana Reddy Kalluru * @brief selftest_clock - Perform clock test 38503dc76caSSudarsana Reddy Kalluru * 38603dc76caSSudarsana Reddy Kalluru * @param cdev 38703dc76caSSudarsana Reddy Kalluru * 38803dc76caSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 38903dc76caSSudarsana Reddy Kalluru */ 39003dc76caSSudarsana Reddy Kalluru int (*selftest_clock)(struct qed_dev *cdev); 39103dc76caSSudarsana Reddy Kalluru }; 39203dc76caSSudarsana Reddy Kalluru 393fe56b9e6SYuval Mintz struct qed_common_ops { 39403dc76caSSudarsana Reddy Kalluru struct qed_selftest_ops *selftest; 39503dc76caSSudarsana Reddy Kalluru 396fe56b9e6SYuval Mintz struct qed_dev* (*probe)(struct pci_dev *dev, 3971408cc1fSYuval Mintz struct qed_probe_params *params); 398fe56b9e6SYuval Mintz 399fe56b9e6SYuval Mintz void (*remove)(struct qed_dev *cdev); 400fe56b9e6SYuval Mintz 401fe56b9e6SYuval Mintz int (*set_power_state)(struct qed_dev *cdev, 402fe56b9e6SYuval Mintz pci_power_t state); 403fe56b9e6SYuval Mintz 404fe56b9e6SYuval Mintz void (*set_id)(struct qed_dev *cdev, 405fe56b9e6SYuval Mintz char name[], 406fe56b9e6SYuval Mintz char ver_str[]); 407fe56b9e6SYuval Mintz 408fe56b9e6SYuval Mintz /* Client drivers need to make this call before slowpath_start. 409fe56b9e6SYuval Mintz * PF params required for the call before slowpath_start is 410fe56b9e6SYuval Mintz * documented within the qed_pf_params structure definition. 411fe56b9e6SYuval Mintz */ 412fe56b9e6SYuval Mintz void (*update_pf_params)(struct qed_dev *cdev, 413fe56b9e6SYuval Mintz struct qed_pf_params *params); 414fe56b9e6SYuval Mintz int (*slowpath_start)(struct qed_dev *cdev, 415fe56b9e6SYuval Mintz struct qed_slowpath_params *params); 416fe56b9e6SYuval Mintz 417fe56b9e6SYuval Mintz int (*slowpath_stop)(struct qed_dev *cdev); 418fe56b9e6SYuval Mintz 419fe56b9e6SYuval Mintz /* Requests to use `cnt' interrupts for fastpath. 420fe56b9e6SYuval Mintz * upon success, returns number of interrupts allocated for fastpath. 421fe56b9e6SYuval Mintz */ 422fe56b9e6SYuval Mintz int (*set_fp_int)(struct qed_dev *cdev, 423fe56b9e6SYuval Mintz u16 cnt); 424fe56b9e6SYuval Mintz 425fe56b9e6SYuval Mintz /* Fills `info' with pointers required for utilizing interrupts */ 426fe56b9e6SYuval Mintz int (*get_fp_int)(struct qed_dev *cdev, 427fe56b9e6SYuval Mintz struct qed_int_info *info); 428fe56b9e6SYuval Mintz 429fe56b9e6SYuval Mintz u32 (*sb_init)(struct qed_dev *cdev, 430fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 431fe56b9e6SYuval Mintz void *sb_virt_addr, 432fe56b9e6SYuval Mintz dma_addr_t sb_phy_addr, 433fe56b9e6SYuval Mintz u16 sb_id, 434fe56b9e6SYuval Mintz enum qed_sb_type type); 435fe56b9e6SYuval Mintz 436fe56b9e6SYuval Mintz u32 (*sb_release)(struct qed_dev *cdev, 437fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 438fe56b9e6SYuval Mintz u16 sb_id); 439fe56b9e6SYuval Mintz 440fe56b9e6SYuval Mintz void (*simd_handler_config)(struct qed_dev *cdev, 441fe56b9e6SYuval Mintz void *token, 442fe56b9e6SYuval Mintz int index, 443fe56b9e6SYuval Mintz void (*handler)(void *)); 444fe56b9e6SYuval Mintz 445fe56b9e6SYuval Mintz void (*simd_handler_clean)(struct qed_dev *cdev, 446fe56b9e6SYuval Mintz int index); 447fe7cd2bfSYuval Mintz 448fe7cd2bfSYuval Mintz /** 449fe7cd2bfSYuval Mintz * @brief can_link_change - can the instance change the link or not 450fe7cd2bfSYuval Mintz * 451fe7cd2bfSYuval Mintz * @param cdev 452fe7cd2bfSYuval Mintz * 453fe7cd2bfSYuval Mintz * @return true if link-change is allowed, false otherwise. 454fe7cd2bfSYuval Mintz */ 455fe7cd2bfSYuval Mintz bool (*can_link_change)(struct qed_dev *cdev); 456fe7cd2bfSYuval Mintz 457fe56b9e6SYuval Mintz /** 458fe56b9e6SYuval Mintz * @brief set_link - set links according to params 459fe56b9e6SYuval Mintz * 460fe56b9e6SYuval Mintz * @param cdev 461fe56b9e6SYuval Mintz * @param params - values used to override the default link configuration 462fe56b9e6SYuval Mintz * 463fe56b9e6SYuval Mintz * @return 0 on success, error otherwise. 464fe56b9e6SYuval Mintz */ 465fe56b9e6SYuval Mintz int (*set_link)(struct qed_dev *cdev, 466fe56b9e6SYuval Mintz struct qed_link_params *params); 467fe56b9e6SYuval Mintz 468fe56b9e6SYuval Mintz /** 469fe56b9e6SYuval Mintz * @brief get_link - returns the current link state. 470fe56b9e6SYuval Mintz * 471fe56b9e6SYuval Mintz * @param cdev 472fe56b9e6SYuval Mintz * @param if_link - structure to be filled with current link configuration. 473fe56b9e6SYuval Mintz */ 474fe56b9e6SYuval Mintz void (*get_link)(struct qed_dev *cdev, 475fe56b9e6SYuval Mintz struct qed_link_output *if_link); 476fe56b9e6SYuval Mintz 477fe56b9e6SYuval Mintz /** 478fe56b9e6SYuval Mintz * @brief - drains chip in case Tx completions fail to arrive due to pause. 479fe56b9e6SYuval Mintz * 480fe56b9e6SYuval Mintz * @param cdev 481fe56b9e6SYuval Mintz */ 482fe56b9e6SYuval Mintz int (*drain)(struct qed_dev *cdev); 483fe56b9e6SYuval Mintz 484fe56b9e6SYuval Mintz /** 485fe56b9e6SYuval Mintz * @brief update_msglvl - update module debug level 486fe56b9e6SYuval Mintz * 487fe56b9e6SYuval Mintz * @param cdev 488fe56b9e6SYuval Mintz * @param dp_module 489fe56b9e6SYuval Mintz * @param dp_level 490fe56b9e6SYuval Mintz */ 491fe56b9e6SYuval Mintz void (*update_msglvl)(struct qed_dev *cdev, 492fe56b9e6SYuval Mintz u32 dp_module, 493fe56b9e6SYuval Mintz u8 dp_level); 494fe56b9e6SYuval Mintz 495fe56b9e6SYuval Mintz int (*chain_alloc)(struct qed_dev *cdev, 496fe56b9e6SYuval Mintz enum qed_chain_use_mode intended_use, 497fe56b9e6SYuval Mintz enum qed_chain_mode mode, 498a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 499a91eb52aSYuval Mintz u32 num_elems, 500fe56b9e6SYuval Mintz size_t elem_size, 501fe56b9e6SYuval Mintz struct qed_chain *p_chain); 502fe56b9e6SYuval Mintz 503fe56b9e6SYuval Mintz void (*chain_free)(struct qed_dev *cdev, 504fe56b9e6SYuval Mintz struct qed_chain *p_chain); 50591420b83SSudarsana Kalluru 50691420b83SSudarsana Kalluru /** 507722003acSSudarsana Reddy Kalluru * @brief get_coalesce - Get coalesce parameters in usec 508722003acSSudarsana Reddy Kalluru * 509722003acSSudarsana Reddy Kalluru * @param cdev 510722003acSSudarsana Reddy Kalluru * @param rx_coal - Rx coalesce value in usec 511722003acSSudarsana Reddy Kalluru * @param tx_coal - Tx coalesce value in usec 512722003acSSudarsana Reddy Kalluru * 513722003acSSudarsana Reddy Kalluru */ 514722003acSSudarsana Reddy Kalluru void (*get_coalesce)(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal); 515722003acSSudarsana Reddy Kalluru 516722003acSSudarsana Reddy Kalluru /** 517722003acSSudarsana Reddy Kalluru * @brief set_coalesce - Configure Rx coalesce value in usec 518722003acSSudarsana Reddy Kalluru * 519722003acSSudarsana Reddy Kalluru * @param cdev 520722003acSSudarsana Reddy Kalluru * @param rx_coal - Rx coalesce value in usec 521722003acSSudarsana Reddy Kalluru * @param tx_coal - Tx coalesce value in usec 522722003acSSudarsana Reddy Kalluru * @param qid - Queue index 523722003acSSudarsana Reddy Kalluru * @param sb_id - Status Block Id 524722003acSSudarsana Reddy Kalluru * 525722003acSSudarsana Reddy Kalluru * @return 0 on success, error otherwise. 526722003acSSudarsana Reddy Kalluru */ 527722003acSSudarsana Reddy Kalluru int (*set_coalesce)(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, 528722003acSSudarsana Reddy Kalluru u8 qid, u16 sb_id); 529722003acSSudarsana Reddy Kalluru 530722003acSSudarsana Reddy Kalluru /** 53191420b83SSudarsana Kalluru * @brief set_led - Configure LED mode 53291420b83SSudarsana Kalluru * 53391420b83SSudarsana Kalluru * @param cdev 53491420b83SSudarsana Kalluru * @param mode - LED mode 53591420b83SSudarsana Kalluru * 53691420b83SSudarsana Kalluru * @return 0 on success, error otherwise. 53791420b83SSudarsana Kalluru */ 53891420b83SSudarsana Kalluru int (*set_led)(struct qed_dev *cdev, 53991420b83SSudarsana Kalluru enum qed_led_mode mode); 540fe56b9e6SYuval Mintz }; 541fe56b9e6SYuval Mintz 542fe56b9e6SYuval Mintz #define MASK_FIELD(_name, _value) \ 543fe56b9e6SYuval Mintz ((_value) &= (_name ## _MASK)) 544fe56b9e6SYuval Mintz 545fe56b9e6SYuval Mintz #define FIELD_VALUE(_name, _value) \ 546fe56b9e6SYuval Mintz ((_value & _name ## _MASK) << _name ## _SHIFT) 547fe56b9e6SYuval Mintz 548fe56b9e6SYuval Mintz #define SET_FIELD(value, name, flag) \ 549fe56b9e6SYuval Mintz do { \ 550fe56b9e6SYuval Mintz (value) &= ~(name ## _MASK << name ## _SHIFT); \ 551fe56b9e6SYuval Mintz (value) |= (((u64)flag) << (name ## _SHIFT)); \ 552fe56b9e6SYuval Mintz } while (0) 553fe56b9e6SYuval Mintz 554fe56b9e6SYuval Mintz #define GET_FIELD(value, name) \ 555fe56b9e6SYuval Mintz (((value) >> (name ## _SHIFT)) & name ## _MASK) 556fe56b9e6SYuval Mintz 557fe56b9e6SYuval Mintz /* Debug print definitions */ 558fe56b9e6SYuval Mintz #define DP_ERR(cdev, fmt, ...) \ 559fe56b9e6SYuval Mintz pr_err("[%s:%d(%s)]" fmt, \ 560fe56b9e6SYuval Mintz __func__, __LINE__, \ 561fe56b9e6SYuval Mintz DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 562fe56b9e6SYuval Mintz ## __VA_ARGS__) \ 563fe56b9e6SYuval Mintz 564fe56b9e6SYuval Mintz #define DP_NOTICE(cdev, fmt, ...) \ 565fe56b9e6SYuval Mintz do { \ 566fe56b9e6SYuval Mintz if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \ 567fe56b9e6SYuval Mintz pr_notice("[%s:%d(%s)]" fmt, \ 568fe56b9e6SYuval Mintz __func__, __LINE__, \ 569fe56b9e6SYuval Mintz DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 570fe56b9e6SYuval Mintz ## __VA_ARGS__); \ 571fe56b9e6SYuval Mintz \ 572fe56b9e6SYuval Mintz } \ 573fe56b9e6SYuval Mintz } while (0) 574fe56b9e6SYuval Mintz 575fe56b9e6SYuval Mintz #define DP_INFO(cdev, fmt, ...) \ 576fe56b9e6SYuval Mintz do { \ 577fe56b9e6SYuval Mintz if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \ 578fe56b9e6SYuval Mintz pr_notice("[%s:%d(%s)]" fmt, \ 579fe56b9e6SYuval Mintz __func__, __LINE__, \ 580fe56b9e6SYuval Mintz DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 581fe56b9e6SYuval Mintz ## __VA_ARGS__); \ 582fe56b9e6SYuval Mintz } \ 583fe56b9e6SYuval Mintz } while (0) 584fe56b9e6SYuval Mintz 585fe56b9e6SYuval Mintz #define DP_VERBOSE(cdev, module, fmt, ...) \ 586fe56b9e6SYuval Mintz do { \ 587fe56b9e6SYuval Mintz if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \ 588fe56b9e6SYuval Mintz ((cdev)->dp_module & module))) { \ 589fe56b9e6SYuval Mintz pr_notice("[%s:%d(%s)]" fmt, \ 590fe56b9e6SYuval Mintz __func__, __LINE__, \ 591fe56b9e6SYuval Mintz DP_NAME(cdev) ? DP_NAME(cdev) : "", \ 592fe56b9e6SYuval Mintz ## __VA_ARGS__); \ 593fe56b9e6SYuval Mintz } \ 594fe56b9e6SYuval Mintz } while (0) 595fe56b9e6SYuval Mintz 596fe56b9e6SYuval Mintz enum DP_LEVEL { 597fe56b9e6SYuval Mintz QED_LEVEL_VERBOSE = 0x0, 598fe56b9e6SYuval Mintz QED_LEVEL_INFO = 0x1, 599fe56b9e6SYuval Mintz QED_LEVEL_NOTICE = 0x2, 600fe56b9e6SYuval Mintz QED_LEVEL_ERR = 0x3, 601fe56b9e6SYuval Mintz }; 602fe56b9e6SYuval Mintz 603fe56b9e6SYuval Mintz #define QED_LOG_LEVEL_SHIFT (30) 604fe56b9e6SYuval Mintz #define QED_LOG_VERBOSE_MASK (0x3fffffff) 605fe56b9e6SYuval Mintz #define QED_LOG_INFO_MASK (0x40000000) 606fe56b9e6SYuval Mintz #define QED_LOG_NOTICE_MASK (0x80000000) 607fe56b9e6SYuval Mintz 608fe56b9e6SYuval Mintz enum DP_MODULE { 609fe56b9e6SYuval Mintz QED_MSG_SPQ = 0x10000, 610fe56b9e6SYuval Mintz QED_MSG_STATS = 0x20000, 611fe56b9e6SYuval Mintz QED_MSG_DCB = 0x40000, 612fe56b9e6SYuval Mintz QED_MSG_IOV = 0x80000, 613fe56b9e6SYuval Mintz QED_MSG_SP = 0x100000, 614fe56b9e6SYuval Mintz QED_MSG_STORAGE = 0x200000, 615fe56b9e6SYuval Mintz QED_MSG_CXT = 0x800000, 616fe56b9e6SYuval Mintz QED_MSG_ILT = 0x2000000, 617fe56b9e6SYuval Mintz QED_MSG_ROCE = 0x4000000, 618fe56b9e6SYuval Mintz QED_MSG_DEBUG = 0x8000000, 619fe56b9e6SYuval Mintz /* to be added...up to 0x8000000 */ 620fe56b9e6SYuval Mintz }; 621fe56b9e6SYuval Mintz 622fc48b7a6SYuval Mintz enum qed_mf_mode { 623fc48b7a6SYuval Mintz QED_MF_DEFAULT, 624fc48b7a6SYuval Mintz QED_MF_OVLAN, 625fc48b7a6SYuval Mintz QED_MF_NPAR, 626fc48b7a6SYuval Mintz }; 627fc48b7a6SYuval Mintz 628fe56b9e6SYuval Mintz struct qed_eth_stats { 629fe56b9e6SYuval Mintz u64 no_buff_discards; 630fe56b9e6SYuval Mintz u64 packet_too_big_discard; 631fe56b9e6SYuval Mintz u64 ttl0_discard; 632fe56b9e6SYuval Mintz u64 rx_ucast_bytes; 633fe56b9e6SYuval Mintz u64 rx_mcast_bytes; 634fe56b9e6SYuval Mintz u64 rx_bcast_bytes; 635fe56b9e6SYuval Mintz u64 rx_ucast_pkts; 636fe56b9e6SYuval Mintz u64 rx_mcast_pkts; 637fe56b9e6SYuval Mintz u64 rx_bcast_pkts; 638fe56b9e6SYuval Mintz u64 mftag_filter_discards; 639fe56b9e6SYuval Mintz u64 mac_filter_discards; 640fe56b9e6SYuval Mintz u64 tx_ucast_bytes; 641fe56b9e6SYuval Mintz u64 tx_mcast_bytes; 642fe56b9e6SYuval Mintz u64 tx_bcast_bytes; 643fe56b9e6SYuval Mintz u64 tx_ucast_pkts; 644fe56b9e6SYuval Mintz u64 tx_mcast_pkts; 645fe56b9e6SYuval Mintz u64 tx_bcast_pkts; 646fe56b9e6SYuval Mintz u64 tx_err_drop_pkts; 647fe56b9e6SYuval Mintz u64 tpa_coalesced_pkts; 648fe56b9e6SYuval Mintz u64 tpa_coalesced_events; 649fe56b9e6SYuval Mintz u64 tpa_aborts_num; 650fe56b9e6SYuval Mintz u64 tpa_not_coalesced_pkts; 651fe56b9e6SYuval Mintz u64 tpa_coalesced_bytes; 652fe56b9e6SYuval Mintz 653fe56b9e6SYuval Mintz /* port */ 654fe56b9e6SYuval Mintz u64 rx_64_byte_packets; 655d4967cf3SYuval Mintz u64 rx_65_to_127_byte_packets; 656d4967cf3SYuval Mintz u64 rx_128_to_255_byte_packets; 657d4967cf3SYuval Mintz u64 rx_256_to_511_byte_packets; 658d4967cf3SYuval Mintz u64 rx_512_to_1023_byte_packets; 659d4967cf3SYuval Mintz u64 rx_1024_to_1518_byte_packets; 660d4967cf3SYuval Mintz u64 rx_1519_to_1522_byte_packets; 661d4967cf3SYuval Mintz u64 rx_1519_to_2047_byte_packets; 662d4967cf3SYuval Mintz u64 rx_2048_to_4095_byte_packets; 663d4967cf3SYuval Mintz u64 rx_4096_to_9216_byte_packets; 664d4967cf3SYuval Mintz u64 rx_9217_to_16383_byte_packets; 665fe56b9e6SYuval Mintz u64 rx_crc_errors; 666fe56b9e6SYuval Mintz u64 rx_mac_crtl_frames; 667fe56b9e6SYuval Mintz u64 rx_pause_frames; 668fe56b9e6SYuval Mintz u64 rx_pfc_frames; 669fe56b9e6SYuval Mintz u64 rx_align_errors; 670fe56b9e6SYuval Mintz u64 rx_carrier_errors; 671fe56b9e6SYuval Mintz u64 rx_oversize_packets; 672fe56b9e6SYuval Mintz u64 rx_jabbers; 673fe56b9e6SYuval Mintz u64 rx_undersize_packets; 674fe56b9e6SYuval Mintz u64 rx_fragments; 675fe56b9e6SYuval Mintz u64 tx_64_byte_packets; 676fe56b9e6SYuval Mintz u64 tx_65_to_127_byte_packets; 677fe56b9e6SYuval Mintz u64 tx_128_to_255_byte_packets; 678fe56b9e6SYuval Mintz u64 tx_256_to_511_byte_packets; 679fe56b9e6SYuval Mintz u64 tx_512_to_1023_byte_packets; 680fe56b9e6SYuval Mintz u64 tx_1024_to_1518_byte_packets; 681fe56b9e6SYuval Mintz u64 tx_1519_to_2047_byte_packets; 682fe56b9e6SYuval Mintz u64 tx_2048_to_4095_byte_packets; 683fe56b9e6SYuval Mintz u64 tx_4096_to_9216_byte_packets; 684fe56b9e6SYuval Mintz u64 tx_9217_to_16383_byte_packets; 685fe56b9e6SYuval Mintz u64 tx_pause_frames; 686fe56b9e6SYuval Mintz u64 tx_pfc_frames; 687fe56b9e6SYuval Mintz u64 tx_lpi_entry_count; 688fe56b9e6SYuval Mintz u64 tx_total_collisions; 689fe56b9e6SYuval Mintz u64 brb_truncates; 690fe56b9e6SYuval Mintz u64 brb_discards; 691fe56b9e6SYuval Mintz u64 rx_mac_bytes; 692fe56b9e6SYuval Mintz u64 rx_mac_uc_packets; 693fe56b9e6SYuval Mintz u64 rx_mac_mc_packets; 694fe56b9e6SYuval Mintz u64 rx_mac_bc_packets; 695fe56b9e6SYuval Mintz u64 rx_mac_frames_ok; 696fe56b9e6SYuval Mintz u64 tx_mac_bytes; 697fe56b9e6SYuval Mintz u64 tx_mac_uc_packets; 698fe56b9e6SYuval Mintz u64 tx_mac_mc_packets; 699fe56b9e6SYuval Mintz u64 tx_mac_bc_packets; 700fe56b9e6SYuval Mintz u64 tx_mac_ctrl_frames; 701fe56b9e6SYuval Mintz }; 702fe56b9e6SYuval Mintz 703fe56b9e6SYuval Mintz #define QED_SB_IDX 0x0002 704fe56b9e6SYuval Mintz 705fe56b9e6SYuval Mintz #define RX_PI 0 706fe56b9e6SYuval Mintz #define TX_PI(tc) (RX_PI + 1 + tc) 707fe56b9e6SYuval Mintz 7084ac801b7SYuval Mintz struct qed_sb_cnt_info { 7094ac801b7SYuval Mintz int sb_cnt; 7104ac801b7SYuval Mintz int sb_iov_cnt; 7114ac801b7SYuval Mintz int sb_free_blk; 7124ac801b7SYuval Mintz }; 7134ac801b7SYuval Mintz 714fe56b9e6SYuval Mintz static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info) 715fe56b9e6SYuval Mintz { 716fe56b9e6SYuval Mintz u32 prod = 0; 717fe56b9e6SYuval Mintz u16 rc = 0; 718fe56b9e6SYuval Mintz 719fe56b9e6SYuval Mintz prod = le32_to_cpu(sb_info->sb_virt->prod_index) & 720fe56b9e6SYuval Mintz STATUS_BLOCK_PROD_INDEX_MASK; 721fe56b9e6SYuval Mintz if (sb_info->sb_ack != prod) { 722fe56b9e6SYuval Mintz sb_info->sb_ack = prod; 723fe56b9e6SYuval Mintz rc |= QED_SB_IDX; 724fe56b9e6SYuval Mintz } 725fe56b9e6SYuval Mintz 726fe56b9e6SYuval Mintz /* Let SB update */ 727fe56b9e6SYuval Mintz mmiowb(); 728fe56b9e6SYuval Mintz return rc; 729fe56b9e6SYuval Mintz } 730fe56b9e6SYuval Mintz 731fe56b9e6SYuval Mintz /** 732fe56b9e6SYuval Mintz * 733fe56b9e6SYuval Mintz * @brief This function creates an update command for interrupts that is 734fe56b9e6SYuval Mintz * written to the IGU. 735fe56b9e6SYuval Mintz * 736fe56b9e6SYuval Mintz * @param sb_info - This is the structure allocated and 737fe56b9e6SYuval Mintz * initialized per status block. Assumption is 738fe56b9e6SYuval Mintz * that it was initialized using qed_sb_init 739fe56b9e6SYuval Mintz * @param int_cmd - Enable/Disable/Nop 740fe56b9e6SYuval Mintz * @param upd_flg - whether igu consumer should be 741fe56b9e6SYuval Mintz * updated. 742fe56b9e6SYuval Mintz * 743fe56b9e6SYuval Mintz * @return inline void 744fe56b9e6SYuval Mintz */ 745fe56b9e6SYuval Mintz static inline void qed_sb_ack(struct qed_sb_info *sb_info, 746fe56b9e6SYuval Mintz enum igu_int_cmd int_cmd, 747fe56b9e6SYuval Mintz u8 upd_flg) 748fe56b9e6SYuval Mintz { 749fe56b9e6SYuval Mintz struct igu_prod_cons_update igu_ack = { 0 }; 750fe56b9e6SYuval Mintz 751fe56b9e6SYuval Mintz igu_ack.sb_id_and_flags = 752fe56b9e6SYuval Mintz ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 753fe56b9e6SYuval Mintz (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 754fe56b9e6SYuval Mintz (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 755fe56b9e6SYuval Mintz (IGU_SEG_ACCESS_REG << 756fe56b9e6SYuval Mintz IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 757fe56b9e6SYuval Mintz 758fe56b9e6SYuval Mintz DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags); 759fe56b9e6SYuval Mintz 760fe56b9e6SYuval Mintz /* Both segments (interrupts & acks) are written to same place address; 761fe56b9e6SYuval Mintz * Need to guarantee all commands will be received (in-order) by HW. 762fe56b9e6SYuval Mintz */ 763fe56b9e6SYuval Mintz mmiowb(); 764fe56b9e6SYuval Mintz barrier(); 765fe56b9e6SYuval Mintz } 766fe56b9e6SYuval Mintz 767fe56b9e6SYuval Mintz static inline void __internal_ram_wr(void *p_hwfn, 768fe56b9e6SYuval Mintz void __iomem *addr, 769fe56b9e6SYuval Mintz int size, 770fe56b9e6SYuval Mintz u32 *data) 771fe56b9e6SYuval Mintz 772fe56b9e6SYuval Mintz { 773fe56b9e6SYuval Mintz unsigned int i; 774fe56b9e6SYuval Mintz 775fe56b9e6SYuval Mintz for (i = 0; i < size / sizeof(*data); i++) 776fe56b9e6SYuval Mintz DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]); 777fe56b9e6SYuval Mintz } 778fe56b9e6SYuval Mintz 779fe56b9e6SYuval Mintz static inline void internal_ram_wr(void __iomem *addr, 780fe56b9e6SYuval Mintz int size, 781fe56b9e6SYuval Mintz u32 *data) 782fe56b9e6SYuval Mintz { 783fe56b9e6SYuval Mintz __internal_ram_wr(NULL, addr, size, data); 784fe56b9e6SYuval Mintz } 785fe56b9e6SYuval Mintz 7868c5ebd0cSSudarsana Reddy Kalluru enum qed_rss_caps { 7878c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV4 = 0x1, 7888c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV6 = 0x2, 7898c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV4_TCP = 0x4, 7908c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV6_TCP = 0x8, 7918c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV4_UDP = 0x10, 7928c5ebd0cSSudarsana Reddy Kalluru QED_RSS_IPV6_UDP = 0x20, 7938c5ebd0cSSudarsana Reddy Kalluru }; 7948c5ebd0cSSudarsana Reddy Kalluru 7958c5ebd0cSSudarsana Reddy Kalluru #define QED_RSS_IND_TABLE_SIZE 128 7968c5ebd0cSSudarsana Reddy Kalluru #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */ 797fe56b9e6SYuval Mintz #endif 798