xref: /linux/include/linux/qed/qed_if.h (revision 03ab8e6297acd1bc0eedaa050e2a1635c576fd11)
11f4d4ed6SAlexander Lobakin /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver
3e8f1cb50SMintz, Yuval  * Copyright (c) 2015-2017  QLogic Corporation
4663eacd8SAlexander Lobakin  * Copyright (c) 2019-2020 Marvell International Ltd.
5fe56b9e6SYuval Mintz  */
6fe56b9e6SYuval Mintz 
7fe56b9e6SYuval Mintz #ifndef _QED_IF_H
8fe56b9e6SYuval Mintz #define _QED_IF_H
9fe56b9e6SYuval Mintz 
10cc69837fSJakub Kicinski #include <linux/ethtool.h>
11fe56b9e6SYuval Mintz #include <linux/types.h>
12fe56b9e6SYuval Mintz #include <linux/interrupt.h>
13fe56b9e6SYuval Mintz #include <linux/netdevice.h>
14fe56b9e6SYuval Mintz #include <linux/pci.h>
15fe56b9e6SYuval Mintz #include <linux/skbuff.h>
16fe56b9e6SYuval Mintz #include <asm/byteorder.h>
17fe56b9e6SYuval Mintz #include <linux/io.h>
18fe56b9e6SYuval Mintz #include <linux/compiler.h>
19fe56b9e6SYuval Mintz #include <linux/kernel.h>
20fe56b9e6SYuval Mintz #include <linux/list.h>
21fe56b9e6SYuval Mintz #include <linux/slab.h>
22fe56b9e6SYuval Mintz #include <linux/qed/common_hsi.h>
23fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h>
2436907cd5SAriel Elior #include <linux/io-64-nonatomic-lo-hi.h>
25755f982bSIgor Russkikh #include <net/devlink.h>
26fe56b9e6SYuval Mintz 
273a6f5d0cSNikolay Assa #define QED_TX_SWS_TIMER_DFLT  500
28a64aa0a8SPrabhakar Kushwaha #define QED_TWO_MSL_TIMER_DFLT 4000
293a6f5d0cSNikolay Assa 
3039651abdSSudarsana Reddy Kalluru enum dcbx_protocol_type {
3139651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_ISCSI,
3239651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_FCOE,
3339651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_ROCE,
3439651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_ROCE_V2,
3539651abdSSudarsana Reddy Kalluru 	DCBX_PROTOCOL_ETH,
3639651abdSSudarsana Reddy Kalluru 	DCBX_MAX_PROTOCOL_TYPE
3739651abdSSudarsana Reddy Kalluru };
3839651abdSSudarsana Reddy Kalluru 
3951ff1725SRam Amrani #define QED_ROCE_PROTOCOL_INDEX (3)
4051ff1725SRam Amrani 
416ad8c632SSudarsana Reddy Kalluru #define QED_LLDP_CHASSIS_ID_STAT_LEN 4
426ad8c632SSudarsana Reddy Kalluru #define QED_LLDP_PORT_ID_STAT_LEN 4
436ad8c632SSudarsana Reddy Kalluru #define QED_DCBX_MAX_APP_PROTOCOL 32
446ad8c632SSudarsana Reddy Kalluru #define QED_MAX_PFC_PRIORITIES 8
456ad8c632SSudarsana Reddy Kalluru #define QED_DCBX_DSCP_SIZE 64
466ad8c632SSudarsana Reddy Kalluru 
476ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_remote {
486ad8c632SSudarsana Reddy Kalluru 	u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
496ad8c632SSudarsana Reddy Kalluru 	u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
506ad8c632SSudarsana Reddy Kalluru 	bool enable_rx;
516ad8c632SSudarsana Reddy Kalluru 	bool enable_tx;
526ad8c632SSudarsana Reddy Kalluru 	u32 tx_interval;
536ad8c632SSudarsana Reddy Kalluru 	u32 max_credit;
546ad8c632SSudarsana Reddy Kalluru };
556ad8c632SSudarsana Reddy Kalluru 
566ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_lldp_local {
576ad8c632SSudarsana Reddy Kalluru 	u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
586ad8c632SSudarsana Reddy Kalluru 	u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
596ad8c632SSudarsana Reddy Kalluru };
606ad8c632SSudarsana Reddy Kalluru 
616ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_app_prio {
626ad8c632SSudarsana Reddy Kalluru 	u8 roce;
636ad8c632SSudarsana Reddy Kalluru 	u8 roce_v2;
646ad8c632SSudarsana Reddy Kalluru 	u8 fcoe;
656ad8c632SSudarsana Reddy Kalluru 	u8 iscsi;
666ad8c632SSudarsana Reddy Kalluru 	u8 eth;
676ad8c632SSudarsana Reddy Kalluru };
686ad8c632SSudarsana Reddy Kalluru 
696ad8c632SSudarsana Reddy Kalluru struct qed_dbcx_pfc_params {
706ad8c632SSudarsana Reddy Kalluru 	bool willing;
716ad8c632SSudarsana Reddy Kalluru 	bool enabled;
726ad8c632SSudarsana Reddy Kalluru 	u8 prio[QED_MAX_PFC_PRIORITIES];
736ad8c632SSudarsana Reddy Kalluru 	u8 max_tc;
746ad8c632SSudarsana Reddy Kalluru };
756ad8c632SSudarsana Reddy Kalluru 
7659bcb797SSudarsana Reddy Kalluru enum qed_dcbx_sf_ieee_type {
7759bcb797SSudarsana Reddy Kalluru 	QED_DCBX_SF_IEEE_ETHTYPE,
7859bcb797SSudarsana Reddy Kalluru 	QED_DCBX_SF_IEEE_TCP_PORT,
7959bcb797SSudarsana Reddy Kalluru 	QED_DCBX_SF_IEEE_UDP_PORT,
8059bcb797SSudarsana Reddy Kalluru 	QED_DCBX_SF_IEEE_TCP_UDP_PORT
8159bcb797SSudarsana Reddy Kalluru };
8259bcb797SSudarsana Reddy Kalluru 
836ad8c632SSudarsana Reddy Kalluru struct qed_app_entry {
846ad8c632SSudarsana Reddy Kalluru 	bool ethtype;
8559bcb797SSudarsana Reddy Kalluru 	enum qed_dcbx_sf_ieee_type sf_ieee;
866ad8c632SSudarsana Reddy Kalluru 	bool enabled;
876ad8c632SSudarsana Reddy Kalluru 	u8 prio;
886ad8c632SSudarsana Reddy Kalluru 	u16 proto_id;
896ad8c632SSudarsana Reddy Kalluru 	enum dcbx_protocol_type proto_type;
906ad8c632SSudarsana Reddy Kalluru };
916ad8c632SSudarsana Reddy Kalluru 
926ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_params {
936ad8c632SSudarsana Reddy Kalluru 	struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
946ad8c632SSudarsana Reddy Kalluru 	u16 num_app_entries;
956ad8c632SSudarsana Reddy Kalluru 	bool app_willing;
966ad8c632SSudarsana Reddy Kalluru 	bool app_valid;
976ad8c632SSudarsana Reddy Kalluru 	bool app_error;
986ad8c632SSudarsana Reddy Kalluru 	bool ets_willing;
996ad8c632SSudarsana Reddy Kalluru 	bool ets_enabled;
1006ad8c632SSudarsana Reddy Kalluru 	bool ets_cbs;
1016ad8c632SSudarsana Reddy Kalluru 	bool valid;
1026ad8c632SSudarsana Reddy Kalluru 	u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
1036ad8c632SSudarsana Reddy Kalluru 	u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
1046ad8c632SSudarsana Reddy Kalluru 	u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
1056ad8c632SSudarsana Reddy Kalluru 	struct qed_dbcx_pfc_params pfc;
1066ad8c632SSudarsana Reddy Kalluru 	u8 max_ets_tc;
1076ad8c632SSudarsana Reddy Kalluru };
1086ad8c632SSudarsana Reddy Kalluru 
1096ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_admin_params {
1106ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_params params;
1116ad8c632SSudarsana Reddy Kalluru 	bool valid;
1126ad8c632SSudarsana Reddy Kalluru };
1136ad8c632SSudarsana Reddy Kalluru 
1146ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_remote_params {
1156ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_params params;
1166ad8c632SSudarsana Reddy Kalluru 	bool valid;
1176ad8c632SSudarsana Reddy Kalluru };
1186ad8c632SSudarsana Reddy Kalluru 
1196ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_operational_params {
1206ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_app_prio app_prio;
1216ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_params params;
1226ad8c632SSudarsana Reddy Kalluru 	bool valid;
1236ad8c632SSudarsana Reddy Kalluru 	bool enabled;
1246ad8c632SSudarsana Reddy Kalluru 	bool ieee;
1256ad8c632SSudarsana Reddy Kalluru 	bool cee;
12649632b58Ssudarsana.kalluru@cavium.com 	bool local;
1276ad8c632SSudarsana Reddy Kalluru 	u32 err;
1286ad8c632SSudarsana Reddy Kalluru };
1296ad8c632SSudarsana Reddy Kalluru 
1306ad8c632SSudarsana Reddy Kalluru struct qed_dcbx_get {
1316ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_operational_params operational;
1326ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_lldp_remote lldp_remote;
1336ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_lldp_local lldp_local;
1346ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_remote_params remote;
1356ad8c632SSudarsana Reddy Kalluru 	struct qed_dcbx_admin_params local;
1366ad8c632SSudarsana Reddy Kalluru };
1376ad8c632SSudarsana Reddy Kalluru 
13820675b37SMintz, Yuval enum qed_nvm_images {
13920675b37SMintz, Yuval 	QED_NVM_IMAGE_ISCSI_CFG,
14020675b37SMintz, Yuval 	QED_NVM_IMAGE_FCOE_CFG,
1418a52bbabSMichal Kalderon 	QED_NVM_IMAGE_MDUMP,
1421ac4329aSDenis Bolotin 	QED_NVM_IMAGE_NVM_CFG1,
1431ac4329aSDenis Bolotin 	QED_NVM_IMAGE_DEFAULT_CFG,
1441ac4329aSDenis Bolotin 	QED_NVM_IMAGE_NVM_META,
14520675b37SMintz, Yuval };
14620675b37SMintz, Yuval 
147645874e5SSudarsana Reddy Kalluru struct qed_link_eee_params {
148645874e5SSudarsana Reddy Kalluru 	u32 tx_lpi_timer;
149645874e5SSudarsana Reddy Kalluru #define QED_EEE_1G_ADV		BIT(0)
150645874e5SSudarsana Reddy Kalluru #define QED_EEE_10G_ADV		BIT(1)
151645874e5SSudarsana Reddy Kalluru 
152645874e5SSudarsana Reddy Kalluru 	/* Capabilities are represented using QED_EEE_*_ADV values */
153645874e5SSudarsana Reddy Kalluru 	u8 adv_caps;
154645874e5SSudarsana Reddy Kalluru 	u8 lp_adv_caps;
155645874e5SSudarsana Reddy Kalluru 	bool enable;
156645874e5SSudarsana Reddy Kalluru 	bool tx_lpi_enable;
157645874e5SSudarsana Reddy Kalluru };
158645874e5SSudarsana Reddy Kalluru 
15991420b83SSudarsana Kalluru enum qed_led_mode {
16091420b83SSudarsana Kalluru 	QED_LED_MODE_OFF,
16191420b83SSudarsana Kalluru 	QED_LED_MODE_ON,
16291420b83SSudarsana Kalluru 	QED_LED_MODE_RESTORE
16391420b83SSudarsana Kalluru };
16491420b83SSudarsana Kalluru 
1652528c389SSudarsana Reddy Kalluru struct qed_mfw_tlv_eth {
1662528c389SSudarsana Reddy Kalluru 	u16 lso_maxoff_size;
1672528c389SSudarsana Reddy Kalluru 	bool lso_maxoff_size_set;
1682528c389SSudarsana Reddy Kalluru 	u16 lso_minseg_size;
1692528c389SSudarsana Reddy Kalluru 	bool lso_minseg_size_set;
1702528c389SSudarsana Reddy Kalluru 	u8 prom_mode;
1712528c389SSudarsana Reddy Kalluru 	bool prom_mode_set;
1722528c389SSudarsana Reddy Kalluru 	u16 tx_descr_size;
1732528c389SSudarsana Reddy Kalluru 	bool tx_descr_size_set;
1742528c389SSudarsana Reddy Kalluru 	u16 rx_descr_size;
1752528c389SSudarsana Reddy Kalluru 	bool rx_descr_size_set;
1762528c389SSudarsana Reddy Kalluru 	u16 netq_count;
1772528c389SSudarsana Reddy Kalluru 	bool netq_count_set;
1782528c389SSudarsana Reddy Kalluru 	u32 tcp4_offloads;
1792528c389SSudarsana Reddy Kalluru 	bool tcp4_offloads_set;
1802528c389SSudarsana Reddy Kalluru 	u32 tcp6_offloads;
1812528c389SSudarsana Reddy Kalluru 	bool tcp6_offloads_set;
1822528c389SSudarsana Reddy Kalluru 	u16 tx_descr_qdepth;
1832528c389SSudarsana Reddy Kalluru 	bool tx_descr_qdepth_set;
1842528c389SSudarsana Reddy Kalluru 	u16 rx_descr_qdepth;
1852528c389SSudarsana Reddy Kalluru 	bool rx_descr_qdepth_set;
1862528c389SSudarsana Reddy Kalluru 	u8 iov_offload;
1872528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_IOV_OFFLOAD_NONE            (0)
1882528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE      (1)
1892528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_IOV_OFFLOAD_VEB             (2)
1902528c389SSudarsana Reddy Kalluru #define QED_MFW_TLV_IOV_OFFLOAD_VEPA            (3)
1912528c389SSudarsana Reddy Kalluru 	bool iov_offload_set;
1922528c389SSudarsana Reddy Kalluru 	u8 txqs_empty;
1932528c389SSudarsana Reddy Kalluru 	bool txqs_empty_set;
1942528c389SSudarsana Reddy Kalluru 	u8 rxqs_empty;
1952528c389SSudarsana Reddy Kalluru 	bool rxqs_empty_set;
1962528c389SSudarsana Reddy Kalluru 	u8 num_txqs_full;
1972528c389SSudarsana Reddy Kalluru 	bool num_txqs_full_set;
1982528c389SSudarsana Reddy Kalluru 	u8 num_rxqs_full;
1992528c389SSudarsana Reddy Kalluru 	bool num_rxqs_full_set;
2002528c389SSudarsana Reddy Kalluru };
2012528c389SSudarsana Reddy Kalluru 
202f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_TIME_SIZE	14
203f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_time {
204f240b688SSudarsana Reddy Kalluru 	bool b_set;
205f240b688SSudarsana Reddy Kalluru 	u8 month;
206f240b688SSudarsana Reddy Kalluru 	u8 day;
207f240b688SSudarsana Reddy Kalluru 	u8 hour;
208f240b688SSudarsana Reddy Kalluru 	u8 min;
209f240b688SSudarsana Reddy Kalluru 	u16 msec;
210f240b688SSudarsana Reddy Kalluru 	u16 usec;
211f240b688SSudarsana Reddy Kalluru };
212f240b688SSudarsana Reddy Kalluru 
213f240b688SSudarsana Reddy Kalluru struct qed_mfw_tlv_fcoe {
214f240b688SSudarsana Reddy Kalluru 	u8 scsi_timeout;
215f240b688SSudarsana Reddy Kalluru 	bool scsi_timeout_set;
216f240b688SSudarsana Reddy Kalluru 	u32 rt_tov;
217f240b688SSudarsana Reddy Kalluru 	bool rt_tov_set;
218f240b688SSudarsana Reddy Kalluru 	u32 ra_tov;
219f240b688SSudarsana Reddy Kalluru 	bool ra_tov_set;
220f240b688SSudarsana Reddy Kalluru 	u32 ed_tov;
221f240b688SSudarsana Reddy Kalluru 	bool ed_tov_set;
222f240b688SSudarsana Reddy Kalluru 	u32 cr_tov;
223f240b688SSudarsana Reddy Kalluru 	bool cr_tov_set;
224f240b688SSudarsana Reddy Kalluru 	u8 boot_type;
225f240b688SSudarsana Reddy Kalluru 	bool boot_type_set;
226f240b688SSudarsana Reddy Kalluru 	u8 npiv_state;
227f240b688SSudarsana Reddy Kalluru 	bool npiv_state_set;
228f240b688SSudarsana Reddy Kalluru 	u32 num_npiv_ids;
229f240b688SSudarsana Reddy Kalluru 	bool num_npiv_ids_set;
230f240b688SSudarsana Reddy Kalluru 	u8 switch_name[8];
231f240b688SSudarsana Reddy Kalluru 	bool switch_name_set;
232f240b688SSudarsana Reddy Kalluru 	u16 switch_portnum;
233f240b688SSudarsana Reddy Kalluru 	bool switch_portnum_set;
234f240b688SSudarsana Reddy Kalluru 	u8 switch_portid[3];
235f240b688SSudarsana Reddy Kalluru 	bool switch_portid_set;
236f240b688SSudarsana Reddy Kalluru 	u8 vendor_name[8];
237f240b688SSudarsana Reddy Kalluru 	bool vendor_name_set;
238f240b688SSudarsana Reddy Kalluru 	u8 switch_model[8];
239f240b688SSudarsana Reddy Kalluru 	bool switch_model_set;
240f240b688SSudarsana Reddy Kalluru 	u8 switch_fw_version[8];
241f240b688SSudarsana Reddy Kalluru 	bool switch_fw_version_set;
242f240b688SSudarsana Reddy Kalluru 	u8 qos_pri;
243f240b688SSudarsana Reddy Kalluru 	bool qos_pri_set;
244f240b688SSudarsana Reddy Kalluru 	u8 port_alias[3];
245f240b688SSudarsana Reddy Kalluru 	bool port_alias_set;
246f240b688SSudarsana Reddy Kalluru 	u8 port_state;
247f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_PORT_STATE_OFFLINE  (0)
248f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_PORT_STATE_LOOP             (1)
249f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_PORT_STATE_P2P              (2)
250f240b688SSudarsana Reddy Kalluru #define QED_MFW_TLV_PORT_STATE_FABRIC           (3)
251f240b688SSudarsana Reddy Kalluru 	bool port_state_set;
252f240b688SSudarsana Reddy Kalluru 	u16 fip_tx_descr_size;
253f240b688SSudarsana Reddy Kalluru 	bool fip_tx_descr_size_set;
254f240b688SSudarsana Reddy Kalluru 	u16 fip_rx_descr_size;
255f240b688SSudarsana Reddy Kalluru 	bool fip_rx_descr_size_set;
256f240b688SSudarsana Reddy Kalluru 	u16 link_failures;
257f240b688SSudarsana Reddy Kalluru 	bool link_failures_set;
258f240b688SSudarsana Reddy Kalluru 	u8 fcoe_boot_progress;
259f240b688SSudarsana Reddy Kalluru 	bool fcoe_boot_progress_set;
260f240b688SSudarsana Reddy Kalluru 	u64 rx_bcast;
261f240b688SSudarsana Reddy Kalluru 	bool rx_bcast_set;
262f240b688SSudarsana Reddy Kalluru 	u64 tx_bcast;
263f240b688SSudarsana Reddy Kalluru 	bool tx_bcast_set;
264f240b688SSudarsana Reddy Kalluru 	u16 fcoe_txq_depth;
265f240b688SSudarsana Reddy Kalluru 	bool fcoe_txq_depth_set;
266f240b688SSudarsana Reddy Kalluru 	u16 fcoe_rxq_depth;
267f240b688SSudarsana Reddy Kalluru 	bool fcoe_rxq_depth_set;
268f240b688SSudarsana Reddy Kalluru 	u64 fcoe_rx_frames;
269f240b688SSudarsana Reddy Kalluru 	bool fcoe_rx_frames_set;
270f240b688SSudarsana Reddy Kalluru 	u64 fcoe_rx_bytes;
271f240b688SSudarsana Reddy Kalluru 	bool fcoe_rx_bytes_set;
272f240b688SSudarsana Reddy Kalluru 	u64 fcoe_tx_frames;
273f240b688SSudarsana Reddy Kalluru 	bool fcoe_tx_frames_set;
274f240b688SSudarsana Reddy Kalluru 	u64 fcoe_tx_bytes;
275f240b688SSudarsana Reddy Kalluru 	bool fcoe_tx_bytes_set;
276f240b688SSudarsana Reddy Kalluru 	u16 crc_count;
277f240b688SSudarsana Reddy Kalluru 	bool crc_count_set;
278f240b688SSudarsana Reddy Kalluru 	u32 crc_err_src_fcid[5];
279f240b688SSudarsana Reddy Kalluru 	bool crc_err_src_fcid_set[5];
280f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time crc_err[5];
281f240b688SSudarsana Reddy Kalluru 	u16 losync_err;
282f240b688SSudarsana Reddy Kalluru 	bool losync_err_set;
283f240b688SSudarsana Reddy Kalluru 	u16 losig_err;
284f240b688SSudarsana Reddy Kalluru 	bool losig_err_set;
285f240b688SSudarsana Reddy Kalluru 	u16 primtive_err;
286f240b688SSudarsana Reddy Kalluru 	bool primtive_err_set;
287f240b688SSudarsana Reddy Kalluru 	u16 disparity_err;
288f240b688SSudarsana Reddy Kalluru 	bool disparity_err_set;
289f240b688SSudarsana Reddy Kalluru 	u16 code_violation_err;
290f240b688SSudarsana Reddy Kalluru 	bool code_violation_err_set;
291f240b688SSudarsana Reddy Kalluru 	u32 flogi_param[4];
292f240b688SSudarsana Reddy Kalluru 	bool flogi_param_set[4];
293f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time flogi_tstamp;
294f240b688SSudarsana Reddy Kalluru 	u32 flogi_acc_param[4];
295f240b688SSudarsana Reddy Kalluru 	bool flogi_acc_param_set[4];
296f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time flogi_acc_tstamp;
297f240b688SSudarsana Reddy Kalluru 	u32 flogi_rjt;
298f240b688SSudarsana Reddy Kalluru 	bool flogi_rjt_set;
299f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time flogi_rjt_tstamp;
300f240b688SSudarsana Reddy Kalluru 	u32 fdiscs;
301f240b688SSudarsana Reddy Kalluru 	bool fdiscs_set;
302f240b688SSudarsana Reddy Kalluru 	u8 fdisc_acc;
303f240b688SSudarsana Reddy Kalluru 	bool fdisc_acc_set;
304f240b688SSudarsana Reddy Kalluru 	u8 fdisc_rjt;
305f240b688SSudarsana Reddy Kalluru 	bool fdisc_rjt_set;
306f240b688SSudarsana Reddy Kalluru 	u8 plogi;
307f240b688SSudarsana Reddy Kalluru 	bool plogi_set;
308f240b688SSudarsana Reddy Kalluru 	u8 plogi_acc;
309f240b688SSudarsana Reddy Kalluru 	bool plogi_acc_set;
310f240b688SSudarsana Reddy Kalluru 	u8 plogi_rjt;
311f240b688SSudarsana Reddy Kalluru 	bool plogi_rjt_set;
312f240b688SSudarsana Reddy Kalluru 	u32 plogi_dst_fcid[5];
313f240b688SSudarsana Reddy Kalluru 	bool plogi_dst_fcid_set[5];
314f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time plogi_tstamp[5];
315f240b688SSudarsana Reddy Kalluru 	u32 plogi_acc_src_fcid[5];
316f240b688SSudarsana Reddy Kalluru 	bool plogi_acc_src_fcid_set[5];
317f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time plogi_acc_tstamp[5];
318f240b688SSudarsana Reddy Kalluru 	u8 tx_plogos;
319f240b688SSudarsana Reddy Kalluru 	bool tx_plogos_set;
320f240b688SSudarsana Reddy Kalluru 	u8 plogo_acc;
321f240b688SSudarsana Reddy Kalluru 	bool plogo_acc_set;
322f240b688SSudarsana Reddy Kalluru 	u8 plogo_rjt;
323f240b688SSudarsana Reddy Kalluru 	bool plogo_rjt_set;
324f240b688SSudarsana Reddy Kalluru 	u32 plogo_src_fcid[5];
325f240b688SSudarsana Reddy Kalluru 	bool plogo_src_fcid_set[5];
326f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time plogo_tstamp[5];
327f240b688SSudarsana Reddy Kalluru 	u8 rx_logos;
328f240b688SSudarsana Reddy Kalluru 	bool rx_logos_set;
329f240b688SSudarsana Reddy Kalluru 	u8 tx_accs;
330f240b688SSudarsana Reddy Kalluru 	bool tx_accs_set;
331f240b688SSudarsana Reddy Kalluru 	u8 tx_prlis;
332f240b688SSudarsana Reddy Kalluru 	bool tx_prlis_set;
333f240b688SSudarsana Reddy Kalluru 	u8 rx_accs;
334f240b688SSudarsana Reddy Kalluru 	bool rx_accs_set;
335f240b688SSudarsana Reddy Kalluru 	u8 tx_abts;
336f240b688SSudarsana Reddy Kalluru 	bool tx_abts_set;
337f240b688SSudarsana Reddy Kalluru 	u8 rx_abts_acc;
338f240b688SSudarsana Reddy Kalluru 	bool rx_abts_acc_set;
339f240b688SSudarsana Reddy Kalluru 	u8 rx_abts_rjt;
340f240b688SSudarsana Reddy Kalluru 	bool rx_abts_rjt_set;
341f240b688SSudarsana Reddy Kalluru 	u32 abts_dst_fcid[5];
342f240b688SSudarsana Reddy Kalluru 	bool abts_dst_fcid_set[5];
343f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time abts_tstamp[5];
344f240b688SSudarsana Reddy Kalluru 	u8 rx_rscn;
345f240b688SSudarsana Reddy Kalluru 	bool rx_rscn_set;
346f240b688SSudarsana Reddy Kalluru 	u32 rx_rscn_nport[4];
347f240b688SSudarsana Reddy Kalluru 	bool rx_rscn_nport_set[4];
348f240b688SSudarsana Reddy Kalluru 	u8 tx_lun_rst;
349f240b688SSudarsana Reddy Kalluru 	bool tx_lun_rst_set;
350f240b688SSudarsana Reddy Kalluru 	u8 abort_task_sets;
351f240b688SSudarsana Reddy Kalluru 	bool abort_task_sets_set;
352f240b688SSudarsana Reddy Kalluru 	u8 tx_tprlos;
353f240b688SSudarsana Reddy Kalluru 	bool tx_tprlos_set;
354f240b688SSudarsana Reddy Kalluru 	u8 tx_nos;
355f240b688SSudarsana Reddy Kalluru 	bool tx_nos_set;
356f240b688SSudarsana Reddy Kalluru 	u8 rx_nos;
357f240b688SSudarsana Reddy Kalluru 	bool rx_nos_set;
358f240b688SSudarsana Reddy Kalluru 	u8 ols;
359f240b688SSudarsana Reddy Kalluru 	bool ols_set;
360f240b688SSudarsana Reddy Kalluru 	u8 lr;
361f240b688SSudarsana Reddy Kalluru 	bool lr_set;
362f240b688SSudarsana Reddy Kalluru 	u8 lrr;
363f240b688SSudarsana Reddy Kalluru 	bool lrr_set;
364f240b688SSudarsana Reddy Kalluru 	u8 tx_lip;
365f240b688SSudarsana Reddy Kalluru 	bool tx_lip_set;
366f240b688SSudarsana Reddy Kalluru 	u8 rx_lip;
367f240b688SSudarsana Reddy Kalluru 	bool rx_lip_set;
368f240b688SSudarsana Reddy Kalluru 	u8 eofa;
369f240b688SSudarsana Reddy Kalluru 	bool eofa_set;
370f240b688SSudarsana Reddy Kalluru 	u8 eofni;
371f240b688SSudarsana Reddy Kalluru 	bool eofni_set;
372f240b688SSudarsana Reddy Kalluru 	u8 scsi_chks;
373f240b688SSudarsana Reddy Kalluru 	bool scsi_chks_set;
374f240b688SSudarsana Reddy Kalluru 	u8 scsi_cond_met;
375f240b688SSudarsana Reddy Kalluru 	bool scsi_cond_met_set;
376f240b688SSudarsana Reddy Kalluru 	u8 scsi_busy;
377f240b688SSudarsana Reddy Kalluru 	bool scsi_busy_set;
378f240b688SSudarsana Reddy Kalluru 	u8 scsi_inter;
379f240b688SSudarsana Reddy Kalluru 	bool scsi_inter_set;
380f240b688SSudarsana Reddy Kalluru 	u8 scsi_inter_cond_met;
381f240b688SSudarsana Reddy Kalluru 	bool scsi_inter_cond_met_set;
382f240b688SSudarsana Reddy Kalluru 	u8 scsi_rsv_conflicts;
383f240b688SSudarsana Reddy Kalluru 	bool scsi_rsv_conflicts_set;
384f240b688SSudarsana Reddy Kalluru 	u8 scsi_tsk_full;
385f240b688SSudarsana Reddy Kalluru 	bool scsi_tsk_full_set;
386f240b688SSudarsana Reddy Kalluru 	u8 scsi_aca_active;
387f240b688SSudarsana Reddy Kalluru 	bool scsi_aca_active_set;
388f240b688SSudarsana Reddy Kalluru 	u8 scsi_tsk_abort;
389f240b688SSudarsana Reddy Kalluru 	bool scsi_tsk_abort_set;
390f240b688SSudarsana Reddy Kalluru 	u32 scsi_rx_chk[5];
391f240b688SSudarsana Reddy Kalluru 	bool scsi_rx_chk_set[5];
392f240b688SSudarsana Reddy Kalluru 	struct qed_mfw_tlv_time scsi_chk_tstamp[5];
393f240b688SSudarsana Reddy Kalluru };
394f240b688SSudarsana Reddy Kalluru 
39577a509e4SSudarsana Reddy Kalluru struct qed_mfw_tlv_iscsi {
39677a509e4SSudarsana Reddy Kalluru 	u8 target_llmnr;
39777a509e4SSudarsana Reddy Kalluru 	bool target_llmnr_set;
39877a509e4SSudarsana Reddy Kalluru 	u8 header_digest;
39977a509e4SSudarsana Reddy Kalluru 	bool header_digest_set;
40077a509e4SSudarsana Reddy Kalluru 	u8 data_digest;
40177a509e4SSudarsana Reddy Kalluru 	bool data_digest_set;
40277a509e4SSudarsana Reddy Kalluru 	u8 auth_method;
40377a509e4SSudarsana Reddy Kalluru #define QED_MFW_TLV_AUTH_METHOD_NONE            (1)
40477a509e4SSudarsana Reddy Kalluru #define QED_MFW_TLV_AUTH_METHOD_CHAP            (2)
40577a509e4SSudarsana Reddy Kalluru #define QED_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP     (3)
40677a509e4SSudarsana Reddy Kalluru 	bool auth_method_set;
40777a509e4SSudarsana Reddy Kalluru 	u16 boot_taget_portal;
40877a509e4SSudarsana Reddy Kalluru 	bool boot_taget_portal_set;
40977a509e4SSudarsana Reddy Kalluru 	u16 frame_size;
41077a509e4SSudarsana Reddy Kalluru 	bool frame_size_set;
41177a509e4SSudarsana Reddy Kalluru 	u16 tx_desc_size;
41277a509e4SSudarsana Reddy Kalluru 	bool tx_desc_size_set;
41377a509e4SSudarsana Reddy Kalluru 	u16 rx_desc_size;
41477a509e4SSudarsana Reddy Kalluru 	bool rx_desc_size_set;
41577a509e4SSudarsana Reddy Kalluru 	u8 boot_progress;
41677a509e4SSudarsana Reddy Kalluru 	bool boot_progress_set;
41777a509e4SSudarsana Reddy Kalluru 	u16 tx_desc_qdepth;
41877a509e4SSudarsana Reddy Kalluru 	bool tx_desc_qdepth_set;
41977a509e4SSudarsana Reddy Kalluru 	u16 rx_desc_qdepth;
42077a509e4SSudarsana Reddy Kalluru 	bool rx_desc_qdepth_set;
42177a509e4SSudarsana Reddy Kalluru 	u64 rx_frames;
42277a509e4SSudarsana Reddy Kalluru 	bool rx_frames_set;
42377a509e4SSudarsana Reddy Kalluru 	u64 rx_bytes;
42477a509e4SSudarsana Reddy Kalluru 	bool rx_bytes_set;
42577a509e4SSudarsana Reddy Kalluru 	u64 tx_frames;
42677a509e4SSudarsana Reddy Kalluru 	bool tx_frames_set;
42777a509e4SSudarsana Reddy Kalluru 	u64 tx_bytes;
42877a509e4SSudarsana Reddy Kalluru 	bool tx_bytes_set;
42977a509e4SSudarsana Reddy Kalluru };
43077a509e4SSudarsana Reddy Kalluru 
43136907cd5SAriel Elior enum qed_db_rec_width {
43236907cd5SAriel Elior 	DB_REC_WIDTH_32B,
43336907cd5SAriel Elior 	DB_REC_WIDTH_64B,
43436907cd5SAriel Elior };
43536907cd5SAriel Elior 
43636907cd5SAriel Elior enum qed_db_rec_space {
43736907cd5SAriel Elior 	DB_REC_KERNEL,
43836907cd5SAriel Elior 	DB_REC_USER,
43936907cd5SAriel Elior };
44036907cd5SAriel Elior 
441fe56b9e6SYuval Mintz #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
442fe56b9e6SYuval Mintz 					    (void __iomem *)(reg_addr))
443fe56b9e6SYuval Mintz 
444fe56b9e6SYuval Mintz #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
445fe56b9e6SYuval Mintz 
446997af5dfSMichal Kalderon #define DIRECT_REG_WR64(reg_addr, val) writeq((u64)val,	\
44736907cd5SAriel Elior 					      (void __iomem *)(reg_addr))
44836907cd5SAriel Elior 
44941822878SRahul Verma #define QED_COALESCE_MAX 0x1FF
4500e191827SSudarsana Reddy Kalluru #define QED_DEFAULT_RX_USECS 12
451bf5a94bfSRahul Verma #define QED_DEFAULT_TX_USECS 48
452fe56b9e6SYuval Mintz 
453fe56b9e6SYuval Mintz /* forward */
454fe56b9e6SYuval Mintz struct qed_dev;
455fe56b9e6SYuval Mintz 
456fe56b9e6SYuval Mintz struct qed_eth_pf_params {
457fe56b9e6SYuval Mintz 	/* The following parameters are used during HW-init
458fe56b9e6SYuval Mintz 	 * and these parameters need to be passed as arguments
459fe56b9e6SYuval Mintz 	 * to update_pf_params routine invoked before slowpath start
460fe56b9e6SYuval Mintz 	 */
461fe56b9e6SYuval Mintz 	u16 num_cons;
462d51e4af5SChopra, Manish 
46308bc8f15SMintz, Yuval 	/* per-VF number of CIDs */
46408bc8f15SMintz, Yuval 	u8 num_vf_cons;
46508bc8f15SMintz, Yuval #define ETH_PF_PARAMS_VF_CONS_DEFAULT	(32)
46608bc8f15SMintz, Yuval 
467d51e4af5SChopra, Manish 	/* To enable arfs, previous to HW-init a positive number needs to be
468d51e4af5SChopra, Manish 	 * set [as filters require allocated searcher ILT memory].
469d51e4af5SChopra, Manish 	 * This will set the maximal number of configured steering-filters.
470d51e4af5SChopra, Manish 	 */
471d51e4af5SChopra, Manish 	u32 num_arfs_filters;
472fe56b9e6SYuval Mintz };
473fe56b9e6SYuval Mintz 
4741e128c81SArun Easi struct qed_fcoe_pf_params {
4751e128c81SArun Easi 	/* The following parameters are used during protocol-init */
4761e128c81SArun Easi 	u64 glbl_q_params_addr;
4771e128c81SArun Easi 	u64 bdq_pbl_base_addr[2];
4781e128c81SArun Easi 
4791e128c81SArun Easi 	/* The following parameters are used during HW-init
4801e128c81SArun Easi 	 * and these parameters need to be passed as arguments
4811e128c81SArun Easi 	 * to update_pf_params routine invoked before slowpath start
4821e128c81SArun Easi 	 */
4831e128c81SArun Easi 	u16 num_cons;
4841e128c81SArun Easi 	u16 num_tasks;
4851e128c81SArun Easi 
4861e128c81SArun Easi 	/* The following parameters are used during protocol-init */
4871e128c81SArun Easi 	u16 sq_num_pbl_pages;
4881e128c81SArun Easi 
4891e128c81SArun Easi 	u16 cq_num_entries;
4901e128c81SArun Easi 	u16 cmdq_num_entries;
4911e128c81SArun Easi 	u16 rq_buffer_log_size;
4921e128c81SArun Easi 	u16 mtu;
4931e128c81SArun Easi 	u16 dummy_icid;
4941e128c81SArun Easi 	u16 bdq_xoff_threshold[2];
4951e128c81SArun Easi 	u16 bdq_xon_threshold[2];
4961e128c81SArun Easi 	u16 rq_buffer_size;
4971e128c81SArun Easi 	u8 num_cqs;		/* num of global CQs */
4981e128c81SArun Easi 	u8 log_page_size;
4991e128c81SArun Easi 	u8 gl_rq_pi;
5001e128c81SArun Easi 	u8 gl_cmd_pi;
5011e128c81SArun Easi 	u8 debug_mode;
5021e128c81SArun Easi 	u8 is_target;
5031e128c81SArun Easi 	u8 bdq_pbl_num_entries[2];
5041e128c81SArun Easi };
5051e128c81SArun Easi 
5060d80b761SRandy Dunlap /* Most of the parameters below are described in the FW iSCSI / TCP HSI */
507c5ac9319SYuval Mintz struct qed_iscsi_pf_params {
508c5ac9319SYuval Mintz 	u64 glbl_q_params_addr;
509da090917STomer Tayar 	u64 bdq_pbl_base_addr[3];
510c5ac9319SYuval Mintz 	u16 cq_num_entries;
511c5ac9319SYuval Mintz 	u16 cmdq_num_entries;
512fc831825SYuval Mintz 	u32 two_msl_timer;
513c5ac9319SYuval Mintz 	u16 tx_sws_timer;
514c5ac9319SYuval Mintz 
515c5ac9319SYuval Mintz 	/* The following parameters are used during HW-init
516c5ac9319SYuval Mintz 	 * and these parameters need to be passed as arguments
517c5ac9319SYuval Mintz 	 * to update_pf_params routine invoked before slowpath start
518c5ac9319SYuval Mintz 	 */
519c5ac9319SYuval Mintz 	u16 num_cons;
520c5ac9319SYuval Mintz 	u16 num_tasks;
521c5ac9319SYuval Mintz 
522c5ac9319SYuval Mintz 	/* The following parameters are used during protocol-init */
523c5ac9319SYuval Mintz 	u16 half_way_close_timeout;
524da090917STomer Tayar 	u16 bdq_xoff_threshold[3];
525da090917STomer Tayar 	u16 bdq_xon_threshold[3];
526c5ac9319SYuval Mintz 	u16 cmdq_xoff_threshold;
527c5ac9319SYuval Mintz 	u16 cmdq_xon_threshold;
528c5ac9319SYuval Mintz 	u16 rq_buffer_size;
529c5ac9319SYuval Mintz 
530c5ac9319SYuval Mintz 	u8 num_sq_pages_in_ring;
531c5ac9319SYuval Mintz 	u8 num_r2tq_pages_in_ring;
532c5ac9319SYuval Mintz 	u8 num_uhq_pages_in_ring;
533c5ac9319SYuval Mintz 	u8 num_queues;
534c5ac9319SYuval Mintz 	u8 log_page_size;
535c5ac9319SYuval Mintz 	u8 rqe_log_size;
536c5ac9319SYuval Mintz 	u8 max_fin_rt;
537c5ac9319SYuval Mintz 	u8 gl_rq_pi;
538c5ac9319SYuval Mintz 	u8 gl_cmd_pi;
539c5ac9319SYuval Mintz 	u8 debug_mode;
540c5ac9319SYuval Mintz 	u8 ll2_ooo_queue_id;
541c5ac9319SYuval Mintz 
542c5ac9319SYuval Mintz 	u8 is_target;
543da090917STomer Tayar 	u8 is_soc_en;
544da090917STomer Tayar 	u8 soc_num_of_blocks_log;
545da090917STomer Tayar 	u8 bdq_pbl_num_entries[3];
546c5ac9319SYuval Mintz };
547c5ac9319SYuval Mintz 
548897e87a1SShai Malin struct qed_nvmetcp_pf_params {
549897e87a1SShai Malin 	u64 glbl_q_params_addr;
550897e87a1SShai Malin 	u16 cq_num_entries;
551897e87a1SShai Malin 	u16 num_cons;
552897e87a1SShai Malin 	u16 num_tasks;
553897e87a1SShai Malin 	u8 num_sq_pages_in_ring;
554897e87a1SShai Malin 	u8 num_r2tq_pages_in_ring;
555897e87a1SShai Malin 	u8 num_uhq_pages_in_ring;
556897e87a1SShai Malin 	u8 num_queues;
557897e87a1SShai Malin 	u8 gl_rq_pi;
558897e87a1SShai Malin 	u8 gl_cmd_pi;
559897e87a1SShai Malin 	u8 debug_mode;
560897e87a1SShai Malin 	u8 ll2_ooo_queue_id;
561897e87a1SShai Malin 	u16 min_rto;
562897e87a1SShai Malin };
563897e87a1SShai Malin 
564c5ac9319SYuval Mintz struct qed_rdma_pf_params {
565c5ac9319SYuval Mintz 	/* Supplied to QED during resource allocation (may affect the ILT and
566c5ac9319SYuval Mintz 	 * the doorbell BAR).
567c5ac9319SYuval Mintz 	 */
568c5ac9319SYuval Mintz 	u32 min_dpis;		/* number of requested DPIs */
569c5ac9319SYuval Mintz 	u32 num_qps;		/* number of requested Queue Pairs */
570c5ac9319SYuval Mintz 	u32 num_srqs;		/* number of requested SRQ */
571c5ac9319SYuval Mintz 	u8 roce_edpm_mode;	/* see QED_ROCE_EDPM_MODE_ENABLE */
572c5ac9319SYuval Mintz 	u8 gl_pi;		/* protocol index */
573c5ac9319SYuval Mintz 
574c5ac9319SYuval Mintz 	/* Will allocate rate limiters to be used with QPs */
575c5ac9319SYuval Mintz 	u8 enable_dcqcn;
576c5ac9319SYuval Mintz };
577c5ac9319SYuval Mintz 
578fe56b9e6SYuval Mintz struct qed_pf_params {
579fe56b9e6SYuval Mintz 	struct qed_eth_pf_params eth_pf_params;
5801e128c81SArun Easi 	struct qed_fcoe_pf_params fcoe_pf_params;
581c5ac9319SYuval Mintz 	struct qed_iscsi_pf_params iscsi_pf_params;
582897e87a1SShai Malin 	struct qed_nvmetcp_pf_params nvmetcp_pf_params;
583c5ac9319SYuval Mintz 	struct qed_rdma_pf_params rdma_pf_params;
584fe56b9e6SYuval Mintz };
585fe56b9e6SYuval Mintz 
586fe56b9e6SYuval Mintz enum qed_int_mode {
587fe56b9e6SYuval Mintz 	QED_INT_MODE_INTA,
588fe56b9e6SYuval Mintz 	QED_INT_MODE_MSIX,
589fe56b9e6SYuval Mintz 	QED_INT_MODE_MSI,
590fe56b9e6SYuval Mintz 	QED_INT_MODE_POLL,
591fe56b9e6SYuval Mintz };
592fe56b9e6SYuval Mintz 
593fe56b9e6SYuval Mintz struct qed_sb_info {
594fb09a1edSShai Malin 	struct status_block *sb_virt;
595fe56b9e6SYuval Mintz 	dma_addr_t sb_phys;
596fe56b9e6SYuval Mintz 	u32 sb_ack; /* Last given ack */
597fe56b9e6SYuval Mintz 	u16 igu_sb_id;
598fe56b9e6SYuval Mintz 	void __iomem *igu_addr;
599fe56b9e6SYuval Mintz 	u8 flags;
600fe56b9e6SYuval Mintz #define QED_SB_INFO_INIT	0x1
601fe56b9e6SYuval Mintz #define QED_SB_INFO_SETUP	0x2
602fe56b9e6SYuval Mintz 
603fe56b9e6SYuval Mintz 	struct qed_dev *cdev;
604fe56b9e6SYuval Mintz };
605fe56b9e6SYuval Mintz 
606d639836aSIgor Russkikh enum qed_hw_err_type {
607d639836aSIgor Russkikh 	QED_HW_ERR_FAN_FAIL,
608d639836aSIgor Russkikh 	QED_HW_ERR_MFW_RESP_FAIL,
609d639836aSIgor Russkikh 	QED_HW_ERR_HW_ATTN,
610d639836aSIgor Russkikh 	QED_HW_ERR_DMAE_FAIL,
611d639836aSIgor Russkikh 	QED_HW_ERR_RAMROD_FAIL,
612d639836aSIgor Russkikh 	QED_HW_ERR_FW_ASSERT,
613d639836aSIgor Russkikh 	QED_HW_ERR_LAST,
614d639836aSIgor Russkikh };
615d639836aSIgor Russkikh 
6169c79ddaaSMintz, Yuval enum qed_dev_type {
6179c79ddaaSMintz, Yuval 	QED_DEV_TYPE_BB,
6189c79ddaaSMintz, Yuval 	QED_DEV_TYPE_AH,
6199c79ddaaSMintz, Yuval };
6209c79ddaaSMintz, Yuval 
621fe56b9e6SYuval Mintz struct qed_dev_info {
622fe56b9e6SYuval Mintz 	unsigned long	pci_mem_start;
623fe56b9e6SYuval Mintz 	unsigned long	pci_mem_end;
624fe56b9e6SYuval Mintz 	unsigned int	pci_irq;
625fe56b9e6SYuval Mintz 	u8		num_hwfns;
626fe56b9e6SYuval Mintz 
627fe56b9e6SYuval Mintz 	u8		hw_mac[ETH_ALEN];
628fe56b9e6SYuval Mintz 
629fe56b9e6SYuval Mintz 	/* FW version */
630fe56b9e6SYuval Mintz 	u16		fw_major;
631fe56b9e6SYuval Mintz 	u16		fw_minor;
632fe56b9e6SYuval Mintz 	u16		fw_rev;
633fe56b9e6SYuval Mintz 	u16		fw_eng;
634fe56b9e6SYuval Mintz 
635fe56b9e6SYuval Mintz 	/* MFW version */
636fe56b9e6SYuval Mintz 	u32		mfw_rev;
637ae33666aSTomer Tayar #define QED_MFW_VERSION_0_MASK		0x000000FF
638ae33666aSTomer Tayar #define QED_MFW_VERSION_0_OFFSET	0
639ae33666aSTomer Tayar #define QED_MFW_VERSION_1_MASK		0x0000FF00
640ae33666aSTomer Tayar #define QED_MFW_VERSION_1_OFFSET	8
641ae33666aSTomer Tayar #define QED_MFW_VERSION_2_MASK		0x00FF0000
642ae33666aSTomer Tayar #define QED_MFW_VERSION_2_OFFSET	16
643ae33666aSTomer Tayar #define QED_MFW_VERSION_3_MASK		0xFF000000
644ae33666aSTomer Tayar #define QED_MFW_VERSION_3_OFFSET	24
645fe56b9e6SYuval Mintz 
646fe56b9e6SYuval Mintz 	u32		flash_size;
6472d2fe843SDmitry Bogdanov 	bool		b_arfs_capable;
6480bc5fe85SSudarsana Reddy Kalluru 	bool		b_inter_pf_switch;
649831bfb0eSYuval Mintz 	bool		tx_switching;
650cee9fbd8SRam Amrani 	bool		rdma_supported;
6510fefbfbaSSudarsana Kalluru 	u16		mtu;
65214d39648SMintz, Yuval 
65314d39648SMintz, Yuval 	bool wol_support;
654df9c716dSSudarsana Reddy Kalluru 	bool smart_an;
655*823163baSManish Chopra 	bool esl;
6569c79ddaaSMintz, Yuval 
657ae33666aSTomer Tayar 	/* MBI version */
658ae33666aSTomer Tayar 	u32 mbi_version;
659ae33666aSTomer Tayar #define QED_MBI_VERSION_0_MASK		0x000000FF
660ae33666aSTomer Tayar #define QED_MBI_VERSION_0_OFFSET	0
661ae33666aSTomer Tayar #define QED_MBI_VERSION_1_MASK		0x0000FF00
662ae33666aSTomer Tayar #define QED_MBI_VERSION_1_OFFSET	8
663ae33666aSTomer Tayar #define QED_MBI_VERSION_2_MASK		0x00FF0000
664ae33666aSTomer Tayar #define QED_MBI_VERSION_2_OFFSET	16
665ae33666aSTomer Tayar 
6669c79ddaaSMintz, Yuval 	enum qed_dev_type dev_type;
66719489c7fSChopra, Manish 
66819489c7fSChopra, Manish 	/* Output parameters for qede */
66919489c7fSChopra, Manish 	bool		vxlan_enable;
67019489c7fSChopra, Manish 	bool		gre_enable;
67119489c7fSChopra, Manish 	bool		geneve_enable;
6723c5da942SMintz, Yuval 
6733c5da942SMintz, Yuval 	u8		abs_pf_id;
674fe56b9e6SYuval Mintz };
675fe56b9e6SYuval Mintz 
676fe56b9e6SYuval Mintz enum qed_sb_type {
677fe56b9e6SYuval Mintz 	QED_SB_TYPE_L2_QUEUE,
67851ff1725SRam Amrani 	QED_SB_TYPE_CNQ,
679fc831825SYuval Mintz 	QED_SB_TYPE_STORAGE,
680fe56b9e6SYuval Mintz };
681fe56b9e6SYuval Mintz 
682fe56b9e6SYuval Mintz enum qed_protocol {
683fe56b9e6SYuval Mintz 	QED_PROTOCOL_ETH,
684c5ac9319SYuval Mintz 	QED_PROTOCOL_ISCSI,
685897e87a1SShai Malin 	QED_PROTOCOL_NVMETCP = QED_PROTOCOL_ISCSI,
6861e128c81SArun Easi 	QED_PROTOCOL_FCOE,
687fe56b9e6SYuval Mintz };
688fe56b9e6SYuval Mintz 
689ae7e6937SAlexander Lobakin enum qed_fec_mode {
690ae7e6937SAlexander Lobakin 	QED_FEC_MODE_NONE			= BIT(0),
691ae7e6937SAlexander Lobakin 	QED_FEC_MODE_FIRECODE			= BIT(1),
692ae7e6937SAlexander Lobakin 	QED_FEC_MODE_RS				= BIT(2),
693ae7e6937SAlexander Lobakin 	QED_FEC_MODE_AUTO			= BIT(3),
694ae7e6937SAlexander Lobakin 	QED_FEC_MODE_UNSUPPORTED		= BIT(4),
695ae7e6937SAlexander Lobakin };
696ae7e6937SAlexander Lobakin 
697fe56b9e6SYuval Mintz struct qed_link_params {
698fe56b9e6SYuval Mintz 	bool					link_up;
699fe56b9e6SYuval Mintz 
70037237b5bSAlexander Lobakin 	u32					override_flags;
701fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_AUTONEG		BIT(0)
702fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS	BIT(1)
703fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED	BIT(2)
704fe56b9e6SYuval Mintz #define QED_LINK_OVERRIDE_PAUSE_CONFIG		BIT(3)
70503dc76caSSudarsana Reddy Kalluru #define QED_LINK_OVERRIDE_LOOPBACK_MODE		BIT(4)
706645874e5SSudarsana Reddy Kalluru #define QED_LINK_OVERRIDE_EEE_CONFIG		BIT(5)
707ae7e6937SAlexander Lobakin #define QED_LINK_OVERRIDE_FEC_CONFIG		BIT(6)
70837237b5bSAlexander Lobakin 
709fe56b9e6SYuval Mintz 	bool					autoneg;
710bdb5d8ecSAlexander Lobakin 	__ETHTOOL_DECLARE_LINK_MODE_MASK(adv_speeds);
711fe56b9e6SYuval Mintz 	u32					forced_speed;
71237237b5bSAlexander Lobakin 
71337237b5bSAlexander Lobakin 	u32					pause_config;
714fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_AUTONEG_ENABLE		BIT(0)
715fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_RX_ENABLE		BIT(1)
716fe56b9e6SYuval Mintz #define QED_LINK_PAUSE_TX_ENABLE		BIT(2)
71737237b5bSAlexander Lobakin 
71837237b5bSAlexander Lobakin 	u32					loopback_mode;
71903dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_NONE			BIT(0)
72003dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_INT_PHY		BIT(1)
72103dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_EXT_PHY		BIT(2)
72203dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_EXT			BIT(3)
72303dc76caSSudarsana Reddy Kalluru #define QED_LINK_LOOPBACK_MAC			BIT(4)
72498e675ecSAlexander Lobakin #define QED_LINK_LOOPBACK_CNIG_AH_ONLY_0123	BIT(5)
72598e675ecSAlexander Lobakin #define QED_LINK_LOOPBACK_CNIG_AH_ONLY_2301	BIT(6)
72698e675ecSAlexander Lobakin #define QED_LINK_LOOPBACK_PCS_AH_ONLY		BIT(7)
72798e675ecSAlexander Lobakin #define QED_LINK_LOOPBACK_REVERSE_MAC_AH_ONLY	BIT(8)
72898e675ecSAlexander Lobakin #define QED_LINK_LOOPBACK_INT_PHY_FEA_AH_ONLY	BIT(9)
72937237b5bSAlexander Lobakin 
730645874e5SSudarsana Reddy Kalluru 	struct qed_link_eee_params		eee;
731ae7e6937SAlexander Lobakin 	u32					fec;
732fe56b9e6SYuval Mintz };
733fe56b9e6SYuval Mintz 
734fe56b9e6SYuval Mintz struct qed_link_output {
735fe56b9e6SYuval Mintz 	bool					link_up;
736fe56b9e6SYuval Mintz 
737bdb5d8ecSAlexander Lobakin 	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported_caps);
738bdb5d8ecSAlexander Lobakin 	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertised_caps);
739bdb5d8ecSAlexander Lobakin 	__ETHTOOL_DECLARE_LINK_MODE_MASK(lp_caps);
740d194fd26SYuval Mintz 
741fe56b9e6SYuval Mintz 	u32					speed;	   /* In Mb/s */
742fe56b9e6SYuval Mintz 	u8					duplex;	   /* In DUPLEX defs */
743fe56b9e6SYuval Mintz 	u8					port;	   /* In PORT defs */
744fe56b9e6SYuval Mintz 	bool					autoneg;
745fe56b9e6SYuval Mintz 	u32					pause_config;
746645874e5SSudarsana Reddy Kalluru 
747645874e5SSudarsana Reddy Kalluru 	/* EEE - capability & param */
748645874e5SSudarsana Reddy Kalluru 	bool					eee_supported;
749645874e5SSudarsana Reddy Kalluru 	bool					eee_active;
750645874e5SSudarsana Reddy Kalluru 	u8					sup_caps;
751645874e5SSudarsana Reddy Kalluru 	struct qed_link_eee_params		eee;
752ae7e6937SAlexander Lobakin 
753ae7e6937SAlexander Lobakin 	u32					sup_fec;
754ae7e6937SAlexander Lobakin 	u32					active_fec;
755fe56b9e6SYuval Mintz };
756fe56b9e6SYuval Mintz 
7571408cc1fSYuval Mintz struct qed_probe_params {
7581408cc1fSYuval Mintz 	enum qed_protocol protocol;
7591408cc1fSYuval Mintz 	u32 dp_module;
7601408cc1fSYuval Mintz 	u8 dp_level;
7611408cc1fSYuval Mintz 	bool is_vf;
76264515dc8STomer Tayar 	bool recov_in_prog;
7631408cc1fSYuval Mintz };
7641408cc1fSYuval Mintz 
765fe56b9e6SYuval Mintz #define QED_DRV_VER_STR_SIZE 12
766fe56b9e6SYuval Mintz struct qed_slowpath_params {
767fe56b9e6SYuval Mintz 	u32	int_mode;
768fe56b9e6SYuval Mintz 	u8	drv_major;
769fe56b9e6SYuval Mintz 	u8	drv_minor;
770fe56b9e6SYuval Mintz 	u8	drv_rev;
771fe56b9e6SYuval Mintz 	u8	drv_eng;
772fe56b9e6SYuval Mintz 	u8	name[QED_DRV_VER_STR_SIZE];
773fe56b9e6SYuval Mintz };
774fe56b9e6SYuval Mintz 
775fe56b9e6SYuval Mintz #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
776fe56b9e6SYuval Mintz 
777fe56b9e6SYuval Mintz struct qed_int_info {
778fe56b9e6SYuval Mintz 	struct msix_entry	*msix;
779fe56b9e6SYuval Mintz 	u8			msix_cnt;
780fe56b9e6SYuval Mintz 
781fe56b9e6SYuval Mintz 	/* This should be updated by the protocol driver */
782fe56b9e6SYuval Mintz 	u8			used_cnt;
783fe56b9e6SYuval Mintz };
784fe56b9e6SYuval Mintz 
78559ccf86fSSudarsana Reddy Kalluru struct qed_generic_tlvs {
78659ccf86fSSudarsana Reddy Kalluru #define QED_TLV_IP_CSUM         BIT(0)
78759ccf86fSSudarsana Reddy Kalluru #define QED_TLV_LSO             BIT(1)
78859ccf86fSSudarsana Reddy Kalluru 	u16 feat_flags;
78959ccf86fSSudarsana Reddy Kalluru #define QED_TLV_MAC_COUNT	3
79059ccf86fSSudarsana Reddy Kalluru 	u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN];
79159ccf86fSSudarsana Reddy Kalluru };
79259ccf86fSSudarsana Reddy Kalluru 
793b51dab46SSudarsana Reddy Kalluru #define QED_I2C_DEV_ADDR_A0 0xA0
794b51dab46SSudarsana Reddy Kalluru #define QED_I2C_DEV_ADDR_A2 0xA2
795b51dab46SSudarsana Reddy Kalluru 
7963a69cae8SSudarsana Reddy Kalluru #define QED_NVM_SIGNATURE 0x12435687
7973a69cae8SSudarsana Reddy Kalluru 
7983a69cae8SSudarsana Reddy Kalluru enum qed_nvm_flash_cmd {
7993a69cae8SSudarsana Reddy Kalluru 	QED_NVM_FLASH_CMD_FILE_DATA = 0x2,
8003a69cae8SSudarsana Reddy Kalluru 	QED_NVM_FLASH_CMD_FILE_START = 0x3,
8013a69cae8SSudarsana Reddy Kalluru 	QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4,
8020dabbe1bSSudarsana Reddy Kalluru 	QED_NVM_FLASH_CMD_NVM_CFG_ID = 0x5,
8033a69cae8SSudarsana Reddy Kalluru 	QED_NVM_FLASH_CMD_NVM_MAX,
8043a69cae8SSudarsana Reddy Kalluru };
8053a69cae8SSudarsana Reddy Kalluru 
806755f982bSIgor Russkikh struct qed_devlink {
807755f982bSIgor Russkikh 	struct qed_dev *cdev;
8089524067bSIgor Russkikh 	struct devlink_health_reporter *fw_reporter;
809755f982bSIgor Russkikh };
810755f982bSIgor Russkikh 
8110cc3a801SManish Chopra struct qed_sb_info_dbg {
8120cc3a801SManish Chopra 	u32 igu_prod;
8130cc3a801SManish Chopra 	u32 igu_cons;
8140cc3a801SManish Chopra 	u16 pi[PIS_PER_SB];
8150cc3a801SManish Chopra };
8160cc3a801SManish Chopra 
817fe56b9e6SYuval Mintz struct qed_common_cb_ops {
818d51e4af5SChopra, Manish 	void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc);
8198f76812eSIgor Russkikh 	void (*link_update)(void *dev, struct qed_link_output *link);
82064515dc8STomer Tayar 	void (*schedule_recovery_handler)(void *dev);
821d639836aSIgor Russkikh 	void (*schedule_hw_err_handler)(void *dev,
822d639836aSIgor Russkikh 					enum qed_hw_err_type err_type);
8231e128c81SArun Easi 	void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
82459ccf86fSSudarsana Reddy Kalluru 	void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data);
82559ccf86fSSudarsana Reddy Kalluru 	void (*get_protocol_tlv_data)(void *dev, void *data);
826699fed4aSSudarsana Reddy Kalluru 	void (*bw_update)(void *dev);
827fe56b9e6SYuval Mintz };
828fe56b9e6SYuval Mintz 
82903dc76caSSudarsana Reddy Kalluru struct qed_selftest_ops {
83003dc76caSSudarsana Reddy Kalluru /**
83119198e4eSPrabhakar Kushwaha  * selftest_interrupt(): Perform interrupt test.
83203dc76caSSudarsana Reddy Kalluru  *
83319198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
83403dc76caSSudarsana Reddy Kalluru  *
83519198e4eSPrabhakar Kushwaha  * Return: 0 on success, error otherwise.
83603dc76caSSudarsana Reddy Kalluru  */
83703dc76caSSudarsana Reddy Kalluru 	int (*selftest_interrupt)(struct qed_dev *cdev);
83803dc76caSSudarsana Reddy Kalluru 
83903dc76caSSudarsana Reddy Kalluru /**
84019198e4eSPrabhakar Kushwaha  * selftest_memory(): Perform memory test.
84103dc76caSSudarsana Reddy Kalluru  *
84219198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
84303dc76caSSudarsana Reddy Kalluru  *
84419198e4eSPrabhakar Kushwaha  * Return: 0 on success, error otherwise.
84503dc76caSSudarsana Reddy Kalluru  */
84603dc76caSSudarsana Reddy Kalluru 	int (*selftest_memory)(struct qed_dev *cdev);
84703dc76caSSudarsana Reddy Kalluru 
84803dc76caSSudarsana Reddy Kalluru /**
84919198e4eSPrabhakar Kushwaha  * selftest_register(): Perform register test.
85003dc76caSSudarsana Reddy Kalluru  *
85119198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
85203dc76caSSudarsana Reddy Kalluru  *
85319198e4eSPrabhakar Kushwaha  * Return: 0 on success, error otherwise.
85403dc76caSSudarsana Reddy Kalluru  */
85503dc76caSSudarsana Reddy Kalluru 	int (*selftest_register)(struct qed_dev *cdev);
85603dc76caSSudarsana Reddy Kalluru 
85703dc76caSSudarsana Reddy Kalluru /**
85819198e4eSPrabhakar Kushwaha  * selftest_clock(): Perform clock test.
85903dc76caSSudarsana Reddy Kalluru  *
86019198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
86103dc76caSSudarsana Reddy Kalluru  *
86219198e4eSPrabhakar Kushwaha  * Return: 0 on success, error otherwise.
86303dc76caSSudarsana Reddy Kalluru  */
86403dc76caSSudarsana Reddy Kalluru 	int (*selftest_clock)(struct qed_dev *cdev);
8657a4b21b7SMintz, Yuval 
8667a4b21b7SMintz, Yuval /**
86719198e4eSPrabhakar Kushwaha  * selftest_nvram(): Perform nvram test.
8687a4b21b7SMintz, Yuval  *
86919198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
8707a4b21b7SMintz, Yuval  *
87119198e4eSPrabhakar Kushwaha  * Return: 0 on success, error otherwise.
8727a4b21b7SMintz, Yuval  */
8737a4b21b7SMintz, Yuval 	int (*selftest_nvram) (struct qed_dev *cdev);
87403dc76caSSudarsana Reddy Kalluru };
87503dc76caSSudarsana Reddy Kalluru 
876fe56b9e6SYuval Mintz struct qed_common_ops {
87703dc76caSSudarsana Reddy Kalluru 	struct qed_selftest_ops *selftest;
87803dc76caSSudarsana Reddy Kalluru 
879fe56b9e6SYuval Mintz 	struct qed_dev*	(*probe)(struct pci_dev *dev,
8801408cc1fSYuval Mintz 				 struct qed_probe_params *params);
881fe56b9e6SYuval Mintz 
882fe56b9e6SYuval Mintz 	void (*remove)(struct qed_dev *cdev);
883fe56b9e6SYuval Mintz 
884c5c642c5SIgor Russkikh 	int (*set_power_state)(struct qed_dev *cdev, pci_power_t state);
885fe56b9e6SYuval Mintz 
886712c3cbfSMintz, Yuval 	void (*set_name) (struct qed_dev *cdev, char name[]);
887fe56b9e6SYuval Mintz 
888fe56b9e6SYuval Mintz 	/* Client drivers need to make this call before slowpath_start.
889fe56b9e6SYuval Mintz 	 * PF params required for the call before slowpath_start is
890fe56b9e6SYuval Mintz 	 * documented within the qed_pf_params structure definition.
891fe56b9e6SYuval Mintz 	 */
892fe56b9e6SYuval Mintz 	void (*update_pf_params)(struct qed_dev *cdev,
893fe56b9e6SYuval Mintz 				 struct qed_pf_params *params);
894c5c642c5SIgor Russkikh 
895fe56b9e6SYuval Mintz 	int (*slowpath_start)(struct qed_dev *cdev,
896fe56b9e6SYuval Mintz 			      struct qed_slowpath_params *params);
897fe56b9e6SYuval Mintz 
898fe56b9e6SYuval Mintz 	int (*slowpath_stop)(struct qed_dev *cdev);
899fe56b9e6SYuval Mintz 
900fe56b9e6SYuval Mintz 	/* Requests to use `cnt' interrupts for fastpath.
901fe56b9e6SYuval Mintz 	 * upon success, returns number of interrupts allocated for fastpath.
902fe56b9e6SYuval Mintz 	 */
903c5c642c5SIgor Russkikh 	int (*set_fp_int)(struct qed_dev *cdev, u16 cnt);
904fe56b9e6SYuval Mintz 
905fe56b9e6SYuval Mintz 	/* Fills `info' with pointers required for utilizing interrupts */
906c5c642c5SIgor Russkikh 	int (*get_fp_int)(struct qed_dev *cdev, struct qed_int_info *info);
907fe56b9e6SYuval Mintz 
908fe56b9e6SYuval Mintz 	u32 (*sb_init)(struct qed_dev *cdev,
909fe56b9e6SYuval Mintz 		       struct qed_sb_info *sb_info,
910fe56b9e6SYuval Mintz 		       void *sb_virt_addr,
911fe56b9e6SYuval Mintz 		       dma_addr_t sb_phy_addr,
912fe56b9e6SYuval Mintz 		       u16 sb_id,
913fe56b9e6SYuval Mintz 		       enum qed_sb_type type);
914fe56b9e6SYuval Mintz 
915fe56b9e6SYuval Mintz 	u32 (*sb_release)(struct qed_dev *cdev,
916fe56b9e6SYuval Mintz 			  struct qed_sb_info *sb_info,
91708eb1fb0SMichal Kalderon 			  u16 sb_id,
91808eb1fb0SMichal Kalderon 			  enum qed_sb_type type);
919fe56b9e6SYuval Mintz 
920fe56b9e6SYuval Mintz 	void (*simd_handler_config)(struct qed_dev *cdev,
921fe56b9e6SYuval Mintz 				    void *token,
922fe56b9e6SYuval Mintz 				    int index,
923fe56b9e6SYuval Mintz 				    void (*handler)(void *));
924fe56b9e6SYuval Mintz 
925c5c642c5SIgor Russkikh 	void (*simd_handler_clean)(struct qed_dev *cdev, int index);
926c5c642c5SIgor Russkikh 
927c5c642c5SIgor Russkikh 	int (*dbg_grc)(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes);
9281e128c81SArun Easi 
9291e128c81SArun Easi 	int (*dbg_grc_size)(struct qed_dev *cdev);
930fe7cd2bfSYuval Mintz 
931e0971c83STomer Tayar 	int (*dbg_all_data)(struct qed_dev *cdev, void *buffer);
932e0971c83STomer Tayar 
933e0971c83STomer Tayar 	int (*dbg_all_data_size)(struct qed_dev *cdev);
934e0971c83STomer Tayar 
9354f5a8db2SIgor Russkikh 	int (*report_fatal_error)(struct devlink *devlink,
9364f5a8db2SIgor Russkikh 				  enum qed_hw_err_type err_type);
9374f5a8db2SIgor Russkikh 
938fe7cd2bfSYuval Mintz /**
93919198e4eSPrabhakar Kushwaha  * can_link_change(): can the instance change the link or not.
940fe7cd2bfSYuval Mintz  *
94119198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
942fe7cd2bfSYuval Mintz  *
94319198e4eSPrabhakar Kushwaha  * Return: true if link-change is allowed, false otherwise.
944fe7cd2bfSYuval Mintz  */
945fe7cd2bfSYuval Mintz 	bool (*can_link_change)(struct qed_dev *cdev);
946fe7cd2bfSYuval Mintz 
947fe56b9e6SYuval Mintz /**
94819198e4eSPrabhakar Kushwaha  * set_link(): set links according to params.
949fe56b9e6SYuval Mintz  *
95019198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
95119198e4eSPrabhakar Kushwaha  * @params: values used to override the default link configuration.
952fe56b9e6SYuval Mintz  *
95319198e4eSPrabhakar Kushwaha  * Return: 0 on success, error otherwise.
954fe56b9e6SYuval Mintz  */
955fe56b9e6SYuval Mintz 	int		(*set_link)(struct qed_dev *cdev,
956fe56b9e6SYuval Mintz 				    struct qed_link_params *params);
957fe56b9e6SYuval Mintz 
958fe56b9e6SYuval Mintz /**
95919198e4eSPrabhakar Kushwaha  * get_link(): returns the current link state.
960fe56b9e6SYuval Mintz  *
96119198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
96219198e4eSPrabhakar Kushwaha  * @if_link: structure to be filled with current link configuration.
96319198e4eSPrabhakar Kushwaha  *
96419198e4eSPrabhakar Kushwaha  * Return: Void.
965fe56b9e6SYuval Mintz  */
966fe56b9e6SYuval Mintz 	void		(*get_link)(struct qed_dev *cdev,
967fe56b9e6SYuval Mintz 				    struct qed_link_output *if_link);
968fe56b9e6SYuval Mintz 
969fe56b9e6SYuval Mintz /**
97019198e4eSPrabhakar Kushwaha  * drain(): drains chip in case Tx completions fail to arrive due to pause.
971fe56b9e6SYuval Mintz  *
97219198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
97319198e4eSPrabhakar Kushwaha  *
97419198e4eSPrabhakar Kushwaha  * Return: Int.
975fe56b9e6SYuval Mintz  */
976fe56b9e6SYuval Mintz 	int		(*drain)(struct qed_dev *cdev);
977fe56b9e6SYuval Mintz 
978fe56b9e6SYuval Mintz /**
97919198e4eSPrabhakar Kushwaha  * update_msglvl(): update module debug level.
980fe56b9e6SYuval Mintz  *
98119198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
98219198e4eSPrabhakar Kushwaha  * @dp_module: Debug module.
98319198e4eSPrabhakar Kushwaha  * @dp_level: Debug level.
98419198e4eSPrabhakar Kushwaha  *
98519198e4eSPrabhakar Kushwaha  * Return: Void.
986fe56b9e6SYuval Mintz  */
987fe56b9e6SYuval Mintz 	void		(*update_msglvl)(struct qed_dev *cdev,
988fe56b9e6SYuval Mintz 					 u32 dp_module,
989fe56b9e6SYuval Mintz 					 u8 dp_level);
990fe56b9e6SYuval Mintz 
991fe56b9e6SYuval Mintz 	int		(*chain_alloc)(struct qed_dev *cdev,
992b6db3f71SAlexander Lobakin 				       struct qed_chain *chain,
993b6db3f71SAlexander Lobakin 				       struct qed_chain_init_params *params);
994fe56b9e6SYuval Mintz 
995fe56b9e6SYuval Mintz 	void		(*chain_free)(struct qed_dev *cdev,
996fe56b9e6SYuval Mintz 				      struct qed_chain *p_chain);
99791420b83SSudarsana Kalluru 
99891420b83SSudarsana Kalluru /**
99919198e4eSPrabhakar Kushwaha  * nvm_flash(): Flash nvm data.
10003a69cae8SSudarsana Reddy Kalluru  *
100119198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
100219198e4eSPrabhakar Kushwaha  * @name: file containing the data.
10033a69cae8SSudarsana Reddy Kalluru  *
100419198e4eSPrabhakar Kushwaha  * Return: 0 on success, error otherwise.
10053a69cae8SSudarsana Reddy Kalluru  */
10063a69cae8SSudarsana Reddy Kalluru 	int (*nvm_flash)(struct qed_dev *cdev, const char *name);
10073a69cae8SSudarsana Reddy Kalluru 
10083a69cae8SSudarsana Reddy Kalluru /**
100919198e4eSPrabhakar Kushwaha  * nvm_get_image(): reads an entire image from nvram.
101020675b37SMintz, Yuval  *
101119198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
101219198e4eSPrabhakar Kushwaha  * @type: type of the request nvram image.
101319198e4eSPrabhakar Kushwaha  * @buf: preallocated buffer to fill with the image.
101419198e4eSPrabhakar Kushwaha  * @len: length of the allocated buffer.
101520675b37SMintz, Yuval  *
101619198e4eSPrabhakar Kushwaha  * Return: 0 on success, error otherwise.
101720675b37SMintz, Yuval  */
101820675b37SMintz, Yuval 	int (*nvm_get_image)(struct qed_dev *cdev,
101920675b37SMintz, Yuval 			     enum qed_nvm_images type, u8 *buf, u16 len);
102020675b37SMintz, Yuval 
102120675b37SMintz, Yuval /**
102219198e4eSPrabhakar Kushwaha  * set_coalesce(): Configure Rx coalesce value in usec.
1023722003acSSudarsana Reddy Kalluru  *
102419198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
102519198e4eSPrabhakar Kushwaha  * @rx_coal: Rx coalesce value in usec.
102619198e4eSPrabhakar Kushwaha  * @tx_coal: Tx coalesce value in usec.
102719198e4eSPrabhakar Kushwaha  * @handle: Handle.
1028722003acSSudarsana Reddy Kalluru  *
102919198e4eSPrabhakar Kushwaha  * Return: 0 on success, error otherwise.
1030722003acSSudarsana Reddy Kalluru  */
1031477f2d14SRahul Verma 	int (*set_coalesce)(struct qed_dev *cdev,
1032477f2d14SRahul Verma 			    u16 rx_coal, u16 tx_coal, void *handle);
1033722003acSSudarsana Reddy Kalluru 
1034722003acSSudarsana Reddy Kalluru /**
103519198e4eSPrabhakar Kushwaha  * set_led() - Configure LED mode.
103691420b83SSudarsana Kalluru  *
103719198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
103819198e4eSPrabhakar Kushwaha  * @mode: LED mode.
103991420b83SSudarsana Kalluru  *
104019198e4eSPrabhakar Kushwaha  * Return: 0 on success, error otherwise.
104191420b83SSudarsana Kalluru  */
104291420b83SSudarsana Kalluru 	int (*set_led)(struct qed_dev *cdev,
104391420b83SSudarsana Kalluru 		       enum qed_led_mode mode);
1044936c7ba4SIgor Russkikh 
1045936c7ba4SIgor Russkikh /**
104619198e4eSPrabhakar Kushwaha  * attn_clr_enable(): Prevent attentions from being reasserted.
1047936c7ba4SIgor Russkikh  *
104819198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
104919198e4eSPrabhakar Kushwaha  * @clr_enable: Clear enable.
105019198e4eSPrabhakar Kushwaha  *
105119198e4eSPrabhakar Kushwaha  * Return: Void.
1052936c7ba4SIgor Russkikh  */
1053936c7ba4SIgor Russkikh 	void (*attn_clr_enable)(struct qed_dev *cdev, bool clr_enable);
1054936c7ba4SIgor Russkikh 
10550e1f1044SAriel Elior /**
105619198e4eSPrabhakar Kushwaha  * db_recovery_add(): add doorbell information to the doorbell
10570e1f1044SAriel Elior  *                    recovery mechanism.
10580e1f1044SAriel Elior  *
105919198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
106019198e4eSPrabhakar Kushwaha  * @db_addr: Doorbell address.
106119198e4eSPrabhakar Kushwaha  * @db_data: Dddress of where db_data is stored.
106219198e4eSPrabhakar Kushwaha  * @db_width: Doorbell is 32b or 64b.
106319198e4eSPrabhakar Kushwaha  * @db_space: Doorbell recovery addresses are user or kernel space.
106419198e4eSPrabhakar Kushwaha  *
106519198e4eSPrabhakar Kushwaha  * Return: Int.
10660e1f1044SAriel Elior  */
10670e1f1044SAriel Elior 	int (*db_recovery_add)(struct qed_dev *cdev,
10680e1f1044SAriel Elior 			       void __iomem *db_addr,
10690e1f1044SAriel Elior 			       void *db_data,
10700e1f1044SAriel Elior 			       enum qed_db_rec_width db_width,
10710e1f1044SAriel Elior 			       enum qed_db_rec_space db_space);
10720e1f1044SAriel Elior 
10730e1f1044SAriel Elior /**
107419198e4eSPrabhakar Kushwaha  * db_recovery_del(): remove doorbell information from the doorbell
10750e1f1044SAriel Elior  * recovery mechanism. db_data serves as key (db_addr is not unique).
10760e1f1044SAriel Elior  *
107719198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
107819198e4eSPrabhakar Kushwaha  * @db_addr: Doorbell address.
107919198e4eSPrabhakar Kushwaha  * @db_data: Address where db_data is stored. Serves as key for the
10800e1f1044SAriel Elior  *           entry to delete.
108119198e4eSPrabhakar Kushwaha  *
108219198e4eSPrabhakar Kushwaha  * Return: Int.
10830e1f1044SAriel Elior  */
10840e1f1044SAriel Elior 	int (*db_recovery_del)(struct qed_dev *cdev,
10850e1f1044SAriel Elior 			       void __iomem *db_addr, void *db_data);
10860fefbfbaSSudarsana Kalluru 
10870fefbfbaSSudarsana Kalluru /**
108819198e4eSPrabhakar Kushwaha  * recovery_process(): Trigger a recovery process.
108964515dc8STomer Tayar  *
109019198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
109164515dc8STomer Tayar  *
109219198e4eSPrabhakar Kushwaha  * Return: 0 on success, error otherwise.
109364515dc8STomer Tayar  */
109464515dc8STomer Tayar 	int (*recovery_process)(struct qed_dev *cdev);
109564515dc8STomer Tayar 
109664515dc8STomer Tayar /**
109719198e4eSPrabhakar Kushwaha  * recovery_prolog(): Execute the prolog operations of a recovery process.
109864515dc8STomer Tayar  *
109919198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
110064515dc8STomer Tayar  *
110119198e4eSPrabhakar Kushwaha  * Return: 0 on success, error otherwise.
110264515dc8STomer Tayar  */
110364515dc8STomer Tayar 	int (*recovery_prolog)(struct qed_dev *cdev);
110464515dc8STomer Tayar 
110564515dc8STomer Tayar /**
110619198e4eSPrabhakar Kushwaha  * update_drv_state(): API to inform the change in the driver state.
11070fefbfbaSSudarsana Kalluru  *
110819198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
110919198e4eSPrabhakar Kushwaha  * @active: Active
11100fefbfbaSSudarsana Kalluru  *
111119198e4eSPrabhakar Kushwaha  * Return: Int.
11120fefbfbaSSudarsana Kalluru  */
11130fefbfbaSSudarsana Kalluru 	int (*update_drv_state)(struct qed_dev *cdev, bool active);
11140fefbfbaSSudarsana Kalluru 
11150fefbfbaSSudarsana Kalluru /**
111619198e4eSPrabhakar Kushwaha  * update_mac(): API to inform the change in the mac address.
11170fefbfbaSSudarsana Kalluru  *
111819198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
111919198e4eSPrabhakar Kushwaha  * @mac: MAC.
11200fefbfbaSSudarsana Kalluru  *
112119198e4eSPrabhakar Kushwaha  * Return: Int.
11220fefbfbaSSudarsana Kalluru  */
112376660757SJakub Kicinski 	int (*update_mac)(struct qed_dev *cdev, const u8 *mac);
11240fefbfbaSSudarsana Kalluru 
11250fefbfbaSSudarsana Kalluru /**
112619198e4eSPrabhakar Kushwaha  * update_mtu(): API to inform the change in the mtu.
11270fefbfbaSSudarsana Kalluru  *
112819198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
112919198e4eSPrabhakar Kushwaha  * @mtu: MTU.
11300fefbfbaSSudarsana Kalluru  *
113119198e4eSPrabhakar Kushwaha  * Return: Int.
11320fefbfbaSSudarsana Kalluru  */
11330fefbfbaSSudarsana Kalluru 	int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
113414d39648SMintz, Yuval 
113514d39648SMintz, Yuval /**
113619198e4eSPrabhakar Kushwaha  * update_wol(): Update of changes in the WoL configuration.
113714d39648SMintz, Yuval  *
113819198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
113919198e4eSPrabhakar Kushwaha  * @enabled: true iff WoL should be enabled.
114019198e4eSPrabhakar Kushwaha  *
114119198e4eSPrabhakar Kushwaha  * Return: Int.
114214d39648SMintz, Yuval  */
114314d39648SMintz, Yuval 	int (*update_wol) (struct qed_dev *cdev, bool enabled);
1144b51dab46SSudarsana Reddy Kalluru 
1145b51dab46SSudarsana Reddy Kalluru /**
114619198e4eSPrabhakar Kushwaha  * read_module_eeprom(): Read EEPROM.
1147b51dab46SSudarsana Reddy Kalluru  *
114819198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
114919198e4eSPrabhakar Kushwaha  * @buf: buffer.
115019198e4eSPrabhakar Kushwaha  * @dev_addr: PHY device memory region.
115119198e4eSPrabhakar Kushwaha  * @offset: offset into eeprom contents to be read.
115219198e4eSPrabhakar Kushwaha  * @len: buffer length, i.e., max bytes to be read.
115319198e4eSPrabhakar Kushwaha  *
115419198e4eSPrabhakar Kushwaha  * Return: Int.
1155b51dab46SSudarsana Reddy Kalluru  */
1156b51dab46SSudarsana Reddy Kalluru 	int (*read_module_eeprom)(struct qed_dev *cdev,
1157b51dab46SSudarsana Reddy Kalluru 				  char *buf, u8 dev_addr, u32 offset, u32 len);
115808eb1fb0SMichal Kalderon 
115908eb1fb0SMichal Kalderon /**
116019198e4eSPrabhakar Kushwaha  * get_affin_hwfn_idx(): Get affine HW function.
116108eb1fb0SMichal Kalderon  *
116219198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
116319198e4eSPrabhakar Kushwaha  *
116419198e4eSPrabhakar Kushwaha  * Return: u8.
116508eb1fb0SMichal Kalderon  */
116608eb1fb0SMichal Kalderon 	u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev);
11672d4c8495SSudarsana Reddy Kalluru 
11682d4c8495SSudarsana Reddy Kalluru /**
116919198e4eSPrabhakar Kushwaha  * read_nvm_cfg(): Read NVM config attribute value.
11702d4c8495SSudarsana Reddy Kalluru  *
117119198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
117219198e4eSPrabhakar Kushwaha  * @buf: Buffer.
117319198e4eSPrabhakar Kushwaha  * @cmd: NVM CFG command id.
117419198e4eSPrabhakar Kushwaha  * @entity_id: Entity id.
117519198e4eSPrabhakar Kushwaha  *
117619198e4eSPrabhakar Kushwaha  * Return: Int.
11772d4c8495SSudarsana Reddy Kalluru  */
11782d4c8495SSudarsana Reddy Kalluru 	int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd,
11792d4c8495SSudarsana Reddy Kalluru 			    u32 entity_id);
11809e54ba7cSSudarsana Reddy Kalluru /**
118119198e4eSPrabhakar Kushwaha  * read_nvm_cfg_len(): Read NVM config attribute value.
11829e54ba7cSSudarsana Reddy Kalluru  *
118319198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
118419198e4eSPrabhakar Kushwaha  * @cmd: NVM CFG command id.
118519198e4eSPrabhakar Kushwaha  *
118619198e4eSPrabhakar Kushwaha  * Return: config id length, 0 on error.
11879e54ba7cSSudarsana Reddy Kalluru  */
11889e54ba7cSSudarsana Reddy Kalluru 	int (*read_nvm_cfg_len)(struct qed_dev *cdev, u32 cmd);
11893b86bd07SSudarsana Reddy Kalluru 
11903b86bd07SSudarsana Reddy Kalluru /**
119119198e4eSPrabhakar Kushwaha  * set_grc_config(): Configure value for grc config id.
11923b86bd07SSudarsana Reddy Kalluru  *
119319198e4eSPrabhakar Kushwaha  * @cdev: Qed dev pointer.
119419198e4eSPrabhakar Kushwaha  * @cfg_id: grc config id
119519198e4eSPrabhakar Kushwaha  * @val: grc config value
119619198e4eSPrabhakar Kushwaha  *
119719198e4eSPrabhakar Kushwaha  * Return: Int.
11983b86bd07SSudarsana Reddy Kalluru  */
11993b86bd07SSudarsana Reddy Kalluru 	int (*set_grc_config)(struct qed_dev *cdev, u32 cfg_id, u32 val);
1200755f982bSIgor Russkikh 
1201755f982bSIgor Russkikh 	struct devlink* (*devlink_register)(struct qed_dev *cdev);
1202755f982bSIgor Russkikh 
1203755f982bSIgor Russkikh 	void (*devlink_unregister)(struct devlink *devlink);
12040cc3a801SManish Chopra 
12050cc3a801SManish Chopra 	__printf(2, 3) void (*mfw_report)(struct qed_dev *cdev, char *fmt, ...);
12060cc3a801SManish Chopra 
12070cc3a801SManish Chopra 	int (*get_sb_info)(struct qed_dev *cdev, struct qed_sb_info *sb,
12080cc3a801SManish Chopra 			   u16 qid, struct qed_sb_info_dbg *sb_dbg);
1209*823163baSManish Chopra 
1210*823163baSManish Chopra 	int (*get_esl_status)(struct qed_dev *cdev, bool *esl_active);
1211fe56b9e6SYuval Mintz };
1212fe56b9e6SYuval Mintz 
1213fe56b9e6SYuval Mintz #define MASK_FIELD(_name, _value) \
1214fe56b9e6SYuval Mintz 	((_value) &= (_name ## _MASK))
1215fe56b9e6SYuval Mintz 
1216fe56b9e6SYuval Mintz #define FIELD_VALUE(_name, _value) \
1217fe56b9e6SYuval Mintz 	((_value & _name ## _MASK) << _name ## _SHIFT)
1218fe56b9e6SYuval Mintz 
1219fe56b9e6SYuval Mintz #define SET_FIELD(value, name, flag)			       \
1220fe56b9e6SYuval Mintz 	do {						       \
1221fe56b9e6SYuval Mintz 		(value) &= ~(name ## _MASK << name ## _SHIFT); \
1222fe56b9e6SYuval Mintz 		(value) |= (((u64)flag) << (name ## _SHIFT));  \
1223fe56b9e6SYuval Mintz 	} while (0)
1224fe56b9e6SYuval Mintz 
1225fe56b9e6SYuval Mintz #define GET_FIELD(value, name) \
1226fe56b9e6SYuval Mintz 	(((value) >> (name ## _SHIFT)) & name ## _MASK)
1227fe56b9e6SYuval Mintz 
12282d22bc83SMichal Kalderon #define GET_MFW_FIELD(name, field) \
12292d22bc83SMichal Kalderon 	(((name) & (field ## _MASK)) >> (field ## _OFFSET))
12302d22bc83SMichal Kalderon 
12312d22bc83SMichal Kalderon #define SET_MFW_FIELD(name, field, value)				 \
12322d22bc83SMichal Kalderon 	do {								 \
12332d22bc83SMichal Kalderon 		(name) &= ~(field ## _MASK);				 \
12342d22bc83SMichal Kalderon 		(name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK));\
12352d22bc83SMichal Kalderon 	} while (0)
12362d22bc83SMichal Kalderon 
1237997af5dfSMichal Kalderon #define DB_ADDR_SHIFT(addr) ((addr) << DB_PWM_ADDR_OFFSET_SHIFT)
1238997af5dfSMichal Kalderon 
1239fe56b9e6SYuval Mintz /* Debug print definitions */
1240fe56b9e6SYuval Mintz #define DP_ERR(cdev, fmt, ...)					\
12419d7650c2SMintz, Yuval 	do {							\
1242fe56b9e6SYuval Mintz 		pr_err("[%s:%d(%s)]" fmt,			\
1243fe56b9e6SYuval Mintz 		       __func__, __LINE__,			\
1244fe56b9e6SYuval Mintz 		       DP_NAME(cdev) ? DP_NAME(cdev) : "",	\
12459d7650c2SMintz, Yuval 		       ## __VA_ARGS__);				\
12469d7650c2SMintz, Yuval 	} while (0)
1247fe56b9e6SYuval Mintz 
1248fe56b9e6SYuval Mintz #define DP_NOTICE(cdev, fmt, ...)				      \
1249fe56b9e6SYuval Mintz 	do {							      \
1250fe56b9e6SYuval Mintz 		if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
1251fe56b9e6SYuval Mintz 			pr_notice("[%s:%d(%s)]" fmt,		      \
1252fe56b9e6SYuval Mintz 				  __func__, __LINE__,		      \
1253fe56b9e6SYuval Mintz 				  DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1254fe56b9e6SYuval Mintz 				  ## __VA_ARGS__);		      \
1255fe56b9e6SYuval Mintz 								      \
1256fe56b9e6SYuval Mintz 		}						      \
1257fe56b9e6SYuval Mintz 	} while (0)
1258fe56b9e6SYuval Mintz 
1259fe56b9e6SYuval Mintz #define DP_INFO(cdev, fmt, ...)					      \
1260fe56b9e6SYuval Mintz 	do {							      \
1261fe56b9e6SYuval Mintz 		if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) {   \
1262fe56b9e6SYuval Mintz 			pr_notice("[%s:%d(%s)]" fmt,		      \
1263fe56b9e6SYuval Mintz 				  __func__, __LINE__,		      \
1264fe56b9e6SYuval Mintz 				  DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1265fe56b9e6SYuval Mintz 				  ## __VA_ARGS__);		      \
1266fe56b9e6SYuval Mintz 		}						      \
1267fe56b9e6SYuval Mintz 	} while (0)
1268fe56b9e6SYuval Mintz 
1269fe56b9e6SYuval Mintz #define DP_VERBOSE(cdev, module, fmt, ...)				\
1270fe56b9e6SYuval Mintz 	do {								\
1271fe56b9e6SYuval Mintz 		if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) &&	\
1272fe56b9e6SYuval Mintz 			     ((cdev)->dp_module & module))) {		\
1273fe56b9e6SYuval Mintz 			pr_notice("[%s:%d(%s)]" fmt,			\
1274fe56b9e6SYuval Mintz 				  __func__, __LINE__,			\
1275fe56b9e6SYuval Mintz 				  DP_NAME(cdev) ? DP_NAME(cdev) : "",	\
1276fe56b9e6SYuval Mintz 				  ## __VA_ARGS__);			\
1277fe56b9e6SYuval Mintz 		}							\
1278fe56b9e6SYuval Mintz 	} while (0)
1279fe56b9e6SYuval Mintz 
1280fe56b9e6SYuval Mintz enum DP_LEVEL {
1281fe56b9e6SYuval Mintz 	QED_LEVEL_VERBOSE	= 0x0,
1282fe56b9e6SYuval Mintz 	QED_LEVEL_INFO		= 0x1,
1283fe56b9e6SYuval Mintz 	QED_LEVEL_NOTICE	= 0x2,
1284fe56b9e6SYuval Mintz 	QED_LEVEL_ERR		= 0x3,
1285fe56b9e6SYuval Mintz };
1286fe56b9e6SYuval Mintz 
1287fe56b9e6SYuval Mintz #define QED_LOG_LEVEL_SHIFT     (30)
1288fe56b9e6SYuval Mintz #define QED_LOG_VERBOSE_MASK    (0x3fffffff)
1289fe56b9e6SYuval Mintz #define QED_LOG_INFO_MASK       (0x40000000)
1290fe56b9e6SYuval Mintz #define QED_LOG_NOTICE_MASK     (0x80000000)
1291fe56b9e6SYuval Mintz 
1292fe56b9e6SYuval Mintz enum DP_MODULE {
1293fe56b9e6SYuval Mintz 	QED_MSG_SPQ	= 0x10000,
1294fe56b9e6SYuval Mintz 	QED_MSG_STATS	= 0x20000,
1295fe56b9e6SYuval Mintz 	QED_MSG_DCB	= 0x40000,
1296fe56b9e6SYuval Mintz 	QED_MSG_IOV	= 0x80000,
1297fe56b9e6SYuval Mintz 	QED_MSG_SP	= 0x100000,
1298fe56b9e6SYuval Mintz 	QED_MSG_STORAGE = 0x200000,
1299fe56b9e6SYuval Mintz 	QED_MSG_CXT	= 0x800000,
13000a7fb11cSYuval Mintz 	QED_MSG_LL2	= 0x1000000,
1301fe56b9e6SYuval Mintz 	QED_MSG_ILT	= 0x2000000,
130251ff1725SRam Amrani 	QED_MSG_RDMA	= 0x4000000,
1303fe56b9e6SYuval Mintz 	QED_MSG_DEBUG	= 0x8000000,
1304fe56b9e6SYuval Mintz 	/* to be added...up to 0x8000000 */
1305fe56b9e6SYuval Mintz };
1306fe56b9e6SYuval Mintz 
1307fc48b7a6SYuval Mintz enum qed_mf_mode {
1308fc48b7a6SYuval Mintz 	QED_MF_DEFAULT,
1309fc48b7a6SYuval Mintz 	QED_MF_OVLAN,
1310fc48b7a6SYuval Mintz 	QED_MF_NPAR,
1311fc48b7a6SYuval Mintz };
1312fc48b7a6SYuval Mintz 
13139c79ddaaSMintz, Yuval struct qed_eth_stats_common {
1314fe56b9e6SYuval Mintz 	u64	no_buff_discards;
1315fe56b9e6SYuval Mintz 	u64	packet_too_big_discard;
1316fe56b9e6SYuval Mintz 	u64	ttl0_discard;
1317fe56b9e6SYuval Mintz 	u64	rx_ucast_bytes;
1318fe56b9e6SYuval Mintz 	u64	rx_mcast_bytes;
1319fe56b9e6SYuval Mintz 	u64	rx_bcast_bytes;
1320fe56b9e6SYuval Mintz 	u64	rx_ucast_pkts;
1321fe56b9e6SYuval Mintz 	u64	rx_mcast_pkts;
1322fe56b9e6SYuval Mintz 	u64	rx_bcast_pkts;
1323fe56b9e6SYuval Mintz 	u64	mftag_filter_discards;
1324fe56b9e6SYuval Mintz 	u64	mac_filter_discards;
1325608e00d0SManish Chopra 	u64	gft_filter_drop;
1326fe56b9e6SYuval Mintz 	u64	tx_ucast_bytes;
1327fe56b9e6SYuval Mintz 	u64	tx_mcast_bytes;
1328fe56b9e6SYuval Mintz 	u64	tx_bcast_bytes;
1329fe56b9e6SYuval Mintz 	u64	tx_ucast_pkts;
1330fe56b9e6SYuval Mintz 	u64	tx_mcast_pkts;
1331fe56b9e6SYuval Mintz 	u64	tx_bcast_pkts;
1332fe56b9e6SYuval Mintz 	u64	tx_err_drop_pkts;
1333fe56b9e6SYuval Mintz 	u64	tpa_coalesced_pkts;
1334fe56b9e6SYuval Mintz 	u64	tpa_coalesced_events;
1335fe56b9e6SYuval Mintz 	u64	tpa_aborts_num;
1336fe56b9e6SYuval Mintz 	u64	tpa_not_coalesced_pkts;
1337fe56b9e6SYuval Mintz 	u64	tpa_coalesced_bytes;
1338fe56b9e6SYuval Mintz 
1339fe56b9e6SYuval Mintz 	/* port */
1340fe56b9e6SYuval Mintz 	u64	rx_64_byte_packets;
1341d4967cf3SYuval Mintz 	u64	rx_65_to_127_byte_packets;
1342d4967cf3SYuval Mintz 	u64	rx_128_to_255_byte_packets;
1343d4967cf3SYuval Mintz 	u64	rx_256_to_511_byte_packets;
1344d4967cf3SYuval Mintz 	u64	rx_512_to_1023_byte_packets;
1345d4967cf3SYuval Mintz 	u64	rx_1024_to_1518_byte_packets;
1346fe56b9e6SYuval Mintz 	u64	rx_crc_errors;
1347fe56b9e6SYuval Mintz 	u64	rx_mac_crtl_frames;
1348fe56b9e6SYuval Mintz 	u64	rx_pause_frames;
1349fe56b9e6SYuval Mintz 	u64	rx_pfc_frames;
1350fe56b9e6SYuval Mintz 	u64	rx_align_errors;
1351fe56b9e6SYuval Mintz 	u64	rx_carrier_errors;
1352fe56b9e6SYuval Mintz 	u64	rx_oversize_packets;
1353fe56b9e6SYuval Mintz 	u64	rx_jabbers;
1354fe56b9e6SYuval Mintz 	u64	rx_undersize_packets;
1355fe56b9e6SYuval Mintz 	u64	rx_fragments;
1356fe56b9e6SYuval Mintz 	u64	tx_64_byte_packets;
1357fe56b9e6SYuval Mintz 	u64	tx_65_to_127_byte_packets;
1358fe56b9e6SYuval Mintz 	u64	tx_128_to_255_byte_packets;
1359fe56b9e6SYuval Mintz 	u64	tx_256_to_511_byte_packets;
1360fe56b9e6SYuval Mintz 	u64	tx_512_to_1023_byte_packets;
1361fe56b9e6SYuval Mintz 	u64	tx_1024_to_1518_byte_packets;
1362fe56b9e6SYuval Mintz 	u64	tx_pause_frames;
1363fe56b9e6SYuval Mintz 	u64	tx_pfc_frames;
1364fe56b9e6SYuval Mintz 	u64	brb_truncates;
1365fe56b9e6SYuval Mintz 	u64	brb_discards;
1366fe56b9e6SYuval Mintz 	u64	rx_mac_bytes;
1367fe56b9e6SYuval Mintz 	u64	rx_mac_uc_packets;
1368fe56b9e6SYuval Mintz 	u64	rx_mac_mc_packets;
1369fe56b9e6SYuval Mintz 	u64	rx_mac_bc_packets;
1370fe56b9e6SYuval Mintz 	u64	rx_mac_frames_ok;
1371fe56b9e6SYuval Mintz 	u64	tx_mac_bytes;
1372fe56b9e6SYuval Mintz 	u64	tx_mac_uc_packets;
1373fe56b9e6SYuval Mintz 	u64	tx_mac_mc_packets;
1374fe56b9e6SYuval Mintz 	u64	tx_mac_bc_packets;
1375fe56b9e6SYuval Mintz 	u64	tx_mac_ctrl_frames;
137632d26a68SSudarsana Reddy Kalluru 	u64	link_change_count;
1377fe56b9e6SYuval Mintz };
1378fe56b9e6SYuval Mintz 
13799c79ddaaSMintz, Yuval struct qed_eth_stats_bb {
13809c79ddaaSMintz, Yuval 	u64 rx_1519_to_1522_byte_packets;
13819c79ddaaSMintz, Yuval 	u64 rx_1519_to_2047_byte_packets;
13829c79ddaaSMintz, Yuval 	u64 rx_2048_to_4095_byte_packets;
13839c79ddaaSMintz, Yuval 	u64 rx_4096_to_9216_byte_packets;
13849c79ddaaSMintz, Yuval 	u64 rx_9217_to_16383_byte_packets;
13859c79ddaaSMintz, Yuval 	u64 tx_1519_to_2047_byte_packets;
13869c79ddaaSMintz, Yuval 	u64 tx_2048_to_4095_byte_packets;
13879c79ddaaSMintz, Yuval 	u64 tx_4096_to_9216_byte_packets;
13889c79ddaaSMintz, Yuval 	u64 tx_9217_to_16383_byte_packets;
13899c79ddaaSMintz, Yuval 	u64 tx_lpi_entry_count;
13909c79ddaaSMintz, Yuval 	u64 tx_total_collisions;
13919c79ddaaSMintz, Yuval };
13929c79ddaaSMintz, Yuval 
13939c79ddaaSMintz, Yuval struct qed_eth_stats_ah {
13949c79ddaaSMintz, Yuval 	u64 rx_1519_to_max_byte_packets;
13959c79ddaaSMintz, Yuval 	u64 tx_1519_to_max_byte_packets;
13969c79ddaaSMintz, Yuval };
13979c79ddaaSMintz, Yuval 
13989c79ddaaSMintz, Yuval struct qed_eth_stats {
13999c79ddaaSMintz, Yuval 	struct qed_eth_stats_common common;
14009c79ddaaSMintz, Yuval 
14019c79ddaaSMintz, Yuval 	union {
14029c79ddaaSMintz, Yuval 		struct qed_eth_stats_bb bb;
14039c79ddaaSMintz, Yuval 		struct qed_eth_stats_ah ah;
14049c79ddaaSMintz, Yuval 	};
14059c79ddaaSMintz, Yuval };
14069c79ddaaSMintz, Yuval 
1407fe56b9e6SYuval Mintz #define QED_SB_IDX              0x0002
1408fe56b9e6SYuval Mintz 
1409fe56b9e6SYuval Mintz #define RX_PI           0
1410fe56b9e6SYuval Mintz #define TX_PI(tc)       (RX_PI + 1 + tc)
1411fe56b9e6SYuval Mintz 
14124ac801b7SYuval Mintz struct qed_sb_cnt_info {
1413726fdbe9SMintz, Yuval 	/* Original, current, and free SBs for PF */
1414726fdbe9SMintz, Yuval 	int orig;
1415726fdbe9SMintz, Yuval 	int cnt;
1416726fdbe9SMintz, Yuval 	int free_cnt;
1417726fdbe9SMintz, Yuval 
1418726fdbe9SMintz, Yuval 	/* Original, current and free SBS for child VFs */
1419726fdbe9SMintz, Yuval 	int iov_orig;
1420726fdbe9SMintz, Yuval 	int iov_cnt;
1421726fdbe9SMintz, Yuval 	int free_cnt_iov;
14224ac801b7SYuval Mintz };
14234ac801b7SYuval Mintz 
qed_sb_update_sb_idx(struct qed_sb_info * sb_info)1424fe56b9e6SYuval Mintz static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
1425fe56b9e6SYuval Mintz {
1426fe56b9e6SYuval Mintz 	u32 prod = 0;
1427fe56b9e6SYuval Mintz 	u16 rc = 0;
1428fe56b9e6SYuval Mintz 
1429fe56b9e6SYuval Mintz 	prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
1430fb09a1edSShai Malin 	       STATUS_BLOCK_PROD_INDEX_MASK;
1431fe56b9e6SYuval Mintz 	if (sb_info->sb_ack != prod) {
1432fe56b9e6SYuval Mintz 		sb_info->sb_ack = prod;
1433fe56b9e6SYuval Mintz 		rc |= QED_SB_IDX;
1434fe56b9e6SYuval Mintz 	}
1435fe56b9e6SYuval Mintz 
1436fe56b9e6SYuval Mintz 	/* Let SB update */
1437fe56b9e6SYuval Mintz 	return rc;
1438fe56b9e6SYuval Mintz }
1439fe56b9e6SYuval Mintz 
1440fe56b9e6SYuval Mintz /**
144119198e4eSPrabhakar Kushwaha  * qed_sb_ack(): This function creates an update command for interrupts
144219198e4eSPrabhakar Kushwaha  *               that is  written to the IGU.
1443fe56b9e6SYuval Mintz  *
144419198e4eSPrabhakar Kushwaha  * @sb_info: This is the structure allocated and
1445fe56b9e6SYuval Mintz  *           initialized per status block. Assumption is
1446fe56b9e6SYuval Mintz  *           that it was initialized using qed_sb_init
144719198e4eSPrabhakar Kushwaha  * @int_cmd: Enable/Disable/Nop
144819198e4eSPrabhakar Kushwaha  * @upd_flg: Whether igu consumer should be updated.
1449fe56b9e6SYuval Mintz  *
145019198e4eSPrabhakar Kushwaha  * Return: inline void.
1451fe56b9e6SYuval Mintz  */
qed_sb_ack(struct qed_sb_info * sb_info,enum igu_int_cmd int_cmd,u8 upd_flg)1452fe56b9e6SYuval Mintz static inline void qed_sb_ack(struct qed_sb_info *sb_info,
1453fe56b9e6SYuval Mintz 			      enum igu_int_cmd int_cmd,
1454fe56b9e6SYuval Mintz 			      u8 upd_flg)
1455fe56b9e6SYuval Mintz {
14565ab90341SAlexander Lobakin 	u32 igu_ack;
1457fe56b9e6SYuval Mintz 
14585ab90341SAlexander Lobakin 	igu_ack = ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1459fe56b9e6SYuval Mintz 		   (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1460fe56b9e6SYuval Mintz 		   (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1461fe56b9e6SYuval Mintz 		   (IGU_SEG_ACCESS_REG <<
1462fe56b9e6SYuval Mintz 		    IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1463fe56b9e6SYuval Mintz 
14645ab90341SAlexander Lobakin 	DIRECT_REG_WR(sb_info->igu_addr, igu_ack);
1465fe56b9e6SYuval Mintz 
1466fe56b9e6SYuval Mintz 	/* Both segments (interrupts & acks) are written to same place address;
1467fe56b9e6SYuval Mintz 	 * Need to guarantee all commands will be received (in-order) by HW.
1468fe56b9e6SYuval Mintz 	 */
1469fe56b9e6SYuval Mintz 	barrier();
1470fe56b9e6SYuval Mintz }
1471fe56b9e6SYuval Mintz 
__internal_ram_wr(void * p_hwfn,void __iomem * addr,int size,u32 * data)1472fe56b9e6SYuval Mintz static inline void __internal_ram_wr(void *p_hwfn,
1473fe56b9e6SYuval Mintz 				     void __iomem *addr,
1474fe56b9e6SYuval Mintz 				     int size,
1475fe56b9e6SYuval Mintz 				     u32 *data)
1476fe56b9e6SYuval Mintz 
1477fe56b9e6SYuval Mintz {
1478fe56b9e6SYuval Mintz 	unsigned int i;
1479fe56b9e6SYuval Mintz 
1480fe56b9e6SYuval Mintz 	for (i = 0; i < size / sizeof(*data); i++)
1481fe56b9e6SYuval Mintz 		DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
1482fe56b9e6SYuval Mintz }
1483fe56b9e6SYuval Mintz 
internal_ram_wr(void __iomem * addr,int size,u32 * data)1484fe56b9e6SYuval Mintz static inline void internal_ram_wr(void __iomem *addr,
1485fe56b9e6SYuval Mintz 				   int size,
1486fe56b9e6SYuval Mintz 				   u32 *data)
1487fe56b9e6SYuval Mintz {
1488fe56b9e6SYuval Mintz 	__internal_ram_wr(NULL, addr, size, data);
1489fe56b9e6SYuval Mintz }
1490fe56b9e6SYuval Mintz 
14918c5ebd0cSSudarsana Reddy Kalluru enum qed_rss_caps {
14928c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV4		= 0x1,
14938c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV6		= 0x2,
14948c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV4_TCP	= 0x4,
14958c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV6_TCP	= 0x8,
14968c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV4_UDP	= 0x10,
14978c5ebd0cSSudarsana Reddy Kalluru 	QED_RSS_IPV6_UDP	= 0x20,
14988c5ebd0cSSudarsana Reddy Kalluru };
14998c5ebd0cSSudarsana Reddy Kalluru 
15008c5ebd0cSSudarsana Reddy Kalluru #define QED_RSS_IND_TABLE_SIZE 128
15018c5ebd0cSSudarsana Reddy Kalluru #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
1502fe56b9e6SYuval Mintz #endif
1503