18425c41dSEsben Haabendal /* SPDX-License-Identifier: GPL-2.0 */ 28425c41dSEsben Haabendal #ifndef __LINUX_XILINX_LL_TEMAC_H 38425c41dSEsben Haabendal #define __LINUX_XILINX_LL_TEMAC_H 48425c41dSEsben Haabendal 58425c41dSEsben Haabendal #include <linux/if_ether.h> 68425c41dSEsben Haabendal #include <linux/phy.h> 78425c41dSEsben Haabendal 88425c41dSEsben Haabendal struct ll_temac_platform_data { 98425c41dSEsben Haabendal bool txcsum; /* Enable/disable TX checksum */ 108425c41dSEsben Haabendal bool rxcsum; /* Enable/disable RX checksum */ 118425c41dSEsben Haabendal u8 mac_addr[ETH_ALEN]; /* MAC address (6 bytes) */ 128425c41dSEsben Haabendal /* Clock frequency for input to MDIO clock generator */ 138425c41dSEsben Haabendal u32 mdio_clk_freq; 148425c41dSEsben Haabendal unsigned long long mdio_bus_id; /* Unique id for MDIO bus */ 158425c41dSEsben Haabendal int phy_addr; /* Address of the PHY to connect to */ 168425c41dSEsben Haabendal phy_interface_t phy_interface; /* PHY interface mode */ 17a3246dc4SEsben Haabendal bool reg_little_endian; /* Little endian TEMAC register access */ 18a3246dc4SEsben Haabendal bool dma_little_endian; /* Little endian DMA register access */ 19*f14f5c11SEsben Haabendal /* Pre-initialized mutex to use for synchronizing indirect 20*f14f5c11SEsben Haabendal * register access. When using both interfaces of a single 21*f14f5c11SEsben Haabendal * TEMAC IP block, the same mutex should be passed here, as 22*f14f5c11SEsben Haabendal * they share the same DCR bus bridge. 23*f14f5c11SEsben Haabendal */ 24*f14f5c11SEsben Haabendal struct mutex *indirect_mutex; 258425c41dSEsben Haabendal }; 268425c41dSEsben Haabendal 278425c41dSEsben Haabendal #endif /* __LINUX_XILINX_LL_TEMAC_H */ 28