1 #ifndef __TI_SYSC_DATA_H__ 2 #define __TI_SYSC_DATA_H__ 3 4 enum ti_sysc_module_type { 5 TI_SYSC_OMAP2, 6 TI_SYSC_OMAP2_TIMER, 7 TI_SYSC_OMAP3_SHAM, 8 TI_SYSC_OMAP3_AES, 9 TI_SYSC_OMAP4, 10 TI_SYSC_OMAP4_TIMER, 11 TI_SYSC_OMAP4_SIMPLE, 12 TI_SYSC_OMAP34XX_SR, 13 TI_SYSC_OMAP36XX_SR, 14 TI_SYSC_OMAP4_SR, 15 TI_SYSC_OMAP4_MCASP, 16 TI_SYSC_OMAP4_USB_HOST_FS, 17 }; 18 19 struct ti_sysc_cookie { 20 void *data; 21 }; 22 23 /** 24 * struct sysc_regbits - TI OCP_SYSCONFIG register field offsets 25 * @midle_shift: Offset of the midle bit 26 * @clkact_shift: Offset of the clockactivity bit 27 * @sidle_shift: Offset of the sidle bit 28 * @enwkup_shift: Offset of the enawakeup bit 29 * @srst_shift: Offset of the softreset bit 30 * @autoidle_shift: Offset of the autoidle bit 31 * @dmadisable_shift: Offset of the dmadisable bit 32 * @emufree_shift; Offset of the emufree bit 33 * 34 * Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a 35 * feature is not available. 36 */ 37 struct sysc_regbits { 38 s8 midle_shift; 39 s8 clkact_shift; 40 s8 sidle_shift; 41 s8 enwkup_shift; 42 s8 srst_shift; 43 s8 autoidle_shift; 44 s8 dmadisable_shift; 45 s8 emufree_shift; 46 }; 47 48 #define SYSC_QUIRK_LEGACY_IDLE BIT(8) 49 #define SYSC_QUIRK_RESET_STATUS BIT(7) 50 #define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6) 51 #define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5) 52 #define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4) 53 #define SYSC_QUIRK_OPT_CLKS_IN_RESET BIT(3) 54 #define SYSC_QUIRK_16BIT BIT(2) 55 #define SYSC_QUIRK_UNCACHED BIT(1) 56 #define SYSC_QUIRK_USE_CLOCKACT BIT(0) 57 58 #define SYSC_NR_IDLEMODES 4 59 60 /** 61 * struct sysc_capabilities - capabilities for an interconnect target module 62 * 63 * @sysc_mask: bitmask of supported SYSCONFIG register bits 64 * @regbits: bitmask of SYSCONFIG register bits 65 * @mod_quirks: bitmask of module specific quirks 66 */ 67 struct sysc_capabilities { 68 const enum ti_sysc_module_type type; 69 const u32 sysc_mask; 70 const struct sysc_regbits *regbits; 71 const u32 mod_quirks; 72 }; 73 74 /** 75 * struct sysc_config - configuration for an interconnect target module 76 * @sysc_val: configured value for sysc register 77 * @midlemodes: bitmask of supported master idle modes 78 * @sidlemodes: bitmask of supported master idle modes 79 * @srst_udelay: optional delay needed after OCP soft reset 80 * @quirks: bitmask of enabled quirks 81 */ 82 struct sysc_config { 83 u32 sysc_val; 84 u32 syss_mask; 85 u8 midlemodes; 86 u8 sidlemodes; 87 u8 srst_udelay; 88 u32 quirks; 89 }; 90 91 enum sysc_registers { 92 SYSC_REVISION, 93 SYSC_SYSCONFIG, 94 SYSC_SYSSTATUS, 95 SYSC_MAX_REGS, 96 }; 97 98 /** 99 * struct ti_sysc_module_data - ti-sysc to hwmod translation data for a module 100 * @name: legacy "ti,hwmods" module name 101 * @module_pa: physical address of the interconnect target module 102 * @module_size: size of the interconnect target module 103 * @offsets: array of register offsets as listed in enum sysc_registers 104 * @nr_offsets: number of registers 105 * @cap: interconnect target module capabilities 106 * @cfg: interconnect target module configuration 107 * 108 * This data is enough to allocate a new struct omap_hwmod_class_sysconfig 109 * based on device tree data parsed by ti-sysc driver. 110 */ 111 struct ti_sysc_module_data { 112 const char *name; 113 u64 module_pa; 114 u32 module_size; 115 int *offsets; 116 int nr_offsets; 117 const struct sysc_capabilities *cap; 118 struct sysc_config *cfg; 119 }; 120 121 struct device; 122 123 struct ti_sysc_platform_data { 124 struct of_dev_auxdata *auxdata; 125 int (*init_module)(struct device *dev, 126 const struct ti_sysc_module_data *data, 127 struct ti_sysc_cookie *cookie); 128 int (*enable_module)(struct device *dev, 129 const struct ti_sysc_cookie *cookie); 130 int (*idle_module)(struct device *dev, 131 const struct ti_sysc_cookie *cookie); 132 int (*shutdown_module)(struct device *dev, 133 const struct ti_sysc_cookie *cookie); 134 }; 135 136 #endif /* __TI_SYSC_DATA_H__ */ 137