149a0a3d8STony Lindgren #ifndef __TI_SYSC_DATA_H__ 249a0a3d8STony Lindgren #define __TI_SYSC_DATA_H__ 349a0a3d8STony Lindgren 470a65240STony Lindgren enum ti_sysc_module_type { 570a65240STony Lindgren TI_SYSC_OMAP2, 670a65240STony Lindgren TI_SYSC_OMAP2_TIMER, 770a65240STony Lindgren TI_SYSC_OMAP3_SHAM, 870a65240STony Lindgren TI_SYSC_OMAP3_AES, 970a65240STony Lindgren TI_SYSC_OMAP4, 1070a65240STony Lindgren TI_SYSC_OMAP4_TIMER, 1170a65240STony Lindgren TI_SYSC_OMAP4_SIMPLE, 1270a65240STony Lindgren TI_SYSC_OMAP34XX_SR, 1370a65240STony Lindgren TI_SYSC_OMAP36XX_SR, 1470a65240STony Lindgren TI_SYSC_OMAP4_SR, 1570a65240STony Lindgren TI_SYSC_OMAP4_MCASP, 1670a65240STony Lindgren TI_SYSC_OMAP4_USB_HOST_FS, 177f35e63dSFaiz Abbas TI_SYSC_DRA7_MCAN, 1870a65240STony Lindgren }; 1970a65240STony Lindgren 20ef70b0bdSTony Lindgren struct ti_sysc_cookie { 21ef70b0bdSTony Lindgren void *data; 222b2f7defSTony Lindgren void *clkdm; 23ef70b0bdSTony Lindgren }; 24ef70b0bdSTony Lindgren 2549a0a3d8STony Lindgren /** 2649a0a3d8STony Lindgren * struct sysc_regbits - TI OCP_SYSCONFIG register field offsets 2749a0a3d8STony Lindgren * @midle_shift: Offset of the midle bit 2849a0a3d8STony Lindgren * @clkact_shift: Offset of the clockactivity bit 2949a0a3d8STony Lindgren * @sidle_shift: Offset of the sidle bit 3049a0a3d8STony Lindgren * @enwkup_shift: Offset of the enawakeup bit 3149a0a3d8STony Lindgren * @srst_shift: Offset of the softreset bit 3249a0a3d8STony Lindgren * @autoidle_shift: Offset of the autoidle bit 3349a0a3d8STony Lindgren * @dmadisable_shift: Offset of the dmadisable bit 3449a0a3d8STony Lindgren * @emufree_shift; Offset of the emufree bit 3549a0a3d8STony Lindgren * 3649a0a3d8STony Lindgren * Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a 3749a0a3d8STony Lindgren * feature is not available. 3849a0a3d8STony Lindgren */ 3949a0a3d8STony Lindgren struct sysc_regbits { 4049a0a3d8STony Lindgren s8 midle_shift; 4149a0a3d8STony Lindgren s8 clkact_shift; 4249a0a3d8STony Lindgren s8 sidle_shift; 4349a0a3d8STony Lindgren s8 enwkup_shift; 4449a0a3d8STony Lindgren s8 srst_shift; 4549a0a3d8STony Lindgren s8 autoidle_shift; 4649a0a3d8STony Lindgren s8 dmadisable_shift; 4749a0a3d8STony Lindgren s8 emufree_shift; 4849a0a3d8STony Lindgren }; 4949a0a3d8STony Lindgren 50*e0db94feSTony Lindgren #define SYSS_QUIRK_RESETDONE_INVERTED BIT(14) 51b4a9a7a3STony Lindgren #define SYSC_QUIRK_SWSUP_MSTANDBY BIT(13) 52b4a9a7a3STony Lindgren #define SYSC_QUIRK_SWSUP_SIDLE_ACT BIT(12) 53b4a9a7a3STony Lindgren #define SYSC_QUIRK_SWSUP_SIDLE BIT(11) 54a54275f4STony Lindgren #define SYSC_QUIRK_EXT_OPT_CLOCK BIT(10) 55386cb766STony Lindgren #define SYSC_QUIRK_LEGACY_IDLE BIT(9) 56386cb766STony Lindgren #define SYSC_QUIRK_RESET_STATUS BIT(8) 57386cb766STony Lindgren #define SYSC_QUIRK_NO_IDLE BIT(7) 58566a9b05STony Lindgren #define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6) 59566a9b05STony Lindgren #define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5) 60566a9b05STony Lindgren #define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4) 61566a9b05STony Lindgren #define SYSC_QUIRK_OPT_CLKS_IN_RESET BIT(3) 62a7199e2bSTony Lindgren #define SYSC_QUIRK_16BIT BIT(2) 6370a65240STony Lindgren #define SYSC_QUIRK_UNCACHED BIT(1) 6470a65240STony Lindgren #define SYSC_QUIRK_USE_CLOCKACT BIT(0) 6570a65240STony Lindgren 66c5a2de97STony Lindgren #define SYSC_NR_IDLEMODES 4 67c5a2de97STony Lindgren 6870a65240STony Lindgren /** 6970a65240STony Lindgren * struct sysc_capabilities - capabilities for an interconnect target module 7070a65240STony Lindgren * 7170a65240STony Lindgren * @sysc_mask: bitmask of supported SYSCONFIG register bits 7270a65240STony Lindgren * @regbits: bitmask of SYSCONFIG register bits 7370a65240STony Lindgren * @mod_quirks: bitmask of module specific quirks 7470a65240STony Lindgren */ 7570a65240STony Lindgren struct sysc_capabilities { 7670a65240STony Lindgren const enum ti_sysc_module_type type; 7770a65240STony Lindgren const u32 sysc_mask; 7870a65240STony Lindgren const struct sysc_regbits *regbits; 7970a65240STony Lindgren const u32 mod_quirks; 8070a65240STony Lindgren }; 8170a65240STony Lindgren 8270a65240STony Lindgren /** 8370a65240STony Lindgren * struct sysc_config - configuration for an interconnect target module 84c5a2de97STony Lindgren * @sysc_val: configured value for sysc register 85c5a2de97STony Lindgren * @midlemodes: bitmask of supported master idle modes 86c5a2de97STony Lindgren * @sidlemodes: bitmask of supported master idle modes 87566a9b05STony Lindgren * @srst_udelay: optional delay needed after OCP soft reset 8870a65240STony Lindgren * @quirks: bitmask of enabled quirks 8970a65240STony Lindgren */ 9070a65240STony Lindgren struct sysc_config { 91c5a2de97STony Lindgren u32 sysc_val; 92c5a2de97STony Lindgren u32 syss_mask; 93c5a2de97STony Lindgren u8 midlemodes; 94c5a2de97STony Lindgren u8 sidlemodes; 95566a9b05STony Lindgren u8 srst_udelay; 9670a65240STony Lindgren u32 quirks; 9770a65240STony Lindgren }; 9870a65240STony Lindgren 99ef70b0bdSTony Lindgren enum sysc_registers { 100ef70b0bdSTony Lindgren SYSC_REVISION, 101ef70b0bdSTony Lindgren SYSC_SYSCONFIG, 102ef70b0bdSTony Lindgren SYSC_SYSSTATUS, 103ef70b0bdSTony Lindgren SYSC_MAX_REGS, 104ef70b0bdSTony Lindgren }; 105ef70b0bdSTony Lindgren 106ef70b0bdSTony Lindgren /** 107ef70b0bdSTony Lindgren * struct ti_sysc_module_data - ti-sysc to hwmod translation data for a module 108ef70b0bdSTony Lindgren * @name: legacy "ti,hwmods" module name 109ef70b0bdSTony Lindgren * @module_pa: physical address of the interconnect target module 110ef70b0bdSTony Lindgren * @module_size: size of the interconnect target module 111ef70b0bdSTony Lindgren * @offsets: array of register offsets as listed in enum sysc_registers 112ef70b0bdSTony Lindgren * @nr_offsets: number of registers 113ef70b0bdSTony Lindgren * @cap: interconnect target module capabilities 114ef70b0bdSTony Lindgren * @cfg: interconnect target module configuration 115ef70b0bdSTony Lindgren * 116ef70b0bdSTony Lindgren * This data is enough to allocate a new struct omap_hwmod_class_sysconfig 117ef70b0bdSTony Lindgren * based on device tree data parsed by ti-sysc driver. 118ef70b0bdSTony Lindgren */ 119ef70b0bdSTony Lindgren struct ti_sysc_module_data { 120ef70b0bdSTony Lindgren const char *name; 121ef70b0bdSTony Lindgren u64 module_pa; 122ef70b0bdSTony Lindgren u32 module_size; 123ef70b0bdSTony Lindgren int *offsets; 124ef70b0bdSTony Lindgren int nr_offsets; 125ef70b0bdSTony Lindgren const struct sysc_capabilities *cap; 126ef70b0bdSTony Lindgren struct sysc_config *cfg; 127ef70b0bdSTony Lindgren }; 128ef70b0bdSTony Lindgren 129ef70b0bdSTony Lindgren struct device; 1302b2f7defSTony Lindgren struct clk; 131ef70b0bdSTony Lindgren 132ef70b0bdSTony Lindgren struct ti_sysc_platform_data { 133ef70b0bdSTony Lindgren struct of_dev_auxdata *auxdata; 1342b2f7defSTony Lindgren int (*init_clockdomain)(struct device *dev, struct clk *fck, 1352b2f7defSTony Lindgren struct clk *ick, struct ti_sysc_cookie *cookie); 1362b2f7defSTony Lindgren void (*clkdm_deny_idle)(struct device *dev, 1372b2f7defSTony Lindgren const struct ti_sysc_cookie *cookie); 1382b2f7defSTony Lindgren void (*clkdm_allow_idle)(struct device *dev, 1392b2f7defSTony Lindgren const struct ti_sysc_cookie *cookie); 140ef70b0bdSTony Lindgren int (*init_module)(struct device *dev, 141ef70b0bdSTony Lindgren const struct ti_sysc_module_data *data, 142ef70b0bdSTony Lindgren struct ti_sysc_cookie *cookie); 143ef70b0bdSTony Lindgren int (*enable_module)(struct device *dev, 144ef70b0bdSTony Lindgren const struct ti_sysc_cookie *cookie); 145ef70b0bdSTony Lindgren int (*idle_module)(struct device *dev, 146ef70b0bdSTony Lindgren const struct ti_sysc_cookie *cookie); 147ef70b0bdSTony Lindgren int (*shutdown_module)(struct device *dev, 148ef70b0bdSTony Lindgren const struct ti_sysc_cookie *cookie); 149ef70b0bdSTony Lindgren }; 150ef70b0bdSTony Lindgren 15149a0a3d8STony Lindgren #endif /* __TI_SYSC_DATA_H__ */ 152