149a0a3d8STony Lindgren #ifndef __TI_SYSC_DATA_H__ 249a0a3d8STony Lindgren #define __TI_SYSC_DATA_H__ 349a0a3d8STony Lindgren 470a65240STony Lindgren enum ti_sysc_module_type { 570a65240STony Lindgren TI_SYSC_OMAP2, 670a65240STony Lindgren TI_SYSC_OMAP2_TIMER, 770a65240STony Lindgren TI_SYSC_OMAP3_SHAM, 870a65240STony Lindgren TI_SYSC_OMAP3_AES, 970a65240STony Lindgren TI_SYSC_OMAP4, 1070a65240STony Lindgren TI_SYSC_OMAP4_TIMER, 1170a65240STony Lindgren TI_SYSC_OMAP4_SIMPLE, 1270a65240STony Lindgren TI_SYSC_OMAP34XX_SR, 1370a65240STony Lindgren TI_SYSC_OMAP36XX_SR, 1470a65240STony Lindgren TI_SYSC_OMAP4_SR, 1570a65240STony Lindgren TI_SYSC_OMAP4_MCASP, 1670a65240STony Lindgren TI_SYSC_OMAP4_USB_HOST_FS, 1770a65240STony Lindgren }; 1870a65240STony Lindgren 1949a0a3d8STony Lindgren /** 2049a0a3d8STony Lindgren * struct sysc_regbits - TI OCP_SYSCONFIG register field offsets 2149a0a3d8STony Lindgren * @midle_shift: Offset of the midle bit 2249a0a3d8STony Lindgren * @clkact_shift: Offset of the clockactivity bit 2349a0a3d8STony Lindgren * @sidle_shift: Offset of the sidle bit 2449a0a3d8STony Lindgren * @enwkup_shift: Offset of the enawakeup bit 2549a0a3d8STony Lindgren * @srst_shift: Offset of the softreset bit 2649a0a3d8STony Lindgren * @autoidle_shift: Offset of the autoidle bit 2749a0a3d8STony Lindgren * @dmadisable_shift: Offset of the dmadisable bit 2849a0a3d8STony Lindgren * @emufree_shift; Offset of the emufree bit 2949a0a3d8STony Lindgren * 3049a0a3d8STony Lindgren * Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a 3149a0a3d8STony Lindgren * feature is not available. 3249a0a3d8STony Lindgren */ 3349a0a3d8STony Lindgren struct sysc_regbits { 3449a0a3d8STony Lindgren s8 midle_shift; 3549a0a3d8STony Lindgren s8 clkact_shift; 3649a0a3d8STony Lindgren s8 sidle_shift; 3749a0a3d8STony Lindgren s8 enwkup_shift; 3849a0a3d8STony Lindgren s8 srst_shift; 3949a0a3d8STony Lindgren s8 autoidle_shift; 4049a0a3d8STony Lindgren s8 dmadisable_shift; 4149a0a3d8STony Lindgren s8 emufree_shift; 4249a0a3d8STony Lindgren }; 4349a0a3d8STony Lindgren 44*566a9b05STony Lindgren #define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6) 45*566a9b05STony Lindgren #define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5) 46*566a9b05STony Lindgren #define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4) 47*566a9b05STony Lindgren #define SYSC_QUIRK_OPT_CLKS_IN_RESET BIT(3) 48a7199e2bSTony Lindgren #define SYSC_QUIRK_16BIT BIT(2) 4970a65240STony Lindgren #define SYSC_QUIRK_UNCACHED BIT(1) 5070a65240STony Lindgren #define SYSC_QUIRK_USE_CLOCKACT BIT(0) 5170a65240STony Lindgren 5270a65240STony Lindgren /** 5370a65240STony Lindgren * struct sysc_capabilities - capabilities for an interconnect target module 5470a65240STony Lindgren * 5570a65240STony Lindgren * @sysc_mask: bitmask of supported SYSCONFIG register bits 5670a65240STony Lindgren * @regbits: bitmask of SYSCONFIG register bits 5770a65240STony Lindgren * @mod_quirks: bitmask of module specific quirks 5870a65240STony Lindgren */ 5970a65240STony Lindgren struct sysc_capabilities { 6070a65240STony Lindgren const enum ti_sysc_module_type type; 6170a65240STony Lindgren const u32 sysc_mask; 6270a65240STony Lindgren const struct sysc_regbits *regbits; 6370a65240STony Lindgren const u32 mod_quirks; 6470a65240STony Lindgren }; 6570a65240STony Lindgren 6670a65240STony Lindgren /** 6770a65240STony Lindgren * struct sysc_config - configuration for an interconnect target module 68*566a9b05STony Lindgren * @srst_udelay: optional delay needed after OCP soft reset 6970a65240STony Lindgren * @quirks: bitmask of enabled quirks 7070a65240STony Lindgren */ 7170a65240STony Lindgren struct sysc_config { 72*566a9b05STony Lindgren u8 srst_udelay; 7370a65240STony Lindgren u32 quirks; 7470a65240STony Lindgren }; 7570a65240STony Lindgren 7649a0a3d8STony Lindgren #endif /* __TI_SYSC_DATA_H__ */ 77