1 /* 2 * SuperH FLCTL nand controller 3 * 4 * Copyright © 2008 Renesas Solutions Corp. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 */ 19 20 #ifndef __SH_FLCTL_H__ 21 #define __SH_FLCTL_H__ 22 23 #include <linux/mtd/mtd.h> 24 #include <linux/mtd/nand.h> 25 #include <linux/mtd/partitions.h> 26 #include <linux/pm_qos.h> 27 28 /* FLCTL registers */ 29 #define FLCMNCR(f) (f->reg + 0x0) 30 #define FLCMDCR(f) (f->reg + 0x4) 31 #define FLCMCDR(f) (f->reg + 0x8) 32 #define FLADR(f) (f->reg + 0xC) 33 #define FLADR2(f) (f->reg + 0x3C) 34 #define FLDATAR(f) (f->reg + 0x10) 35 #define FLDTCNTR(f) (f->reg + 0x14) 36 #define FLINTDMACR(f) (f->reg + 0x18) 37 #define FLBSYTMR(f) (f->reg + 0x1C) 38 #define FLBSYCNT(f) (f->reg + 0x20) 39 #define FLDTFIFO(f) (f->reg + 0x24) 40 #define FLECFIFO(f) (f->reg + 0x28) 41 #define FLTRCR(f) (f->reg + 0x2C) 42 #define FLHOLDCR(f) (f->reg + 0x38) 43 #define FL4ECCRESULT0(f) (f->reg + 0x80) 44 #define FL4ECCRESULT1(f) (f->reg + 0x84) 45 #define FL4ECCRESULT2(f) (f->reg + 0x88) 46 #define FL4ECCRESULT3(f) (f->reg + 0x8C) 47 #define FL4ECCCR(f) (f->reg + 0x90) 48 #define FL4ECCCNT(f) (f->reg + 0x94) 49 #define FLERRADR(f) (f->reg + 0x98) 50 51 /* FLCMNCR control bits */ 52 #define ECCPOS2 (0x1 << 25) 53 #define _4ECCCNTEN (0x1 << 24) 54 #define _4ECCEN (0x1 << 23) 55 #define _4ECCCORRECT (0x1 << 22) 56 #define SHBUSSEL (0x1 << 20) 57 #define SEL_16BIT (0x1 << 19) 58 #define SNAND_E (0x1 << 18) /* SNAND (0=512 1=2048)*/ 59 #define QTSEL_E (0x1 << 17) 60 #define ENDIAN (0x1 << 16) /* 1 = little endian */ 61 #define FCKSEL_E (0x1 << 15) 62 #define ECCPOS_00 (0x00 << 12) 63 #define ECCPOS_01 (0x01 << 12) 64 #define ECCPOS_02 (0x02 << 12) 65 #define ACM_SACCES_MODE (0x01 << 10) 66 #define NANWF_E (0x1 << 9) 67 #define SE_D (0x1 << 8) /* Spare area disable */ 68 #define CE1_ENABLE (0x1 << 4) /* Chip Enable 1 */ 69 #define CE0_ENABLE (0x1 << 3) /* Chip Enable 0 */ 70 #define TYPESEL_SET (0x1 << 0) 71 72 /* 73 * Clock settings using the PULSEx registers from FLCMNCR 74 * 75 * Some hardware uses bits called PULSEx instead of FCKSEL_E and QTSEL_E 76 * to control the clock divider used between the High-Speed Peripheral Clock 77 * and the FLCTL internal clock. If so, use CLK_8_BIT_xxx for connecting 8 bit 78 * and CLK_16_BIT_xxx for connecting 16 bit bus bandwith NAND chips. For the 16 79 * bit version the divider is seperate for the pulse width of high and low 80 * signals. 81 */ 82 #define PULSE3 (0x1 << 27) 83 #define PULSE2 (0x1 << 17) 84 #define PULSE1 (0x1 << 15) 85 #define PULSE0 (0x1 << 9) 86 #define CLK_8B_0_5 PULSE1 87 #define CLK_8B_1 0x0 88 #define CLK_8B_1_5 (PULSE1 | PULSE2) 89 #define CLK_8B_2 PULSE0 90 #define CLK_8B_3 (PULSE0 | PULSE1 | PULSE2) 91 #define CLK_8B_4 (PULSE0 | PULSE2) 92 #define CLK_16B_6L_2H PULSE0 93 #define CLK_16B_9L_3H (PULSE0 | PULSE1 | PULSE2) 94 #define CLK_16B_12L_4H (PULSE0 | PULSE2) 95 96 /* FLCMDCR control bits */ 97 #define ADRCNT2_E (0x1 << 31) /* 5byte address enable */ 98 #define ADRMD_E (0x1 << 26) /* Sector address access */ 99 #define CDSRC_E (0x1 << 25) /* Data buffer selection */ 100 #define DOSR_E (0x1 << 24) /* Status read check */ 101 #define SELRW (0x1 << 21) /* 0:read 1:write */ 102 #define DOADR_E (0x1 << 20) /* Address stage execute */ 103 #define ADRCNT_1 (0x00 << 18) /* Address data bytes: 1byte */ 104 #define ADRCNT_2 (0x01 << 18) /* Address data bytes: 2byte */ 105 #define ADRCNT_3 (0x02 << 18) /* Address data bytes: 3byte */ 106 #define ADRCNT_4 (0x03 << 18) /* Address data bytes: 4byte */ 107 #define DOCMD2_E (0x1 << 17) /* 2nd cmd stage execute */ 108 #define DOCMD1_E (0x1 << 16) /* 1st cmd stage execute */ 109 110 /* FLTRCR control bits */ 111 #define TRSTRT (0x1 << 0) /* translation start */ 112 #define TREND (0x1 << 1) /* translation end */ 113 114 /* 115 * FLHOLDCR control bits 116 * 117 * HOLDEN: Bus Occupancy Enable (inverted) 118 * Enable this bit when the external bus might be used in between transfers. 119 * If not set and the bus gets used by other modules, a deadlock occurs. 120 */ 121 #define HOLDEN (0x1 << 0) 122 123 /* FL4ECCCR control bits */ 124 #define _4ECCFA (0x1 << 2) /* 4 symbols correct fault */ 125 #define _4ECCEND (0x1 << 1) /* 4 symbols end */ 126 #define _4ECCEXST (0x1 << 0) /* 4 symbols exist */ 127 128 #define INIT_FL4ECCRESULT_VAL 0x03FF03FF 129 #define LOOP_TIMEOUT_MAX 0x00010000 130 131 struct sh_flctl { 132 struct mtd_info mtd; 133 struct nand_chip chip; 134 struct platform_device *pdev; 135 struct dev_pm_qos_request pm_qos; 136 void __iomem *reg; 137 138 uint8_t done_buff[2048 + 64]; /* max size 2048 + 64 */ 139 int read_bytes; 140 int index; 141 int seqin_column; /* column in SEQIN cmd */ 142 int seqin_page_addr; /* page_addr in SEQIN cmd */ 143 uint32_t seqin_read_cmd; /* read cmd in SEQIN cmd */ 144 int erase1_page_addr; /* page_addr in ERASE1 cmd */ 145 uint32_t erase_ADRCNT; /* bits of FLCMDCR in ERASE1 cmd */ 146 uint32_t rw_ADRCNT; /* bits of FLCMDCR in READ WRITE cmd */ 147 uint32_t flcmncr_base; /* base value of FLCMNCR */ 148 149 int hwecc_cant_correct[4]; 150 151 unsigned page_size:1; /* NAND page size (0 = 512, 1 = 2048) */ 152 unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */ 153 unsigned holden:1; /* Hardware has FLHOLDCR and HOLDEN is set */ 154 unsigned qos_request:1; /* QoS request to prevent deep power shutdown */ 155 }; 156 157 struct sh_flctl_platform_data { 158 struct mtd_partition *parts; 159 int nr_parts; 160 unsigned long flcmncr_val; 161 162 unsigned has_hwecc:1; 163 unsigned use_holden:1; 164 }; 165 166 static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo) 167 { 168 return container_of(mtdinfo, struct sh_flctl, mtd); 169 } 170 171 #endif /* __SH_FLCTL_H__ */ 172