1 /* 2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_QP_H 34 #define MLX5_QP_H 35 36 #include <linux/mlx5/device.h> 37 #include <linux/mlx5/driver.h> 38 39 #define MLX5_INVALID_LKEY 0x100 40 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5) 41 #define MLX5_DIF_SIZE 8 42 #define MLX5_STRIDE_BLOCK_OP 0x400 43 44 enum mlx5_qp_optpar { 45 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 46 MLX5_QP_OPTPAR_RRE = 1 << 1, 47 MLX5_QP_OPTPAR_RAE = 1 << 2, 48 MLX5_QP_OPTPAR_RWE = 1 << 3, 49 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, 50 MLX5_QP_OPTPAR_Q_KEY = 1 << 5, 51 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 52 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 53 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, 54 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, 55 MLX5_QP_OPTPAR_PM_STATE = 1 << 10, 56 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, 57 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, 58 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 59 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, 60 MLX5_QP_OPTPAR_SRQN = 1 << 18, 61 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, 62 MLX5_QP_OPTPAR_DC_HS = 1 << 20, 63 MLX5_QP_OPTPAR_DC_KEY = 1 << 21, 64 }; 65 66 enum mlx5_qp_state { 67 MLX5_QP_STATE_RST = 0, 68 MLX5_QP_STATE_INIT = 1, 69 MLX5_QP_STATE_RTR = 2, 70 MLX5_QP_STATE_RTS = 3, 71 MLX5_QP_STATE_SQER = 4, 72 MLX5_QP_STATE_SQD = 5, 73 MLX5_QP_STATE_ERR = 6, 74 MLX5_QP_STATE_SQ_DRAINING = 7, 75 MLX5_QP_STATE_SUSPENDED = 9, 76 MLX5_QP_NUM_STATE 77 }; 78 79 enum { 80 MLX5_QP_ST_RC = 0x0, 81 MLX5_QP_ST_UC = 0x1, 82 MLX5_QP_ST_UD = 0x2, 83 MLX5_QP_ST_XRC = 0x3, 84 MLX5_QP_ST_MLX = 0x4, 85 MLX5_QP_ST_DCI = 0x5, 86 MLX5_QP_ST_DCT = 0x6, 87 MLX5_QP_ST_QP0 = 0x7, 88 MLX5_QP_ST_QP1 = 0x8, 89 MLX5_QP_ST_RAW_ETHERTYPE = 0x9, 90 MLX5_QP_ST_RAW_IPV6 = 0xa, 91 MLX5_QP_ST_SNIFFER = 0xb, 92 MLX5_QP_ST_SYNC_UMR = 0xe, 93 MLX5_QP_ST_PTP_1588 = 0xd, 94 MLX5_QP_ST_REG_UMR = 0xc, 95 MLX5_QP_ST_MAX 96 }; 97 98 enum { 99 MLX5_QP_PM_MIGRATED = 0x3, 100 MLX5_QP_PM_ARMED = 0x0, 101 MLX5_QP_PM_REARM = 0x1 102 }; 103 104 enum { 105 MLX5_NON_ZERO_RQ = 0 << 24, 106 MLX5_SRQ_RQ = 1 << 24, 107 MLX5_CRQ_RQ = 2 << 24, 108 MLX5_ZERO_LEN_RQ = 3 << 24 109 }; 110 111 enum { 112 /* params1 */ 113 MLX5_QP_BIT_SRE = 1 << 15, 114 MLX5_QP_BIT_SWE = 1 << 14, 115 MLX5_QP_BIT_SAE = 1 << 13, 116 /* params2 */ 117 MLX5_QP_BIT_RRE = 1 << 15, 118 MLX5_QP_BIT_RWE = 1 << 14, 119 MLX5_QP_BIT_RAE = 1 << 13, 120 MLX5_QP_BIT_RIC = 1 << 4, 121 }; 122 123 enum { 124 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 125 MLX5_WQE_CTRL_SOLICITED = 1 << 1, 126 }; 127 128 enum { 129 MLX5_SEND_WQE_BB = 64, 130 }; 131 132 enum { 133 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 134 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 135 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 136 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 137 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 138 }; 139 140 enum { 141 MLX5_FENCE_MODE_NONE = 0 << 5, 142 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, 143 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, 144 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, 145 }; 146 147 enum { 148 MLX5_QP_LAT_SENSITIVE = 1 << 28, 149 MLX5_QP_BLOCK_MCAST = 1 << 30, 150 MLX5_QP_ENABLE_SIG = 1 << 31, 151 }; 152 153 enum { 154 MLX5_RCV_DBR = 0, 155 MLX5_SND_DBR = 1, 156 }; 157 158 enum { 159 MLX5_FLAGS_INLINE = 1<<7, 160 MLX5_FLAGS_CHECK_FREE = 1<<5, 161 }; 162 163 struct mlx5_wqe_fmr_seg { 164 __be32 flags; 165 __be32 mem_key; 166 __be64 buf_list; 167 __be64 start_addr; 168 __be64 reg_len; 169 __be32 offset; 170 __be32 page_size; 171 u32 reserved[2]; 172 }; 173 174 struct mlx5_wqe_ctrl_seg { 175 __be32 opmod_idx_opcode; 176 __be32 qpn_ds; 177 u8 signature; 178 u8 rsvd[2]; 179 u8 fm_ce_se; 180 __be32 imm; 181 }; 182 183 struct mlx5_wqe_xrc_seg { 184 __be32 xrc_srqn; 185 u8 rsvd[12]; 186 }; 187 188 struct mlx5_wqe_masked_atomic_seg { 189 __be64 swap_add; 190 __be64 compare; 191 __be64 swap_add_mask; 192 __be64 compare_mask; 193 }; 194 195 struct mlx5_av { 196 union { 197 struct { 198 __be32 qkey; 199 __be32 reserved; 200 } qkey; 201 __be64 dc_key; 202 } key; 203 __be32 dqp_dct; 204 u8 stat_rate_sl; 205 u8 fl_mlid; 206 __be16 rlid; 207 u8 reserved0[10]; 208 u8 tclass; 209 u8 hop_limit; 210 __be32 grh_gid_fl; 211 u8 rgid[16]; 212 }; 213 214 struct mlx5_wqe_datagram_seg { 215 struct mlx5_av av; 216 }; 217 218 struct mlx5_wqe_raddr_seg { 219 __be64 raddr; 220 __be32 rkey; 221 u32 reserved; 222 }; 223 224 struct mlx5_wqe_atomic_seg { 225 __be64 swap_add; 226 __be64 compare; 227 }; 228 229 struct mlx5_wqe_data_seg { 230 __be32 byte_count; 231 __be32 lkey; 232 __be64 addr; 233 }; 234 235 struct mlx5_wqe_umr_ctrl_seg { 236 u8 flags; 237 u8 rsvd0[3]; 238 __be16 klm_octowords; 239 __be16 bsf_octowords; 240 __be64 mkey_mask; 241 u8 rsvd1[32]; 242 }; 243 244 struct mlx5_seg_set_psv { 245 __be32 psv_num; 246 __be16 syndrome; 247 __be16 status; 248 __be32 transient_sig; 249 __be32 ref_tag; 250 }; 251 252 struct mlx5_seg_get_psv { 253 u8 rsvd[19]; 254 u8 num_psv; 255 __be32 l_key; 256 __be64 va; 257 __be32 psv_index[4]; 258 }; 259 260 struct mlx5_seg_check_psv { 261 u8 rsvd0[2]; 262 __be16 err_coalescing_op; 263 u8 rsvd1[2]; 264 __be16 xport_err_op; 265 u8 rsvd2[2]; 266 __be16 xport_err_mask; 267 u8 rsvd3[7]; 268 u8 num_psv; 269 __be32 l_key; 270 __be64 va; 271 __be32 psv_index[4]; 272 }; 273 274 struct mlx5_rwqe_sig { 275 u8 rsvd0[4]; 276 u8 signature; 277 u8 rsvd1[11]; 278 }; 279 280 struct mlx5_wqe_signature_seg { 281 u8 rsvd0[4]; 282 u8 signature; 283 u8 rsvd1[11]; 284 }; 285 286 struct mlx5_wqe_inline_seg { 287 __be32 byte_count; 288 }; 289 290 struct mlx5_bsf { 291 struct mlx5_bsf_basic { 292 u8 bsf_size_sbs; 293 u8 check_byte_mask; 294 union { 295 u8 copy_byte_mask; 296 u8 bs_selector; 297 u8 rsvd_wflags; 298 } wire; 299 union { 300 u8 bs_selector; 301 u8 rsvd_mflags; 302 } mem; 303 __be32 raw_data_size; 304 __be32 w_bfs_psv; 305 __be32 m_bfs_psv; 306 } basic; 307 struct mlx5_bsf_ext { 308 __be32 t_init_gen_pro_size; 309 __be32 rsvd_epi_size; 310 __be32 w_tfs_psv; 311 __be32 m_tfs_psv; 312 } ext; 313 struct mlx5_bsf_inl { 314 __be32 w_inl_vld; 315 __be32 w_rsvd; 316 __be64 w_block_format; 317 __be32 m_inl_vld; 318 __be32 m_rsvd; 319 __be64 m_block_format; 320 } inl; 321 }; 322 323 struct mlx5_klm { 324 __be32 bcount; 325 __be32 key; 326 __be64 va; 327 }; 328 329 struct mlx5_stride_block_entry { 330 __be16 stride; 331 __be16 bcount; 332 __be32 key; 333 __be64 va; 334 }; 335 336 struct mlx5_stride_block_ctrl_seg { 337 __be32 bcount_per_cycle; 338 __be32 op; 339 __be32 repeat_count; 340 u16 rsvd; 341 __be16 num_entries; 342 }; 343 344 struct mlx5_core_qp { 345 void (*event) (struct mlx5_core_qp *, int); 346 int qpn; 347 atomic_t refcount; 348 struct completion free; 349 struct mlx5_rsc_debug *dbg; 350 int pid; 351 }; 352 353 struct mlx5_qp_path { 354 u8 fl; 355 u8 rsvd3; 356 u8 free_ar; 357 u8 pkey_index; 358 u8 rsvd0; 359 u8 grh_mlid; 360 __be16 rlid; 361 u8 ackto_lt; 362 u8 mgid_index; 363 u8 static_rate; 364 u8 hop_limit; 365 __be32 tclass_flowlabel; 366 u8 rgid[16]; 367 u8 rsvd1[4]; 368 u8 sl; 369 u8 port; 370 u8 rsvd2[6]; 371 }; 372 373 struct mlx5_qp_context { 374 __be32 flags; 375 __be32 flags_pd; 376 u8 mtu_msgmax; 377 u8 rq_size_stride; 378 __be16 sq_crq_size; 379 __be32 qp_counter_set_usr_page; 380 __be32 wire_qpn; 381 __be32 log_pg_sz_remote_qpn; 382 struct mlx5_qp_path pri_path; 383 struct mlx5_qp_path alt_path; 384 __be32 params1; 385 u8 reserved2[4]; 386 __be32 next_send_psn; 387 __be32 cqn_send; 388 u8 reserved3[8]; 389 __be32 last_acked_psn; 390 __be32 ssn; 391 __be32 params2; 392 __be32 rnr_nextrecvpsn; 393 __be32 xrcd; 394 __be32 cqn_recv; 395 __be64 db_rec_addr; 396 __be32 qkey; 397 __be32 rq_type_srqn; 398 __be32 rmsn; 399 __be16 hw_sq_wqe_counter; 400 __be16 sw_sq_wqe_counter; 401 __be16 hw_rcyclic_byte_counter; 402 __be16 hw_rq_counter; 403 __be16 sw_rcyclic_byte_counter; 404 __be16 sw_rq_counter; 405 u8 rsvd0[5]; 406 u8 cgs; 407 u8 cs_req; 408 u8 cs_res; 409 __be64 dc_access_key; 410 u8 rsvd1[24]; 411 }; 412 413 struct mlx5_create_qp_mbox_in { 414 struct mlx5_inbox_hdr hdr; 415 __be32 input_qpn; 416 u8 rsvd0[4]; 417 __be32 opt_param_mask; 418 u8 rsvd1[4]; 419 struct mlx5_qp_context ctx; 420 u8 rsvd3[16]; 421 __be64 pas[0]; 422 }; 423 424 struct mlx5_create_qp_mbox_out { 425 struct mlx5_outbox_hdr hdr; 426 __be32 qpn; 427 u8 rsvd0[4]; 428 }; 429 430 struct mlx5_destroy_qp_mbox_in { 431 struct mlx5_inbox_hdr hdr; 432 __be32 qpn; 433 u8 rsvd0[4]; 434 }; 435 436 struct mlx5_destroy_qp_mbox_out { 437 struct mlx5_outbox_hdr hdr; 438 u8 rsvd0[8]; 439 }; 440 441 struct mlx5_modify_qp_mbox_in { 442 struct mlx5_inbox_hdr hdr; 443 __be32 qpn; 444 u8 rsvd1[4]; 445 __be32 optparam; 446 u8 rsvd0[4]; 447 struct mlx5_qp_context ctx; 448 }; 449 450 struct mlx5_modify_qp_mbox_out { 451 struct mlx5_outbox_hdr hdr; 452 u8 rsvd0[8]; 453 }; 454 455 struct mlx5_query_qp_mbox_in { 456 struct mlx5_inbox_hdr hdr; 457 __be32 qpn; 458 u8 rsvd[4]; 459 }; 460 461 struct mlx5_query_qp_mbox_out { 462 struct mlx5_outbox_hdr hdr; 463 u8 rsvd1[8]; 464 __be32 optparam; 465 u8 rsvd0[4]; 466 struct mlx5_qp_context ctx; 467 u8 rsvd2[16]; 468 __be64 pas[0]; 469 }; 470 471 struct mlx5_conf_sqp_mbox_in { 472 struct mlx5_inbox_hdr hdr; 473 __be32 qpn; 474 u8 rsvd[3]; 475 u8 type; 476 }; 477 478 struct mlx5_conf_sqp_mbox_out { 479 struct mlx5_outbox_hdr hdr; 480 u8 rsvd[8]; 481 }; 482 483 struct mlx5_alloc_xrcd_mbox_in { 484 struct mlx5_inbox_hdr hdr; 485 u8 rsvd[8]; 486 }; 487 488 struct mlx5_alloc_xrcd_mbox_out { 489 struct mlx5_outbox_hdr hdr; 490 __be32 xrcdn; 491 u8 rsvd[4]; 492 }; 493 494 struct mlx5_dealloc_xrcd_mbox_in { 495 struct mlx5_inbox_hdr hdr; 496 __be32 xrcdn; 497 u8 rsvd[4]; 498 }; 499 500 struct mlx5_dealloc_xrcd_mbox_out { 501 struct mlx5_outbox_hdr hdr; 502 u8 rsvd[8]; 503 }; 504 505 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn) 506 { 507 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn); 508 } 509 510 static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key) 511 { 512 return radix_tree_lookup(&dev->priv.mr_table.tree, key); 513 } 514 515 int mlx5_core_create_qp(struct mlx5_core_dev *dev, 516 struct mlx5_core_qp *qp, 517 struct mlx5_create_qp_mbox_in *in, 518 int inlen); 519 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state, 520 enum mlx5_qp_state new_state, 521 struct mlx5_modify_qp_mbox_in *in, int sqd_event, 522 struct mlx5_core_qp *qp); 523 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev, 524 struct mlx5_core_qp *qp); 525 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp, 526 struct mlx5_query_qp_mbox_out *out, int outlen); 527 528 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn); 529 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn); 530 void mlx5_init_qp_table(struct mlx5_core_dev *dev); 531 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev); 532 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 533 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 534 535 static inline const char *mlx5_qp_type_str(int type) 536 { 537 switch (type) { 538 case MLX5_QP_ST_RC: return "RC"; 539 case MLX5_QP_ST_UC: return "C"; 540 case MLX5_QP_ST_UD: return "UD"; 541 case MLX5_QP_ST_XRC: return "XRC"; 542 case MLX5_QP_ST_MLX: return "MLX"; 543 case MLX5_QP_ST_QP0: return "QP0"; 544 case MLX5_QP_ST_QP1: return "QP1"; 545 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; 546 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; 547 case MLX5_QP_ST_SNIFFER: return "SNIFFER"; 548 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; 549 case MLX5_QP_ST_PTP_1588: return "PTP_1588"; 550 case MLX5_QP_ST_REG_UMR: return "REG_UMR"; 551 default: return "Invalid transport type"; 552 } 553 } 554 555 static inline const char *mlx5_qp_state_str(int state) 556 { 557 switch (state) { 558 case MLX5_QP_STATE_RST: 559 return "RST"; 560 case MLX5_QP_STATE_INIT: 561 return "INIT"; 562 case MLX5_QP_STATE_RTR: 563 return "RTR"; 564 case MLX5_QP_STATE_RTS: 565 return "RTS"; 566 case MLX5_QP_STATE_SQER: 567 return "SQER"; 568 case MLX5_QP_STATE_SQD: 569 return "SQD"; 570 case MLX5_QP_STATE_ERR: 571 return "ERR"; 572 case MLX5_QP_STATE_SQ_DRAINING: 573 return "SQ_DRAINING"; 574 case MLX5_QP_STATE_SUSPENDED: 575 return "SUSPENDED"; 576 default: return "Invalid QP state"; 577 } 578 } 579 580 #endif /* MLX5_QP_H */ 581