1 /* 2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_QP_H 34 #define MLX5_QP_H 35 36 #include <linux/mlx5/device.h> 37 #include <linux/mlx5/driver.h> 38 39 #define MLX5_INVALID_LKEY 0x100 40 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5) 41 #define MLX5_DIF_SIZE 8 42 #define MLX5_STRIDE_BLOCK_OP 0x400 43 44 enum mlx5_qp_optpar { 45 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 46 MLX5_QP_OPTPAR_RRE = 1 << 1, 47 MLX5_QP_OPTPAR_RAE = 1 << 2, 48 MLX5_QP_OPTPAR_RWE = 1 << 3, 49 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, 50 MLX5_QP_OPTPAR_Q_KEY = 1 << 5, 51 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 52 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 53 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, 54 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, 55 MLX5_QP_OPTPAR_PM_STATE = 1 << 10, 56 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, 57 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, 58 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 59 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, 60 MLX5_QP_OPTPAR_SRQN = 1 << 18, 61 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, 62 MLX5_QP_OPTPAR_DC_HS = 1 << 20, 63 MLX5_QP_OPTPAR_DC_KEY = 1 << 21, 64 }; 65 66 enum mlx5_qp_state { 67 MLX5_QP_STATE_RST = 0, 68 MLX5_QP_STATE_INIT = 1, 69 MLX5_QP_STATE_RTR = 2, 70 MLX5_QP_STATE_RTS = 3, 71 MLX5_QP_STATE_SQER = 4, 72 MLX5_QP_STATE_SQD = 5, 73 MLX5_QP_STATE_ERR = 6, 74 MLX5_QP_STATE_SQ_DRAINING = 7, 75 MLX5_QP_STATE_SUSPENDED = 9, 76 MLX5_QP_NUM_STATE 77 }; 78 79 enum { 80 MLX5_QP_ST_RC = 0x0, 81 MLX5_QP_ST_UC = 0x1, 82 MLX5_QP_ST_UD = 0x2, 83 MLX5_QP_ST_XRC = 0x3, 84 MLX5_QP_ST_MLX = 0x4, 85 MLX5_QP_ST_DCI = 0x5, 86 MLX5_QP_ST_DCT = 0x6, 87 MLX5_QP_ST_QP0 = 0x7, 88 MLX5_QP_ST_QP1 = 0x8, 89 MLX5_QP_ST_RAW_ETHERTYPE = 0x9, 90 MLX5_QP_ST_RAW_IPV6 = 0xa, 91 MLX5_QP_ST_SNIFFER = 0xb, 92 MLX5_QP_ST_SYNC_UMR = 0xe, 93 MLX5_QP_ST_PTP_1588 = 0xd, 94 MLX5_QP_ST_REG_UMR = 0xc, 95 MLX5_QP_ST_MAX 96 }; 97 98 enum { 99 MLX5_QP_PM_MIGRATED = 0x3, 100 MLX5_QP_PM_ARMED = 0x0, 101 MLX5_QP_PM_REARM = 0x1 102 }; 103 104 enum { 105 MLX5_NON_ZERO_RQ = 0 << 24, 106 MLX5_SRQ_RQ = 1 << 24, 107 MLX5_CRQ_RQ = 2 << 24, 108 MLX5_ZERO_LEN_RQ = 3 << 24 109 }; 110 111 enum { 112 /* params1 */ 113 MLX5_QP_BIT_SRE = 1 << 15, 114 MLX5_QP_BIT_SWE = 1 << 14, 115 MLX5_QP_BIT_SAE = 1 << 13, 116 /* params2 */ 117 MLX5_QP_BIT_RRE = 1 << 15, 118 MLX5_QP_BIT_RWE = 1 << 14, 119 MLX5_QP_BIT_RAE = 1 << 13, 120 MLX5_QP_BIT_RIC = 1 << 4, 121 }; 122 123 enum { 124 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 125 MLX5_WQE_CTRL_SOLICITED = 1 << 1, 126 }; 127 128 enum { 129 MLX5_SEND_WQE_BB = 64, 130 }; 131 132 enum { 133 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 134 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 135 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 136 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 137 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 138 }; 139 140 enum { 141 MLX5_FENCE_MODE_NONE = 0 << 5, 142 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, 143 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, 144 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, 145 }; 146 147 enum { 148 MLX5_QP_LAT_SENSITIVE = 1 << 28, 149 MLX5_QP_ENABLE_SIG = 1 << 31, 150 }; 151 152 enum { 153 MLX5_RCV_DBR = 0, 154 MLX5_SND_DBR = 1, 155 }; 156 157 enum { 158 MLX5_FLAGS_INLINE = 1<<7, 159 MLX5_FLAGS_CHECK_FREE = 1<<5, 160 }; 161 162 struct mlx5_wqe_fmr_seg { 163 __be32 flags; 164 __be32 mem_key; 165 __be64 buf_list; 166 __be64 start_addr; 167 __be64 reg_len; 168 __be32 offset; 169 __be32 page_size; 170 u32 reserved[2]; 171 }; 172 173 struct mlx5_wqe_ctrl_seg { 174 __be32 opmod_idx_opcode; 175 __be32 qpn_ds; 176 u8 signature; 177 u8 rsvd[2]; 178 u8 fm_ce_se; 179 __be32 imm; 180 }; 181 182 struct mlx5_wqe_xrc_seg { 183 __be32 xrc_srqn; 184 u8 rsvd[12]; 185 }; 186 187 struct mlx5_wqe_masked_atomic_seg { 188 __be64 swap_add; 189 __be64 compare; 190 __be64 swap_add_mask; 191 __be64 compare_mask; 192 }; 193 194 struct mlx5_av { 195 union { 196 struct { 197 __be32 qkey; 198 __be32 reserved; 199 } qkey; 200 __be64 dc_key; 201 } key; 202 __be32 dqp_dct; 203 u8 stat_rate_sl; 204 u8 fl_mlid; 205 __be16 rlid; 206 u8 reserved0[10]; 207 u8 tclass; 208 u8 hop_limit; 209 __be32 grh_gid_fl; 210 u8 rgid[16]; 211 }; 212 213 struct mlx5_wqe_datagram_seg { 214 struct mlx5_av av; 215 }; 216 217 struct mlx5_wqe_raddr_seg { 218 __be64 raddr; 219 __be32 rkey; 220 u32 reserved; 221 }; 222 223 struct mlx5_wqe_atomic_seg { 224 __be64 swap_add; 225 __be64 compare; 226 }; 227 228 struct mlx5_wqe_data_seg { 229 __be32 byte_count; 230 __be32 lkey; 231 __be64 addr; 232 }; 233 234 struct mlx5_wqe_umr_ctrl_seg { 235 u8 flags; 236 u8 rsvd0[3]; 237 __be16 klm_octowords; 238 __be16 bsf_octowords; 239 __be64 mkey_mask; 240 u8 rsvd1[32]; 241 }; 242 243 struct mlx5_seg_set_psv { 244 __be32 psv_num; 245 __be16 syndrome; 246 __be16 status; 247 __be32 transient_sig; 248 __be32 ref_tag; 249 }; 250 251 struct mlx5_seg_get_psv { 252 u8 rsvd[19]; 253 u8 num_psv; 254 __be32 l_key; 255 __be64 va; 256 __be32 psv_index[4]; 257 }; 258 259 struct mlx5_seg_check_psv { 260 u8 rsvd0[2]; 261 __be16 err_coalescing_op; 262 u8 rsvd1[2]; 263 __be16 xport_err_op; 264 u8 rsvd2[2]; 265 __be16 xport_err_mask; 266 u8 rsvd3[7]; 267 u8 num_psv; 268 __be32 l_key; 269 __be64 va; 270 __be32 psv_index[4]; 271 }; 272 273 struct mlx5_rwqe_sig { 274 u8 rsvd0[4]; 275 u8 signature; 276 u8 rsvd1[11]; 277 }; 278 279 struct mlx5_wqe_signature_seg { 280 u8 rsvd0[4]; 281 u8 signature; 282 u8 rsvd1[11]; 283 }; 284 285 struct mlx5_wqe_inline_seg { 286 __be32 byte_count; 287 }; 288 289 struct mlx5_bsf { 290 struct mlx5_bsf_basic { 291 u8 bsf_size_sbs; 292 u8 check_byte_mask; 293 union { 294 u8 copy_byte_mask; 295 u8 bs_selector; 296 u8 rsvd_wflags; 297 } wire; 298 union { 299 u8 bs_selector; 300 u8 rsvd_mflags; 301 } mem; 302 __be32 raw_data_size; 303 __be32 w_bfs_psv; 304 __be32 m_bfs_psv; 305 } basic; 306 struct mlx5_bsf_ext { 307 __be32 t_init_gen_pro_size; 308 __be32 rsvd_epi_size; 309 __be32 w_tfs_psv; 310 __be32 m_tfs_psv; 311 } ext; 312 struct mlx5_bsf_inl { 313 __be32 w_inl_vld; 314 __be32 w_rsvd; 315 __be64 w_block_format; 316 __be32 m_inl_vld; 317 __be32 m_rsvd; 318 __be64 m_block_format; 319 } inl; 320 }; 321 322 struct mlx5_klm { 323 __be32 bcount; 324 __be32 key; 325 __be64 va; 326 }; 327 328 struct mlx5_stride_block_entry { 329 __be16 stride; 330 __be16 bcount; 331 __be32 key; 332 __be64 va; 333 }; 334 335 struct mlx5_stride_block_ctrl_seg { 336 __be32 bcount_per_cycle; 337 __be32 op; 338 __be32 repeat_count; 339 u16 rsvd; 340 __be16 num_entries; 341 }; 342 343 struct mlx5_core_qp { 344 void (*event) (struct mlx5_core_qp *, int); 345 int qpn; 346 atomic_t refcount; 347 struct completion free; 348 struct mlx5_rsc_debug *dbg; 349 int pid; 350 }; 351 352 struct mlx5_qp_path { 353 u8 fl; 354 u8 rsvd3; 355 u8 free_ar; 356 u8 pkey_index; 357 u8 rsvd0; 358 u8 grh_mlid; 359 __be16 rlid; 360 u8 ackto_lt; 361 u8 mgid_index; 362 u8 static_rate; 363 u8 hop_limit; 364 __be32 tclass_flowlabel; 365 u8 rgid[16]; 366 u8 rsvd1[4]; 367 u8 sl; 368 u8 port; 369 u8 rsvd2[6]; 370 }; 371 372 struct mlx5_qp_context { 373 __be32 flags; 374 __be32 flags_pd; 375 u8 mtu_msgmax; 376 u8 rq_size_stride; 377 __be16 sq_crq_size; 378 __be32 qp_counter_set_usr_page; 379 __be32 wire_qpn; 380 __be32 log_pg_sz_remote_qpn; 381 struct mlx5_qp_path pri_path; 382 struct mlx5_qp_path alt_path; 383 __be32 params1; 384 u8 reserved2[4]; 385 __be32 next_send_psn; 386 __be32 cqn_send; 387 u8 reserved3[8]; 388 __be32 last_acked_psn; 389 __be32 ssn; 390 __be32 params2; 391 __be32 rnr_nextrecvpsn; 392 __be32 xrcd; 393 __be32 cqn_recv; 394 __be64 db_rec_addr; 395 __be32 qkey; 396 __be32 rq_type_srqn; 397 __be32 rmsn; 398 __be16 hw_sq_wqe_counter; 399 __be16 sw_sq_wqe_counter; 400 __be16 hw_rcyclic_byte_counter; 401 __be16 hw_rq_counter; 402 __be16 sw_rcyclic_byte_counter; 403 __be16 sw_rq_counter; 404 u8 rsvd0[5]; 405 u8 cgs; 406 u8 cs_req; 407 u8 cs_res; 408 __be64 dc_access_key; 409 u8 rsvd1[24]; 410 }; 411 412 struct mlx5_create_qp_mbox_in { 413 struct mlx5_inbox_hdr hdr; 414 __be32 input_qpn; 415 u8 rsvd0[4]; 416 __be32 opt_param_mask; 417 u8 rsvd1[4]; 418 struct mlx5_qp_context ctx; 419 u8 rsvd3[16]; 420 __be64 pas[0]; 421 }; 422 423 struct mlx5_create_qp_mbox_out { 424 struct mlx5_outbox_hdr hdr; 425 __be32 qpn; 426 u8 rsvd0[4]; 427 }; 428 429 struct mlx5_destroy_qp_mbox_in { 430 struct mlx5_inbox_hdr hdr; 431 __be32 qpn; 432 u8 rsvd0[4]; 433 }; 434 435 struct mlx5_destroy_qp_mbox_out { 436 struct mlx5_outbox_hdr hdr; 437 u8 rsvd0[8]; 438 }; 439 440 struct mlx5_modify_qp_mbox_in { 441 struct mlx5_inbox_hdr hdr; 442 __be32 qpn; 443 u8 rsvd1[4]; 444 __be32 optparam; 445 u8 rsvd0[4]; 446 struct mlx5_qp_context ctx; 447 }; 448 449 struct mlx5_modify_qp_mbox_out { 450 struct mlx5_outbox_hdr hdr; 451 u8 rsvd0[8]; 452 }; 453 454 struct mlx5_query_qp_mbox_in { 455 struct mlx5_inbox_hdr hdr; 456 __be32 qpn; 457 u8 rsvd[4]; 458 }; 459 460 struct mlx5_query_qp_mbox_out { 461 struct mlx5_outbox_hdr hdr; 462 u8 rsvd1[8]; 463 __be32 optparam; 464 u8 rsvd0[4]; 465 struct mlx5_qp_context ctx; 466 u8 rsvd2[16]; 467 __be64 pas[0]; 468 }; 469 470 struct mlx5_conf_sqp_mbox_in { 471 struct mlx5_inbox_hdr hdr; 472 __be32 qpn; 473 u8 rsvd[3]; 474 u8 type; 475 }; 476 477 struct mlx5_conf_sqp_mbox_out { 478 struct mlx5_outbox_hdr hdr; 479 u8 rsvd[8]; 480 }; 481 482 struct mlx5_alloc_xrcd_mbox_in { 483 struct mlx5_inbox_hdr hdr; 484 u8 rsvd[8]; 485 }; 486 487 struct mlx5_alloc_xrcd_mbox_out { 488 struct mlx5_outbox_hdr hdr; 489 __be32 xrcdn; 490 u8 rsvd[4]; 491 }; 492 493 struct mlx5_dealloc_xrcd_mbox_in { 494 struct mlx5_inbox_hdr hdr; 495 __be32 xrcdn; 496 u8 rsvd[4]; 497 }; 498 499 struct mlx5_dealloc_xrcd_mbox_out { 500 struct mlx5_outbox_hdr hdr; 501 u8 rsvd[8]; 502 }; 503 504 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn) 505 { 506 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn); 507 } 508 509 static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key) 510 { 511 return radix_tree_lookup(&dev->priv.mr_table.tree, key); 512 } 513 514 int mlx5_core_create_qp(struct mlx5_core_dev *dev, 515 struct mlx5_core_qp *qp, 516 struct mlx5_create_qp_mbox_in *in, 517 int inlen); 518 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state, 519 enum mlx5_qp_state new_state, 520 struct mlx5_modify_qp_mbox_in *in, int sqd_event, 521 struct mlx5_core_qp *qp); 522 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev, 523 struct mlx5_core_qp *qp); 524 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp, 525 struct mlx5_query_qp_mbox_out *out, int outlen); 526 527 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn); 528 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn); 529 void mlx5_init_qp_table(struct mlx5_core_dev *dev); 530 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev); 531 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 532 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 533 534 static inline const char *mlx5_qp_type_str(int type) 535 { 536 switch (type) { 537 case MLX5_QP_ST_RC: return "RC"; 538 case MLX5_QP_ST_UC: return "C"; 539 case MLX5_QP_ST_UD: return "UD"; 540 case MLX5_QP_ST_XRC: return "XRC"; 541 case MLX5_QP_ST_MLX: return "MLX"; 542 case MLX5_QP_ST_QP0: return "QP0"; 543 case MLX5_QP_ST_QP1: return "QP1"; 544 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; 545 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; 546 case MLX5_QP_ST_SNIFFER: return "SNIFFER"; 547 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; 548 case MLX5_QP_ST_PTP_1588: return "PTP_1588"; 549 case MLX5_QP_ST_REG_UMR: return "REG_UMR"; 550 default: return "Invalid transport type"; 551 } 552 } 553 554 static inline const char *mlx5_qp_state_str(int state) 555 { 556 switch (state) { 557 case MLX5_QP_STATE_RST: 558 return "RST"; 559 case MLX5_QP_STATE_INIT: 560 return "INIT"; 561 case MLX5_QP_STATE_RTR: 562 return "RTR"; 563 case MLX5_QP_STATE_RTS: 564 return "RTS"; 565 case MLX5_QP_STATE_SQER: 566 return "SQER"; 567 case MLX5_QP_STATE_SQD: 568 return "SQD"; 569 case MLX5_QP_STATE_ERR: 570 return "ERR"; 571 case MLX5_QP_STATE_SQ_DRAINING: 572 return "SQ_DRAINING"; 573 case MLX5_QP_STATE_SUSPENDED: 574 return "SUSPENDED"; 575 default: return "Invalid QP state"; 576 } 577 } 578 579 #endif /* MLX5_QP_H */ 580