1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_QP_H 34 #define MLX5_QP_H 35 36 #include <linux/mlx5/device.h> 37 #include <linux/mlx5/driver.h> 38 39 #define MLX5_INVALID_LKEY 0x100 40 /* UMR (3 WQE_BB's) + SIG (3 WQE_BB's) + PSV (mem) + PSV (wire) */ 41 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 8) 42 #define MLX5_DIF_SIZE 8 43 #define MLX5_STRIDE_BLOCK_OP 0x400 44 #define MLX5_CPY_GRD_MASK 0xc0 45 #define MLX5_CPY_APP_MASK 0x30 46 #define MLX5_CPY_REF_MASK 0x0f 47 #define MLX5_BSF_INC_REFTAG (1 << 6) 48 #define MLX5_BSF_INL_VALID (1 << 15) 49 #define MLX5_BSF_REFRESH_DIF (1 << 14) 50 #define MLX5_BSF_REPEAT_BLOCK (1 << 7) 51 #define MLX5_BSF_APPTAG_ESCAPE 0x1 52 #define MLX5_BSF_APPREF_ESCAPE 0x2 53 54 enum mlx5_qp_optpar { 55 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 56 MLX5_QP_OPTPAR_RRE = 1 << 1, 57 MLX5_QP_OPTPAR_RAE = 1 << 2, 58 MLX5_QP_OPTPAR_RWE = 1 << 3, 59 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, 60 MLX5_QP_OPTPAR_Q_KEY = 1 << 5, 61 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 62 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 63 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, 64 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, 65 MLX5_QP_OPTPAR_PM_STATE = 1 << 10, 66 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, 67 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, 68 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 69 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, 70 MLX5_QP_OPTPAR_SRQN = 1 << 18, 71 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, 72 MLX5_QP_OPTPAR_DC_HS = 1 << 20, 73 MLX5_QP_OPTPAR_DC_KEY = 1 << 21, 74 MLX5_QP_OPTPAR_COUNTER_SET_ID = 1 << 25, 75 }; 76 77 enum mlx5_qp_state { 78 MLX5_QP_STATE_RST = 0, 79 MLX5_QP_STATE_INIT = 1, 80 MLX5_QP_STATE_RTR = 2, 81 MLX5_QP_STATE_RTS = 3, 82 MLX5_QP_STATE_SQER = 4, 83 MLX5_QP_STATE_SQD = 5, 84 MLX5_QP_STATE_ERR = 6, 85 MLX5_QP_STATE_SQ_DRAINING = 7, 86 MLX5_QP_STATE_SUSPENDED = 9, 87 MLX5_QP_NUM_STATE, 88 MLX5_QP_STATE, 89 MLX5_QP_STATE_BAD, 90 }; 91 92 enum { 93 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1, 94 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1, 95 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1, 96 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1, 97 }; 98 99 enum { 100 MLX5_QP_ST_RC = 0x0, 101 MLX5_QP_ST_UC = 0x1, 102 MLX5_QP_ST_UD = 0x2, 103 MLX5_QP_ST_XRC = 0x3, 104 MLX5_QP_ST_MLX = 0x4, 105 MLX5_QP_ST_DCI = 0x5, 106 MLX5_QP_ST_DCT = 0x6, 107 MLX5_QP_ST_QP0 = 0x7, 108 MLX5_QP_ST_QP1 = 0x8, 109 MLX5_QP_ST_RAW_ETHERTYPE = 0x9, 110 MLX5_QP_ST_RAW_IPV6 = 0xa, 111 MLX5_QP_ST_SNIFFER = 0xb, 112 MLX5_QP_ST_SYNC_UMR = 0xe, 113 MLX5_QP_ST_PTP_1588 = 0xd, 114 MLX5_QP_ST_REG_UMR = 0xc, 115 MLX5_QP_ST_MAX 116 }; 117 118 enum { 119 MLX5_QP_PM_MIGRATED = 0x3, 120 MLX5_QP_PM_ARMED = 0x0, 121 MLX5_QP_PM_REARM = 0x1 122 }; 123 124 enum { 125 MLX5_NON_ZERO_RQ = 0x0, 126 MLX5_SRQ_RQ = 0x1, 127 MLX5_CRQ_RQ = 0x2, 128 MLX5_ZERO_LEN_RQ = 0x3 129 }; 130 131 /* TODO REM */ 132 enum { 133 /* params1 */ 134 MLX5_QP_BIT_SRE = 1 << 15, 135 MLX5_QP_BIT_SWE = 1 << 14, 136 MLX5_QP_BIT_SAE = 1 << 13, 137 /* params2 */ 138 MLX5_QP_BIT_RRE = 1 << 15, 139 MLX5_QP_BIT_RWE = 1 << 14, 140 MLX5_QP_BIT_RAE = 1 << 13, 141 MLX5_QP_BIT_RIC = 1 << 4, 142 MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2, 143 MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1, 144 MLX5_QP_BIT_CC_MASTER = 1 << 0 145 }; 146 147 enum { 148 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 149 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2, 150 MLX5_WQE_CTRL_SOLICITED = 1 << 1, 151 }; 152 153 enum { 154 MLX5_SEND_WQE_DS = 16, 155 MLX5_SEND_WQE_BB = 64, 156 }; 157 158 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS) 159 160 enum { 161 MLX5_SEND_WQE_MAX_WQEBBS = 16, 162 }; 163 164 enum { 165 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 166 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 167 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 168 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 169 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 170 }; 171 172 enum { 173 MLX5_FENCE_MODE_NONE = 0 << 5, 174 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, 175 MLX5_FENCE_MODE_FENCE = 2 << 5, 176 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, 177 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, 178 }; 179 180 enum { 181 MLX5_RCV_DBR = 0, 182 MLX5_SND_DBR = 1, 183 }; 184 185 enum { 186 MLX5_FLAGS_INLINE = 1<<7, 187 MLX5_FLAGS_CHECK_FREE = 1<<5, 188 }; 189 190 struct mlx5_wqe_fmr_seg { 191 __be32 flags; 192 __be32 mem_key; 193 __be64 buf_list; 194 __be64 start_addr; 195 __be64 reg_len; 196 __be32 offset; 197 __be32 page_size; 198 u32 reserved[2]; 199 }; 200 201 struct mlx5_wqe_ctrl_seg { 202 __be32 opmod_idx_opcode; 203 __be32 qpn_ds; 204 u8 signature; 205 u8 rsvd[2]; 206 u8 fm_ce_se; 207 union { 208 __be32 general_id; 209 __be32 imm; 210 __be32 umr_mkey; 211 __be32 tisn; 212 }; 213 }; 214 215 #define MLX5_WQE_CTRL_DS_MASK 0x3f 216 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00 217 #define MLX5_WQE_CTRL_QPN_SHIFT 8 218 #define MLX5_WQE_DS_UNITS 16 219 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff 220 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00 221 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8 222 223 enum { 224 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4, 225 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5, 226 MLX5_ETH_WQE_L3_CSUM = 1 << 6, 227 MLX5_ETH_WQE_L4_CSUM = 1 << 7, 228 }; 229 230 enum { 231 MLX5_ETH_WQE_SVLAN = 1 << 0, 232 MLX5_ETH_WQE_TRAILER_HDR_OUTER_IP_ASSOC = 1 << 26, 233 MLX5_ETH_WQE_TRAILER_HDR_OUTER_L4_ASSOC = 1 << 27, 234 MLX5_ETH_WQE_TRAILER_HDR_INNER_IP_ASSOC = 3 << 26, 235 MLX5_ETH_WQE_TRAILER_HDR_INNER_L4_ASSOC = 1 << 28, 236 MLX5_ETH_WQE_INSERT_TRAILER = 1 << 30, 237 MLX5_ETH_WQE_INSERT_VLAN = 1 << 15, 238 }; 239 240 enum { 241 MLX5_ETH_WQE_SWP_INNER_L3_IPV6 = 1 << 0, 242 MLX5_ETH_WQE_SWP_INNER_L4_UDP = 1 << 1, 243 MLX5_ETH_WQE_SWP_OUTER_L3_IPV6 = 1 << 4, 244 MLX5_ETH_WQE_SWP_OUTER_L4_UDP = 1 << 5, 245 }; 246 247 struct mlx5_wqe_eth_seg { 248 u8 swp_outer_l4_offset; 249 u8 swp_outer_l3_offset; 250 u8 swp_inner_l4_offset; 251 u8 swp_inner_l3_offset; 252 u8 cs_flags; 253 u8 swp_flags; 254 __be16 mss; 255 __be32 rsvd2; 256 union { 257 struct { 258 __be16 sz; 259 u8 start[2]; 260 } inline_hdr; 261 struct { 262 __be16 type; 263 __be16 vlan_tci; 264 } insert; 265 __be32 trailer; 266 }; 267 }; 268 269 struct mlx5_wqe_xrc_seg { 270 __be32 xrc_srqn; 271 u8 rsvd[12]; 272 }; 273 274 struct mlx5_wqe_masked_atomic_seg { 275 __be64 swap_add; 276 __be64 compare; 277 __be64 swap_add_mask; 278 __be64 compare_mask; 279 }; 280 281 struct mlx5_base_av { 282 union { 283 struct { 284 __be32 qkey; 285 __be32 reserved; 286 } qkey; 287 __be64 dc_key; 288 } key; 289 __be32 dqp_dct; 290 u8 stat_rate_sl; 291 u8 fl_mlid; 292 union { 293 __be16 rlid; 294 __be16 udp_sport; 295 }; 296 }; 297 298 struct mlx5_av { 299 union { 300 struct { 301 __be32 qkey; 302 __be32 reserved; 303 } qkey; 304 __be64 dc_key; 305 } key; 306 __be32 dqp_dct; 307 u8 stat_rate_sl; 308 u8 fl_mlid; 309 union { 310 __be16 rlid; 311 __be16 udp_sport; 312 }; 313 u8 reserved0[4]; 314 u8 rmac[6]; 315 u8 tclass; 316 u8 hop_limit; 317 __be32 grh_gid_fl; 318 u8 rgid[16]; 319 }; 320 321 struct mlx5_ib_ah { 322 struct ib_ah ibah; 323 struct mlx5_av av; 324 }; 325 326 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah) 327 { 328 return container_of(ibah, struct mlx5_ib_ah, ibah); 329 } 330 331 struct mlx5_wqe_datagram_seg { 332 struct mlx5_av av; 333 }; 334 335 struct mlx5_wqe_raddr_seg { 336 __be64 raddr; 337 __be32 rkey; 338 u32 reserved; 339 }; 340 341 struct mlx5_wqe_atomic_seg { 342 __be64 swap_add; 343 __be64 compare; 344 }; 345 346 struct mlx5_wqe_data_seg { 347 __be32 byte_count; 348 __be32 lkey; 349 __be64 addr; 350 }; 351 352 struct mlx5_wqe_umr_ctrl_seg { 353 u8 flags; 354 u8 rsvd0[3]; 355 __be16 xlt_octowords; 356 union { 357 __be16 xlt_offset; 358 __be16 bsf_octowords; 359 }; 360 __be64 mkey_mask; 361 __be32 xlt_offset_47_16; 362 u8 rsvd1[28]; 363 }; 364 365 struct mlx5_seg_set_psv { 366 __be32 psv_num; 367 __be16 syndrome; 368 __be16 status; 369 __be32 transient_sig; 370 __be32 ref_tag; 371 }; 372 373 struct mlx5_seg_get_psv { 374 u8 rsvd[19]; 375 u8 num_psv; 376 __be32 l_key; 377 __be64 va; 378 __be32 psv_index[4]; 379 }; 380 381 struct mlx5_seg_check_psv { 382 u8 rsvd0[2]; 383 __be16 err_coalescing_op; 384 u8 rsvd1[2]; 385 __be16 xport_err_op; 386 u8 rsvd2[2]; 387 __be16 xport_err_mask; 388 u8 rsvd3[7]; 389 u8 num_psv; 390 __be32 l_key; 391 __be64 va; 392 __be32 psv_index[4]; 393 }; 394 395 struct mlx5_rwqe_sig { 396 u8 rsvd0[4]; 397 u8 signature; 398 u8 rsvd1[11]; 399 }; 400 401 struct mlx5_wqe_signature_seg { 402 u8 rsvd0[4]; 403 u8 signature; 404 u8 rsvd1[11]; 405 }; 406 407 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff 408 409 struct mlx5_wqe_inline_seg { 410 __be32 byte_count; 411 __be32 data[0]; 412 }; 413 414 enum mlx5_sig_type { 415 MLX5_DIF_CRC = 0x1, 416 MLX5_DIF_IPCS = 0x2, 417 }; 418 419 struct mlx5_bsf_inl { 420 __be16 vld_refresh; 421 __be16 dif_apptag; 422 __be32 dif_reftag; 423 u8 sig_type; 424 u8 rp_inv_seed; 425 u8 rsvd[3]; 426 u8 dif_inc_ref_guard_check; 427 __be16 dif_app_bitmask_check; 428 }; 429 430 struct mlx5_bsf { 431 struct mlx5_bsf_basic { 432 u8 bsf_size_sbs; 433 u8 check_byte_mask; 434 union { 435 u8 copy_byte_mask; 436 u8 bs_selector; 437 u8 rsvd_wflags; 438 } wire; 439 union { 440 u8 bs_selector; 441 u8 rsvd_mflags; 442 } mem; 443 __be32 raw_data_size; 444 __be32 w_bfs_psv; 445 __be32 m_bfs_psv; 446 } basic; 447 struct mlx5_bsf_ext { 448 __be32 t_init_gen_pro_size; 449 __be32 rsvd_epi_size; 450 __be32 w_tfs_psv; 451 __be32 m_tfs_psv; 452 } ext; 453 struct mlx5_bsf_inl w_inl; 454 struct mlx5_bsf_inl m_inl; 455 }; 456 457 struct mlx5_mtt { 458 __be64 ptag; 459 }; 460 461 struct mlx5_klm { 462 __be32 bcount; 463 __be32 key; 464 __be64 va; 465 }; 466 467 struct mlx5_stride_block_entry { 468 __be16 stride; 469 __be16 bcount; 470 __be32 key; 471 __be64 va; 472 }; 473 474 struct mlx5_stride_block_ctrl_seg { 475 __be32 bcount_per_cycle; 476 __be32 op; 477 __be32 repeat_count; 478 u16 rsvd; 479 __be16 num_entries; 480 }; 481 482 struct mlx5_core_qp { 483 struct mlx5_core_rsc_common common; /* must be first */ 484 void (*event) (struct mlx5_core_qp *, int); 485 int qpn; 486 struct mlx5_rsc_debug *dbg; 487 int pid; 488 u16 uid; 489 }; 490 491 struct mlx5_core_dct { 492 struct mlx5_core_qp mqp; 493 struct completion drained; 494 }; 495 496 struct mlx5_qp_path { 497 u8 fl_free_ar; 498 u8 rsvd3; 499 __be16 pkey_index; 500 u8 rsvd0; 501 u8 grh_mlid; 502 __be16 rlid; 503 u8 ackto_lt; 504 u8 mgid_index; 505 u8 static_rate; 506 u8 hop_limit; 507 __be32 tclass_flowlabel; 508 union { 509 u8 rgid[16]; 510 u8 rip[16]; 511 }; 512 u8 f_dscp_ecn_prio; 513 u8 ecn_dscp; 514 __be16 udp_sport; 515 u8 dci_cfi_prio_sl; 516 u8 port; 517 u8 rmac[6]; 518 }; 519 520 /* FIXME: use mlx5_ifc.h qpc */ 521 struct mlx5_qp_context { 522 __be32 flags; 523 __be32 flags_pd; 524 u8 mtu_msgmax; 525 u8 rq_size_stride; 526 __be16 sq_crq_size; 527 __be32 qp_counter_set_usr_page; 528 __be32 wire_qpn; 529 __be32 log_pg_sz_remote_qpn; 530 struct mlx5_qp_path pri_path; 531 struct mlx5_qp_path alt_path; 532 __be32 params1; 533 u8 reserved2[4]; 534 __be32 next_send_psn; 535 __be32 cqn_send; 536 __be32 deth_sqpn; 537 u8 reserved3[4]; 538 __be32 last_acked_psn; 539 __be32 ssn; 540 __be32 params2; 541 __be32 rnr_nextrecvpsn; 542 __be32 xrcd; 543 __be32 cqn_recv; 544 __be64 db_rec_addr; 545 __be32 qkey; 546 __be32 rq_type_srqn; 547 __be32 rmsn; 548 __be16 hw_sq_wqe_counter; 549 __be16 sw_sq_wqe_counter; 550 __be16 hw_rcyclic_byte_counter; 551 __be16 hw_rq_counter; 552 __be16 sw_rcyclic_byte_counter; 553 __be16 sw_rq_counter; 554 u8 rsvd0[5]; 555 u8 cgs; 556 u8 cs_req; 557 u8 cs_res; 558 __be64 dc_access_key; 559 u8 rsvd1[24]; 560 }; 561 562 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 563 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 564 565 static inline const char *mlx5_qp_type_str(int type) 566 { 567 switch (type) { 568 case MLX5_QP_ST_RC: return "RC"; 569 case MLX5_QP_ST_UC: return "C"; 570 case MLX5_QP_ST_UD: return "UD"; 571 case MLX5_QP_ST_XRC: return "XRC"; 572 case MLX5_QP_ST_MLX: return "MLX"; 573 case MLX5_QP_ST_QP0: return "QP0"; 574 case MLX5_QP_ST_QP1: return "QP1"; 575 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; 576 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; 577 case MLX5_QP_ST_SNIFFER: return "SNIFFER"; 578 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; 579 case MLX5_QP_ST_PTP_1588: return "PTP_1588"; 580 case MLX5_QP_ST_REG_UMR: return "REG_UMR"; 581 default: return "Invalid transport type"; 582 } 583 } 584 585 static inline const char *mlx5_qp_state_str(int state) 586 { 587 switch (state) { 588 case MLX5_QP_STATE_RST: 589 return "RST"; 590 case MLX5_QP_STATE_INIT: 591 return "INIT"; 592 case MLX5_QP_STATE_RTR: 593 return "RTR"; 594 case MLX5_QP_STATE_RTS: 595 return "RTS"; 596 case MLX5_QP_STATE_SQER: 597 return "SQER"; 598 case MLX5_QP_STATE_SQD: 599 return "SQD"; 600 case MLX5_QP_STATE_ERR: 601 return "ERR"; 602 case MLX5_QP_STATE_SQ_DRAINING: 603 return "SQ_DRAINING"; 604 case MLX5_QP_STATE_SUSPENDED: 605 return "SUSPENDED"; 606 default: return "Invalid QP state"; 607 } 608 } 609 610 #endif /* MLX5_QP_H */ 611