1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_QP_H 34 #define MLX5_QP_H 35 36 #include <linux/mlx5/device.h> 37 #include <linux/mlx5/driver.h> 38 39 #define MLX5_INVALID_LKEY 0x100 40 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5) 41 #define MLX5_DIF_SIZE 8 42 #define MLX5_STRIDE_BLOCK_OP 0x400 43 #define MLX5_CPY_GRD_MASK 0xc0 44 #define MLX5_CPY_APP_MASK 0x30 45 #define MLX5_CPY_REF_MASK 0x0f 46 #define MLX5_BSF_INC_REFTAG (1 << 6) 47 #define MLX5_BSF_INL_VALID (1 << 15) 48 #define MLX5_BSF_REFRESH_DIF (1 << 14) 49 #define MLX5_BSF_REPEAT_BLOCK (1 << 7) 50 #define MLX5_BSF_APPTAG_ESCAPE 0x1 51 #define MLX5_BSF_APPREF_ESCAPE 0x2 52 53 enum mlx5_qp_optpar { 54 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 55 MLX5_QP_OPTPAR_RRE = 1 << 1, 56 MLX5_QP_OPTPAR_RAE = 1 << 2, 57 MLX5_QP_OPTPAR_RWE = 1 << 3, 58 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, 59 MLX5_QP_OPTPAR_Q_KEY = 1 << 5, 60 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 61 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 62 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, 63 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, 64 MLX5_QP_OPTPAR_PM_STATE = 1 << 10, 65 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, 66 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, 67 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 68 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, 69 MLX5_QP_OPTPAR_SRQN = 1 << 18, 70 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, 71 MLX5_QP_OPTPAR_DC_HS = 1 << 20, 72 MLX5_QP_OPTPAR_DC_KEY = 1 << 21, 73 }; 74 75 enum mlx5_qp_state { 76 MLX5_QP_STATE_RST = 0, 77 MLX5_QP_STATE_INIT = 1, 78 MLX5_QP_STATE_RTR = 2, 79 MLX5_QP_STATE_RTS = 3, 80 MLX5_QP_STATE_SQER = 4, 81 MLX5_QP_STATE_SQD = 5, 82 MLX5_QP_STATE_ERR = 6, 83 MLX5_QP_STATE_SQ_DRAINING = 7, 84 MLX5_QP_STATE_SUSPENDED = 9, 85 MLX5_QP_NUM_STATE, 86 MLX5_QP_STATE, 87 MLX5_QP_STATE_BAD, 88 }; 89 90 enum { 91 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1, 92 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1, 93 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1, 94 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1, 95 }; 96 97 enum { 98 MLX5_QP_ST_RC = 0x0, 99 MLX5_QP_ST_UC = 0x1, 100 MLX5_QP_ST_UD = 0x2, 101 MLX5_QP_ST_XRC = 0x3, 102 MLX5_QP_ST_MLX = 0x4, 103 MLX5_QP_ST_DCI = 0x5, 104 MLX5_QP_ST_DCT = 0x6, 105 MLX5_QP_ST_QP0 = 0x7, 106 MLX5_QP_ST_QP1 = 0x8, 107 MLX5_QP_ST_RAW_ETHERTYPE = 0x9, 108 MLX5_QP_ST_RAW_IPV6 = 0xa, 109 MLX5_QP_ST_SNIFFER = 0xb, 110 MLX5_QP_ST_SYNC_UMR = 0xe, 111 MLX5_QP_ST_PTP_1588 = 0xd, 112 MLX5_QP_ST_REG_UMR = 0xc, 113 MLX5_QP_ST_MAX 114 }; 115 116 enum { 117 MLX5_QP_PM_MIGRATED = 0x3, 118 MLX5_QP_PM_ARMED = 0x0, 119 MLX5_QP_PM_REARM = 0x1 120 }; 121 122 enum { 123 MLX5_NON_ZERO_RQ = 0x0, 124 MLX5_SRQ_RQ = 0x1, 125 MLX5_CRQ_RQ = 0x2, 126 MLX5_ZERO_LEN_RQ = 0x3 127 }; 128 129 /* TODO REM */ 130 enum { 131 /* params1 */ 132 MLX5_QP_BIT_SRE = 1 << 15, 133 MLX5_QP_BIT_SWE = 1 << 14, 134 MLX5_QP_BIT_SAE = 1 << 13, 135 /* params2 */ 136 MLX5_QP_BIT_RRE = 1 << 15, 137 MLX5_QP_BIT_RWE = 1 << 14, 138 MLX5_QP_BIT_RAE = 1 << 13, 139 MLX5_QP_BIT_RIC = 1 << 4, 140 MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2, 141 MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1, 142 MLX5_QP_BIT_CC_MASTER = 1 << 0 143 }; 144 145 enum { 146 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 147 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2, 148 MLX5_WQE_CTRL_SOLICITED = 1 << 1, 149 }; 150 151 enum { 152 MLX5_SEND_WQE_DS = 16, 153 MLX5_SEND_WQE_BB = 64, 154 }; 155 156 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS) 157 158 enum { 159 MLX5_SEND_WQE_MAX_WQEBBS = 16, 160 }; 161 162 enum { 163 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 164 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 165 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 166 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 167 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 168 }; 169 170 enum { 171 MLX5_FENCE_MODE_NONE = 0 << 5, 172 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, 173 MLX5_FENCE_MODE_FENCE = 2 << 5, 174 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, 175 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, 176 }; 177 178 enum { 179 MLX5_RCV_DBR = 0, 180 MLX5_SND_DBR = 1, 181 }; 182 183 enum { 184 MLX5_FLAGS_INLINE = 1<<7, 185 MLX5_FLAGS_CHECK_FREE = 1<<5, 186 }; 187 188 struct mlx5_wqe_fmr_seg { 189 __be32 flags; 190 __be32 mem_key; 191 __be64 buf_list; 192 __be64 start_addr; 193 __be64 reg_len; 194 __be32 offset; 195 __be32 page_size; 196 u32 reserved[2]; 197 }; 198 199 struct mlx5_wqe_ctrl_seg { 200 __be32 opmod_idx_opcode; 201 __be32 qpn_ds; 202 u8 signature; 203 u8 rsvd[2]; 204 u8 fm_ce_se; 205 union { 206 __be32 general_id; 207 __be32 imm; 208 __be32 umr_mkey; 209 __be32 tisn; 210 }; 211 }; 212 213 #define MLX5_WQE_CTRL_DS_MASK 0x3f 214 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00 215 #define MLX5_WQE_CTRL_QPN_SHIFT 8 216 #define MLX5_WQE_DS_UNITS 16 217 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff 218 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00 219 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8 220 221 enum { 222 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4, 223 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5, 224 MLX5_ETH_WQE_L3_CSUM = 1 << 6, 225 MLX5_ETH_WQE_L4_CSUM = 1 << 7, 226 }; 227 228 enum { 229 MLX5_ETH_WQE_SVLAN = 1 << 0, 230 MLX5_ETH_WQE_INSERT_VLAN = 1 << 15, 231 }; 232 233 enum { 234 MLX5_ETH_WQE_SWP_INNER_L3_IPV6 = 1 << 0, 235 MLX5_ETH_WQE_SWP_INNER_L4_UDP = 1 << 1, 236 MLX5_ETH_WQE_SWP_OUTER_L3_IPV6 = 1 << 4, 237 MLX5_ETH_WQE_SWP_OUTER_L4_UDP = 1 << 5, 238 }; 239 240 struct mlx5_wqe_eth_seg { 241 u8 swp_outer_l4_offset; 242 u8 swp_outer_l3_offset; 243 u8 swp_inner_l4_offset; 244 u8 swp_inner_l3_offset; 245 u8 cs_flags; 246 u8 swp_flags; 247 __be16 mss; 248 __be32 rsvd2; 249 union { 250 struct { 251 __be16 sz; 252 u8 start[2]; 253 } inline_hdr; 254 struct { 255 __be16 type; 256 __be16 vlan_tci; 257 } insert; 258 }; 259 }; 260 261 struct mlx5_wqe_xrc_seg { 262 __be32 xrc_srqn; 263 u8 rsvd[12]; 264 }; 265 266 struct mlx5_wqe_masked_atomic_seg { 267 __be64 swap_add; 268 __be64 compare; 269 __be64 swap_add_mask; 270 __be64 compare_mask; 271 }; 272 273 struct mlx5_base_av { 274 union { 275 struct { 276 __be32 qkey; 277 __be32 reserved; 278 } qkey; 279 __be64 dc_key; 280 } key; 281 __be32 dqp_dct; 282 u8 stat_rate_sl; 283 u8 fl_mlid; 284 union { 285 __be16 rlid; 286 __be16 udp_sport; 287 }; 288 }; 289 290 struct mlx5_av { 291 union { 292 struct { 293 __be32 qkey; 294 __be32 reserved; 295 } qkey; 296 __be64 dc_key; 297 } key; 298 __be32 dqp_dct; 299 u8 stat_rate_sl; 300 u8 fl_mlid; 301 union { 302 __be16 rlid; 303 __be16 udp_sport; 304 }; 305 u8 reserved0[4]; 306 u8 rmac[6]; 307 u8 tclass; 308 u8 hop_limit; 309 __be32 grh_gid_fl; 310 u8 rgid[16]; 311 }; 312 313 struct mlx5_ib_ah { 314 struct ib_ah ibah; 315 struct mlx5_av av; 316 }; 317 318 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah) 319 { 320 return container_of(ibah, struct mlx5_ib_ah, ibah); 321 } 322 323 struct mlx5_wqe_datagram_seg { 324 struct mlx5_av av; 325 }; 326 327 struct mlx5_wqe_raddr_seg { 328 __be64 raddr; 329 __be32 rkey; 330 u32 reserved; 331 }; 332 333 struct mlx5_wqe_atomic_seg { 334 __be64 swap_add; 335 __be64 compare; 336 }; 337 338 struct mlx5_wqe_data_seg { 339 __be32 byte_count; 340 __be32 lkey; 341 __be64 addr; 342 }; 343 344 struct mlx5_wqe_umr_ctrl_seg { 345 u8 flags; 346 u8 rsvd0[3]; 347 __be16 xlt_octowords; 348 union { 349 __be16 xlt_offset; 350 __be16 bsf_octowords; 351 }; 352 __be64 mkey_mask; 353 __be32 xlt_offset_47_16; 354 u8 rsvd1[28]; 355 }; 356 357 struct mlx5_seg_set_psv { 358 __be32 psv_num; 359 __be16 syndrome; 360 __be16 status; 361 __be32 transient_sig; 362 __be32 ref_tag; 363 }; 364 365 struct mlx5_seg_get_psv { 366 u8 rsvd[19]; 367 u8 num_psv; 368 __be32 l_key; 369 __be64 va; 370 __be32 psv_index[4]; 371 }; 372 373 struct mlx5_seg_check_psv { 374 u8 rsvd0[2]; 375 __be16 err_coalescing_op; 376 u8 rsvd1[2]; 377 __be16 xport_err_op; 378 u8 rsvd2[2]; 379 __be16 xport_err_mask; 380 u8 rsvd3[7]; 381 u8 num_psv; 382 __be32 l_key; 383 __be64 va; 384 __be32 psv_index[4]; 385 }; 386 387 struct mlx5_rwqe_sig { 388 u8 rsvd0[4]; 389 u8 signature; 390 u8 rsvd1[11]; 391 }; 392 393 struct mlx5_wqe_signature_seg { 394 u8 rsvd0[4]; 395 u8 signature; 396 u8 rsvd1[11]; 397 }; 398 399 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff 400 401 struct mlx5_wqe_inline_seg { 402 __be32 byte_count; 403 __be32 data[0]; 404 }; 405 406 enum mlx5_sig_type { 407 MLX5_DIF_CRC = 0x1, 408 MLX5_DIF_IPCS = 0x2, 409 }; 410 411 struct mlx5_bsf_inl { 412 __be16 vld_refresh; 413 __be16 dif_apptag; 414 __be32 dif_reftag; 415 u8 sig_type; 416 u8 rp_inv_seed; 417 u8 rsvd[3]; 418 u8 dif_inc_ref_guard_check; 419 __be16 dif_app_bitmask_check; 420 }; 421 422 struct mlx5_bsf { 423 struct mlx5_bsf_basic { 424 u8 bsf_size_sbs; 425 u8 check_byte_mask; 426 union { 427 u8 copy_byte_mask; 428 u8 bs_selector; 429 u8 rsvd_wflags; 430 } wire; 431 union { 432 u8 bs_selector; 433 u8 rsvd_mflags; 434 } mem; 435 __be32 raw_data_size; 436 __be32 w_bfs_psv; 437 __be32 m_bfs_psv; 438 } basic; 439 struct mlx5_bsf_ext { 440 __be32 t_init_gen_pro_size; 441 __be32 rsvd_epi_size; 442 __be32 w_tfs_psv; 443 __be32 m_tfs_psv; 444 } ext; 445 struct mlx5_bsf_inl w_inl; 446 struct mlx5_bsf_inl m_inl; 447 }; 448 449 struct mlx5_mtt { 450 __be64 ptag; 451 }; 452 453 struct mlx5_klm { 454 __be32 bcount; 455 __be32 key; 456 __be64 va; 457 }; 458 459 struct mlx5_stride_block_entry { 460 __be16 stride; 461 __be16 bcount; 462 __be32 key; 463 __be64 va; 464 }; 465 466 struct mlx5_stride_block_ctrl_seg { 467 __be32 bcount_per_cycle; 468 __be32 op; 469 __be32 repeat_count; 470 u16 rsvd; 471 __be16 num_entries; 472 }; 473 474 struct mlx5_core_qp { 475 struct mlx5_core_rsc_common common; /* must be first */ 476 void (*event) (struct mlx5_core_qp *, int); 477 int qpn; 478 struct mlx5_rsc_debug *dbg; 479 int pid; 480 u16 uid; 481 }; 482 483 struct mlx5_core_dct { 484 struct mlx5_core_qp mqp; 485 struct completion drained; 486 }; 487 488 struct mlx5_qp_path { 489 u8 fl_free_ar; 490 u8 rsvd3; 491 __be16 pkey_index; 492 u8 rsvd0; 493 u8 grh_mlid; 494 __be16 rlid; 495 u8 ackto_lt; 496 u8 mgid_index; 497 u8 static_rate; 498 u8 hop_limit; 499 __be32 tclass_flowlabel; 500 union { 501 u8 rgid[16]; 502 u8 rip[16]; 503 }; 504 u8 f_dscp_ecn_prio; 505 u8 ecn_dscp; 506 __be16 udp_sport; 507 u8 dci_cfi_prio_sl; 508 u8 port; 509 u8 rmac[6]; 510 }; 511 512 /* FIXME: use mlx5_ifc.h qpc */ 513 struct mlx5_qp_context { 514 __be32 flags; 515 __be32 flags_pd; 516 u8 mtu_msgmax; 517 u8 rq_size_stride; 518 __be16 sq_crq_size; 519 __be32 qp_counter_set_usr_page; 520 __be32 wire_qpn; 521 __be32 log_pg_sz_remote_qpn; 522 struct mlx5_qp_path pri_path; 523 struct mlx5_qp_path alt_path; 524 __be32 params1; 525 u8 reserved2[4]; 526 __be32 next_send_psn; 527 __be32 cqn_send; 528 __be32 deth_sqpn; 529 u8 reserved3[4]; 530 __be32 last_acked_psn; 531 __be32 ssn; 532 __be32 params2; 533 __be32 rnr_nextrecvpsn; 534 __be32 xrcd; 535 __be32 cqn_recv; 536 __be64 db_rec_addr; 537 __be32 qkey; 538 __be32 rq_type_srqn; 539 __be32 rmsn; 540 __be16 hw_sq_wqe_counter; 541 __be16 sw_sq_wqe_counter; 542 __be16 hw_rcyclic_byte_counter; 543 __be16 hw_rq_counter; 544 __be16 sw_rcyclic_byte_counter; 545 __be16 sw_rq_counter; 546 u8 rsvd0[5]; 547 u8 cgs; 548 u8 cs_req; 549 u8 cs_res; 550 __be64 dc_access_key; 551 u8 rsvd1[24]; 552 }; 553 554 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn) 555 { 556 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn); 557 } 558 559 int mlx5_core_create_dct(struct mlx5_core_dev *dev, 560 struct mlx5_core_dct *qp, 561 u32 *in, int inlen, 562 u32 *out, int outlen); 563 int mlx5_core_create_qp(struct mlx5_core_dev *dev, 564 struct mlx5_core_qp *qp, 565 u32 *in, 566 int inlen); 567 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 opcode, 568 u32 opt_param_mask, void *qpc, 569 struct mlx5_core_qp *qp); 570 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev, 571 struct mlx5_core_qp *qp); 572 int mlx5_core_destroy_dct(struct mlx5_core_dev *dev, 573 struct mlx5_core_dct *dct); 574 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp, 575 u32 *out, int outlen); 576 int mlx5_core_dct_query(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct, 577 u32 *out, int outlen); 578 579 int mlx5_core_set_delay_drop(struct mlx5_core_dev *dev, 580 u32 timeout_usec); 581 582 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn); 583 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn); 584 void mlx5_init_qp_table(struct mlx5_core_dev *dev); 585 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev); 586 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 587 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 588 int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 589 struct mlx5_core_qp *rq); 590 void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev, 591 struct mlx5_core_qp *rq); 592 int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 593 struct mlx5_core_qp *sq); 594 void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev, 595 struct mlx5_core_qp *sq); 596 int mlx5_core_alloc_q_counter(struct mlx5_core_dev *dev, u16 *counter_id); 597 int mlx5_core_dealloc_q_counter(struct mlx5_core_dev *dev, u16 counter_id); 598 int mlx5_core_query_q_counter(struct mlx5_core_dev *dev, u16 counter_id, 599 int reset, void *out, int out_size); 600 601 struct mlx5_core_rsc_common *mlx5_core_res_hold(struct mlx5_core_dev *dev, 602 int res_num, 603 enum mlx5_res_type res_type); 604 void mlx5_core_res_put(struct mlx5_core_rsc_common *res); 605 606 static inline const char *mlx5_qp_type_str(int type) 607 { 608 switch (type) { 609 case MLX5_QP_ST_RC: return "RC"; 610 case MLX5_QP_ST_UC: return "C"; 611 case MLX5_QP_ST_UD: return "UD"; 612 case MLX5_QP_ST_XRC: return "XRC"; 613 case MLX5_QP_ST_MLX: return "MLX"; 614 case MLX5_QP_ST_QP0: return "QP0"; 615 case MLX5_QP_ST_QP1: return "QP1"; 616 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; 617 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; 618 case MLX5_QP_ST_SNIFFER: return "SNIFFER"; 619 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; 620 case MLX5_QP_ST_PTP_1588: return "PTP_1588"; 621 case MLX5_QP_ST_REG_UMR: return "REG_UMR"; 622 default: return "Invalid transport type"; 623 } 624 } 625 626 static inline const char *mlx5_qp_state_str(int state) 627 { 628 switch (state) { 629 case MLX5_QP_STATE_RST: 630 return "RST"; 631 case MLX5_QP_STATE_INIT: 632 return "INIT"; 633 case MLX5_QP_STATE_RTR: 634 return "RTR"; 635 case MLX5_QP_STATE_RTS: 636 return "RTS"; 637 case MLX5_QP_STATE_SQER: 638 return "SQER"; 639 case MLX5_QP_STATE_SQD: 640 return "SQD"; 641 case MLX5_QP_STATE_ERR: 642 return "ERR"; 643 case MLX5_QP_STATE_SQ_DRAINING: 644 return "SQ_DRAINING"; 645 case MLX5_QP_STATE_SUSPENDED: 646 return "SUSPENDED"; 647 default: return "Invalid QP state"; 648 } 649 } 650 651 #endif /* MLX5_QP_H */ 652