1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_QP_H 34 #define MLX5_QP_H 35 36 #include <linux/mlx5/device.h> 37 #include <linux/mlx5/driver.h> 38 39 #define MLX5_TERMINATE_SCATTER_LIST_LKEY cpu_to_be32(0x100) 40 /* UMR (3 WQE_BB's) + SIG (3 WQE_BB's) + PSV (mem) + PSV (wire) */ 41 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 8) 42 #define MLX5_DIF_SIZE 8 43 #define MLX5_STRIDE_BLOCK_OP 0x400 44 #define MLX5_CPY_GRD_MASK 0xc0 45 #define MLX5_CPY_APP_MASK 0x30 46 #define MLX5_CPY_REF_MASK 0x0f 47 #define MLX5_BSF_INC_REFTAG (1 << 6) 48 #define MLX5_BSF_INL_VALID (1 << 15) 49 #define MLX5_BSF_REFRESH_DIF (1 << 14) 50 #define MLX5_BSF_REPEAT_BLOCK (1 << 7) 51 #define MLX5_BSF_APPTAG_ESCAPE 0x1 52 #define MLX5_BSF_APPREF_ESCAPE 0x2 53 54 enum mlx5_qp_optpar { 55 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 56 MLX5_QP_OPTPAR_RRE = 1 << 1, 57 MLX5_QP_OPTPAR_RAE = 1 << 2, 58 MLX5_QP_OPTPAR_RWE = 1 << 3, 59 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, 60 MLX5_QP_OPTPAR_Q_KEY = 1 << 5, 61 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 62 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 63 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, 64 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, 65 MLX5_QP_OPTPAR_PM_STATE = 1 << 10, 66 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, 67 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, 68 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 69 MLX5_QP_OPTPAR_LAG_TX_AFF = 1 << 15, 70 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, 71 MLX5_QP_OPTPAR_SRQN = 1 << 18, 72 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, 73 MLX5_QP_OPTPAR_DC_HS = 1 << 20, 74 MLX5_QP_OPTPAR_DC_KEY = 1 << 21, 75 MLX5_QP_OPTPAR_COUNTER_SET_ID = 1 << 25, 76 }; 77 78 enum mlx5_qp_state { 79 MLX5_QP_STATE_RST = 0, 80 MLX5_QP_STATE_INIT = 1, 81 MLX5_QP_STATE_RTR = 2, 82 MLX5_QP_STATE_RTS = 3, 83 MLX5_QP_STATE_SQER = 4, 84 MLX5_QP_STATE_SQD = 5, 85 MLX5_QP_STATE_ERR = 6, 86 MLX5_QP_STATE_SQ_DRAINING = 7, 87 MLX5_QP_STATE_SUSPENDED = 9, 88 MLX5_QP_NUM_STATE, 89 MLX5_QP_STATE, 90 MLX5_QP_STATE_BAD, 91 }; 92 93 enum { 94 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1, 95 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1, 96 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1, 97 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1, 98 }; 99 100 enum { 101 MLX5_QP_ST_RC = 0x0, 102 MLX5_QP_ST_UC = 0x1, 103 MLX5_QP_ST_UD = 0x2, 104 MLX5_QP_ST_XRC = 0x3, 105 MLX5_QP_ST_MLX = 0x4, 106 MLX5_QP_ST_DCI = 0x5, 107 MLX5_QP_ST_DCT = 0x6, 108 MLX5_QP_ST_QP0 = 0x7, 109 MLX5_QP_ST_QP1 = 0x8, 110 MLX5_QP_ST_RAW_ETHERTYPE = 0x9, 111 MLX5_QP_ST_RAW_IPV6 = 0xa, 112 MLX5_QP_ST_SNIFFER = 0xb, 113 MLX5_QP_ST_SYNC_UMR = 0xe, 114 MLX5_QP_ST_PTP_1588 = 0xd, 115 MLX5_QP_ST_REG_UMR = 0xc, 116 MLX5_QP_ST_MAX 117 }; 118 119 enum { 120 MLX5_QP_PM_MIGRATED = 0x3, 121 MLX5_QP_PM_ARMED = 0x0, 122 MLX5_QP_PM_REARM = 0x1 123 }; 124 125 enum { 126 MLX5_NON_ZERO_RQ = 0x0, 127 MLX5_SRQ_RQ = 0x1, 128 MLX5_CRQ_RQ = 0x2, 129 MLX5_ZERO_LEN_RQ = 0x3 130 }; 131 132 /* TODO REM */ 133 enum { 134 /* params1 */ 135 MLX5_QP_BIT_SRE = 1 << 15, 136 MLX5_QP_BIT_SWE = 1 << 14, 137 MLX5_QP_BIT_SAE = 1 << 13, 138 /* params2 */ 139 MLX5_QP_BIT_RRE = 1 << 15, 140 MLX5_QP_BIT_RWE = 1 << 14, 141 MLX5_QP_BIT_RAE = 1 << 13, 142 MLX5_QP_BIT_RIC = 1 << 4, 143 MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2, 144 MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1, 145 MLX5_QP_BIT_CC_MASTER = 1 << 0 146 }; 147 148 enum { 149 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 150 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2, 151 MLX5_WQE_CTRL_SOLICITED = 1 << 1, 152 }; 153 154 enum { 155 MLX5_SEND_WQE_DS = 16, 156 MLX5_SEND_WQE_BB = 64, 157 }; 158 159 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS) 160 161 enum { 162 MLX5_SEND_WQE_MAX_WQEBBS = 16, 163 }; 164 165 #define MLX5_SEND_WQE_MAX_SIZE (MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQE_BB) 166 167 enum { 168 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 169 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 170 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 171 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 172 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 173 }; 174 175 enum { 176 MLX5_FENCE_MODE_NONE = 0 << 5, 177 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, 178 MLX5_FENCE_MODE_FENCE = 2 << 5, 179 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, 180 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, 181 }; 182 183 enum { 184 MLX5_RCV_DBR = 0, 185 MLX5_SND_DBR = 1, 186 }; 187 188 enum { 189 MLX5_FLAGS_INLINE = 1<<7, 190 MLX5_FLAGS_CHECK_FREE = 1<<5, 191 }; 192 193 struct mlx5_wqe_fmr_seg { 194 __be32 flags; 195 __be32 mem_key; 196 __be64 buf_list; 197 __be64 start_addr; 198 __be64 reg_len; 199 __be32 offset; 200 __be32 page_size; 201 u32 reserved[2]; 202 }; 203 204 struct mlx5_wqe_ctrl_seg { 205 __be32 opmod_idx_opcode; 206 __be32 qpn_ds; 207 208 struct_group(trailer, 209 210 u8 signature; 211 u8 rsvd[2]; 212 u8 fm_ce_se; 213 union { 214 __be32 general_id; 215 __be32 imm; 216 __be32 umr_mkey; 217 __be32 tis_tir_num; 218 }; 219 220 ); /* end of trailer group */ 221 }; 222 223 #define MLX5_WQE_CTRL_DS_MASK 0x3f 224 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00 225 #define MLX5_WQE_CTRL_QPN_SHIFT 8 226 #define MLX5_WQE_DS_UNITS 16 227 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff 228 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00 229 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8 230 231 enum { 232 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4, 233 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5, 234 MLX5_ETH_WQE_L3_CSUM = 1 << 6, 235 MLX5_ETH_WQE_L4_CSUM = 1 << 7, 236 }; 237 238 enum { 239 MLX5_ETH_WQE_SVLAN = 1 << 0, 240 MLX5_ETH_WQE_TRAILER_HDR_OUTER_IP_ASSOC = 1 << 26, 241 MLX5_ETH_WQE_TRAILER_HDR_OUTER_L4_ASSOC = 1 << 27, 242 MLX5_ETH_WQE_TRAILER_HDR_INNER_IP_ASSOC = 3 << 26, 243 MLX5_ETH_WQE_TRAILER_HDR_INNER_L4_ASSOC = 1 << 28, 244 MLX5_ETH_WQE_INSERT_TRAILER = 1 << 30, 245 MLX5_ETH_WQE_INSERT_VLAN = 1 << 15, 246 }; 247 248 enum { 249 MLX5_ETH_WQE_SWP_INNER_L3_IPV6 = 1 << 0, 250 MLX5_ETH_WQE_SWP_INNER_L4_UDP = 1 << 1, 251 MLX5_ETH_WQE_SWP_OUTER_L3_IPV6 = 1 << 4, 252 MLX5_ETH_WQE_SWP_OUTER_L4_UDP = 1 << 5, 253 }; 254 255 enum { 256 MLX5_ETH_WQE_FT_META_IPSEC = BIT(0), 257 MLX5_ETH_WQE_FT_META_MACSEC = BIT(1), 258 }; 259 260 struct mlx5_wqe_eth_seg { 261 u8 swp_outer_l4_offset; 262 u8 swp_outer_l3_offset; 263 u8 swp_inner_l4_offset; 264 u8 swp_inner_l3_offset; 265 u8 cs_flags; 266 u8 swp_flags; 267 __be16 mss; 268 __be32 flow_table_metadata; 269 union { 270 struct { 271 __be16 sz; 272 union { 273 u8 start[2]; 274 DECLARE_FLEX_ARRAY(u8, data); 275 }; 276 } inline_hdr; 277 struct { 278 __be16 type; 279 __be16 vlan_tci; 280 } insert; 281 __be32 trailer; 282 }; 283 }; 284 285 struct mlx5_wqe_xrc_seg { 286 __be32 xrc_srqn; 287 u8 rsvd[12]; 288 }; 289 290 struct mlx5_wqe_masked_atomic_seg { 291 __be64 swap_add; 292 __be64 compare; 293 __be64 swap_add_mask; 294 __be64 compare_mask; 295 }; 296 297 struct mlx5_base_av { 298 union { 299 struct { 300 __be32 qkey; 301 __be32 reserved; 302 } qkey; 303 __be64 dc_key; 304 } key; 305 __be32 dqp_dct; 306 u8 stat_rate_sl; 307 u8 fl_mlid; 308 union { 309 __be16 rlid; 310 __be16 udp_sport; 311 }; 312 }; 313 314 struct mlx5_av { 315 union { 316 struct { 317 __be32 qkey; 318 __be32 reserved; 319 } qkey; 320 __be64 dc_key; 321 } key; 322 __be32 dqp_dct; 323 u8 stat_rate_sl; 324 u8 fl_mlid; 325 union { 326 __be16 rlid; 327 __be16 udp_sport; 328 }; 329 u8 reserved0[4]; 330 u8 rmac[6]; 331 u8 tclass; 332 u8 hop_limit; 333 __be32 grh_gid_fl; 334 u8 rgid[16]; 335 }; 336 337 struct mlx5_ib_ah { 338 struct ib_ah ibah; 339 struct mlx5_av av; 340 u8 xmit_port; 341 }; 342 343 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah) 344 { 345 return container_of(ibah, struct mlx5_ib_ah, ibah); 346 } 347 348 struct mlx5_wqe_datagram_seg { 349 struct mlx5_av av; 350 }; 351 352 struct mlx5_wqe_raddr_seg { 353 __be64 raddr; 354 __be32 rkey; 355 u32 reserved; 356 }; 357 358 struct mlx5_wqe_atomic_seg { 359 __be64 swap_add; 360 __be64 compare; 361 }; 362 363 struct mlx5_wqe_data_seg { 364 __be32 byte_count; 365 __be32 lkey; 366 __be64 addr; 367 }; 368 369 struct mlx5_wqe_umr_ctrl_seg { 370 u8 flags; 371 u8 rsvd0[3]; 372 __be16 xlt_octowords; 373 union { 374 __be16 xlt_offset; 375 __be16 bsf_octowords; 376 }; 377 __be64 mkey_mask; 378 __be32 xlt_offset_47_16; 379 u8 rsvd1[28]; 380 }; 381 382 struct mlx5_seg_set_psv { 383 __be32 psv_num; 384 __be16 syndrome; 385 __be16 status; 386 __be32 transient_sig; 387 __be32 ref_tag; 388 }; 389 390 struct mlx5_seg_get_psv { 391 u8 rsvd[19]; 392 u8 num_psv; 393 __be32 l_key; 394 __be64 va; 395 __be32 psv_index[4]; 396 }; 397 398 struct mlx5_seg_check_psv { 399 u8 rsvd0[2]; 400 __be16 err_coalescing_op; 401 u8 rsvd1[2]; 402 __be16 xport_err_op; 403 u8 rsvd2[2]; 404 __be16 xport_err_mask; 405 u8 rsvd3[7]; 406 u8 num_psv; 407 __be32 l_key; 408 __be64 va; 409 __be32 psv_index[4]; 410 }; 411 412 struct mlx5_rwqe_sig { 413 u8 rsvd0[4]; 414 u8 signature; 415 u8 rsvd1[11]; 416 }; 417 418 struct mlx5_wqe_signature_seg { 419 u8 rsvd0[4]; 420 u8 signature; 421 u8 rsvd1[11]; 422 }; 423 424 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff 425 426 struct mlx5_wqe_inline_seg { 427 __be32 byte_count; 428 __be32 data[]; 429 }; 430 431 enum mlx5_sig_type { 432 MLX5_DIF_CRC = 0x1, 433 MLX5_DIF_IPCS = 0x2, 434 }; 435 436 struct mlx5_bsf_inl { 437 __be16 vld_refresh; 438 __be16 dif_apptag; 439 __be32 dif_reftag; 440 u8 sig_type; 441 u8 rp_inv_seed; 442 u8 rsvd[3]; 443 u8 dif_inc_ref_guard_check; 444 __be16 dif_app_bitmask_check; 445 }; 446 447 struct mlx5_bsf { 448 struct mlx5_bsf_basic { 449 u8 bsf_size_sbs; 450 u8 check_byte_mask; 451 union { 452 u8 copy_byte_mask; 453 u8 bs_selector; 454 u8 rsvd_wflags; 455 } wire; 456 union { 457 u8 bs_selector; 458 u8 rsvd_mflags; 459 } mem; 460 __be32 raw_data_size; 461 __be32 w_bfs_psv; 462 __be32 m_bfs_psv; 463 } basic; 464 struct mlx5_bsf_ext { 465 __be32 t_init_gen_pro_size; 466 __be32 rsvd_epi_size; 467 __be32 w_tfs_psv; 468 __be32 m_tfs_psv; 469 } ext; 470 struct mlx5_bsf_inl w_inl; 471 struct mlx5_bsf_inl m_inl; 472 }; 473 474 struct mlx5_mtt { 475 __be64 ptag; 476 }; 477 478 struct mlx5_klm { 479 __be32 bcount; 480 __be32 key; 481 __be64 va; 482 }; 483 484 struct mlx5_ksm { 485 __be32 reserved; 486 __be32 key; 487 __be64 va; 488 }; 489 490 struct mlx5_stride_block_entry { 491 __be16 stride; 492 __be16 bcount; 493 __be32 key; 494 __be64 va; 495 }; 496 497 struct mlx5_stride_block_ctrl_seg { 498 __be32 bcount_per_cycle; 499 __be32 op; 500 __be32 repeat_count; 501 u16 rsvd; 502 __be16 num_entries; 503 }; 504 505 struct mlx5_wqe_flow_update_ctrl_seg { 506 __be32 flow_idx_update; 507 __be32 dest_handle; 508 u8 reserved0[40]; 509 }; 510 511 struct mlx5_wqe_header_modify_argument_update_seg { 512 u8 argument_list[64]; 513 }; 514 515 struct mlx5_core_qp { 516 struct mlx5_core_rsc_common common; /* must be first */ 517 void (*event) (struct mlx5_core_qp *, int); 518 int qpn; 519 struct mlx5_rsc_debug *dbg; 520 int pid; 521 u16 uid; 522 }; 523 524 struct mlx5_core_dct { 525 struct mlx5_core_qp mqp; 526 struct completion drained; 527 }; 528 529 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 530 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 531 532 static inline const char *mlx5_qp_type_str(int type) 533 { 534 switch (type) { 535 case MLX5_QP_ST_RC: return "RC"; 536 case MLX5_QP_ST_UC: return "C"; 537 case MLX5_QP_ST_UD: return "UD"; 538 case MLX5_QP_ST_XRC: return "XRC"; 539 case MLX5_QP_ST_MLX: return "MLX"; 540 case MLX5_QP_ST_QP0: return "QP0"; 541 case MLX5_QP_ST_QP1: return "QP1"; 542 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; 543 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; 544 case MLX5_QP_ST_SNIFFER: return "SNIFFER"; 545 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; 546 case MLX5_QP_ST_PTP_1588: return "PTP_1588"; 547 case MLX5_QP_ST_REG_UMR: return "REG_UMR"; 548 default: return "Invalid transport type"; 549 } 550 } 551 552 static inline const char *mlx5_qp_state_str(int state) 553 { 554 switch (state) { 555 case MLX5_QP_STATE_RST: 556 return "RST"; 557 case MLX5_QP_STATE_INIT: 558 return "INIT"; 559 case MLX5_QP_STATE_RTR: 560 return "RTR"; 561 case MLX5_QP_STATE_RTS: 562 return "RTS"; 563 case MLX5_QP_STATE_SQER: 564 return "SQER"; 565 case MLX5_QP_STATE_SQD: 566 return "SQD"; 567 case MLX5_QP_STATE_ERR: 568 return "ERR"; 569 case MLX5_QP_STATE_SQ_DRAINING: 570 return "SQ_DRAINING"; 571 case MLX5_QP_STATE_SUSPENDED: 572 return "SUSPENDED"; 573 default: return "Invalid QP state"; 574 } 575 } 576 577 static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev) 578 { 579 return !MLX5_CAP_ROCE(dev, qp_ts_format) ? 580 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING : 581 MLX5_TIMESTAMP_FORMAT_DEFAULT; 582 } 583 584 #endif /* MLX5_QP_H */ 585