1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_QP_H 34 #define MLX5_QP_H 35 36 #include <linux/mlx5/device.h> 37 #include <linux/mlx5/driver.h> 38 39 #define MLX5_INVALID_LKEY 0x100 40 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5) 41 #define MLX5_DIF_SIZE 8 42 #define MLX5_STRIDE_BLOCK_OP 0x400 43 #define MLX5_CPY_GRD_MASK 0xc0 44 #define MLX5_CPY_APP_MASK 0x30 45 #define MLX5_CPY_REF_MASK 0x0f 46 #define MLX5_BSF_INC_REFTAG (1 << 6) 47 #define MLX5_BSF_INL_VALID (1 << 15) 48 #define MLX5_BSF_REFRESH_DIF (1 << 14) 49 #define MLX5_BSF_REPEAT_BLOCK (1 << 7) 50 #define MLX5_BSF_APPTAG_ESCAPE 0x1 51 #define MLX5_BSF_APPREF_ESCAPE 0x2 52 53 #define MLX5_QPN_BITS 24 54 #define MLX5_QPN_MASK ((1 << MLX5_QPN_BITS) - 1) 55 56 enum mlx5_qp_optpar { 57 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 58 MLX5_QP_OPTPAR_RRE = 1 << 1, 59 MLX5_QP_OPTPAR_RAE = 1 << 2, 60 MLX5_QP_OPTPAR_RWE = 1 << 3, 61 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, 62 MLX5_QP_OPTPAR_Q_KEY = 1 << 5, 63 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 64 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 65 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, 66 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, 67 MLX5_QP_OPTPAR_PM_STATE = 1 << 10, 68 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, 69 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, 70 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 71 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, 72 MLX5_QP_OPTPAR_SRQN = 1 << 18, 73 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, 74 MLX5_QP_OPTPAR_DC_HS = 1 << 20, 75 MLX5_QP_OPTPAR_DC_KEY = 1 << 21, 76 }; 77 78 enum mlx5_qp_state { 79 MLX5_QP_STATE_RST = 0, 80 MLX5_QP_STATE_INIT = 1, 81 MLX5_QP_STATE_RTR = 2, 82 MLX5_QP_STATE_RTS = 3, 83 MLX5_QP_STATE_SQER = 4, 84 MLX5_QP_STATE_SQD = 5, 85 MLX5_QP_STATE_ERR = 6, 86 MLX5_QP_STATE_SQ_DRAINING = 7, 87 MLX5_QP_STATE_SUSPENDED = 9, 88 MLX5_QP_NUM_STATE, 89 MLX5_QP_STATE, 90 MLX5_QP_STATE_BAD, 91 }; 92 93 enum { 94 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1, 95 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1, 96 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1, 97 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1, 98 }; 99 100 enum { 101 MLX5_QP_ST_RC = 0x0, 102 MLX5_QP_ST_UC = 0x1, 103 MLX5_QP_ST_UD = 0x2, 104 MLX5_QP_ST_XRC = 0x3, 105 MLX5_QP_ST_MLX = 0x4, 106 MLX5_QP_ST_DCI = 0x5, 107 MLX5_QP_ST_DCT = 0x6, 108 MLX5_QP_ST_QP0 = 0x7, 109 MLX5_QP_ST_QP1 = 0x8, 110 MLX5_QP_ST_RAW_ETHERTYPE = 0x9, 111 MLX5_QP_ST_RAW_IPV6 = 0xa, 112 MLX5_QP_ST_SNIFFER = 0xb, 113 MLX5_QP_ST_SYNC_UMR = 0xe, 114 MLX5_QP_ST_PTP_1588 = 0xd, 115 MLX5_QP_ST_REG_UMR = 0xc, 116 MLX5_QP_ST_MAX 117 }; 118 119 enum { 120 MLX5_QP_PM_MIGRATED = 0x3, 121 MLX5_QP_PM_ARMED = 0x0, 122 MLX5_QP_PM_REARM = 0x1 123 }; 124 125 enum { 126 MLX5_NON_ZERO_RQ = 0 << 24, 127 MLX5_SRQ_RQ = 1 << 24, 128 MLX5_CRQ_RQ = 2 << 24, 129 MLX5_ZERO_LEN_RQ = 3 << 24 130 }; 131 132 enum { 133 /* params1 */ 134 MLX5_QP_BIT_SRE = 1 << 15, 135 MLX5_QP_BIT_SWE = 1 << 14, 136 MLX5_QP_BIT_SAE = 1 << 13, 137 /* params2 */ 138 MLX5_QP_BIT_RRE = 1 << 15, 139 MLX5_QP_BIT_RWE = 1 << 14, 140 MLX5_QP_BIT_RAE = 1 << 13, 141 MLX5_QP_BIT_RIC = 1 << 4, 142 MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2, 143 MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1, 144 MLX5_QP_BIT_CC_MASTER = 1 << 0 145 }; 146 147 enum { 148 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 149 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2, 150 MLX5_WQE_CTRL_SOLICITED = 1 << 1, 151 }; 152 153 enum { 154 MLX5_SEND_WQE_DS = 16, 155 MLX5_SEND_WQE_BB = 64, 156 }; 157 158 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS) 159 160 enum { 161 MLX5_SEND_WQE_MAX_WQEBBS = 16, 162 }; 163 164 enum { 165 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 166 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 167 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 168 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 169 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 170 }; 171 172 enum { 173 MLX5_FENCE_MODE_NONE = 0 << 5, 174 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, 175 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, 176 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, 177 }; 178 179 enum { 180 MLX5_QP_LAT_SENSITIVE = 1 << 28, 181 MLX5_QP_BLOCK_MCAST = 1 << 30, 182 MLX5_QP_ENABLE_SIG = 1 << 31, 183 }; 184 185 enum { 186 MLX5_RCV_DBR = 0, 187 MLX5_SND_DBR = 1, 188 }; 189 190 enum { 191 MLX5_FLAGS_INLINE = 1<<7, 192 MLX5_FLAGS_CHECK_FREE = 1<<5, 193 }; 194 195 struct mlx5_wqe_fmr_seg { 196 __be32 flags; 197 __be32 mem_key; 198 __be64 buf_list; 199 __be64 start_addr; 200 __be64 reg_len; 201 __be32 offset; 202 __be32 page_size; 203 u32 reserved[2]; 204 }; 205 206 struct mlx5_wqe_ctrl_seg { 207 __be32 opmod_idx_opcode; 208 __be32 qpn_ds; 209 u8 signature; 210 u8 rsvd[2]; 211 u8 fm_ce_se; 212 __be32 imm; 213 }; 214 215 #define MLX5_WQE_CTRL_DS_MASK 0x3f 216 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00 217 #define MLX5_WQE_CTRL_QPN_SHIFT 8 218 #define MLX5_WQE_DS_UNITS 16 219 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff 220 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00 221 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8 222 223 enum { 224 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4, 225 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5, 226 MLX5_ETH_WQE_L3_CSUM = 1 << 6, 227 MLX5_ETH_WQE_L4_CSUM = 1 << 7, 228 }; 229 230 struct mlx5_wqe_eth_seg { 231 u8 rsvd0[4]; 232 u8 cs_flags; 233 u8 rsvd1; 234 __be16 mss; 235 __be32 rsvd2; 236 __be16 inline_hdr_sz; 237 u8 inline_hdr_start[2]; 238 }; 239 240 struct mlx5_wqe_xrc_seg { 241 __be32 xrc_srqn; 242 u8 rsvd[12]; 243 }; 244 245 struct mlx5_wqe_masked_atomic_seg { 246 __be64 swap_add; 247 __be64 compare; 248 __be64 swap_add_mask; 249 __be64 compare_mask; 250 }; 251 252 struct mlx5_av { 253 union { 254 struct { 255 __be32 qkey; 256 __be32 reserved; 257 } qkey; 258 __be64 dc_key; 259 } key; 260 __be32 dqp_dct; 261 u8 stat_rate_sl; 262 u8 fl_mlid; 263 union { 264 __be16 rlid; 265 __be16 udp_sport; 266 }; 267 u8 reserved0[4]; 268 u8 rmac[6]; 269 u8 tclass; 270 u8 hop_limit; 271 __be32 grh_gid_fl; 272 u8 rgid[16]; 273 }; 274 275 struct mlx5_wqe_datagram_seg { 276 struct mlx5_av av; 277 }; 278 279 struct mlx5_wqe_raddr_seg { 280 __be64 raddr; 281 __be32 rkey; 282 u32 reserved; 283 }; 284 285 struct mlx5_wqe_atomic_seg { 286 __be64 swap_add; 287 __be64 compare; 288 }; 289 290 struct mlx5_wqe_data_seg { 291 __be32 byte_count; 292 __be32 lkey; 293 __be64 addr; 294 }; 295 296 struct mlx5_wqe_umr_ctrl_seg { 297 u8 flags; 298 u8 rsvd0[3]; 299 __be16 klm_octowords; 300 __be16 bsf_octowords; 301 __be64 mkey_mask; 302 u8 rsvd1[32]; 303 }; 304 305 struct mlx5_seg_set_psv { 306 __be32 psv_num; 307 __be16 syndrome; 308 __be16 status; 309 __be32 transient_sig; 310 __be32 ref_tag; 311 }; 312 313 struct mlx5_seg_get_psv { 314 u8 rsvd[19]; 315 u8 num_psv; 316 __be32 l_key; 317 __be64 va; 318 __be32 psv_index[4]; 319 }; 320 321 struct mlx5_seg_check_psv { 322 u8 rsvd0[2]; 323 __be16 err_coalescing_op; 324 u8 rsvd1[2]; 325 __be16 xport_err_op; 326 u8 rsvd2[2]; 327 __be16 xport_err_mask; 328 u8 rsvd3[7]; 329 u8 num_psv; 330 __be32 l_key; 331 __be64 va; 332 __be32 psv_index[4]; 333 }; 334 335 struct mlx5_rwqe_sig { 336 u8 rsvd0[4]; 337 u8 signature; 338 u8 rsvd1[11]; 339 }; 340 341 struct mlx5_wqe_signature_seg { 342 u8 rsvd0[4]; 343 u8 signature; 344 u8 rsvd1[11]; 345 }; 346 347 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff 348 349 struct mlx5_wqe_inline_seg { 350 __be32 byte_count; 351 }; 352 353 enum mlx5_sig_type { 354 MLX5_DIF_CRC = 0x1, 355 MLX5_DIF_IPCS = 0x2, 356 }; 357 358 struct mlx5_bsf_inl { 359 __be16 vld_refresh; 360 __be16 dif_apptag; 361 __be32 dif_reftag; 362 u8 sig_type; 363 u8 rp_inv_seed; 364 u8 rsvd[3]; 365 u8 dif_inc_ref_guard_check; 366 __be16 dif_app_bitmask_check; 367 }; 368 369 struct mlx5_bsf { 370 struct mlx5_bsf_basic { 371 u8 bsf_size_sbs; 372 u8 check_byte_mask; 373 union { 374 u8 copy_byte_mask; 375 u8 bs_selector; 376 u8 rsvd_wflags; 377 } wire; 378 union { 379 u8 bs_selector; 380 u8 rsvd_mflags; 381 } mem; 382 __be32 raw_data_size; 383 __be32 w_bfs_psv; 384 __be32 m_bfs_psv; 385 } basic; 386 struct mlx5_bsf_ext { 387 __be32 t_init_gen_pro_size; 388 __be32 rsvd_epi_size; 389 __be32 w_tfs_psv; 390 __be32 m_tfs_psv; 391 } ext; 392 struct mlx5_bsf_inl w_inl; 393 struct mlx5_bsf_inl m_inl; 394 }; 395 396 struct mlx5_klm { 397 __be32 bcount; 398 __be32 key; 399 __be64 va; 400 }; 401 402 struct mlx5_stride_block_entry { 403 __be16 stride; 404 __be16 bcount; 405 __be32 key; 406 __be64 va; 407 }; 408 409 struct mlx5_stride_block_ctrl_seg { 410 __be32 bcount_per_cycle; 411 __be32 op; 412 __be32 repeat_count; 413 u16 rsvd; 414 __be16 num_entries; 415 }; 416 417 enum mlx5_pagefault_flags { 418 MLX5_PFAULT_REQUESTOR = 1 << 0, 419 MLX5_PFAULT_WRITE = 1 << 1, 420 MLX5_PFAULT_RDMA = 1 << 2, 421 }; 422 423 /* Contains the details of a pagefault. */ 424 struct mlx5_pagefault { 425 u32 bytes_committed; 426 u8 event_subtype; 427 enum mlx5_pagefault_flags flags; 428 union { 429 /* Initiator or send message responder pagefault details. */ 430 struct { 431 /* Received packet size, only valid for responders. */ 432 u32 packet_size; 433 /* 434 * WQE index. Refers to either the send queue or 435 * receive queue, according to event_subtype. 436 */ 437 u16 wqe_index; 438 } wqe; 439 /* RDMA responder pagefault details */ 440 struct { 441 u32 r_key; 442 /* 443 * Received packet size, minimal size page fault 444 * resolution required for forward progress. 445 */ 446 u32 packet_size; 447 u32 rdma_op_len; 448 u64 rdma_va; 449 } rdma; 450 }; 451 }; 452 453 struct mlx5_core_qp { 454 struct mlx5_core_rsc_common common; /* must be first */ 455 void (*event) (struct mlx5_core_qp *, int); 456 void (*pfault_handler)(struct mlx5_core_qp *, struct mlx5_pagefault *); 457 int qpn; 458 struct mlx5_rsc_debug *dbg; 459 int pid; 460 }; 461 462 struct mlx5_qp_path { 463 u8 fl_free_ar; 464 u8 rsvd3; 465 __be16 pkey_index; 466 u8 rsvd0; 467 u8 grh_mlid; 468 __be16 rlid; 469 u8 ackto_lt; 470 u8 mgid_index; 471 u8 static_rate; 472 u8 hop_limit; 473 __be32 tclass_flowlabel; 474 union { 475 u8 rgid[16]; 476 u8 rip[16]; 477 }; 478 u8 f_dscp_ecn_prio; 479 u8 ecn_dscp; 480 __be16 udp_sport; 481 u8 dci_cfi_prio_sl; 482 u8 port; 483 u8 rmac[6]; 484 }; 485 486 struct mlx5_qp_context { 487 __be32 flags; 488 __be32 flags_pd; 489 u8 mtu_msgmax; 490 u8 rq_size_stride; 491 __be16 sq_crq_size; 492 __be32 qp_counter_set_usr_page; 493 __be32 wire_qpn; 494 __be32 log_pg_sz_remote_qpn; 495 struct mlx5_qp_path pri_path; 496 struct mlx5_qp_path alt_path; 497 __be32 params1; 498 u8 reserved2[4]; 499 __be32 next_send_psn; 500 __be32 cqn_send; 501 __be32 deth_sqpn; 502 u8 reserved3[4]; 503 __be32 last_acked_psn; 504 __be32 ssn; 505 __be32 params2; 506 __be32 rnr_nextrecvpsn; 507 __be32 xrcd; 508 __be32 cqn_recv; 509 __be64 db_rec_addr; 510 __be32 qkey; 511 __be32 rq_type_srqn; 512 __be32 rmsn; 513 __be16 hw_sq_wqe_counter; 514 __be16 sw_sq_wqe_counter; 515 __be16 hw_rcyclic_byte_counter; 516 __be16 hw_rq_counter; 517 __be16 sw_rcyclic_byte_counter; 518 __be16 sw_rq_counter; 519 u8 rsvd0[5]; 520 u8 cgs; 521 u8 cs_req; 522 u8 cs_res; 523 __be64 dc_access_key; 524 u8 rsvd1[24]; 525 }; 526 527 struct mlx5_create_qp_mbox_in { 528 struct mlx5_inbox_hdr hdr; 529 __be32 input_qpn; 530 u8 rsvd0[4]; 531 __be32 opt_param_mask; 532 u8 rsvd1[4]; 533 struct mlx5_qp_context ctx; 534 u8 rsvd3[16]; 535 __be64 pas[0]; 536 }; 537 538 struct mlx5_create_qp_mbox_out { 539 struct mlx5_outbox_hdr hdr; 540 __be32 qpn; 541 u8 rsvd0[4]; 542 }; 543 544 struct mlx5_destroy_qp_mbox_in { 545 struct mlx5_inbox_hdr hdr; 546 __be32 qpn; 547 u8 rsvd0[4]; 548 }; 549 550 struct mlx5_destroy_qp_mbox_out { 551 struct mlx5_outbox_hdr hdr; 552 u8 rsvd0[8]; 553 }; 554 555 struct mlx5_modify_qp_mbox_in { 556 struct mlx5_inbox_hdr hdr; 557 __be32 qpn; 558 u8 rsvd1[4]; 559 __be32 optparam; 560 u8 rsvd0[4]; 561 struct mlx5_qp_context ctx; 562 u8 rsvd2[16]; 563 }; 564 565 struct mlx5_modify_qp_mbox_out { 566 struct mlx5_outbox_hdr hdr; 567 u8 rsvd0[8]; 568 }; 569 570 struct mlx5_query_qp_mbox_in { 571 struct mlx5_inbox_hdr hdr; 572 __be32 qpn; 573 u8 rsvd[4]; 574 }; 575 576 struct mlx5_query_qp_mbox_out { 577 struct mlx5_outbox_hdr hdr; 578 u8 rsvd1[8]; 579 __be32 optparam; 580 u8 rsvd0[4]; 581 struct mlx5_qp_context ctx; 582 u8 rsvd2[16]; 583 __be64 pas[0]; 584 }; 585 586 struct mlx5_conf_sqp_mbox_in { 587 struct mlx5_inbox_hdr hdr; 588 __be32 qpn; 589 u8 rsvd[3]; 590 u8 type; 591 }; 592 593 struct mlx5_conf_sqp_mbox_out { 594 struct mlx5_outbox_hdr hdr; 595 u8 rsvd[8]; 596 }; 597 598 struct mlx5_alloc_xrcd_mbox_in { 599 struct mlx5_inbox_hdr hdr; 600 u8 rsvd[8]; 601 }; 602 603 struct mlx5_alloc_xrcd_mbox_out { 604 struct mlx5_outbox_hdr hdr; 605 __be32 xrcdn; 606 u8 rsvd[4]; 607 }; 608 609 struct mlx5_dealloc_xrcd_mbox_in { 610 struct mlx5_inbox_hdr hdr; 611 __be32 xrcdn; 612 u8 rsvd[4]; 613 }; 614 615 struct mlx5_dealloc_xrcd_mbox_out { 616 struct mlx5_outbox_hdr hdr; 617 u8 rsvd[8]; 618 }; 619 620 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn) 621 { 622 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn); 623 } 624 625 static inline struct mlx5_core_mkey *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key) 626 { 627 return radix_tree_lookup(&dev->priv.mkey_table.tree, key); 628 } 629 630 struct mlx5_page_fault_resume_mbox_in { 631 struct mlx5_inbox_hdr hdr; 632 __be32 flags_qpn; 633 u8 reserved[4]; 634 }; 635 636 struct mlx5_page_fault_resume_mbox_out { 637 struct mlx5_outbox_hdr hdr; 638 u8 rsvd[8]; 639 }; 640 641 int mlx5_core_create_qp(struct mlx5_core_dev *dev, 642 struct mlx5_core_qp *qp, 643 struct mlx5_create_qp_mbox_in *in, 644 int inlen); 645 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 operation, 646 struct mlx5_modify_qp_mbox_in *in, int sqd_event, 647 struct mlx5_core_qp *qp); 648 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev, 649 struct mlx5_core_qp *qp); 650 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp, 651 struct mlx5_query_qp_mbox_out *out, int outlen); 652 653 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn); 654 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn); 655 void mlx5_init_qp_table(struct mlx5_core_dev *dev); 656 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev); 657 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 658 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 659 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 660 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 qpn, 661 u8 context, int error); 662 #endif 663 int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 664 struct mlx5_core_qp *rq); 665 void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev, 666 struct mlx5_core_qp *rq); 667 int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 668 struct mlx5_core_qp *sq); 669 void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev, 670 struct mlx5_core_qp *sq); 671 int mlx5_core_alloc_q_counter(struct mlx5_core_dev *dev, u16 *counter_id); 672 int mlx5_core_dealloc_q_counter(struct mlx5_core_dev *dev, u16 counter_id); 673 int mlx5_core_query_q_counter(struct mlx5_core_dev *dev, u16 counter_id, 674 int reset, void *out, int out_size); 675 int mlx5_core_query_out_of_buffer(struct mlx5_core_dev *dev, u16 counter_id, 676 u32 *out_of_buffer); 677 678 static inline const char *mlx5_qp_type_str(int type) 679 { 680 switch (type) { 681 case MLX5_QP_ST_RC: return "RC"; 682 case MLX5_QP_ST_UC: return "C"; 683 case MLX5_QP_ST_UD: return "UD"; 684 case MLX5_QP_ST_XRC: return "XRC"; 685 case MLX5_QP_ST_MLX: return "MLX"; 686 case MLX5_QP_ST_QP0: return "QP0"; 687 case MLX5_QP_ST_QP1: return "QP1"; 688 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; 689 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; 690 case MLX5_QP_ST_SNIFFER: return "SNIFFER"; 691 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; 692 case MLX5_QP_ST_PTP_1588: return "PTP_1588"; 693 case MLX5_QP_ST_REG_UMR: return "REG_UMR"; 694 default: return "Invalid transport type"; 695 } 696 } 697 698 static inline const char *mlx5_qp_state_str(int state) 699 { 700 switch (state) { 701 case MLX5_QP_STATE_RST: 702 return "RST"; 703 case MLX5_QP_STATE_INIT: 704 return "INIT"; 705 case MLX5_QP_STATE_RTR: 706 return "RTR"; 707 case MLX5_QP_STATE_RTS: 708 return "RTS"; 709 case MLX5_QP_STATE_SQER: 710 return "SQER"; 711 case MLX5_QP_STATE_SQD: 712 return "SQD"; 713 case MLX5_QP_STATE_ERR: 714 return "ERR"; 715 case MLX5_QP_STATE_SQ_DRAINING: 716 return "SQ_DRAINING"; 717 case MLX5_QP_STATE_SUSPENDED: 718 return "SUSPENDED"; 719 default: return "Invalid QP state"; 720 } 721 } 722 723 #endif /* MLX5_QP_H */ 724