1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33e126ba97SEli Cohen #ifndef MLX5_QP_H 34e126ba97SEli Cohen #define MLX5_QP_H 35e126ba97SEli Cohen 36e126ba97SEli Cohen #include <linux/mlx5/device.h> 37e126ba97SEli Cohen #include <linux/mlx5/driver.h> 38e126ba97SEli Cohen 39e126ba97SEli Cohen #define MLX5_INVALID_LKEY 0x100 40e1e66cc2SSagi Grimberg #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5) 41e6631814SSagi Grimberg #define MLX5_DIF_SIZE 8 42e6631814SSagi Grimberg #define MLX5_STRIDE_BLOCK_OP 0x400 43fd22f78cSSagi Grimberg #define MLX5_CPY_GRD_MASK 0xc0 44fd22f78cSSagi Grimberg #define MLX5_CPY_APP_MASK 0x30 45fd22f78cSSagi Grimberg #define MLX5_CPY_REF_MASK 0x0f 46142537f4SSagi Grimberg #define MLX5_BSF_INC_REFTAG (1 << 6) 47142537f4SSagi Grimberg #define MLX5_BSF_INL_VALID (1 << 15) 48142537f4SSagi Grimberg #define MLX5_BSF_REFRESH_DIF (1 << 14) 49142537f4SSagi Grimberg #define MLX5_BSF_REPEAT_BLOCK (1 << 7) 50142537f4SSagi Grimberg #define MLX5_BSF_APPTAG_ESCAPE 0x1 51142537f4SSagi Grimberg #define MLX5_BSF_APPREF_ESCAPE 0x2 52e126ba97SEli Cohen 53e420f0c0SHaggai Eran #define MLX5_QPN_BITS 24 54e420f0c0SHaggai Eran #define MLX5_QPN_MASK ((1 << MLX5_QPN_BITS) - 1) 55e420f0c0SHaggai Eran 56e126ba97SEli Cohen enum mlx5_qp_optpar { 57e126ba97SEli Cohen MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 58e126ba97SEli Cohen MLX5_QP_OPTPAR_RRE = 1 << 1, 59e126ba97SEli Cohen MLX5_QP_OPTPAR_RAE = 1 << 2, 60e126ba97SEli Cohen MLX5_QP_OPTPAR_RWE = 1 << 3, 61e126ba97SEli Cohen MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, 62e126ba97SEli Cohen MLX5_QP_OPTPAR_Q_KEY = 1 << 5, 63e126ba97SEli Cohen MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 64e126ba97SEli Cohen MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 65e126ba97SEli Cohen MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, 66e126ba97SEli Cohen MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, 67e126ba97SEli Cohen MLX5_QP_OPTPAR_PM_STATE = 1 << 10, 68e126ba97SEli Cohen MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, 69e126ba97SEli Cohen MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, 70e126ba97SEli Cohen MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 71e126ba97SEli Cohen MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, 72e126ba97SEli Cohen MLX5_QP_OPTPAR_SRQN = 1 << 18, 73e126ba97SEli Cohen MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, 74e126ba97SEli Cohen MLX5_QP_OPTPAR_DC_HS = 1 << 20, 75e126ba97SEli Cohen MLX5_QP_OPTPAR_DC_KEY = 1 << 21, 76e126ba97SEli Cohen }; 77e126ba97SEli Cohen 78e126ba97SEli Cohen enum mlx5_qp_state { 79e126ba97SEli Cohen MLX5_QP_STATE_RST = 0, 80e126ba97SEli Cohen MLX5_QP_STATE_INIT = 1, 81e126ba97SEli Cohen MLX5_QP_STATE_RTR = 2, 82e126ba97SEli Cohen MLX5_QP_STATE_RTS = 3, 83e126ba97SEli Cohen MLX5_QP_STATE_SQER = 4, 84e126ba97SEli Cohen MLX5_QP_STATE_SQD = 5, 85e126ba97SEli Cohen MLX5_QP_STATE_ERR = 6, 86e126ba97SEli Cohen MLX5_QP_STATE_SQ_DRAINING = 7, 87e126ba97SEli Cohen MLX5_QP_STATE_SUSPENDED = 9, 88*6d2f89dfSmajd@mellanox.com MLX5_QP_NUM_STATE, 89*6d2f89dfSmajd@mellanox.com MLX5_QP_STATE, 90*6d2f89dfSmajd@mellanox.com MLX5_QP_STATE_BAD, 91*6d2f89dfSmajd@mellanox.com }; 92*6d2f89dfSmajd@mellanox.com 93*6d2f89dfSmajd@mellanox.com enum { 94*6d2f89dfSmajd@mellanox.com MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1, 95*6d2f89dfSmajd@mellanox.com MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1, 96*6d2f89dfSmajd@mellanox.com MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1, 97*6d2f89dfSmajd@mellanox.com MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1, 98e126ba97SEli Cohen }; 99e126ba97SEli Cohen 100e126ba97SEli Cohen enum { 101e126ba97SEli Cohen MLX5_QP_ST_RC = 0x0, 102e126ba97SEli Cohen MLX5_QP_ST_UC = 0x1, 103e126ba97SEli Cohen MLX5_QP_ST_UD = 0x2, 104e126ba97SEli Cohen MLX5_QP_ST_XRC = 0x3, 105e126ba97SEli Cohen MLX5_QP_ST_MLX = 0x4, 106e126ba97SEli Cohen MLX5_QP_ST_DCI = 0x5, 107e126ba97SEli Cohen MLX5_QP_ST_DCT = 0x6, 108e126ba97SEli Cohen MLX5_QP_ST_QP0 = 0x7, 109e126ba97SEli Cohen MLX5_QP_ST_QP1 = 0x8, 110e126ba97SEli Cohen MLX5_QP_ST_RAW_ETHERTYPE = 0x9, 111e126ba97SEli Cohen MLX5_QP_ST_RAW_IPV6 = 0xa, 112e126ba97SEli Cohen MLX5_QP_ST_SNIFFER = 0xb, 113e126ba97SEli Cohen MLX5_QP_ST_SYNC_UMR = 0xe, 114e126ba97SEli Cohen MLX5_QP_ST_PTP_1588 = 0xd, 115e126ba97SEli Cohen MLX5_QP_ST_REG_UMR = 0xc, 116e126ba97SEli Cohen MLX5_QP_ST_MAX 117e126ba97SEli Cohen }; 118e126ba97SEli Cohen 119e126ba97SEli Cohen enum { 120e126ba97SEli Cohen MLX5_QP_PM_MIGRATED = 0x3, 121e126ba97SEli Cohen MLX5_QP_PM_ARMED = 0x0, 122e126ba97SEli Cohen MLX5_QP_PM_REARM = 0x1 123e126ba97SEli Cohen }; 124e126ba97SEli Cohen 125e126ba97SEli Cohen enum { 126e126ba97SEli Cohen MLX5_NON_ZERO_RQ = 0 << 24, 127e126ba97SEli Cohen MLX5_SRQ_RQ = 1 << 24, 128e126ba97SEli Cohen MLX5_CRQ_RQ = 2 << 24, 129e126ba97SEli Cohen MLX5_ZERO_LEN_RQ = 3 << 24 130e126ba97SEli Cohen }; 131e126ba97SEli Cohen 132e126ba97SEli Cohen enum { 133e126ba97SEli Cohen /* params1 */ 134e126ba97SEli Cohen MLX5_QP_BIT_SRE = 1 << 15, 135e126ba97SEli Cohen MLX5_QP_BIT_SWE = 1 << 14, 136e126ba97SEli Cohen MLX5_QP_BIT_SAE = 1 << 13, 137e126ba97SEli Cohen /* params2 */ 138e126ba97SEli Cohen MLX5_QP_BIT_RRE = 1 << 15, 139e126ba97SEli Cohen MLX5_QP_BIT_RWE = 1 << 14, 140e126ba97SEli Cohen MLX5_QP_BIT_RAE = 1 << 13, 141e126ba97SEli Cohen MLX5_QP_BIT_RIC = 1 << 4, 142051f2630SLeon Romanovsky MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2, 143051f2630SLeon Romanovsky MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1, 144051f2630SLeon Romanovsky MLX5_QP_BIT_CC_MASTER = 1 << 0 145e126ba97SEli Cohen }; 146e126ba97SEli Cohen 147e126ba97SEli Cohen enum { 148e126ba97SEli Cohen MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 149e281682bSSaeed Mahameed MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2, 150e126ba97SEli Cohen MLX5_WQE_CTRL_SOLICITED = 1 << 1, 151e126ba97SEli Cohen }; 152e126ba97SEli Cohen 153e126ba97SEli Cohen enum { 154e281682bSSaeed Mahameed MLX5_SEND_WQE_DS = 16, 155e126ba97SEli Cohen MLX5_SEND_WQE_BB = 64, 156e126ba97SEli Cohen }; 157e126ba97SEli Cohen 158e281682bSSaeed Mahameed #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS) 159e281682bSSaeed Mahameed 160e281682bSSaeed Mahameed enum { 161e281682bSSaeed Mahameed MLX5_SEND_WQE_MAX_WQEBBS = 16, 162e281682bSSaeed Mahameed }; 163e281682bSSaeed Mahameed 164e126ba97SEli Cohen enum { 165e126ba97SEli Cohen MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 166e126ba97SEli Cohen MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 167e126ba97SEli Cohen MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 168e126ba97SEli Cohen MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 169e126ba97SEli Cohen MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 170e126ba97SEli Cohen }; 171e126ba97SEli Cohen 172e126ba97SEli Cohen enum { 173e126ba97SEli Cohen MLX5_FENCE_MODE_NONE = 0 << 5, 174e126ba97SEli Cohen MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, 175e126ba97SEli Cohen MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, 176e126ba97SEli Cohen MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, 177e126ba97SEli Cohen }; 178e126ba97SEli Cohen 179e126ba97SEli Cohen enum { 180e126ba97SEli Cohen MLX5_QP_LAT_SENSITIVE = 1 << 28, 181f360d88aSEli Cohen MLX5_QP_BLOCK_MCAST = 1 << 30, 182e126ba97SEli Cohen MLX5_QP_ENABLE_SIG = 1 << 31, 183e126ba97SEli Cohen }; 184e126ba97SEli Cohen 185e126ba97SEli Cohen enum { 186e126ba97SEli Cohen MLX5_RCV_DBR = 0, 187e126ba97SEli Cohen MLX5_SND_DBR = 1, 188e126ba97SEli Cohen }; 189e126ba97SEli Cohen 190e6631814SSagi Grimberg enum { 191e6631814SSagi Grimberg MLX5_FLAGS_INLINE = 1<<7, 192e6631814SSagi Grimberg MLX5_FLAGS_CHECK_FREE = 1<<5, 193e6631814SSagi Grimberg }; 194e6631814SSagi Grimberg 195e126ba97SEli Cohen struct mlx5_wqe_fmr_seg { 196e126ba97SEli Cohen __be32 flags; 197e126ba97SEli Cohen __be32 mem_key; 198e126ba97SEli Cohen __be64 buf_list; 199e126ba97SEli Cohen __be64 start_addr; 200e126ba97SEli Cohen __be64 reg_len; 201e126ba97SEli Cohen __be32 offset; 202e126ba97SEli Cohen __be32 page_size; 203e126ba97SEli Cohen u32 reserved[2]; 204e126ba97SEli Cohen }; 205e126ba97SEli Cohen 206e126ba97SEli Cohen struct mlx5_wqe_ctrl_seg { 207e126ba97SEli Cohen __be32 opmod_idx_opcode; 208e126ba97SEli Cohen __be32 qpn_ds; 209e126ba97SEli Cohen u8 signature; 210e126ba97SEli Cohen u8 rsvd[2]; 211e126ba97SEli Cohen u8 fm_ce_se; 212e126ba97SEli Cohen __be32 imm; 213e126ba97SEli Cohen }; 214e126ba97SEli Cohen 215c1395a2aSHaggai Eran #define MLX5_WQE_CTRL_DS_MASK 0x3f 2167bdf65d4SHaggai Eran #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00 2177bdf65d4SHaggai Eran #define MLX5_WQE_CTRL_QPN_SHIFT 8 218c1395a2aSHaggai Eran #define MLX5_WQE_DS_UNITS 16 2197bdf65d4SHaggai Eran #define MLX5_WQE_CTRL_OPCODE_MASK 0xff 2207bdf65d4SHaggai Eran #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00 2217bdf65d4SHaggai Eran #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8 222c1395a2aSHaggai Eran 223e281682bSSaeed Mahameed enum { 224e281682bSSaeed Mahameed MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4, 225e281682bSSaeed Mahameed MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5, 226e281682bSSaeed Mahameed MLX5_ETH_WQE_L3_CSUM = 1 << 6, 227e281682bSSaeed Mahameed MLX5_ETH_WQE_L4_CSUM = 1 << 7, 228e281682bSSaeed Mahameed }; 229e281682bSSaeed Mahameed 230e281682bSSaeed Mahameed struct mlx5_wqe_eth_seg { 231e281682bSSaeed Mahameed u8 rsvd0[4]; 232e281682bSSaeed Mahameed u8 cs_flags; 233e281682bSSaeed Mahameed u8 rsvd1; 234e281682bSSaeed Mahameed __be16 mss; 235e281682bSSaeed Mahameed __be32 rsvd2; 236e281682bSSaeed Mahameed __be16 inline_hdr_sz; 237e281682bSSaeed Mahameed u8 inline_hdr_start[2]; 238e281682bSSaeed Mahameed }; 239e281682bSSaeed Mahameed 240e126ba97SEli Cohen struct mlx5_wqe_xrc_seg { 241e126ba97SEli Cohen __be32 xrc_srqn; 242e126ba97SEli Cohen u8 rsvd[12]; 243e126ba97SEli Cohen }; 244e126ba97SEli Cohen 245e126ba97SEli Cohen struct mlx5_wqe_masked_atomic_seg { 246e126ba97SEli Cohen __be64 swap_add; 247e126ba97SEli Cohen __be64 compare; 248e126ba97SEli Cohen __be64 swap_add_mask; 249e126ba97SEli Cohen __be64 compare_mask; 250e126ba97SEli Cohen }; 251e126ba97SEli Cohen 252e126ba97SEli Cohen struct mlx5_av { 253e126ba97SEli Cohen union { 254e126ba97SEli Cohen struct { 255e126ba97SEli Cohen __be32 qkey; 256e126ba97SEli Cohen __be32 reserved; 257e126ba97SEli Cohen } qkey; 258e126ba97SEli Cohen __be64 dc_key; 259e126ba97SEli Cohen } key; 260e126ba97SEli Cohen __be32 dqp_dct; 261e126ba97SEli Cohen u8 stat_rate_sl; 262e126ba97SEli Cohen u8 fl_mlid; 2632811ba51SAchiad Shochat union { 264e126ba97SEli Cohen __be16 rlid; 2652811ba51SAchiad Shochat __be16 udp_sport; 2662811ba51SAchiad Shochat }; 2672811ba51SAchiad Shochat u8 reserved0[4]; 2682811ba51SAchiad Shochat u8 rmac[6]; 269e126ba97SEli Cohen u8 tclass; 270e126ba97SEli Cohen u8 hop_limit; 271e126ba97SEli Cohen __be32 grh_gid_fl; 272e126ba97SEli Cohen u8 rgid[16]; 273e126ba97SEli Cohen }; 274e126ba97SEli Cohen 275e126ba97SEli Cohen struct mlx5_wqe_datagram_seg { 276e126ba97SEli Cohen struct mlx5_av av; 277e126ba97SEli Cohen }; 278e126ba97SEli Cohen 279e126ba97SEli Cohen struct mlx5_wqe_raddr_seg { 280e126ba97SEli Cohen __be64 raddr; 281e126ba97SEli Cohen __be32 rkey; 282e126ba97SEli Cohen u32 reserved; 283e126ba97SEli Cohen }; 284e126ba97SEli Cohen 285e126ba97SEli Cohen struct mlx5_wqe_atomic_seg { 286e126ba97SEli Cohen __be64 swap_add; 287e126ba97SEli Cohen __be64 compare; 288e126ba97SEli Cohen }; 289e126ba97SEli Cohen 290e126ba97SEli Cohen struct mlx5_wqe_data_seg { 291e126ba97SEli Cohen __be32 byte_count; 292e126ba97SEli Cohen __be32 lkey; 293e126ba97SEli Cohen __be64 addr; 294e126ba97SEli Cohen }; 295e126ba97SEli Cohen 296e126ba97SEli Cohen struct mlx5_wqe_umr_ctrl_seg { 297e126ba97SEli Cohen u8 flags; 298e126ba97SEli Cohen u8 rsvd0[3]; 299e126ba97SEli Cohen __be16 klm_octowords; 300e126ba97SEli Cohen __be16 bsf_octowords; 301e126ba97SEli Cohen __be64 mkey_mask; 302e126ba97SEli Cohen u8 rsvd1[32]; 303e126ba97SEli Cohen }; 304e126ba97SEli Cohen 305e126ba97SEli Cohen struct mlx5_seg_set_psv { 306e126ba97SEli Cohen __be32 psv_num; 307e126ba97SEli Cohen __be16 syndrome; 308e126ba97SEli Cohen __be16 status; 309e126ba97SEli Cohen __be32 transient_sig; 310e126ba97SEli Cohen __be32 ref_tag; 311e126ba97SEli Cohen }; 312e126ba97SEli Cohen 313e126ba97SEli Cohen struct mlx5_seg_get_psv { 314e126ba97SEli Cohen u8 rsvd[19]; 315e126ba97SEli Cohen u8 num_psv; 316e126ba97SEli Cohen __be32 l_key; 317e126ba97SEli Cohen __be64 va; 318e126ba97SEli Cohen __be32 psv_index[4]; 319e126ba97SEli Cohen }; 320e126ba97SEli Cohen 321e126ba97SEli Cohen struct mlx5_seg_check_psv { 322e126ba97SEli Cohen u8 rsvd0[2]; 323e126ba97SEli Cohen __be16 err_coalescing_op; 324e126ba97SEli Cohen u8 rsvd1[2]; 325e126ba97SEli Cohen __be16 xport_err_op; 326e126ba97SEli Cohen u8 rsvd2[2]; 327e126ba97SEli Cohen __be16 xport_err_mask; 328e126ba97SEli Cohen u8 rsvd3[7]; 329e126ba97SEli Cohen u8 num_psv; 330e126ba97SEli Cohen __be32 l_key; 331e126ba97SEli Cohen __be64 va; 332e126ba97SEli Cohen __be32 psv_index[4]; 333e126ba97SEli Cohen }; 334e126ba97SEli Cohen 335e126ba97SEli Cohen struct mlx5_rwqe_sig { 336e126ba97SEli Cohen u8 rsvd0[4]; 337e126ba97SEli Cohen u8 signature; 338e126ba97SEli Cohen u8 rsvd1[11]; 339e126ba97SEli Cohen }; 340e126ba97SEli Cohen 341e126ba97SEli Cohen struct mlx5_wqe_signature_seg { 342e126ba97SEli Cohen u8 rsvd0[4]; 343e126ba97SEli Cohen u8 signature; 344e126ba97SEli Cohen u8 rsvd1[11]; 345e126ba97SEli Cohen }; 346e126ba97SEli Cohen 3477bdf65d4SHaggai Eran #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff 3487bdf65d4SHaggai Eran 349e126ba97SEli Cohen struct mlx5_wqe_inline_seg { 350e126ba97SEli Cohen __be32 byte_count; 351e126ba97SEli Cohen }; 352e126ba97SEli Cohen 353142537f4SSagi Grimberg enum mlx5_sig_type { 354142537f4SSagi Grimberg MLX5_DIF_CRC = 0x1, 355142537f4SSagi Grimberg MLX5_DIF_IPCS = 0x2, 356142537f4SSagi Grimberg }; 357142537f4SSagi Grimberg 358142537f4SSagi Grimberg struct mlx5_bsf_inl { 359142537f4SSagi Grimberg __be16 vld_refresh; 360142537f4SSagi Grimberg __be16 dif_apptag; 361142537f4SSagi Grimberg __be32 dif_reftag; 362142537f4SSagi Grimberg u8 sig_type; 363142537f4SSagi Grimberg u8 rp_inv_seed; 364142537f4SSagi Grimberg u8 rsvd[3]; 365142537f4SSagi Grimberg u8 dif_inc_ref_guard_check; 366142537f4SSagi Grimberg __be16 dif_app_bitmask_check; 367142537f4SSagi Grimberg }; 368142537f4SSagi Grimberg 369e6631814SSagi Grimberg struct mlx5_bsf { 370e6631814SSagi Grimberg struct mlx5_bsf_basic { 371e6631814SSagi Grimberg u8 bsf_size_sbs; 372e6631814SSagi Grimberg u8 check_byte_mask; 373e6631814SSagi Grimberg union { 374e6631814SSagi Grimberg u8 copy_byte_mask; 375e6631814SSagi Grimberg u8 bs_selector; 376e6631814SSagi Grimberg u8 rsvd_wflags; 377e6631814SSagi Grimberg } wire; 378e6631814SSagi Grimberg union { 379e6631814SSagi Grimberg u8 bs_selector; 380e6631814SSagi Grimberg u8 rsvd_mflags; 381e6631814SSagi Grimberg } mem; 382e6631814SSagi Grimberg __be32 raw_data_size; 383e6631814SSagi Grimberg __be32 w_bfs_psv; 384e6631814SSagi Grimberg __be32 m_bfs_psv; 385e6631814SSagi Grimberg } basic; 386e6631814SSagi Grimberg struct mlx5_bsf_ext { 387e6631814SSagi Grimberg __be32 t_init_gen_pro_size; 388e6631814SSagi Grimberg __be32 rsvd_epi_size; 389e6631814SSagi Grimberg __be32 w_tfs_psv; 390e6631814SSagi Grimberg __be32 m_tfs_psv; 391e6631814SSagi Grimberg } ext; 392142537f4SSagi Grimberg struct mlx5_bsf_inl w_inl; 393142537f4SSagi Grimberg struct mlx5_bsf_inl m_inl; 394e6631814SSagi Grimberg }; 395e6631814SSagi Grimberg 396e6631814SSagi Grimberg struct mlx5_klm { 397e6631814SSagi Grimberg __be32 bcount; 398e6631814SSagi Grimberg __be32 key; 399e6631814SSagi Grimberg __be64 va; 400e6631814SSagi Grimberg }; 401e6631814SSagi Grimberg 402e6631814SSagi Grimberg struct mlx5_stride_block_entry { 403e6631814SSagi Grimberg __be16 stride; 404e6631814SSagi Grimberg __be16 bcount; 405e6631814SSagi Grimberg __be32 key; 406e6631814SSagi Grimberg __be64 va; 407e6631814SSagi Grimberg }; 408e6631814SSagi Grimberg 409e6631814SSagi Grimberg struct mlx5_stride_block_ctrl_seg { 410e6631814SSagi Grimberg __be32 bcount_per_cycle; 411e6631814SSagi Grimberg __be32 op; 412e6631814SSagi Grimberg __be32 repeat_count; 413e6631814SSagi Grimberg u16 rsvd; 414e6631814SSagi Grimberg __be16 num_entries; 415e6631814SSagi Grimberg }; 416e6631814SSagi Grimberg 417e420f0c0SHaggai Eran enum mlx5_pagefault_flags { 418e420f0c0SHaggai Eran MLX5_PFAULT_REQUESTOR = 1 << 0, 419e420f0c0SHaggai Eran MLX5_PFAULT_WRITE = 1 << 1, 420e420f0c0SHaggai Eran MLX5_PFAULT_RDMA = 1 << 2, 421e420f0c0SHaggai Eran }; 422e420f0c0SHaggai Eran 423e420f0c0SHaggai Eran /* Contains the details of a pagefault. */ 424e420f0c0SHaggai Eran struct mlx5_pagefault { 425e420f0c0SHaggai Eran u32 bytes_committed; 426e420f0c0SHaggai Eran u8 event_subtype; 427e420f0c0SHaggai Eran enum mlx5_pagefault_flags flags; 428e420f0c0SHaggai Eran union { 429e420f0c0SHaggai Eran /* Initiator or send message responder pagefault details. */ 430e420f0c0SHaggai Eran struct { 431e420f0c0SHaggai Eran /* Received packet size, only valid for responders. */ 432e420f0c0SHaggai Eran u32 packet_size; 433e420f0c0SHaggai Eran /* 434e420f0c0SHaggai Eran * WQE index. Refers to either the send queue or 435e420f0c0SHaggai Eran * receive queue, according to event_subtype. 436e420f0c0SHaggai Eran */ 437e420f0c0SHaggai Eran u16 wqe_index; 438e420f0c0SHaggai Eran } wqe; 439e420f0c0SHaggai Eran /* RDMA responder pagefault details */ 440e420f0c0SHaggai Eran struct { 441e420f0c0SHaggai Eran u32 r_key; 442e420f0c0SHaggai Eran /* 443e420f0c0SHaggai Eran * Received packet size, minimal size page fault 444e420f0c0SHaggai Eran * resolution required for forward progress. 445e420f0c0SHaggai Eran */ 446e420f0c0SHaggai Eran u32 packet_size; 447e420f0c0SHaggai Eran u32 rdma_op_len; 448e420f0c0SHaggai Eran u64 rdma_va; 449e420f0c0SHaggai Eran } rdma; 450e420f0c0SHaggai Eran }; 451e420f0c0SHaggai Eran }; 452e420f0c0SHaggai Eran 453e126ba97SEli Cohen struct mlx5_core_qp { 4545903325aSEli Cohen struct mlx5_core_rsc_common common; /* must be first */ 455e126ba97SEli Cohen void (*event) (struct mlx5_core_qp *, int); 456e420f0c0SHaggai Eran void (*pfault_handler)(struct mlx5_core_qp *, struct mlx5_pagefault *); 457e126ba97SEli Cohen int qpn; 458e126ba97SEli Cohen struct mlx5_rsc_debug *dbg; 459e126ba97SEli Cohen int pid; 460e126ba97SEli Cohen }; 461e126ba97SEli Cohen 462e126ba97SEli Cohen struct mlx5_qp_path { 463e126ba97SEli Cohen u8 fl; 464e126ba97SEli Cohen u8 rsvd3; 465e126ba97SEli Cohen u8 free_ar; 466e126ba97SEli Cohen u8 pkey_index; 467e126ba97SEli Cohen u8 rsvd0; 468e126ba97SEli Cohen u8 grh_mlid; 469e126ba97SEli Cohen __be16 rlid; 470e126ba97SEli Cohen u8 ackto_lt; 471e126ba97SEli Cohen u8 mgid_index; 472e126ba97SEli Cohen u8 static_rate; 473e126ba97SEli Cohen u8 hop_limit; 474e126ba97SEli Cohen __be32 tclass_flowlabel; 4752811ba51SAchiad Shochat union { 476e126ba97SEli Cohen u8 rgid[16]; 4772811ba51SAchiad Shochat u8 rip[16]; 4782811ba51SAchiad Shochat }; 4792811ba51SAchiad Shochat u8 f_dscp_ecn_prio; 4802811ba51SAchiad Shochat u8 ecn_dscp; 4812811ba51SAchiad Shochat __be16 udp_sport; 4822811ba51SAchiad Shochat u8 dci_cfi_prio_sl; 483e126ba97SEli Cohen u8 port; 4842811ba51SAchiad Shochat u8 rmac[6]; 485e126ba97SEli Cohen }; 486e126ba97SEli Cohen 487e126ba97SEli Cohen struct mlx5_qp_context { 488e126ba97SEli Cohen __be32 flags; 489e126ba97SEli Cohen __be32 flags_pd; 490e126ba97SEli Cohen u8 mtu_msgmax; 491e126ba97SEli Cohen u8 rq_size_stride; 492e126ba97SEli Cohen __be16 sq_crq_size; 493e126ba97SEli Cohen __be32 qp_counter_set_usr_page; 494e126ba97SEli Cohen __be32 wire_qpn; 495e126ba97SEli Cohen __be32 log_pg_sz_remote_qpn; 496e126ba97SEli Cohen struct mlx5_qp_path pri_path; 497e126ba97SEli Cohen struct mlx5_qp_path alt_path; 498e126ba97SEli Cohen __be32 params1; 499e126ba97SEli Cohen u8 reserved2[4]; 500e126ba97SEli Cohen __be32 next_send_psn; 501e126ba97SEli Cohen __be32 cqn_send; 502e126ba97SEli Cohen u8 reserved3[8]; 503e126ba97SEli Cohen __be32 last_acked_psn; 504e126ba97SEli Cohen __be32 ssn; 505e126ba97SEli Cohen __be32 params2; 506e126ba97SEli Cohen __be32 rnr_nextrecvpsn; 507e126ba97SEli Cohen __be32 xrcd; 508e126ba97SEli Cohen __be32 cqn_recv; 509e126ba97SEli Cohen __be64 db_rec_addr; 510e126ba97SEli Cohen __be32 qkey; 511e126ba97SEli Cohen __be32 rq_type_srqn; 512e126ba97SEli Cohen __be32 rmsn; 513e126ba97SEli Cohen __be16 hw_sq_wqe_counter; 514e126ba97SEli Cohen __be16 sw_sq_wqe_counter; 515e126ba97SEli Cohen __be16 hw_rcyclic_byte_counter; 516e126ba97SEli Cohen __be16 hw_rq_counter; 517e126ba97SEli Cohen __be16 sw_rcyclic_byte_counter; 518e126ba97SEli Cohen __be16 sw_rq_counter; 519e126ba97SEli Cohen u8 rsvd0[5]; 520e126ba97SEli Cohen u8 cgs; 521e126ba97SEli Cohen u8 cs_req; 522e126ba97SEli Cohen u8 cs_res; 523e126ba97SEli Cohen __be64 dc_access_key; 524e126ba97SEli Cohen u8 rsvd1[24]; 525e126ba97SEli Cohen }; 526e126ba97SEli Cohen 527e126ba97SEli Cohen struct mlx5_create_qp_mbox_in { 528e126ba97SEli Cohen struct mlx5_inbox_hdr hdr; 529e126ba97SEli Cohen __be32 input_qpn; 530e126ba97SEli Cohen u8 rsvd0[4]; 531e126ba97SEli Cohen __be32 opt_param_mask; 532e126ba97SEli Cohen u8 rsvd1[4]; 533e126ba97SEli Cohen struct mlx5_qp_context ctx; 534e126ba97SEli Cohen u8 rsvd3[16]; 535e126ba97SEli Cohen __be64 pas[0]; 536e126ba97SEli Cohen }; 537e126ba97SEli Cohen 538e126ba97SEli Cohen struct mlx5_create_qp_mbox_out { 539e126ba97SEli Cohen struct mlx5_outbox_hdr hdr; 540e126ba97SEli Cohen __be32 qpn; 541e126ba97SEli Cohen u8 rsvd0[4]; 542e126ba97SEli Cohen }; 543e126ba97SEli Cohen 544e126ba97SEli Cohen struct mlx5_destroy_qp_mbox_in { 545e126ba97SEli Cohen struct mlx5_inbox_hdr hdr; 546e126ba97SEli Cohen __be32 qpn; 547e126ba97SEli Cohen u8 rsvd0[4]; 548e126ba97SEli Cohen }; 549e126ba97SEli Cohen 550e126ba97SEli Cohen struct mlx5_destroy_qp_mbox_out { 551e126ba97SEli Cohen struct mlx5_outbox_hdr hdr; 552e126ba97SEli Cohen u8 rsvd0[8]; 553e126ba97SEli Cohen }; 554e126ba97SEli Cohen 555e126ba97SEli Cohen struct mlx5_modify_qp_mbox_in { 556e126ba97SEli Cohen struct mlx5_inbox_hdr hdr; 557e126ba97SEli Cohen __be32 qpn; 558e126ba97SEli Cohen u8 rsvd1[4]; 559e126ba97SEli Cohen __be32 optparam; 560e126ba97SEli Cohen u8 rsvd0[4]; 561e126ba97SEli Cohen struct mlx5_qp_context ctx; 562e126ba97SEli Cohen }; 563e126ba97SEli Cohen 564e126ba97SEli Cohen struct mlx5_modify_qp_mbox_out { 565e126ba97SEli Cohen struct mlx5_outbox_hdr hdr; 566e126ba97SEli Cohen u8 rsvd0[8]; 567e126ba97SEli Cohen }; 568e126ba97SEli Cohen 569e126ba97SEli Cohen struct mlx5_query_qp_mbox_in { 570e126ba97SEli Cohen struct mlx5_inbox_hdr hdr; 571e126ba97SEli Cohen __be32 qpn; 572e126ba97SEli Cohen u8 rsvd[4]; 573e126ba97SEli Cohen }; 574e126ba97SEli Cohen 575e126ba97SEli Cohen struct mlx5_query_qp_mbox_out { 576e126ba97SEli Cohen struct mlx5_outbox_hdr hdr; 577e126ba97SEli Cohen u8 rsvd1[8]; 578e126ba97SEli Cohen __be32 optparam; 579e126ba97SEli Cohen u8 rsvd0[4]; 580e126ba97SEli Cohen struct mlx5_qp_context ctx; 581e126ba97SEli Cohen u8 rsvd2[16]; 582e126ba97SEli Cohen __be64 pas[0]; 583e126ba97SEli Cohen }; 584e126ba97SEli Cohen 585e126ba97SEli Cohen struct mlx5_conf_sqp_mbox_in { 586e126ba97SEli Cohen struct mlx5_inbox_hdr hdr; 587e126ba97SEli Cohen __be32 qpn; 588e126ba97SEli Cohen u8 rsvd[3]; 589e126ba97SEli Cohen u8 type; 590e126ba97SEli Cohen }; 591e126ba97SEli Cohen 592e126ba97SEli Cohen struct mlx5_conf_sqp_mbox_out { 593e126ba97SEli Cohen struct mlx5_outbox_hdr hdr; 594e126ba97SEli Cohen u8 rsvd[8]; 595e126ba97SEli Cohen }; 596e126ba97SEli Cohen 597e126ba97SEli Cohen struct mlx5_alloc_xrcd_mbox_in { 598e126ba97SEli Cohen struct mlx5_inbox_hdr hdr; 599e126ba97SEli Cohen u8 rsvd[8]; 600e126ba97SEli Cohen }; 601e126ba97SEli Cohen 602e126ba97SEli Cohen struct mlx5_alloc_xrcd_mbox_out { 603e126ba97SEli Cohen struct mlx5_outbox_hdr hdr; 604e126ba97SEli Cohen __be32 xrcdn; 605e126ba97SEli Cohen u8 rsvd[4]; 606e126ba97SEli Cohen }; 607e126ba97SEli Cohen 608e126ba97SEli Cohen struct mlx5_dealloc_xrcd_mbox_in { 609e126ba97SEli Cohen struct mlx5_inbox_hdr hdr; 610e126ba97SEli Cohen __be32 xrcdn; 611e126ba97SEli Cohen u8 rsvd[4]; 612e126ba97SEli Cohen }; 613e126ba97SEli Cohen 614e126ba97SEli Cohen struct mlx5_dealloc_xrcd_mbox_out { 615e126ba97SEli Cohen struct mlx5_outbox_hdr hdr; 616e126ba97SEli Cohen u8 rsvd[8]; 617e126ba97SEli Cohen }; 618e126ba97SEli Cohen 619e126ba97SEli Cohen static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn) 620e126ba97SEli Cohen { 621e126ba97SEli Cohen return radix_tree_lookup(&dev->priv.qp_table.tree, qpn); 622e126ba97SEli Cohen } 623e126ba97SEli Cohen 624d5436ba0SSagi Grimberg static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key) 625d5436ba0SSagi Grimberg { 626d5436ba0SSagi Grimberg return radix_tree_lookup(&dev->priv.mr_table.tree, key); 627d5436ba0SSagi Grimberg } 628d5436ba0SSagi Grimberg 629e420f0c0SHaggai Eran struct mlx5_page_fault_resume_mbox_in { 630e420f0c0SHaggai Eran struct mlx5_inbox_hdr hdr; 631e420f0c0SHaggai Eran __be32 flags_qpn; 632e420f0c0SHaggai Eran u8 reserved[4]; 633e420f0c0SHaggai Eran }; 634e420f0c0SHaggai Eran 635e420f0c0SHaggai Eran struct mlx5_page_fault_resume_mbox_out { 636e420f0c0SHaggai Eran struct mlx5_outbox_hdr hdr; 637e420f0c0SHaggai Eran u8 rsvd[8]; 638e420f0c0SHaggai Eran }; 639e420f0c0SHaggai Eran 640e126ba97SEli Cohen int mlx5_core_create_qp(struct mlx5_core_dev *dev, 641e126ba97SEli Cohen struct mlx5_core_qp *qp, 642e126ba97SEli Cohen struct mlx5_create_qp_mbox_in *in, 643e126ba97SEli Cohen int inlen); 644e126ba97SEli Cohen int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state, 645e126ba97SEli Cohen enum mlx5_qp_state new_state, 646e126ba97SEli Cohen struct mlx5_modify_qp_mbox_in *in, int sqd_event, 647e126ba97SEli Cohen struct mlx5_core_qp *qp); 648e126ba97SEli Cohen int mlx5_core_destroy_qp(struct mlx5_core_dev *dev, 649e126ba97SEli Cohen struct mlx5_core_qp *qp); 650e126ba97SEli Cohen int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp, 651e126ba97SEli Cohen struct mlx5_query_qp_mbox_out *out, int outlen); 652e126ba97SEli Cohen 653e126ba97SEli Cohen int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn); 654e126ba97SEli Cohen int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn); 655e126ba97SEli Cohen void mlx5_init_qp_table(struct mlx5_core_dev *dev); 656e126ba97SEli Cohen void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev); 657e126ba97SEli Cohen int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 658e126ba97SEli Cohen void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 659e420f0c0SHaggai Eran #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 660e420f0c0SHaggai Eran int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 qpn, 661e420f0c0SHaggai Eran u8 context, int error); 662e420f0c0SHaggai Eran #endif 663e2013b21Smajd@mellanox.com int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 664e2013b21Smajd@mellanox.com struct mlx5_core_qp *rq); 665e2013b21Smajd@mellanox.com void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev, 666e2013b21Smajd@mellanox.com struct mlx5_core_qp *rq); 667e2013b21Smajd@mellanox.com int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 668e2013b21Smajd@mellanox.com struct mlx5_core_qp *sq); 669e2013b21Smajd@mellanox.com void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev, 670e2013b21Smajd@mellanox.com struct mlx5_core_qp *sq); 671e126ba97SEli Cohen 672db81a5c3SEli Cohen static inline const char *mlx5_qp_type_str(int type) 673db81a5c3SEli Cohen { 674db81a5c3SEli Cohen switch (type) { 675db81a5c3SEli Cohen case MLX5_QP_ST_RC: return "RC"; 676db81a5c3SEli Cohen case MLX5_QP_ST_UC: return "C"; 677db81a5c3SEli Cohen case MLX5_QP_ST_UD: return "UD"; 678db81a5c3SEli Cohen case MLX5_QP_ST_XRC: return "XRC"; 679db81a5c3SEli Cohen case MLX5_QP_ST_MLX: return "MLX"; 680db81a5c3SEli Cohen case MLX5_QP_ST_QP0: return "QP0"; 681db81a5c3SEli Cohen case MLX5_QP_ST_QP1: return "QP1"; 682db81a5c3SEli Cohen case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; 683db81a5c3SEli Cohen case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; 684db81a5c3SEli Cohen case MLX5_QP_ST_SNIFFER: return "SNIFFER"; 685db81a5c3SEli Cohen case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; 686db81a5c3SEli Cohen case MLX5_QP_ST_PTP_1588: return "PTP_1588"; 687db81a5c3SEli Cohen case MLX5_QP_ST_REG_UMR: return "REG_UMR"; 688db81a5c3SEli Cohen default: return "Invalid transport type"; 689db81a5c3SEli Cohen } 690db81a5c3SEli Cohen } 691db81a5c3SEli Cohen 692db81a5c3SEli Cohen static inline const char *mlx5_qp_state_str(int state) 693db81a5c3SEli Cohen { 694db81a5c3SEli Cohen switch (state) { 695db81a5c3SEli Cohen case MLX5_QP_STATE_RST: 696db81a5c3SEli Cohen return "RST"; 697db81a5c3SEli Cohen case MLX5_QP_STATE_INIT: 698db81a5c3SEli Cohen return "INIT"; 699db81a5c3SEli Cohen case MLX5_QP_STATE_RTR: 700db81a5c3SEli Cohen return "RTR"; 701db81a5c3SEli Cohen case MLX5_QP_STATE_RTS: 702db81a5c3SEli Cohen return "RTS"; 703db81a5c3SEli Cohen case MLX5_QP_STATE_SQER: 704db81a5c3SEli Cohen return "SQER"; 705db81a5c3SEli Cohen case MLX5_QP_STATE_SQD: 706db81a5c3SEli Cohen return "SQD"; 707db81a5c3SEli Cohen case MLX5_QP_STATE_ERR: 708db81a5c3SEli Cohen return "ERR"; 709db81a5c3SEli Cohen case MLX5_QP_STATE_SQ_DRAINING: 710db81a5c3SEli Cohen return "SQ_DRAINING"; 711db81a5c3SEli Cohen case MLX5_QP_STATE_SUSPENDED: 712db81a5c3SEli Cohen return "SUSPENDED"; 713db81a5c3SEli Cohen default: return "Invalid QP state"; 714db81a5c3SEli Cohen } 715db81a5c3SEli Cohen } 716db81a5c3SEli Cohen 717e126ba97SEli Cohen #endif /* MLX5_QP_H */ 718