1e126ba97SEli Cohen /* 2302bdf68SSaeed Mahameed * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3e126ba97SEli Cohen * 4e126ba97SEli Cohen * This software is available to you under a choice of one of two 5e126ba97SEli Cohen * licenses. You may choose to be licensed under the terms of the GNU 6e126ba97SEli Cohen * General Public License (GPL) Version 2, available from the file 7e126ba97SEli Cohen * COPYING in the main directory of this source tree, or the 8e126ba97SEli Cohen * OpenIB.org BSD license below: 9e126ba97SEli Cohen * 10e126ba97SEli Cohen * Redistribution and use in source and binary forms, with or 11e126ba97SEli Cohen * without modification, are permitted provided that the following 12e126ba97SEli Cohen * conditions are met: 13e126ba97SEli Cohen * 14e126ba97SEli Cohen * - Redistributions of source code must retain the above 15e126ba97SEli Cohen * copyright notice, this list of conditions and the following 16e126ba97SEli Cohen * disclaimer. 17e126ba97SEli Cohen * 18e126ba97SEli Cohen * - Redistributions in binary form must reproduce the above 19e126ba97SEli Cohen * copyright notice, this list of conditions and the following 20e126ba97SEli Cohen * disclaimer in the documentation and/or other materials 21e126ba97SEli Cohen * provided with the distribution. 22e126ba97SEli Cohen * 23e126ba97SEli Cohen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e126ba97SEli Cohen * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e126ba97SEli Cohen * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e126ba97SEli Cohen * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e126ba97SEli Cohen * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e126ba97SEli Cohen * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e126ba97SEli Cohen * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e126ba97SEli Cohen * SOFTWARE. 31e126ba97SEli Cohen */ 32e126ba97SEli Cohen 33e126ba97SEli Cohen #ifndef MLX5_QP_H 34e126ba97SEli Cohen #define MLX5_QP_H 35e126ba97SEli Cohen 36e126ba97SEli Cohen #include <linux/mlx5/device.h> 37e126ba97SEli Cohen #include <linux/mlx5/driver.h> 38e126ba97SEli Cohen 39e126ba97SEli Cohen #define MLX5_INVALID_LKEY 0x100 40e1e66cc2SSagi Grimberg #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5) 41e6631814SSagi Grimberg #define MLX5_DIF_SIZE 8 42e6631814SSagi Grimberg #define MLX5_STRIDE_BLOCK_OP 0x400 43fd22f78cSSagi Grimberg #define MLX5_CPY_GRD_MASK 0xc0 44fd22f78cSSagi Grimberg #define MLX5_CPY_APP_MASK 0x30 45fd22f78cSSagi Grimberg #define MLX5_CPY_REF_MASK 0x0f 46142537f4SSagi Grimberg #define MLX5_BSF_INC_REFTAG (1 << 6) 47142537f4SSagi Grimberg #define MLX5_BSF_INL_VALID (1 << 15) 48142537f4SSagi Grimberg #define MLX5_BSF_REFRESH_DIF (1 << 14) 49142537f4SSagi Grimberg #define MLX5_BSF_REPEAT_BLOCK (1 << 7) 50142537f4SSagi Grimberg #define MLX5_BSF_APPTAG_ESCAPE 0x1 51142537f4SSagi Grimberg #define MLX5_BSF_APPREF_ESCAPE 0x2 52e126ba97SEli Cohen 53e420f0c0SHaggai Eran #define MLX5_QPN_BITS 24 54e420f0c0SHaggai Eran #define MLX5_QPN_MASK ((1 << MLX5_QPN_BITS) - 1) 55e420f0c0SHaggai Eran 56e126ba97SEli Cohen enum mlx5_qp_optpar { 57e126ba97SEli Cohen MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 58e126ba97SEli Cohen MLX5_QP_OPTPAR_RRE = 1 << 1, 59e126ba97SEli Cohen MLX5_QP_OPTPAR_RAE = 1 << 2, 60e126ba97SEli Cohen MLX5_QP_OPTPAR_RWE = 1 << 3, 61e126ba97SEli Cohen MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, 62e126ba97SEli Cohen MLX5_QP_OPTPAR_Q_KEY = 1 << 5, 63e126ba97SEli Cohen MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 64e126ba97SEli Cohen MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 65e126ba97SEli Cohen MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, 66e126ba97SEli Cohen MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, 67e126ba97SEli Cohen MLX5_QP_OPTPAR_PM_STATE = 1 << 10, 68e126ba97SEli Cohen MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, 69e126ba97SEli Cohen MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, 70e126ba97SEli Cohen MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 71e126ba97SEli Cohen MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, 72e126ba97SEli Cohen MLX5_QP_OPTPAR_SRQN = 1 << 18, 73e126ba97SEli Cohen MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, 74e126ba97SEli Cohen MLX5_QP_OPTPAR_DC_HS = 1 << 20, 75e126ba97SEli Cohen MLX5_QP_OPTPAR_DC_KEY = 1 << 21, 76e126ba97SEli Cohen }; 77e126ba97SEli Cohen 78e126ba97SEli Cohen enum mlx5_qp_state { 79e126ba97SEli Cohen MLX5_QP_STATE_RST = 0, 80e126ba97SEli Cohen MLX5_QP_STATE_INIT = 1, 81e126ba97SEli Cohen MLX5_QP_STATE_RTR = 2, 82e126ba97SEli Cohen MLX5_QP_STATE_RTS = 3, 83e126ba97SEli Cohen MLX5_QP_STATE_SQER = 4, 84e126ba97SEli Cohen MLX5_QP_STATE_SQD = 5, 85e126ba97SEli Cohen MLX5_QP_STATE_ERR = 6, 86e126ba97SEli Cohen MLX5_QP_STATE_SQ_DRAINING = 7, 87e126ba97SEli Cohen MLX5_QP_STATE_SUSPENDED = 9, 88e126ba97SEli Cohen MLX5_QP_NUM_STATE 89e126ba97SEli Cohen }; 90e126ba97SEli Cohen 91e126ba97SEli Cohen enum { 92e126ba97SEli Cohen MLX5_QP_ST_RC = 0x0, 93e126ba97SEli Cohen MLX5_QP_ST_UC = 0x1, 94e126ba97SEli Cohen MLX5_QP_ST_UD = 0x2, 95e126ba97SEli Cohen MLX5_QP_ST_XRC = 0x3, 96e126ba97SEli Cohen MLX5_QP_ST_MLX = 0x4, 97e126ba97SEli Cohen MLX5_QP_ST_DCI = 0x5, 98e126ba97SEli Cohen MLX5_QP_ST_DCT = 0x6, 99e126ba97SEli Cohen MLX5_QP_ST_QP0 = 0x7, 100e126ba97SEli Cohen MLX5_QP_ST_QP1 = 0x8, 101e126ba97SEli Cohen MLX5_QP_ST_RAW_ETHERTYPE = 0x9, 102e126ba97SEli Cohen MLX5_QP_ST_RAW_IPV6 = 0xa, 103e126ba97SEli Cohen MLX5_QP_ST_SNIFFER = 0xb, 104e126ba97SEli Cohen MLX5_QP_ST_SYNC_UMR = 0xe, 105e126ba97SEli Cohen MLX5_QP_ST_PTP_1588 = 0xd, 106e126ba97SEli Cohen MLX5_QP_ST_REG_UMR = 0xc, 107e126ba97SEli Cohen MLX5_QP_ST_MAX 108e126ba97SEli Cohen }; 109e126ba97SEli Cohen 110e126ba97SEli Cohen enum { 111e126ba97SEli Cohen MLX5_QP_PM_MIGRATED = 0x3, 112e126ba97SEli Cohen MLX5_QP_PM_ARMED = 0x0, 113e126ba97SEli Cohen MLX5_QP_PM_REARM = 0x1 114e126ba97SEli Cohen }; 115e126ba97SEli Cohen 116e126ba97SEli Cohen enum { 117e126ba97SEli Cohen MLX5_NON_ZERO_RQ = 0 << 24, 118e126ba97SEli Cohen MLX5_SRQ_RQ = 1 << 24, 119e126ba97SEli Cohen MLX5_CRQ_RQ = 2 << 24, 120e126ba97SEli Cohen MLX5_ZERO_LEN_RQ = 3 << 24 121e126ba97SEli Cohen }; 122e126ba97SEli Cohen 123e126ba97SEli Cohen enum { 124e126ba97SEli Cohen /* params1 */ 125e126ba97SEli Cohen MLX5_QP_BIT_SRE = 1 << 15, 126e126ba97SEli Cohen MLX5_QP_BIT_SWE = 1 << 14, 127e126ba97SEli Cohen MLX5_QP_BIT_SAE = 1 << 13, 128e126ba97SEli Cohen /* params2 */ 129e126ba97SEli Cohen MLX5_QP_BIT_RRE = 1 << 15, 130e126ba97SEli Cohen MLX5_QP_BIT_RWE = 1 << 14, 131e126ba97SEli Cohen MLX5_QP_BIT_RAE = 1 << 13, 132e126ba97SEli Cohen MLX5_QP_BIT_RIC = 1 << 4, 133e126ba97SEli Cohen }; 134e126ba97SEli Cohen 135e126ba97SEli Cohen enum { 136e126ba97SEli Cohen MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 137e281682bSSaeed Mahameed MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2, 138e126ba97SEli Cohen MLX5_WQE_CTRL_SOLICITED = 1 << 1, 139e126ba97SEli Cohen }; 140e126ba97SEli Cohen 141e126ba97SEli Cohen enum { 142e281682bSSaeed Mahameed MLX5_SEND_WQE_DS = 16, 143e126ba97SEli Cohen MLX5_SEND_WQE_BB = 64, 144e126ba97SEli Cohen }; 145e126ba97SEli Cohen 146e281682bSSaeed Mahameed #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS) 147e281682bSSaeed Mahameed 148e281682bSSaeed Mahameed enum { 149e281682bSSaeed Mahameed MLX5_SEND_WQE_MAX_WQEBBS = 16, 150e281682bSSaeed Mahameed }; 151e281682bSSaeed Mahameed 152e126ba97SEli Cohen enum { 153e126ba97SEli Cohen MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 154e126ba97SEli Cohen MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 155e126ba97SEli Cohen MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 156e126ba97SEli Cohen MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 157e126ba97SEli Cohen MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 158e126ba97SEli Cohen }; 159e126ba97SEli Cohen 160e126ba97SEli Cohen enum { 161e126ba97SEli Cohen MLX5_FENCE_MODE_NONE = 0 << 5, 162e126ba97SEli Cohen MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, 163e126ba97SEli Cohen MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, 164e126ba97SEli Cohen MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, 165e126ba97SEli Cohen }; 166e126ba97SEli Cohen 167e126ba97SEli Cohen enum { 168e126ba97SEli Cohen MLX5_QP_LAT_SENSITIVE = 1 << 28, 169f360d88aSEli Cohen MLX5_QP_BLOCK_MCAST = 1 << 30, 170e126ba97SEli Cohen MLX5_QP_ENABLE_SIG = 1 << 31, 171e126ba97SEli Cohen }; 172e126ba97SEli Cohen 173e126ba97SEli Cohen enum { 174e126ba97SEli Cohen MLX5_RCV_DBR = 0, 175e126ba97SEli Cohen MLX5_SND_DBR = 1, 176e126ba97SEli Cohen }; 177e126ba97SEli Cohen 178e6631814SSagi Grimberg enum { 179e6631814SSagi Grimberg MLX5_FLAGS_INLINE = 1<<7, 180e6631814SSagi Grimberg MLX5_FLAGS_CHECK_FREE = 1<<5, 181e6631814SSagi Grimberg }; 182e6631814SSagi Grimberg 183e126ba97SEli Cohen struct mlx5_wqe_fmr_seg { 184e126ba97SEli Cohen __be32 flags; 185e126ba97SEli Cohen __be32 mem_key; 186e126ba97SEli Cohen __be64 buf_list; 187e126ba97SEli Cohen __be64 start_addr; 188e126ba97SEli Cohen __be64 reg_len; 189e126ba97SEli Cohen __be32 offset; 190e126ba97SEli Cohen __be32 page_size; 191e126ba97SEli Cohen u32 reserved[2]; 192e126ba97SEli Cohen }; 193e126ba97SEli Cohen 194e126ba97SEli Cohen struct mlx5_wqe_ctrl_seg { 195e126ba97SEli Cohen __be32 opmod_idx_opcode; 196e126ba97SEli Cohen __be32 qpn_ds; 197e126ba97SEli Cohen u8 signature; 198e126ba97SEli Cohen u8 rsvd[2]; 199e126ba97SEli Cohen u8 fm_ce_se; 200e126ba97SEli Cohen __be32 imm; 201e126ba97SEli Cohen }; 202e126ba97SEli Cohen 203c1395a2aSHaggai Eran #define MLX5_WQE_CTRL_DS_MASK 0x3f 2047bdf65d4SHaggai Eran #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00 2057bdf65d4SHaggai Eran #define MLX5_WQE_CTRL_QPN_SHIFT 8 206c1395a2aSHaggai Eran #define MLX5_WQE_DS_UNITS 16 2077bdf65d4SHaggai Eran #define MLX5_WQE_CTRL_OPCODE_MASK 0xff 2087bdf65d4SHaggai Eran #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00 2097bdf65d4SHaggai Eran #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8 210c1395a2aSHaggai Eran 211e281682bSSaeed Mahameed enum { 212e281682bSSaeed Mahameed MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4, 213e281682bSSaeed Mahameed MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5, 214e281682bSSaeed Mahameed MLX5_ETH_WQE_L3_CSUM = 1 << 6, 215e281682bSSaeed Mahameed MLX5_ETH_WQE_L4_CSUM = 1 << 7, 216e281682bSSaeed Mahameed }; 217e281682bSSaeed Mahameed 218e281682bSSaeed Mahameed struct mlx5_wqe_eth_seg { 219e281682bSSaeed Mahameed u8 rsvd0[4]; 220e281682bSSaeed Mahameed u8 cs_flags; 221e281682bSSaeed Mahameed u8 rsvd1; 222e281682bSSaeed Mahameed __be16 mss; 223e281682bSSaeed Mahameed __be32 rsvd2; 224e281682bSSaeed Mahameed __be16 inline_hdr_sz; 225e281682bSSaeed Mahameed u8 inline_hdr_start[2]; 226e281682bSSaeed Mahameed }; 227e281682bSSaeed Mahameed 228e126ba97SEli Cohen struct mlx5_wqe_xrc_seg { 229e126ba97SEli Cohen __be32 xrc_srqn; 230e126ba97SEli Cohen u8 rsvd[12]; 231e126ba97SEli Cohen }; 232e126ba97SEli Cohen 233e126ba97SEli Cohen struct mlx5_wqe_masked_atomic_seg { 234e126ba97SEli Cohen __be64 swap_add; 235e126ba97SEli Cohen __be64 compare; 236e126ba97SEli Cohen __be64 swap_add_mask; 237e126ba97SEli Cohen __be64 compare_mask; 238e126ba97SEli Cohen }; 239e126ba97SEli Cohen 240e126ba97SEli Cohen struct mlx5_av { 241e126ba97SEli Cohen union { 242e126ba97SEli Cohen struct { 243e126ba97SEli Cohen __be32 qkey; 244e126ba97SEli Cohen __be32 reserved; 245e126ba97SEli Cohen } qkey; 246e126ba97SEli Cohen __be64 dc_key; 247e126ba97SEli Cohen } key; 248e126ba97SEli Cohen __be32 dqp_dct; 249e126ba97SEli Cohen u8 stat_rate_sl; 250e126ba97SEli Cohen u8 fl_mlid; 251*2811ba51SAchiad Shochat union { 252e126ba97SEli Cohen __be16 rlid; 253*2811ba51SAchiad Shochat __be16 udp_sport; 254*2811ba51SAchiad Shochat }; 255*2811ba51SAchiad Shochat u8 reserved0[4]; 256*2811ba51SAchiad Shochat u8 rmac[6]; 257e126ba97SEli Cohen u8 tclass; 258e126ba97SEli Cohen u8 hop_limit; 259e126ba97SEli Cohen __be32 grh_gid_fl; 260e126ba97SEli Cohen u8 rgid[16]; 261e126ba97SEli Cohen }; 262e126ba97SEli Cohen 263e126ba97SEli Cohen struct mlx5_wqe_datagram_seg { 264e126ba97SEli Cohen struct mlx5_av av; 265e126ba97SEli Cohen }; 266e126ba97SEli Cohen 267e126ba97SEli Cohen struct mlx5_wqe_raddr_seg { 268e126ba97SEli Cohen __be64 raddr; 269e126ba97SEli Cohen __be32 rkey; 270e126ba97SEli Cohen u32 reserved; 271e126ba97SEli Cohen }; 272e126ba97SEli Cohen 273e126ba97SEli Cohen struct mlx5_wqe_atomic_seg { 274e126ba97SEli Cohen __be64 swap_add; 275e126ba97SEli Cohen __be64 compare; 276e126ba97SEli Cohen }; 277e126ba97SEli Cohen 278e126ba97SEli Cohen struct mlx5_wqe_data_seg { 279e126ba97SEli Cohen __be32 byte_count; 280e126ba97SEli Cohen __be32 lkey; 281e126ba97SEli Cohen __be64 addr; 282e126ba97SEli Cohen }; 283e126ba97SEli Cohen 284e126ba97SEli Cohen struct mlx5_wqe_umr_ctrl_seg { 285e126ba97SEli Cohen u8 flags; 286e126ba97SEli Cohen u8 rsvd0[3]; 287e126ba97SEli Cohen __be16 klm_octowords; 288e126ba97SEli Cohen __be16 bsf_octowords; 289e126ba97SEli Cohen __be64 mkey_mask; 290e126ba97SEli Cohen u8 rsvd1[32]; 291e126ba97SEli Cohen }; 292e126ba97SEli Cohen 293e126ba97SEli Cohen struct mlx5_seg_set_psv { 294e126ba97SEli Cohen __be32 psv_num; 295e126ba97SEli Cohen __be16 syndrome; 296e126ba97SEli Cohen __be16 status; 297e126ba97SEli Cohen __be32 transient_sig; 298e126ba97SEli Cohen __be32 ref_tag; 299e126ba97SEli Cohen }; 300e126ba97SEli Cohen 301e126ba97SEli Cohen struct mlx5_seg_get_psv { 302e126ba97SEli Cohen u8 rsvd[19]; 303e126ba97SEli Cohen u8 num_psv; 304e126ba97SEli Cohen __be32 l_key; 305e126ba97SEli Cohen __be64 va; 306e126ba97SEli Cohen __be32 psv_index[4]; 307e126ba97SEli Cohen }; 308e126ba97SEli Cohen 309e126ba97SEli Cohen struct mlx5_seg_check_psv { 310e126ba97SEli Cohen u8 rsvd0[2]; 311e126ba97SEli Cohen __be16 err_coalescing_op; 312e126ba97SEli Cohen u8 rsvd1[2]; 313e126ba97SEli Cohen __be16 xport_err_op; 314e126ba97SEli Cohen u8 rsvd2[2]; 315e126ba97SEli Cohen __be16 xport_err_mask; 316e126ba97SEli Cohen u8 rsvd3[7]; 317e126ba97SEli Cohen u8 num_psv; 318e126ba97SEli Cohen __be32 l_key; 319e126ba97SEli Cohen __be64 va; 320e126ba97SEli Cohen __be32 psv_index[4]; 321e126ba97SEli Cohen }; 322e126ba97SEli Cohen 323e126ba97SEli Cohen struct mlx5_rwqe_sig { 324e126ba97SEli Cohen u8 rsvd0[4]; 325e126ba97SEli Cohen u8 signature; 326e126ba97SEli Cohen u8 rsvd1[11]; 327e126ba97SEli Cohen }; 328e126ba97SEli Cohen 329e126ba97SEli Cohen struct mlx5_wqe_signature_seg { 330e126ba97SEli Cohen u8 rsvd0[4]; 331e126ba97SEli Cohen u8 signature; 332e126ba97SEli Cohen u8 rsvd1[11]; 333e126ba97SEli Cohen }; 334e126ba97SEli Cohen 3357bdf65d4SHaggai Eran #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff 3367bdf65d4SHaggai Eran 337e126ba97SEli Cohen struct mlx5_wqe_inline_seg { 338e126ba97SEli Cohen __be32 byte_count; 339e126ba97SEli Cohen }; 340e126ba97SEli Cohen 341142537f4SSagi Grimberg enum mlx5_sig_type { 342142537f4SSagi Grimberg MLX5_DIF_CRC = 0x1, 343142537f4SSagi Grimberg MLX5_DIF_IPCS = 0x2, 344142537f4SSagi Grimberg }; 345142537f4SSagi Grimberg 346142537f4SSagi Grimberg struct mlx5_bsf_inl { 347142537f4SSagi Grimberg __be16 vld_refresh; 348142537f4SSagi Grimberg __be16 dif_apptag; 349142537f4SSagi Grimberg __be32 dif_reftag; 350142537f4SSagi Grimberg u8 sig_type; 351142537f4SSagi Grimberg u8 rp_inv_seed; 352142537f4SSagi Grimberg u8 rsvd[3]; 353142537f4SSagi Grimberg u8 dif_inc_ref_guard_check; 354142537f4SSagi Grimberg __be16 dif_app_bitmask_check; 355142537f4SSagi Grimberg }; 356142537f4SSagi Grimberg 357e6631814SSagi Grimberg struct mlx5_bsf { 358e6631814SSagi Grimberg struct mlx5_bsf_basic { 359e6631814SSagi Grimberg u8 bsf_size_sbs; 360e6631814SSagi Grimberg u8 check_byte_mask; 361e6631814SSagi Grimberg union { 362e6631814SSagi Grimberg u8 copy_byte_mask; 363e6631814SSagi Grimberg u8 bs_selector; 364e6631814SSagi Grimberg u8 rsvd_wflags; 365e6631814SSagi Grimberg } wire; 366e6631814SSagi Grimberg union { 367e6631814SSagi Grimberg u8 bs_selector; 368e6631814SSagi Grimberg u8 rsvd_mflags; 369e6631814SSagi Grimberg } mem; 370e6631814SSagi Grimberg __be32 raw_data_size; 371e6631814SSagi Grimberg __be32 w_bfs_psv; 372e6631814SSagi Grimberg __be32 m_bfs_psv; 373e6631814SSagi Grimberg } basic; 374e6631814SSagi Grimberg struct mlx5_bsf_ext { 375e6631814SSagi Grimberg __be32 t_init_gen_pro_size; 376e6631814SSagi Grimberg __be32 rsvd_epi_size; 377e6631814SSagi Grimberg __be32 w_tfs_psv; 378e6631814SSagi Grimberg __be32 m_tfs_psv; 379e6631814SSagi Grimberg } ext; 380142537f4SSagi Grimberg struct mlx5_bsf_inl w_inl; 381142537f4SSagi Grimberg struct mlx5_bsf_inl m_inl; 382e6631814SSagi Grimberg }; 383e6631814SSagi Grimberg 384e6631814SSagi Grimberg struct mlx5_klm { 385e6631814SSagi Grimberg __be32 bcount; 386e6631814SSagi Grimberg __be32 key; 387e6631814SSagi Grimberg __be64 va; 388e6631814SSagi Grimberg }; 389e6631814SSagi Grimberg 390e6631814SSagi Grimberg struct mlx5_stride_block_entry { 391e6631814SSagi Grimberg __be16 stride; 392e6631814SSagi Grimberg __be16 bcount; 393e6631814SSagi Grimberg __be32 key; 394e6631814SSagi Grimberg __be64 va; 395e6631814SSagi Grimberg }; 396e6631814SSagi Grimberg 397e6631814SSagi Grimberg struct mlx5_stride_block_ctrl_seg { 398e6631814SSagi Grimberg __be32 bcount_per_cycle; 399e6631814SSagi Grimberg __be32 op; 400e6631814SSagi Grimberg __be32 repeat_count; 401e6631814SSagi Grimberg u16 rsvd; 402e6631814SSagi Grimberg __be16 num_entries; 403e6631814SSagi Grimberg }; 404e6631814SSagi Grimberg 405e420f0c0SHaggai Eran enum mlx5_pagefault_flags { 406e420f0c0SHaggai Eran MLX5_PFAULT_REQUESTOR = 1 << 0, 407e420f0c0SHaggai Eran MLX5_PFAULT_WRITE = 1 << 1, 408e420f0c0SHaggai Eran MLX5_PFAULT_RDMA = 1 << 2, 409e420f0c0SHaggai Eran }; 410e420f0c0SHaggai Eran 411e420f0c0SHaggai Eran /* Contains the details of a pagefault. */ 412e420f0c0SHaggai Eran struct mlx5_pagefault { 413e420f0c0SHaggai Eran u32 bytes_committed; 414e420f0c0SHaggai Eran u8 event_subtype; 415e420f0c0SHaggai Eran enum mlx5_pagefault_flags flags; 416e420f0c0SHaggai Eran union { 417e420f0c0SHaggai Eran /* Initiator or send message responder pagefault details. */ 418e420f0c0SHaggai Eran struct { 419e420f0c0SHaggai Eran /* Received packet size, only valid for responders. */ 420e420f0c0SHaggai Eran u32 packet_size; 421e420f0c0SHaggai Eran /* 422e420f0c0SHaggai Eran * WQE index. Refers to either the send queue or 423e420f0c0SHaggai Eran * receive queue, according to event_subtype. 424e420f0c0SHaggai Eran */ 425e420f0c0SHaggai Eran u16 wqe_index; 426e420f0c0SHaggai Eran } wqe; 427e420f0c0SHaggai Eran /* RDMA responder pagefault details */ 428e420f0c0SHaggai Eran struct { 429e420f0c0SHaggai Eran u32 r_key; 430e420f0c0SHaggai Eran /* 431e420f0c0SHaggai Eran * Received packet size, minimal size page fault 432e420f0c0SHaggai Eran * resolution required for forward progress. 433e420f0c0SHaggai Eran */ 434e420f0c0SHaggai Eran u32 packet_size; 435e420f0c0SHaggai Eran u32 rdma_op_len; 436e420f0c0SHaggai Eran u64 rdma_va; 437e420f0c0SHaggai Eran } rdma; 438e420f0c0SHaggai Eran }; 439e420f0c0SHaggai Eran }; 440e420f0c0SHaggai Eran 441e126ba97SEli Cohen struct mlx5_core_qp { 4425903325aSEli Cohen struct mlx5_core_rsc_common common; /* must be first */ 443e126ba97SEli Cohen void (*event) (struct mlx5_core_qp *, int); 444e420f0c0SHaggai Eran void (*pfault_handler)(struct mlx5_core_qp *, struct mlx5_pagefault *); 445e126ba97SEli Cohen int qpn; 446e126ba97SEli Cohen struct mlx5_rsc_debug *dbg; 447e126ba97SEli Cohen int pid; 448e126ba97SEli Cohen }; 449e126ba97SEli Cohen 450e126ba97SEli Cohen struct mlx5_qp_path { 451e126ba97SEli Cohen u8 fl; 452e126ba97SEli Cohen u8 rsvd3; 453e126ba97SEli Cohen u8 free_ar; 454e126ba97SEli Cohen u8 pkey_index; 455e126ba97SEli Cohen u8 rsvd0; 456e126ba97SEli Cohen u8 grh_mlid; 457e126ba97SEli Cohen __be16 rlid; 458e126ba97SEli Cohen u8 ackto_lt; 459e126ba97SEli Cohen u8 mgid_index; 460e126ba97SEli Cohen u8 static_rate; 461e126ba97SEli Cohen u8 hop_limit; 462e126ba97SEli Cohen __be32 tclass_flowlabel; 463*2811ba51SAchiad Shochat union { 464e126ba97SEli Cohen u8 rgid[16]; 465*2811ba51SAchiad Shochat u8 rip[16]; 466*2811ba51SAchiad Shochat }; 467*2811ba51SAchiad Shochat u8 f_dscp_ecn_prio; 468*2811ba51SAchiad Shochat u8 ecn_dscp; 469*2811ba51SAchiad Shochat __be16 udp_sport; 470*2811ba51SAchiad Shochat u8 dci_cfi_prio_sl; 471e126ba97SEli Cohen u8 port; 472*2811ba51SAchiad Shochat u8 rmac[6]; 473e126ba97SEli Cohen }; 474e126ba97SEli Cohen 475e126ba97SEli Cohen struct mlx5_qp_context { 476e126ba97SEli Cohen __be32 flags; 477e126ba97SEli Cohen __be32 flags_pd; 478e126ba97SEli Cohen u8 mtu_msgmax; 479e126ba97SEli Cohen u8 rq_size_stride; 480e126ba97SEli Cohen __be16 sq_crq_size; 481e126ba97SEli Cohen __be32 qp_counter_set_usr_page; 482e126ba97SEli Cohen __be32 wire_qpn; 483e126ba97SEli Cohen __be32 log_pg_sz_remote_qpn; 484e126ba97SEli Cohen struct mlx5_qp_path pri_path; 485e126ba97SEli Cohen struct mlx5_qp_path alt_path; 486e126ba97SEli Cohen __be32 params1; 487e126ba97SEli Cohen u8 reserved2[4]; 488e126ba97SEli Cohen __be32 next_send_psn; 489e126ba97SEli Cohen __be32 cqn_send; 490e126ba97SEli Cohen u8 reserved3[8]; 491e126ba97SEli Cohen __be32 last_acked_psn; 492e126ba97SEli Cohen __be32 ssn; 493e126ba97SEli Cohen __be32 params2; 494e126ba97SEli Cohen __be32 rnr_nextrecvpsn; 495e126ba97SEli Cohen __be32 xrcd; 496e126ba97SEli Cohen __be32 cqn_recv; 497e126ba97SEli Cohen __be64 db_rec_addr; 498e126ba97SEli Cohen __be32 qkey; 499e126ba97SEli Cohen __be32 rq_type_srqn; 500e126ba97SEli Cohen __be32 rmsn; 501e126ba97SEli Cohen __be16 hw_sq_wqe_counter; 502e126ba97SEli Cohen __be16 sw_sq_wqe_counter; 503e126ba97SEli Cohen __be16 hw_rcyclic_byte_counter; 504e126ba97SEli Cohen __be16 hw_rq_counter; 505e126ba97SEli Cohen __be16 sw_rcyclic_byte_counter; 506e126ba97SEli Cohen __be16 sw_rq_counter; 507e126ba97SEli Cohen u8 rsvd0[5]; 508e126ba97SEli Cohen u8 cgs; 509e126ba97SEli Cohen u8 cs_req; 510e126ba97SEli Cohen u8 cs_res; 511e126ba97SEli Cohen __be64 dc_access_key; 512e126ba97SEli Cohen u8 rsvd1[24]; 513e126ba97SEli Cohen }; 514e126ba97SEli Cohen 515e126ba97SEli Cohen struct mlx5_create_qp_mbox_in { 516e126ba97SEli Cohen struct mlx5_inbox_hdr hdr; 517e126ba97SEli Cohen __be32 input_qpn; 518e126ba97SEli Cohen u8 rsvd0[4]; 519e126ba97SEli Cohen __be32 opt_param_mask; 520e126ba97SEli Cohen u8 rsvd1[4]; 521e126ba97SEli Cohen struct mlx5_qp_context ctx; 522e126ba97SEli Cohen u8 rsvd3[16]; 523e126ba97SEli Cohen __be64 pas[0]; 524e126ba97SEli Cohen }; 525e126ba97SEli Cohen 526e126ba97SEli Cohen struct mlx5_create_qp_mbox_out { 527e126ba97SEli Cohen struct mlx5_outbox_hdr hdr; 528e126ba97SEli Cohen __be32 qpn; 529e126ba97SEli Cohen u8 rsvd0[4]; 530e126ba97SEli Cohen }; 531e126ba97SEli Cohen 532e126ba97SEli Cohen struct mlx5_destroy_qp_mbox_in { 533e126ba97SEli Cohen struct mlx5_inbox_hdr hdr; 534e126ba97SEli Cohen __be32 qpn; 535e126ba97SEli Cohen u8 rsvd0[4]; 536e126ba97SEli Cohen }; 537e126ba97SEli Cohen 538e126ba97SEli Cohen struct mlx5_destroy_qp_mbox_out { 539e126ba97SEli Cohen struct mlx5_outbox_hdr hdr; 540e126ba97SEli Cohen u8 rsvd0[8]; 541e126ba97SEli Cohen }; 542e126ba97SEli Cohen 543e126ba97SEli Cohen struct mlx5_modify_qp_mbox_in { 544e126ba97SEli Cohen struct mlx5_inbox_hdr hdr; 545e126ba97SEli Cohen __be32 qpn; 546e126ba97SEli Cohen u8 rsvd1[4]; 547e126ba97SEli Cohen __be32 optparam; 548e126ba97SEli Cohen u8 rsvd0[4]; 549e126ba97SEli Cohen struct mlx5_qp_context ctx; 550e126ba97SEli Cohen }; 551e126ba97SEli Cohen 552e126ba97SEli Cohen struct mlx5_modify_qp_mbox_out { 553e126ba97SEli Cohen struct mlx5_outbox_hdr hdr; 554e126ba97SEli Cohen u8 rsvd0[8]; 555e126ba97SEli Cohen }; 556e126ba97SEli Cohen 557e126ba97SEli Cohen struct mlx5_query_qp_mbox_in { 558e126ba97SEli Cohen struct mlx5_inbox_hdr hdr; 559e126ba97SEli Cohen __be32 qpn; 560e126ba97SEli Cohen u8 rsvd[4]; 561e126ba97SEli Cohen }; 562e126ba97SEli Cohen 563e126ba97SEli Cohen struct mlx5_query_qp_mbox_out { 564e126ba97SEli Cohen struct mlx5_outbox_hdr hdr; 565e126ba97SEli Cohen u8 rsvd1[8]; 566e126ba97SEli Cohen __be32 optparam; 567e126ba97SEli Cohen u8 rsvd0[4]; 568e126ba97SEli Cohen struct mlx5_qp_context ctx; 569e126ba97SEli Cohen u8 rsvd2[16]; 570e126ba97SEli Cohen __be64 pas[0]; 571e126ba97SEli Cohen }; 572e126ba97SEli Cohen 573e126ba97SEli Cohen struct mlx5_conf_sqp_mbox_in { 574e126ba97SEli Cohen struct mlx5_inbox_hdr hdr; 575e126ba97SEli Cohen __be32 qpn; 576e126ba97SEli Cohen u8 rsvd[3]; 577e126ba97SEli Cohen u8 type; 578e126ba97SEli Cohen }; 579e126ba97SEli Cohen 580e126ba97SEli Cohen struct mlx5_conf_sqp_mbox_out { 581e126ba97SEli Cohen struct mlx5_outbox_hdr hdr; 582e126ba97SEli Cohen u8 rsvd[8]; 583e126ba97SEli Cohen }; 584e126ba97SEli Cohen 585e126ba97SEli Cohen struct mlx5_alloc_xrcd_mbox_in { 586e126ba97SEli Cohen struct mlx5_inbox_hdr hdr; 587e126ba97SEli Cohen u8 rsvd[8]; 588e126ba97SEli Cohen }; 589e126ba97SEli Cohen 590e126ba97SEli Cohen struct mlx5_alloc_xrcd_mbox_out { 591e126ba97SEli Cohen struct mlx5_outbox_hdr hdr; 592e126ba97SEli Cohen __be32 xrcdn; 593e126ba97SEli Cohen u8 rsvd[4]; 594e126ba97SEli Cohen }; 595e126ba97SEli Cohen 596e126ba97SEli Cohen struct mlx5_dealloc_xrcd_mbox_in { 597e126ba97SEli Cohen struct mlx5_inbox_hdr hdr; 598e126ba97SEli Cohen __be32 xrcdn; 599e126ba97SEli Cohen u8 rsvd[4]; 600e126ba97SEli Cohen }; 601e126ba97SEli Cohen 602e126ba97SEli Cohen struct mlx5_dealloc_xrcd_mbox_out { 603e126ba97SEli Cohen struct mlx5_outbox_hdr hdr; 604e126ba97SEli Cohen u8 rsvd[8]; 605e126ba97SEli Cohen }; 606e126ba97SEli Cohen 607e126ba97SEli Cohen static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn) 608e126ba97SEli Cohen { 609e126ba97SEli Cohen return radix_tree_lookup(&dev->priv.qp_table.tree, qpn); 610e126ba97SEli Cohen } 611e126ba97SEli Cohen 612d5436ba0SSagi Grimberg static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key) 613d5436ba0SSagi Grimberg { 614d5436ba0SSagi Grimberg return radix_tree_lookup(&dev->priv.mr_table.tree, key); 615d5436ba0SSagi Grimberg } 616d5436ba0SSagi Grimberg 617e420f0c0SHaggai Eran struct mlx5_page_fault_resume_mbox_in { 618e420f0c0SHaggai Eran struct mlx5_inbox_hdr hdr; 619e420f0c0SHaggai Eran __be32 flags_qpn; 620e420f0c0SHaggai Eran u8 reserved[4]; 621e420f0c0SHaggai Eran }; 622e420f0c0SHaggai Eran 623e420f0c0SHaggai Eran struct mlx5_page_fault_resume_mbox_out { 624e420f0c0SHaggai Eran struct mlx5_outbox_hdr hdr; 625e420f0c0SHaggai Eran u8 rsvd[8]; 626e420f0c0SHaggai Eran }; 627e420f0c0SHaggai Eran 628e126ba97SEli Cohen int mlx5_core_create_qp(struct mlx5_core_dev *dev, 629e126ba97SEli Cohen struct mlx5_core_qp *qp, 630e126ba97SEli Cohen struct mlx5_create_qp_mbox_in *in, 631e126ba97SEli Cohen int inlen); 632e126ba97SEli Cohen int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state, 633e126ba97SEli Cohen enum mlx5_qp_state new_state, 634e126ba97SEli Cohen struct mlx5_modify_qp_mbox_in *in, int sqd_event, 635e126ba97SEli Cohen struct mlx5_core_qp *qp); 636e126ba97SEli Cohen int mlx5_core_destroy_qp(struct mlx5_core_dev *dev, 637e126ba97SEli Cohen struct mlx5_core_qp *qp); 638e126ba97SEli Cohen int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp, 639e126ba97SEli Cohen struct mlx5_query_qp_mbox_out *out, int outlen); 640e126ba97SEli Cohen 641e126ba97SEli Cohen int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn); 642e126ba97SEli Cohen int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn); 643e126ba97SEli Cohen void mlx5_init_qp_table(struct mlx5_core_dev *dev); 644e126ba97SEli Cohen void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev); 645e126ba97SEli Cohen int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 646e126ba97SEli Cohen void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 647e420f0c0SHaggai Eran #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 648e420f0c0SHaggai Eran int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 qpn, 649e420f0c0SHaggai Eran u8 context, int error); 650e420f0c0SHaggai Eran #endif 651e126ba97SEli Cohen 652db81a5c3SEli Cohen static inline const char *mlx5_qp_type_str(int type) 653db81a5c3SEli Cohen { 654db81a5c3SEli Cohen switch (type) { 655db81a5c3SEli Cohen case MLX5_QP_ST_RC: return "RC"; 656db81a5c3SEli Cohen case MLX5_QP_ST_UC: return "C"; 657db81a5c3SEli Cohen case MLX5_QP_ST_UD: return "UD"; 658db81a5c3SEli Cohen case MLX5_QP_ST_XRC: return "XRC"; 659db81a5c3SEli Cohen case MLX5_QP_ST_MLX: return "MLX"; 660db81a5c3SEli Cohen case MLX5_QP_ST_QP0: return "QP0"; 661db81a5c3SEli Cohen case MLX5_QP_ST_QP1: return "QP1"; 662db81a5c3SEli Cohen case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; 663db81a5c3SEli Cohen case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; 664db81a5c3SEli Cohen case MLX5_QP_ST_SNIFFER: return "SNIFFER"; 665db81a5c3SEli Cohen case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; 666db81a5c3SEli Cohen case MLX5_QP_ST_PTP_1588: return "PTP_1588"; 667db81a5c3SEli Cohen case MLX5_QP_ST_REG_UMR: return "REG_UMR"; 668db81a5c3SEli Cohen default: return "Invalid transport type"; 669db81a5c3SEli Cohen } 670db81a5c3SEli Cohen } 671db81a5c3SEli Cohen 672db81a5c3SEli Cohen static inline const char *mlx5_qp_state_str(int state) 673db81a5c3SEli Cohen { 674db81a5c3SEli Cohen switch (state) { 675db81a5c3SEli Cohen case MLX5_QP_STATE_RST: 676db81a5c3SEli Cohen return "RST"; 677db81a5c3SEli Cohen case MLX5_QP_STATE_INIT: 678db81a5c3SEli Cohen return "INIT"; 679db81a5c3SEli Cohen case MLX5_QP_STATE_RTR: 680db81a5c3SEli Cohen return "RTR"; 681db81a5c3SEli Cohen case MLX5_QP_STATE_RTS: 682db81a5c3SEli Cohen return "RTS"; 683db81a5c3SEli Cohen case MLX5_QP_STATE_SQER: 684db81a5c3SEli Cohen return "SQER"; 685db81a5c3SEli Cohen case MLX5_QP_STATE_SQD: 686db81a5c3SEli Cohen return "SQD"; 687db81a5c3SEli Cohen case MLX5_QP_STATE_ERR: 688db81a5c3SEli Cohen return "ERR"; 689db81a5c3SEli Cohen case MLX5_QP_STATE_SQ_DRAINING: 690db81a5c3SEli Cohen return "SQ_DRAINING"; 691db81a5c3SEli Cohen case MLX5_QP_STATE_SUSPENDED: 692db81a5c3SEli Cohen return "SUSPENDED"; 693db81a5c3SEli Cohen default: return "Invalid QP state"; 694db81a5c3SEli Cohen } 695db81a5c3SEli Cohen } 696db81a5c3SEli Cohen 697e126ba97SEli Cohen #endif /* MLX5_QP_H */ 698