1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 enum { 36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb 60 }; 61 62 enum { 63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 67 }; 68 69 enum { 70 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 71 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 72 MLX5_CMD_OP_INIT_HCA = 0x102, 73 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 74 MLX5_CMD_OP_ENABLE_HCA = 0x104, 75 MLX5_CMD_OP_DISABLE_HCA = 0x105, 76 MLX5_CMD_OP_QUERY_PAGES = 0x107, 77 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 78 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 79 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 80 MLX5_CMD_OP_SET_ISSI = 0x10b, 81 MLX5_CMD_OP_CREATE_MKEY = 0x200, 82 MLX5_CMD_OP_QUERY_MKEY = 0x201, 83 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 84 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 85 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 86 MLX5_CMD_OP_CREATE_EQ = 0x301, 87 MLX5_CMD_OP_DESTROY_EQ = 0x302, 88 MLX5_CMD_OP_QUERY_EQ = 0x303, 89 MLX5_CMD_OP_GEN_EQE = 0x304, 90 MLX5_CMD_OP_CREATE_CQ = 0x400, 91 MLX5_CMD_OP_DESTROY_CQ = 0x401, 92 MLX5_CMD_OP_QUERY_CQ = 0x402, 93 MLX5_CMD_OP_MODIFY_CQ = 0x403, 94 MLX5_CMD_OP_CREATE_QP = 0x500, 95 MLX5_CMD_OP_DESTROY_QP = 0x501, 96 MLX5_CMD_OP_RST2INIT_QP = 0x502, 97 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 98 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 99 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 100 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 101 MLX5_CMD_OP_2ERR_QP = 0x507, 102 MLX5_CMD_OP_2RST_QP = 0x50a, 103 MLX5_CMD_OP_QUERY_QP = 0x50b, 104 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 105 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 106 MLX5_CMD_OP_CREATE_PSV = 0x600, 107 MLX5_CMD_OP_DESTROY_PSV = 0x601, 108 MLX5_CMD_OP_CREATE_SRQ = 0x700, 109 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 110 MLX5_CMD_OP_QUERY_SRQ = 0x702, 111 MLX5_CMD_OP_ARM_RQ = 0x703, 112 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 113 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 114 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 115 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 116 MLX5_CMD_OP_CREATE_DCT = 0x710, 117 MLX5_CMD_OP_DESTROY_DCT = 0x711, 118 MLX5_CMD_OP_DRAIN_DCT = 0x712, 119 MLX5_CMD_OP_QUERY_DCT = 0x713, 120 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 121 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 122 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 123 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 124 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 125 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 126 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 127 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 128 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 129 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 130 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 131 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 132 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 133 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 134 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 135 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 136 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 137 MLX5_CMD_OP_ALLOC_PD = 0x800, 138 MLX5_CMD_OP_DEALLOC_PD = 0x801, 139 MLX5_CMD_OP_ALLOC_UAR = 0x802, 140 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 141 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 142 MLX5_CMD_OP_ACCESS_REG = 0x805, 143 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 144 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807, 145 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 146 MLX5_CMD_OP_MAD_IFC = 0x50d, 147 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 148 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 149 MLX5_CMD_OP_NOP = 0x80d, 150 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 151 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 152 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 153 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 154 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 155 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 156 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 157 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 158 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 159 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 160 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 161 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 162 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 163 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 164 MLX5_CMD_OP_CREATE_TIR = 0x900, 165 MLX5_CMD_OP_MODIFY_TIR = 0x901, 166 MLX5_CMD_OP_DESTROY_TIR = 0x902, 167 MLX5_CMD_OP_QUERY_TIR = 0x903, 168 MLX5_CMD_OP_CREATE_SQ = 0x904, 169 MLX5_CMD_OP_MODIFY_SQ = 0x905, 170 MLX5_CMD_OP_DESTROY_SQ = 0x906, 171 MLX5_CMD_OP_QUERY_SQ = 0x907, 172 MLX5_CMD_OP_CREATE_RQ = 0x908, 173 MLX5_CMD_OP_MODIFY_RQ = 0x909, 174 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 175 MLX5_CMD_OP_QUERY_RQ = 0x90b, 176 MLX5_CMD_OP_CREATE_RMP = 0x90c, 177 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 178 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 179 MLX5_CMD_OP_QUERY_RMP = 0x90f, 180 MLX5_CMD_OP_CREATE_TIS = 0x912, 181 MLX5_CMD_OP_MODIFY_TIS = 0x913, 182 MLX5_CMD_OP_DESTROY_TIS = 0x914, 183 MLX5_CMD_OP_QUERY_TIS = 0x915, 184 MLX5_CMD_OP_CREATE_RQT = 0x916, 185 MLX5_CMD_OP_MODIFY_RQT = 0x917, 186 MLX5_CMD_OP_DESTROY_RQT = 0x918, 187 MLX5_CMD_OP_QUERY_RQT = 0x919, 188 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 189 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 190 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 191 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 192 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 193 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 194 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 195 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 196 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938 197 }; 198 199 struct mlx5_ifc_flow_table_fields_supported_bits { 200 u8 outer_dmac[0x1]; 201 u8 outer_smac[0x1]; 202 u8 outer_ether_type[0x1]; 203 u8 reserved_0[0x1]; 204 u8 outer_first_prio[0x1]; 205 u8 outer_first_cfi[0x1]; 206 u8 outer_first_vid[0x1]; 207 u8 reserved_1[0x1]; 208 u8 outer_second_prio[0x1]; 209 u8 outer_second_cfi[0x1]; 210 u8 outer_second_vid[0x1]; 211 u8 reserved_2[0x1]; 212 u8 outer_sip[0x1]; 213 u8 outer_dip[0x1]; 214 u8 outer_frag[0x1]; 215 u8 outer_ip_protocol[0x1]; 216 u8 outer_ip_ecn[0x1]; 217 u8 outer_ip_dscp[0x1]; 218 u8 outer_udp_sport[0x1]; 219 u8 outer_udp_dport[0x1]; 220 u8 outer_tcp_sport[0x1]; 221 u8 outer_tcp_dport[0x1]; 222 u8 outer_tcp_flags[0x1]; 223 u8 outer_gre_protocol[0x1]; 224 u8 outer_gre_key[0x1]; 225 u8 outer_vxlan_vni[0x1]; 226 u8 reserved_3[0x5]; 227 u8 source_eswitch_port[0x1]; 228 229 u8 inner_dmac[0x1]; 230 u8 inner_smac[0x1]; 231 u8 inner_ether_type[0x1]; 232 u8 reserved_4[0x1]; 233 u8 inner_first_prio[0x1]; 234 u8 inner_first_cfi[0x1]; 235 u8 inner_first_vid[0x1]; 236 u8 reserved_5[0x1]; 237 u8 inner_second_prio[0x1]; 238 u8 inner_second_cfi[0x1]; 239 u8 inner_second_vid[0x1]; 240 u8 reserved_6[0x1]; 241 u8 inner_sip[0x1]; 242 u8 inner_dip[0x1]; 243 u8 inner_frag[0x1]; 244 u8 inner_ip_protocol[0x1]; 245 u8 inner_ip_ecn[0x1]; 246 u8 inner_ip_dscp[0x1]; 247 u8 inner_udp_sport[0x1]; 248 u8 inner_udp_dport[0x1]; 249 u8 inner_tcp_sport[0x1]; 250 u8 inner_tcp_dport[0x1]; 251 u8 inner_tcp_flags[0x1]; 252 u8 reserved_7[0x9]; 253 254 u8 reserved_8[0x40]; 255 }; 256 257 struct mlx5_ifc_flow_table_prop_layout_bits { 258 u8 ft_support[0x1]; 259 u8 reserved_0[0x1f]; 260 261 u8 reserved_1[0x2]; 262 u8 log_max_ft_size[0x6]; 263 u8 reserved_2[0x10]; 264 u8 max_ft_level[0x8]; 265 266 u8 reserved_3[0x20]; 267 268 u8 reserved_4[0x18]; 269 u8 log_max_ft_num[0x8]; 270 271 u8 reserved_5[0x18]; 272 u8 log_max_destination[0x8]; 273 274 u8 reserved_6[0x18]; 275 u8 log_max_flow[0x8]; 276 277 u8 reserved_7[0x40]; 278 279 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 280 281 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 282 }; 283 284 struct mlx5_ifc_odp_per_transport_service_cap_bits { 285 u8 send[0x1]; 286 u8 receive[0x1]; 287 u8 write[0x1]; 288 u8 read[0x1]; 289 u8 reserved_0[0x1]; 290 u8 srq_receive[0x1]; 291 u8 reserved_1[0x1a]; 292 }; 293 294 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 295 u8 smac_47_16[0x20]; 296 297 u8 smac_15_0[0x10]; 298 u8 ethertype[0x10]; 299 300 u8 dmac_47_16[0x20]; 301 302 u8 dmac_15_0[0x10]; 303 u8 first_prio[0x3]; 304 u8 first_cfi[0x1]; 305 u8 first_vid[0xc]; 306 307 u8 ip_protocol[0x8]; 308 u8 ip_dscp[0x6]; 309 u8 ip_ecn[0x2]; 310 u8 vlan_tag[0x1]; 311 u8 reserved_0[0x1]; 312 u8 frag[0x1]; 313 u8 reserved_1[0x4]; 314 u8 tcp_flags[0x9]; 315 316 u8 tcp_sport[0x10]; 317 u8 tcp_dport[0x10]; 318 319 u8 reserved_2[0x20]; 320 321 u8 udp_sport[0x10]; 322 u8 udp_dport[0x10]; 323 324 u8 src_ip[4][0x20]; 325 326 u8 dst_ip[4][0x20]; 327 }; 328 329 struct mlx5_ifc_fte_match_set_misc_bits { 330 u8 reserved_0[0x20]; 331 332 u8 reserved_1[0x10]; 333 u8 source_port[0x10]; 334 335 u8 outer_second_prio[0x3]; 336 u8 outer_second_cfi[0x1]; 337 u8 outer_second_vid[0xc]; 338 u8 inner_second_prio[0x3]; 339 u8 inner_second_cfi[0x1]; 340 u8 inner_second_vid[0xc]; 341 342 u8 outer_second_vlan_tag[0x1]; 343 u8 inner_second_vlan_tag[0x1]; 344 u8 reserved_2[0xe]; 345 u8 gre_protocol[0x10]; 346 347 u8 gre_key_h[0x18]; 348 u8 gre_key_l[0x8]; 349 350 u8 vxlan_vni[0x18]; 351 u8 reserved_3[0x8]; 352 353 u8 reserved_4[0x20]; 354 355 u8 reserved_5[0xc]; 356 u8 outer_ipv6_flow_label[0x14]; 357 358 u8 reserved_6[0xc]; 359 u8 inner_ipv6_flow_label[0x14]; 360 361 u8 reserved_7[0xe0]; 362 }; 363 364 struct mlx5_ifc_cmd_pas_bits { 365 u8 pa_h[0x20]; 366 367 u8 pa_l[0x14]; 368 u8 reserved_0[0xc]; 369 }; 370 371 struct mlx5_ifc_uint64_bits { 372 u8 hi[0x20]; 373 374 u8 lo[0x20]; 375 }; 376 377 enum { 378 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 379 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 380 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 381 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 382 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 383 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 384 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 385 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 386 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 387 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 388 }; 389 390 struct mlx5_ifc_ads_bits { 391 u8 fl[0x1]; 392 u8 free_ar[0x1]; 393 u8 reserved_0[0xe]; 394 u8 pkey_index[0x10]; 395 396 u8 reserved_1[0x8]; 397 u8 grh[0x1]; 398 u8 mlid[0x7]; 399 u8 rlid[0x10]; 400 401 u8 ack_timeout[0x5]; 402 u8 reserved_2[0x3]; 403 u8 src_addr_index[0x8]; 404 u8 reserved_3[0x4]; 405 u8 stat_rate[0x4]; 406 u8 hop_limit[0x8]; 407 408 u8 reserved_4[0x4]; 409 u8 tclass[0x8]; 410 u8 flow_label[0x14]; 411 412 u8 rgid_rip[16][0x8]; 413 414 u8 reserved_5[0x4]; 415 u8 f_dscp[0x1]; 416 u8 f_ecn[0x1]; 417 u8 reserved_6[0x1]; 418 u8 f_eth_prio[0x1]; 419 u8 ecn[0x2]; 420 u8 dscp[0x6]; 421 u8 udp_sport[0x10]; 422 423 u8 dei_cfi[0x1]; 424 u8 eth_prio[0x3]; 425 u8 sl[0x4]; 426 u8 port[0x8]; 427 u8 rmac_47_32[0x10]; 428 429 u8 rmac_31_0[0x20]; 430 }; 431 432 struct mlx5_ifc_flow_table_nic_cap_bits { 433 u8 reserved_0[0x200]; 434 435 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 436 437 u8 reserved_1[0x200]; 438 439 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 440 441 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 442 443 u8 reserved_2[0x200]; 444 445 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 446 447 u8 reserved_3[0x7200]; 448 }; 449 450 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 451 u8 csum_cap[0x1]; 452 u8 vlan_cap[0x1]; 453 u8 lro_cap[0x1]; 454 u8 lro_psh_flag[0x1]; 455 u8 lro_time_stamp[0x1]; 456 u8 reserved_0[0x3]; 457 u8 self_lb_en_modifiable[0x1]; 458 u8 reserved_1[0x2]; 459 u8 max_lso_cap[0x5]; 460 u8 reserved_2[0x4]; 461 u8 rss_ind_tbl_cap[0x4]; 462 u8 reserved_3[0x3]; 463 u8 tunnel_lso_const_out_ip_id[0x1]; 464 u8 reserved_4[0x2]; 465 u8 tunnel_statless_gre[0x1]; 466 u8 tunnel_stateless_vxlan[0x1]; 467 468 u8 reserved_5[0x20]; 469 470 u8 reserved_6[0x10]; 471 u8 lro_min_mss_size[0x10]; 472 473 u8 reserved_7[0x120]; 474 475 u8 lro_timer_supported_periods[4][0x20]; 476 477 u8 reserved_8[0x600]; 478 }; 479 480 struct mlx5_ifc_roce_cap_bits { 481 u8 roce_apm[0x1]; 482 u8 reserved_0[0x1f]; 483 484 u8 reserved_1[0x60]; 485 486 u8 reserved_2[0xc]; 487 u8 l3_type[0x4]; 488 u8 reserved_3[0x8]; 489 u8 roce_version[0x8]; 490 491 u8 reserved_4[0x10]; 492 u8 r_roce_dest_udp_port[0x10]; 493 494 u8 r_roce_max_src_udp_port[0x10]; 495 u8 r_roce_min_src_udp_port[0x10]; 496 497 u8 reserved_5[0x10]; 498 u8 roce_address_table_size[0x10]; 499 500 u8 reserved_6[0x700]; 501 }; 502 503 enum { 504 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 505 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 506 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 507 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 508 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 509 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 510 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 511 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 512 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 513 }; 514 515 enum { 516 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 517 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 518 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 519 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 520 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 521 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 522 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 523 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 524 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 525 }; 526 527 struct mlx5_ifc_atomic_caps_bits { 528 u8 reserved_0[0x40]; 529 530 u8 atomic_req_endianness[0x1]; 531 u8 reserved_1[0x1f]; 532 533 u8 reserved_2[0x20]; 534 535 u8 reserved_3[0x10]; 536 u8 atomic_operations[0x10]; 537 538 u8 reserved_4[0x10]; 539 u8 atomic_size_qp[0x10]; 540 541 u8 reserved_5[0x10]; 542 u8 atomic_size_dc[0x10]; 543 544 u8 reserved_6[0x720]; 545 }; 546 547 struct mlx5_ifc_odp_cap_bits { 548 u8 reserved_0[0x40]; 549 550 u8 sig[0x1]; 551 u8 reserved_1[0x1f]; 552 553 u8 reserved_2[0x20]; 554 555 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 556 557 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 558 559 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 560 561 u8 reserved_3[0x720]; 562 }; 563 564 enum { 565 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 566 MLX5_WQ_TYPE_CYCLIC = 0x1, 567 MLX5_WQ_TYPE_STRQ = 0x2, 568 }; 569 570 enum { 571 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 572 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 573 }; 574 575 enum { 576 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 577 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 578 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 579 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 580 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 581 }; 582 583 enum { 584 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 585 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 586 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 587 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 588 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 589 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 590 }; 591 592 enum { 593 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 594 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 595 }; 596 597 enum { 598 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 599 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 600 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 601 }; 602 603 enum { 604 MLX5_CAP_PORT_TYPE_IB = 0x0, 605 MLX5_CAP_PORT_TYPE_ETH = 0x1, 606 }; 607 608 struct mlx5_ifc_cmd_hca_cap_bits { 609 u8 reserved_0[0x80]; 610 611 u8 log_max_srq_sz[0x8]; 612 u8 log_max_qp_sz[0x8]; 613 u8 reserved_1[0xb]; 614 u8 log_max_qp[0x5]; 615 616 u8 reserved_2[0xb]; 617 u8 log_max_srq[0x5]; 618 u8 reserved_3[0x10]; 619 620 u8 reserved_4[0x8]; 621 u8 log_max_cq_sz[0x8]; 622 u8 reserved_5[0xb]; 623 u8 log_max_cq[0x5]; 624 625 u8 log_max_eq_sz[0x8]; 626 u8 reserved_6[0x2]; 627 u8 log_max_mkey[0x6]; 628 u8 reserved_7[0xc]; 629 u8 log_max_eq[0x4]; 630 631 u8 max_indirection[0x8]; 632 u8 reserved_8[0x1]; 633 u8 log_max_mrw_sz[0x7]; 634 u8 reserved_9[0x2]; 635 u8 log_max_bsf_list_size[0x6]; 636 u8 reserved_10[0x2]; 637 u8 log_max_klm_list_size[0x6]; 638 639 u8 reserved_11[0xa]; 640 u8 log_max_ra_req_dc[0x6]; 641 u8 reserved_12[0xa]; 642 u8 log_max_ra_res_dc[0x6]; 643 644 u8 reserved_13[0xa]; 645 u8 log_max_ra_req_qp[0x6]; 646 u8 reserved_14[0xa]; 647 u8 log_max_ra_res_qp[0x6]; 648 649 u8 pad_cap[0x1]; 650 u8 cc_query_allowed[0x1]; 651 u8 cc_modify_allowed[0x1]; 652 u8 reserved_15[0xd]; 653 u8 gid_table_size[0x10]; 654 655 u8 out_of_seq_cnt[0x1]; 656 u8 vport_counters[0x1]; 657 u8 reserved_16[0x4]; 658 u8 max_qp_cnt[0xa]; 659 u8 pkey_table_size[0x10]; 660 661 u8 vport_group_manager[0x1]; 662 u8 vhca_group_manager[0x1]; 663 u8 ib_virt[0x1]; 664 u8 eth_virt[0x1]; 665 u8 reserved_17[0x1]; 666 u8 ets[0x1]; 667 u8 nic_flow_table[0x1]; 668 u8 reserved_18[0x4]; 669 u8 local_ca_ack_delay[0x5]; 670 u8 reserved_19[0x6]; 671 u8 port_type[0x2]; 672 u8 num_ports[0x8]; 673 674 u8 reserved_20[0x3]; 675 u8 log_max_msg[0x5]; 676 u8 reserved_21[0x18]; 677 678 u8 stat_rate_support[0x10]; 679 u8 reserved_22[0xc]; 680 u8 cqe_version[0x4]; 681 682 u8 compact_address_vector[0x1]; 683 u8 reserved_23[0xe]; 684 u8 drain_sigerr[0x1]; 685 u8 cmdif_checksum[0x2]; 686 u8 sigerr_cqe[0x1]; 687 u8 reserved_24[0x1]; 688 u8 wq_signature[0x1]; 689 u8 sctr_data_cqe[0x1]; 690 u8 reserved_25[0x1]; 691 u8 sho[0x1]; 692 u8 tph[0x1]; 693 u8 rf[0x1]; 694 u8 dct[0x1]; 695 u8 reserved_26[0x1]; 696 u8 eth_net_offloads[0x1]; 697 u8 roce[0x1]; 698 u8 atomic[0x1]; 699 u8 reserved_27[0x1]; 700 701 u8 cq_oi[0x1]; 702 u8 cq_resize[0x1]; 703 u8 cq_moderation[0x1]; 704 u8 reserved_28[0x3]; 705 u8 cq_eq_remap[0x1]; 706 u8 pg[0x1]; 707 u8 block_lb_mc[0x1]; 708 u8 reserved_29[0x1]; 709 u8 scqe_break_moderation[0x1]; 710 u8 reserved_30[0x1]; 711 u8 cd[0x1]; 712 u8 reserved_31[0x1]; 713 u8 apm[0x1]; 714 u8 reserved_32[0x7]; 715 u8 qkv[0x1]; 716 u8 pkv[0x1]; 717 u8 reserved_33[0x4]; 718 u8 xrc[0x1]; 719 u8 ud[0x1]; 720 u8 uc[0x1]; 721 u8 rc[0x1]; 722 723 u8 reserved_34[0xa]; 724 u8 uar_sz[0x6]; 725 u8 reserved_35[0x8]; 726 u8 log_pg_sz[0x8]; 727 728 u8 bf[0x1]; 729 u8 reserved_36[0x1]; 730 u8 pad_tx_eth_packet[0x1]; 731 u8 reserved_37[0x8]; 732 u8 log_bf_reg_size[0x5]; 733 u8 reserved_38[0x10]; 734 735 u8 reserved_39[0x10]; 736 u8 max_wqe_sz_sq[0x10]; 737 738 u8 reserved_40[0x10]; 739 u8 max_wqe_sz_rq[0x10]; 740 741 u8 reserved_41[0x10]; 742 u8 max_wqe_sz_sq_dc[0x10]; 743 744 u8 reserved_42[0x7]; 745 u8 max_qp_mcg[0x19]; 746 747 u8 reserved_43[0x18]; 748 u8 log_max_mcg[0x8]; 749 750 u8 reserved_44[0x3]; 751 u8 log_max_transport_domain[0x5]; 752 u8 reserved_45[0x3]; 753 u8 log_max_pd[0x5]; 754 u8 reserved_46[0xb]; 755 u8 log_max_xrcd[0x5]; 756 757 u8 reserved_47[0x20]; 758 759 u8 reserved_48[0x3]; 760 u8 log_max_rq[0x5]; 761 u8 reserved_49[0x3]; 762 u8 log_max_sq[0x5]; 763 u8 reserved_50[0x3]; 764 u8 log_max_tir[0x5]; 765 u8 reserved_51[0x3]; 766 u8 log_max_tis[0x5]; 767 768 u8 basic_cyclic_rcv_wqe[0x1]; 769 u8 reserved_52[0x2]; 770 u8 log_max_rmp[0x5]; 771 u8 reserved_53[0x3]; 772 u8 log_max_rqt[0x5]; 773 u8 reserved_54[0x3]; 774 u8 log_max_rqt_size[0x5]; 775 u8 reserved_55[0x3]; 776 u8 log_max_tis_per_sq[0x5]; 777 778 u8 reserved_56[0x3]; 779 u8 log_max_stride_sz_rq[0x5]; 780 u8 reserved_57[0x3]; 781 u8 log_min_stride_sz_rq[0x5]; 782 u8 reserved_58[0x3]; 783 u8 log_max_stride_sz_sq[0x5]; 784 u8 reserved_59[0x3]; 785 u8 log_min_stride_sz_sq[0x5]; 786 787 u8 reserved_60[0x1b]; 788 u8 log_max_wq_sz[0x5]; 789 790 u8 reserved_61[0xa0]; 791 792 u8 reserved_62[0x3]; 793 u8 log_max_l2_table[0x5]; 794 u8 reserved_63[0x8]; 795 u8 log_uar_page_sz[0x10]; 796 797 u8 reserved_64[0x100]; 798 799 u8 reserved_65[0x1f]; 800 u8 cqe_zip[0x1]; 801 802 u8 cqe_zip_timeout[0x10]; 803 u8 cqe_zip_max_num[0x10]; 804 805 u8 reserved_66[0x220]; 806 }; 807 808 enum { 809 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_FLOW_TABLE_ = 0x1, 810 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_TIR = 0x2, 811 }; 812 813 struct mlx5_ifc_dest_format_struct_bits { 814 u8 destination_type[0x8]; 815 u8 destination_id[0x18]; 816 817 u8 reserved_0[0x20]; 818 }; 819 820 struct mlx5_ifc_fte_match_param_bits { 821 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 822 823 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 824 825 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 826 827 u8 reserved_0[0xa00]; 828 }; 829 830 enum { 831 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 832 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 833 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 834 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 835 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 836 }; 837 838 struct mlx5_ifc_rx_hash_field_select_bits { 839 u8 l3_prot_type[0x1]; 840 u8 l4_prot_type[0x1]; 841 u8 selected_fields[0x1e]; 842 }; 843 844 enum { 845 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 846 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 847 }; 848 849 enum { 850 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 851 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 852 }; 853 854 struct mlx5_ifc_wq_bits { 855 u8 wq_type[0x4]; 856 u8 wq_signature[0x1]; 857 u8 end_padding_mode[0x2]; 858 u8 cd_slave[0x1]; 859 u8 reserved_0[0x18]; 860 861 u8 hds_skip_first_sge[0x1]; 862 u8 log2_hds_buf_size[0x3]; 863 u8 reserved_1[0x7]; 864 u8 page_offset[0x5]; 865 u8 lwm[0x10]; 866 867 u8 reserved_2[0x8]; 868 u8 pd[0x18]; 869 870 u8 reserved_3[0x8]; 871 u8 uar_page[0x18]; 872 873 u8 dbr_addr[0x40]; 874 875 u8 hw_counter[0x20]; 876 877 u8 sw_counter[0x20]; 878 879 u8 reserved_4[0xc]; 880 u8 log_wq_stride[0x4]; 881 u8 reserved_5[0x3]; 882 u8 log_wq_pg_sz[0x5]; 883 u8 reserved_6[0x3]; 884 u8 log_wq_sz[0x5]; 885 886 u8 reserved_7[0x4e0]; 887 888 struct mlx5_ifc_cmd_pas_bits pas[0]; 889 }; 890 891 struct mlx5_ifc_rq_num_bits { 892 u8 reserved_0[0x8]; 893 u8 rq_num[0x18]; 894 }; 895 896 struct mlx5_ifc_mac_address_layout_bits { 897 u8 reserved_0[0x10]; 898 u8 mac_addr_47_32[0x10]; 899 900 u8 mac_addr_31_0[0x20]; 901 }; 902 903 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 904 u8 reserved_0[0xa0]; 905 906 u8 min_time_between_cnps[0x20]; 907 908 u8 reserved_1[0x12]; 909 u8 cnp_dscp[0x6]; 910 u8 reserved_2[0x5]; 911 u8 cnp_802p_prio[0x3]; 912 913 u8 reserved_3[0x720]; 914 }; 915 916 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 917 u8 reserved_0[0x60]; 918 919 u8 reserved_1[0x4]; 920 u8 clamp_tgt_rate[0x1]; 921 u8 reserved_2[0x3]; 922 u8 clamp_tgt_rate_after_time_inc[0x1]; 923 u8 reserved_3[0x17]; 924 925 u8 reserved_4[0x20]; 926 927 u8 rpg_time_reset[0x20]; 928 929 u8 rpg_byte_reset[0x20]; 930 931 u8 rpg_threshold[0x20]; 932 933 u8 rpg_max_rate[0x20]; 934 935 u8 rpg_ai_rate[0x20]; 936 937 u8 rpg_hai_rate[0x20]; 938 939 u8 rpg_gd[0x20]; 940 941 u8 rpg_min_dec_fac[0x20]; 942 943 u8 rpg_min_rate[0x20]; 944 945 u8 reserved_5[0xe0]; 946 947 u8 rate_to_set_on_first_cnp[0x20]; 948 949 u8 dce_tcp_g[0x20]; 950 951 u8 dce_tcp_rtt[0x20]; 952 953 u8 rate_reduce_monitor_period[0x20]; 954 955 u8 reserved_6[0x20]; 956 957 u8 initial_alpha_value[0x20]; 958 959 u8 reserved_7[0x4a0]; 960 }; 961 962 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 963 u8 reserved_0[0x80]; 964 965 u8 rppp_max_rps[0x20]; 966 967 u8 rpg_time_reset[0x20]; 968 969 u8 rpg_byte_reset[0x20]; 970 971 u8 rpg_threshold[0x20]; 972 973 u8 rpg_max_rate[0x20]; 974 975 u8 rpg_ai_rate[0x20]; 976 977 u8 rpg_hai_rate[0x20]; 978 979 u8 rpg_gd[0x20]; 980 981 u8 rpg_min_dec_fac[0x20]; 982 983 u8 rpg_min_rate[0x20]; 984 985 u8 reserved_1[0x640]; 986 }; 987 988 enum { 989 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 990 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 991 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 992 }; 993 994 struct mlx5_ifc_resize_field_select_bits { 995 u8 resize_field_select[0x20]; 996 }; 997 998 enum { 999 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1000 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1001 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1002 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1003 }; 1004 1005 struct mlx5_ifc_modify_field_select_bits { 1006 u8 modify_field_select[0x20]; 1007 }; 1008 1009 struct mlx5_ifc_field_select_r_roce_np_bits { 1010 u8 field_select_r_roce_np[0x20]; 1011 }; 1012 1013 struct mlx5_ifc_field_select_r_roce_rp_bits { 1014 u8 field_select_r_roce_rp[0x20]; 1015 }; 1016 1017 enum { 1018 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1019 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1020 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1021 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1022 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1023 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1024 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1025 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1026 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1027 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1028 }; 1029 1030 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1031 u8 field_select_8021qaurp[0x20]; 1032 }; 1033 1034 struct mlx5_ifc_phys_layer_cntrs_bits { 1035 u8 time_since_last_clear_high[0x20]; 1036 1037 u8 time_since_last_clear_low[0x20]; 1038 1039 u8 symbol_errors_high[0x20]; 1040 1041 u8 symbol_errors_low[0x20]; 1042 1043 u8 sync_headers_errors_high[0x20]; 1044 1045 u8 sync_headers_errors_low[0x20]; 1046 1047 u8 edpl_bip_errors_lane0_high[0x20]; 1048 1049 u8 edpl_bip_errors_lane0_low[0x20]; 1050 1051 u8 edpl_bip_errors_lane1_high[0x20]; 1052 1053 u8 edpl_bip_errors_lane1_low[0x20]; 1054 1055 u8 edpl_bip_errors_lane2_high[0x20]; 1056 1057 u8 edpl_bip_errors_lane2_low[0x20]; 1058 1059 u8 edpl_bip_errors_lane3_high[0x20]; 1060 1061 u8 edpl_bip_errors_lane3_low[0x20]; 1062 1063 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1064 1065 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1066 1067 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1068 1069 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1070 1071 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1072 1073 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1074 1075 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1076 1077 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1078 1079 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1080 1081 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1082 1083 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1084 1085 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1086 1087 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1088 1089 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1090 1091 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1092 1093 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1094 1095 u8 rs_fec_corrected_blocks_high[0x20]; 1096 1097 u8 rs_fec_corrected_blocks_low[0x20]; 1098 1099 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1100 1101 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1102 1103 u8 rs_fec_no_errors_blocks_high[0x20]; 1104 1105 u8 rs_fec_no_errors_blocks_low[0x20]; 1106 1107 u8 rs_fec_single_error_blocks_high[0x20]; 1108 1109 u8 rs_fec_single_error_blocks_low[0x20]; 1110 1111 u8 rs_fec_corrected_symbols_total_high[0x20]; 1112 1113 u8 rs_fec_corrected_symbols_total_low[0x20]; 1114 1115 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1116 1117 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1118 1119 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1120 1121 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1122 1123 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1124 1125 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1126 1127 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1128 1129 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1130 1131 u8 link_down_events[0x20]; 1132 1133 u8 successful_recovery_events[0x20]; 1134 1135 u8 reserved_0[0x180]; 1136 }; 1137 1138 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1139 u8 transmit_queue_high[0x20]; 1140 1141 u8 transmit_queue_low[0x20]; 1142 1143 u8 reserved_0[0x780]; 1144 }; 1145 1146 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1147 u8 rx_octets_high[0x20]; 1148 1149 u8 rx_octets_low[0x20]; 1150 1151 u8 reserved_0[0xc0]; 1152 1153 u8 rx_frames_high[0x20]; 1154 1155 u8 rx_frames_low[0x20]; 1156 1157 u8 tx_octets_high[0x20]; 1158 1159 u8 tx_octets_low[0x20]; 1160 1161 u8 reserved_1[0xc0]; 1162 1163 u8 tx_frames_high[0x20]; 1164 1165 u8 tx_frames_low[0x20]; 1166 1167 u8 rx_pause_high[0x20]; 1168 1169 u8 rx_pause_low[0x20]; 1170 1171 u8 rx_pause_duration_high[0x20]; 1172 1173 u8 rx_pause_duration_low[0x20]; 1174 1175 u8 tx_pause_high[0x20]; 1176 1177 u8 tx_pause_low[0x20]; 1178 1179 u8 tx_pause_duration_high[0x20]; 1180 1181 u8 tx_pause_duration_low[0x20]; 1182 1183 u8 rx_pause_transition_high[0x20]; 1184 1185 u8 rx_pause_transition_low[0x20]; 1186 1187 u8 reserved_2[0x400]; 1188 }; 1189 1190 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1191 u8 port_transmit_wait_high[0x20]; 1192 1193 u8 port_transmit_wait_low[0x20]; 1194 1195 u8 reserved_0[0x780]; 1196 }; 1197 1198 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1199 u8 dot3stats_alignment_errors_high[0x20]; 1200 1201 u8 dot3stats_alignment_errors_low[0x20]; 1202 1203 u8 dot3stats_fcs_errors_high[0x20]; 1204 1205 u8 dot3stats_fcs_errors_low[0x20]; 1206 1207 u8 dot3stats_single_collision_frames_high[0x20]; 1208 1209 u8 dot3stats_single_collision_frames_low[0x20]; 1210 1211 u8 dot3stats_multiple_collision_frames_high[0x20]; 1212 1213 u8 dot3stats_multiple_collision_frames_low[0x20]; 1214 1215 u8 dot3stats_sqe_test_errors_high[0x20]; 1216 1217 u8 dot3stats_sqe_test_errors_low[0x20]; 1218 1219 u8 dot3stats_deferred_transmissions_high[0x20]; 1220 1221 u8 dot3stats_deferred_transmissions_low[0x20]; 1222 1223 u8 dot3stats_late_collisions_high[0x20]; 1224 1225 u8 dot3stats_late_collisions_low[0x20]; 1226 1227 u8 dot3stats_excessive_collisions_high[0x20]; 1228 1229 u8 dot3stats_excessive_collisions_low[0x20]; 1230 1231 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1232 1233 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1234 1235 u8 dot3stats_carrier_sense_errors_high[0x20]; 1236 1237 u8 dot3stats_carrier_sense_errors_low[0x20]; 1238 1239 u8 dot3stats_frame_too_longs_high[0x20]; 1240 1241 u8 dot3stats_frame_too_longs_low[0x20]; 1242 1243 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1244 1245 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1246 1247 u8 dot3stats_symbol_errors_high[0x20]; 1248 1249 u8 dot3stats_symbol_errors_low[0x20]; 1250 1251 u8 dot3control_in_unknown_opcodes_high[0x20]; 1252 1253 u8 dot3control_in_unknown_opcodes_low[0x20]; 1254 1255 u8 dot3in_pause_frames_high[0x20]; 1256 1257 u8 dot3in_pause_frames_low[0x20]; 1258 1259 u8 dot3out_pause_frames_high[0x20]; 1260 1261 u8 dot3out_pause_frames_low[0x20]; 1262 1263 u8 reserved_0[0x3c0]; 1264 }; 1265 1266 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1267 u8 ether_stats_drop_events_high[0x20]; 1268 1269 u8 ether_stats_drop_events_low[0x20]; 1270 1271 u8 ether_stats_octets_high[0x20]; 1272 1273 u8 ether_stats_octets_low[0x20]; 1274 1275 u8 ether_stats_pkts_high[0x20]; 1276 1277 u8 ether_stats_pkts_low[0x20]; 1278 1279 u8 ether_stats_broadcast_pkts_high[0x20]; 1280 1281 u8 ether_stats_broadcast_pkts_low[0x20]; 1282 1283 u8 ether_stats_multicast_pkts_high[0x20]; 1284 1285 u8 ether_stats_multicast_pkts_low[0x20]; 1286 1287 u8 ether_stats_crc_align_errors_high[0x20]; 1288 1289 u8 ether_stats_crc_align_errors_low[0x20]; 1290 1291 u8 ether_stats_undersize_pkts_high[0x20]; 1292 1293 u8 ether_stats_undersize_pkts_low[0x20]; 1294 1295 u8 ether_stats_oversize_pkts_high[0x20]; 1296 1297 u8 ether_stats_oversize_pkts_low[0x20]; 1298 1299 u8 ether_stats_fragments_high[0x20]; 1300 1301 u8 ether_stats_fragments_low[0x20]; 1302 1303 u8 ether_stats_jabbers_high[0x20]; 1304 1305 u8 ether_stats_jabbers_low[0x20]; 1306 1307 u8 ether_stats_collisions_high[0x20]; 1308 1309 u8 ether_stats_collisions_low[0x20]; 1310 1311 u8 ether_stats_pkts64octets_high[0x20]; 1312 1313 u8 ether_stats_pkts64octets_low[0x20]; 1314 1315 u8 ether_stats_pkts65to127octets_high[0x20]; 1316 1317 u8 ether_stats_pkts65to127octets_low[0x20]; 1318 1319 u8 ether_stats_pkts128to255octets_high[0x20]; 1320 1321 u8 ether_stats_pkts128to255octets_low[0x20]; 1322 1323 u8 ether_stats_pkts256to511octets_high[0x20]; 1324 1325 u8 ether_stats_pkts256to511octets_low[0x20]; 1326 1327 u8 ether_stats_pkts512to1023octets_high[0x20]; 1328 1329 u8 ether_stats_pkts512to1023octets_low[0x20]; 1330 1331 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1332 1333 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1334 1335 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1336 1337 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1338 1339 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1340 1341 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1342 1343 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1344 1345 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1346 1347 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1348 1349 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1350 1351 u8 reserved_0[0x280]; 1352 }; 1353 1354 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1355 u8 if_in_octets_high[0x20]; 1356 1357 u8 if_in_octets_low[0x20]; 1358 1359 u8 if_in_ucast_pkts_high[0x20]; 1360 1361 u8 if_in_ucast_pkts_low[0x20]; 1362 1363 u8 if_in_discards_high[0x20]; 1364 1365 u8 if_in_discards_low[0x20]; 1366 1367 u8 if_in_errors_high[0x20]; 1368 1369 u8 if_in_errors_low[0x20]; 1370 1371 u8 if_in_unknown_protos_high[0x20]; 1372 1373 u8 if_in_unknown_protos_low[0x20]; 1374 1375 u8 if_out_octets_high[0x20]; 1376 1377 u8 if_out_octets_low[0x20]; 1378 1379 u8 if_out_ucast_pkts_high[0x20]; 1380 1381 u8 if_out_ucast_pkts_low[0x20]; 1382 1383 u8 if_out_discards_high[0x20]; 1384 1385 u8 if_out_discards_low[0x20]; 1386 1387 u8 if_out_errors_high[0x20]; 1388 1389 u8 if_out_errors_low[0x20]; 1390 1391 u8 if_in_multicast_pkts_high[0x20]; 1392 1393 u8 if_in_multicast_pkts_low[0x20]; 1394 1395 u8 if_in_broadcast_pkts_high[0x20]; 1396 1397 u8 if_in_broadcast_pkts_low[0x20]; 1398 1399 u8 if_out_multicast_pkts_high[0x20]; 1400 1401 u8 if_out_multicast_pkts_low[0x20]; 1402 1403 u8 if_out_broadcast_pkts_high[0x20]; 1404 1405 u8 if_out_broadcast_pkts_low[0x20]; 1406 1407 u8 reserved_0[0x480]; 1408 }; 1409 1410 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1411 u8 a_frames_transmitted_ok_high[0x20]; 1412 1413 u8 a_frames_transmitted_ok_low[0x20]; 1414 1415 u8 a_frames_received_ok_high[0x20]; 1416 1417 u8 a_frames_received_ok_low[0x20]; 1418 1419 u8 a_frame_check_sequence_errors_high[0x20]; 1420 1421 u8 a_frame_check_sequence_errors_low[0x20]; 1422 1423 u8 a_alignment_errors_high[0x20]; 1424 1425 u8 a_alignment_errors_low[0x20]; 1426 1427 u8 a_octets_transmitted_ok_high[0x20]; 1428 1429 u8 a_octets_transmitted_ok_low[0x20]; 1430 1431 u8 a_octets_received_ok_high[0x20]; 1432 1433 u8 a_octets_received_ok_low[0x20]; 1434 1435 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1436 1437 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1438 1439 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1440 1441 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1442 1443 u8 a_multicast_frames_received_ok_high[0x20]; 1444 1445 u8 a_multicast_frames_received_ok_low[0x20]; 1446 1447 u8 a_broadcast_frames_received_ok_high[0x20]; 1448 1449 u8 a_broadcast_frames_received_ok_low[0x20]; 1450 1451 u8 a_in_range_length_errors_high[0x20]; 1452 1453 u8 a_in_range_length_errors_low[0x20]; 1454 1455 u8 a_out_of_range_length_field_high[0x20]; 1456 1457 u8 a_out_of_range_length_field_low[0x20]; 1458 1459 u8 a_frame_too_long_errors_high[0x20]; 1460 1461 u8 a_frame_too_long_errors_low[0x20]; 1462 1463 u8 a_symbol_error_during_carrier_high[0x20]; 1464 1465 u8 a_symbol_error_during_carrier_low[0x20]; 1466 1467 u8 a_mac_control_frames_transmitted_high[0x20]; 1468 1469 u8 a_mac_control_frames_transmitted_low[0x20]; 1470 1471 u8 a_mac_control_frames_received_high[0x20]; 1472 1473 u8 a_mac_control_frames_received_low[0x20]; 1474 1475 u8 a_unsupported_opcodes_received_high[0x20]; 1476 1477 u8 a_unsupported_opcodes_received_low[0x20]; 1478 1479 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1480 1481 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1482 1483 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1484 1485 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 1486 1487 u8 reserved_0[0x300]; 1488 }; 1489 1490 struct mlx5_ifc_cmd_inter_comp_event_bits { 1491 u8 command_completion_vector[0x20]; 1492 1493 u8 reserved_0[0xc0]; 1494 }; 1495 1496 struct mlx5_ifc_stall_vl_event_bits { 1497 u8 reserved_0[0x18]; 1498 u8 port_num[0x1]; 1499 u8 reserved_1[0x3]; 1500 u8 vl[0x4]; 1501 1502 u8 reserved_2[0xa0]; 1503 }; 1504 1505 struct mlx5_ifc_db_bf_congestion_event_bits { 1506 u8 event_subtype[0x8]; 1507 u8 reserved_0[0x8]; 1508 u8 congestion_level[0x8]; 1509 u8 reserved_1[0x8]; 1510 1511 u8 reserved_2[0xa0]; 1512 }; 1513 1514 struct mlx5_ifc_gpio_event_bits { 1515 u8 reserved_0[0x60]; 1516 1517 u8 gpio_event_hi[0x20]; 1518 1519 u8 gpio_event_lo[0x20]; 1520 1521 u8 reserved_1[0x40]; 1522 }; 1523 1524 struct mlx5_ifc_port_state_change_event_bits { 1525 u8 reserved_0[0x40]; 1526 1527 u8 port_num[0x4]; 1528 u8 reserved_1[0x1c]; 1529 1530 u8 reserved_2[0x80]; 1531 }; 1532 1533 struct mlx5_ifc_dropped_packet_logged_bits { 1534 u8 reserved_0[0xe0]; 1535 }; 1536 1537 enum { 1538 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1539 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1540 }; 1541 1542 struct mlx5_ifc_cq_error_bits { 1543 u8 reserved_0[0x8]; 1544 u8 cqn[0x18]; 1545 1546 u8 reserved_1[0x20]; 1547 1548 u8 reserved_2[0x18]; 1549 u8 syndrome[0x8]; 1550 1551 u8 reserved_3[0x80]; 1552 }; 1553 1554 struct mlx5_ifc_rdma_page_fault_event_bits { 1555 u8 bytes_committed[0x20]; 1556 1557 u8 r_key[0x20]; 1558 1559 u8 reserved_0[0x10]; 1560 u8 packet_len[0x10]; 1561 1562 u8 rdma_op_len[0x20]; 1563 1564 u8 rdma_va[0x40]; 1565 1566 u8 reserved_1[0x5]; 1567 u8 rdma[0x1]; 1568 u8 write[0x1]; 1569 u8 requestor[0x1]; 1570 u8 qp_number[0x18]; 1571 }; 1572 1573 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1574 u8 bytes_committed[0x20]; 1575 1576 u8 reserved_0[0x10]; 1577 u8 wqe_index[0x10]; 1578 1579 u8 reserved_1[0x10]; 1580 u8 len[0x10]; 1581 1582 u8 reserved_2[0x60]; 1583 1584 u8 reserved_3[0x5]; 1585 u8 rdma[0x1]; 1586 u8 write_read[0x1]; 1587 u8 requestor[0x1]; 1588 u8 qpn[0x18]; 1589 }; 1590 1591 struct mlx5_ifc_qp_events_bits { 1592 u8 reserved_0[0xa0]; 1593 1594 u8 type[0x8]; 1595 u8 reserved_1[0x18]; 1596 1597 u8 reserved_2[0x8]; 1598 u8 qpn_rqn_sqn[0x18]; 1599 }; 1600 1601 struct mlx5_ifc_dct_events_bits { 1602 u8 reserved_0[0xc0]; 1603 1604 u8 reserved_1[0x8]; 1605 u8 dct_number[0x18]; 1606 }; 1607 1608 struct mlx5_ifc_comp_event_bits { 1609 u8 reserved_0[0xc0]; 1610 1611 u8 reserved_1[0x8]; 1612 u8 cq_number[0x18]; 1613 }; 1614 1615 enum { 1616 MLX5_QPC_STATE_RST = 0x0, 1617 MLX5_QPC_STATE_INIT = 0x1, 1618 MLX5_QPC_STATE_RTR = 0x2, 1619 MLX5_QPC_STATE_RTS = 0x3, 1620 MLX5_QPC_STATE_SQER = 0x4, 1621 MLX5_QPC_STATE_ERR = 0x6, 1622 MLX5_QPC_STATE_SQD = 0x7, 1623 MLX5_QPC_STATE_SUSPENDED = 0x9, 1624 }; 1625 1626 enum { 1627 MLX5_QPC_ST_RC = 0x0, 1628 MLX5_QPC_ST_UC = 0x1, 1629 MLX5_QPC_ST_UD = 0x2, 1630 MLX5_QPC_ST_XRC = 0x3, 1631 MLX5_QPC_ST_DCI = 0x5, 1632 MLX5_QPC_ST_QP0 = 0x7, 1633 MLX5_QPC_ST_QP1 = 0x8, 1634 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1635 MLX5_QPC_ST_REG_UMR = 0xc, 1636 }; 1637 1638 enum { 1639 MLX5_QPC_PM_STATE_ARMED = 0x0, 1640 MLX5_QPC_PM_STATE_REARM = 0x1, 1641 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1642 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 1643 }; 1644 1645 enum { 1646 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1647 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1648 }; 1649 1650 enum { 1651 MLX5_QPC_MTU_256_BYTES = 0x1, 1652 MLX5_QPC_MTU_512_BYTES = 0x2, 1653 MLX5_QPC_MTU_1K_BYTES = 0x3, 1654 MLX5_QPC_MTU_2K_BYTES = 0x4, 1655 MLX5_QPC_MTU_4K_BYTES = 0x5, 1656 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1657 }; 1658 1659 enum { 1660 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1661 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1662 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1663 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1664 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1665 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1666 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1667 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1668 }; 1669 1670 enum { 1671 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1672 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1673 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1674 }; 1675 1676 enum { 1677 MLX5_QPC_CS_RES_DISABLE = 0x0, 1678 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1679 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1680 }; 1681 1682 struct mlx5_ifc_qpc_bits { 1683 u8 state[0x4]; 1684 u8 reserved_0[0x4]; 1685 u8 st[0x8]; 1686 u8 reserved_1[0x3]; 1687 u8 pm_state[0x2]; 1688 u8 reserved_2[0x7]; 1689 u8 end_padding_mode[0x2]; 1690 u8 reserved_3[0x2]; 1691 1692 u8 wq_signature[0x1]; 1693 u8 block_lb_mc[0x1]; 1694 u8 atomic_like_write_en[0x1]; 1695 u8 latency_sensitive[0x1]; 1696 u8 reserved_4[0x1]; 1697 u8 drain_sigerr[0x1]; 1698 u8 reserved_5[0x2]; 1699 u8 pd[0x18]; 1700 1701 u8 mtu[0x3]; 1702 u8 log_msg_max[0x5]; 1703 u8 reserved_6[0x1]; 1704 u8 log_rq_size[0x4]; 1705 u8 log_rq_stride[0x3]; 1706 u8 no_sq[0x1]; 1707 u8 log_sq_size[0x4]; 1708 u8 reserved_7[0x6]; 1709 u8 rlky[0x1]; 1710 u8 reserved_8[0x4]; 1711 1712 u8 counter_set_id[0x8]; 1713 u8 uar_page[0x18]; 1714 1715 u8 reserved_9[0x8]; 1716 u8 user_index[0x18]; 1717 1718 u8 reserved_10[0x3]; 1719 u8 log_page_size[0x5]; 1720 u8 remote_qpn[0x18]; 1721 1722 struct mlx5_ifc_ads_bits primary_address_path; 1723 1724 struct mlx5_ifc_ads_bits secondary_address_path; 1725 1726 u8 log_ack_req_freq[0x4]; 1727 u8 reserved_11[0x4]; 1728 u8 log_sra_max[0x3]; 1729 u8 reserved_12[0x2]; 1730 u8 retry_count[0x3]; 1731 u8 rnr_retry[0x3]; 1732 u8 reserved_13[0x1]; 1733 u8 fre[0x1]; 1734 u8 cur_rnr_retry[0x3]; 1735 u8 cur_retry_count[0x3]; 1736 u8 reserved_14[0x5]; 1737 1738 u8 reserved_15[0x20]; 1739 1740 u8 reserved_16[0x8]; 1741 u8 next_send_psn[0x18]; 1742 1743 u8 reserved_17[0x8]; 1744 u8 cqn_snd[0x18]; 1745 1746 u8 reserved_18[0x40]; 1747 1748 u8 reserved_19[0x8]; 1749 u8 last_acked_psn[0x18]; 1750 1751 u8 reserved_20[0x8]; 1752 u8 ssn[0x18]; 1753 1754 u8 reserved_21[0x8]; 1755 u8 log_rra_max[0x3]; 1756 u8 reserved_22[0x1]; 1757 u8 atomic_mode[0x4]; 1758 u8 rre[0x1]; 1759 u8 rwe[0x1]; 1760 u8 rae[0x1]; 1761 u8 reserved_23[0x1]; 1762 u8 page_offset[0x6]; 1763 u8 reserved_24[0x3]; 1764 u8 cd_slave_receive[0x1]; 1765 u8 cd_slave_send[0x1]; 1766 u8 cd_master[0x1]; 1767 1768 u8 reserved_25[0x3]; 1769 u8 min_rnr_nak[0x5]; 1770 u8 next_rcv_psn[0x18]; 1771 1772 u8 reserved_26[0x8]; 1773 u8 xrcd[0x18]; 1774 1775 u8 reserved_27[0x8]; 1776 u8 cqn_rcv[0x18]; 1777 1778 u8 dbr_addr[0x40]; 1779 1780 u8 q_key[0x20]; 1781 1782 u8 reserved_28[0x5]; 1783 u8 rq_type[0x3]; 1784 u8 srqn_rmpn[0x18]; 1785 1786 u8 reserved_29[0x8]; 1787 u8 rmsn[0x18]; 1788 1789 u8 hw_sq_wqebb_counter[0x10]; 1790 u8 sw_sq_wqebb_counter[0x10]; 1791 1792 u8 hw_rq_counter[0x20]; 1793 1794 u8 sw_rq_counter[0x20]; 1795 1796 u8 reserved_30[0x20]; 1797 1798 u8 reserved_31[0xf]; 1799 u8 cgs[0x1]; 1800 u8 cs_req[0x8]; 1801 u8 cs_res[0x8]; 1802 1803 u8 dc_access_key[0x40]; 1804 1805 u8 reserved_32[0xc0]; 1806 }; 1807 1808 struct mlx5_ifc_roce_addr_layout_bits { 1809 u8 source_l3_address[16][0x8]; 1810 1811 u8 reserved_0[0x3]; 1812 u8 vlan_valid[0x1]; 1813 u8 vlan_id[0xc]; 1814 u8 source_mac_47_32[0x10]; 1815 1816 u8 source_mac_31_0[0x20]; 1817 1818 u8 reserved_1[0x14]; 1819 u8 roce_l3_type[0x4]; 1820 u8 roce_version[0x8]; 1821 1822 u8 reserved_2[0x20]; 1823 }; 1824 1825 union mlx5_ifc_hca_cap_union_bits { 1826 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 1827 struct mlx5_ifc_odp_cap_bits odp_cap; 1828 struct mlx5_ifc_atomic_caps_bits atomic_caps; 1829 struct mlx5_ifc_roce_cap_bits roce_cap; 1830 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 1831 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 1832 u8 reserved_0[0x8000]; 1833 }; 1834 1835 enum { 1836 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 1837 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 1838 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 1839 }; 1840 1841 struct mlx5_ifc_flow_context_bits { 1842 u8 reserved_0[0x20]; 1843 1844 u8 group_id[0x20]; 1845 1846 u8 reserved_1[0x8]; 1847 u8 flow_tag[0x18]; 1848 1849 u8 reserved_2[0x10]; 1850 u8 action[0x10]; 1851 1852 u8 reserved_3[0x8]; 1853 u8 destination_list_size[0x18]; 1854 1855 u8 reserved_4[0x160]; 1856 1857 struct mlx5_ifc_fte_match_param_bits match_value; 1858 1859 u8 reserved_5[0x600]; 1860 1861 struct mlx5_ifc_dest_format_struct_bits destination[0]; 1862 }; 1863 1864 enum { 1865 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 1866 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 1867 }; 1868 1869 struct mlx5_ifc_xrc_srqc_bits { 1870 u8 state[0x4]; 1871 u8 log_xrc_srq_size[0x4]; 1872 u8 reserved_0[0x18]; 1873 1874 u8 wq_signature[0x1]; 1875 u8 cont_srq[0x1]; 1876 u8 reserved_1[0x1]; 1877 u8 rlky[0x1]; 1878 u8 basic_cyclic_rcv_wqe[0x1]; 1879 u8 log_rq_stride[0x3]; 1880 u8 xrcd[0x18]; 1881 1882 u8 page_offset[0x6]; 1883 u8 reserved_2[0x2]; 1884 u8 cqn[0x18]; 1885 1886 u8 reserved_3[0x20]; 1887 1888 u8 user_index_equal_xrc_srqn[0x1]; 1889 u8 reserved_4[0x1]; 1890 u8 log_page_size[0x6]; 1891 u8 user_index[0x18]; 1892 1893 u8 reserved_5[0x20]; 1894 1895 u8 reserved_6[0x8]; 1896 u8 pd[0x18]; 1897 1898 u8 lwm[0x10]; 1899 u8 wqe_cnt[0x10]; 1900 1901 u8 reserved_7[0x40]; 1902 1903 u8 db_record_addr_h[0x20]; 1904 1905 u8 db_record_addr_l[0x1e]; 1906 u8 reserved_8[0x2]; 1907 1908 u8 reserved_9[0x80]; 1909 }; 1910 1911 struct mlx5_ifc_traffic_counter_bits { 1912 u8 packets[0x40]; 1913 1914 u8 octets[0x40]; 1915 }; 1916 1917 struct mlx5_ifc_tisc_bits { 1918 u8 reserved_0[0xc]; 1919 u8 prio[0x4]; 1920 u8 reserved_1[0x10]; 1921 1922 u8 reserved_2[0x100]; 1923 1924 u8 reserved_3[0x8]; 1925 u8 transport_domain[0x18]; 1926 1927 u8 reserved_4[0x3c0]; 1928 }; 1929 1930 enum { 1931 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 1932 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 1933 }; 1934 1935 enum { 1936 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 1937 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 1938 }; 1939 1940 enum { 1941 MLX5_RX_HASH_FN_NONE = 0x0, 1942 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 1943 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 1944 }; 1945 1946 enum { 1947 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 1948 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 1949 }; 1950 1951 struct mlx5_ifc_tirc_bits { 1952 u8 reserved_0[0x20]; 1953 1954 u8 disp_type[0x4]; 1955 u8 reserved_1[0x1c]; 1956 1957 u8 reserved_2[0x40]; 1958 1959 u8 reserved_3[0x4]; 1960 u8 lro_timeout_period_usecs[0x10]; 1961 u8 lro_enable_mask[0x4]; 1962 u8 lro_max_ip_payload_size[0x8]; 1963 1964 u8 reserved_4[0x40]; 1965 1966 u8 reserved_5[0x8]; 1967 u8 inline_rqn[0x18]; 1968 1969 u8 rx_hash_symmetric[0x1]; 1970 u8 reserved_6[0x1]; 1971 u8 tunneled_offload_en[0x1]; 1972 u8 reserved_7[0x5]; 1973 u8 indirect_table[0x18]; 1974 1975 u8 rx_hash_fn[0x4]; 1976 u8 reserved_8[0x2]; 1977 u8 self_lb_block[0x2]; 1978 u8 transport_domain[0x18]; 1979 1980 u8 rx_hash_toeplitz_key[10][0x20]; 1981 1982 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 1983 1984 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 1985 1986 u8 reserved_9[0x4c0]; 1987 }; 1988 1989 enum { 1990 MLX5_SRQC_STATE_GOOD = 0x0, 1991 MLX5_SRQC_STATE_ERROR = 0x1, 1992 }; 1993 1994 struct mlx5_ifc_srqc_bits { 1995 u8 state[0x4]; 1996 u8 log_srq_size[0x4]; 1997 u8 reserved_0[0x18]; 1998 1999 u8 wq_signature[0x1]; 2000 u8 cont_srq[0x1]; 2001 u8 reserved_1[0x1]; 2002 u8 rlky[0x1]; 2003 u8 reserved_2[0x1]; 2004 u8 log_rq_stride[0x3]; 2005 u8 xrcd[0x18]; 2006 2007 u8 page_offset[0x6]; 2008 u8 reserved_3[0x2]; 2009 u8 cqn[0x18]; 2010 2011 u8 reserved_4[0x20]; 2012 2013 u8 reserved_5[0x2]; 2014 u8 log_page_size[0x6]; 2015 u8 reserved_6[0x18]; 2016 2017 u8 reserved_7[0x20]; 2018 2019 u8 reserved_8[0x8]; 2020 u8 pd[0x18]; 2021 2022 u8 lwm[0x10]; 2023 u8 wqe_cnt[0x10]; 2024 2025 u8 reserved_9[0x40]; 2026 2027 u8 dbr_addr[0x40]; 2028 2029 u8 reserved_10[0x80]; 2030 }; 2031 2032 enum { 2033 MLX5_SQC_STATE_RST = 0x0, 2034 MLX5_SQC_STATE_RDY = 0x1, 2035 MLX5_SQC_STATE_ERR = 0x3, 2036 }; 2037 2038 struct mlx5_ifc_sqc_bits { 2039 u8 rlky[0x1]; 2040 u8 cd_master[0x1]; 2041 u8 fre[0x1]; 2042 u8 flush_in_error_en[0x1]; 2043 u8 reserved_0[0x4]; 2044 u8 state[0x4]; 2045 u8 reserved_1[0x14]; 2046 2047 u8 reserved_2[0x8]; 2048 u8 user_index[0x18]; 2049 2050 u8 reserved_3[0x8]; 2051 u8 cqn[0x18]; 2052 2053 u8 reserved_4[0xa0]; 2054 2055 u8 tis_lst_sz[0x10]; 2056 u8 reserved_5[0x10]; 2057 2058 u8 reserved_6[0x40]; 2059 2060 u8 reserved_7[0x8]; 2061 u8 tis_num_0[0x18]; 2062 2063 struct mlx5_ifc_wq_bits wq; 2064 }; 2065 2066 struct mlx5_ifc_rqtc_bits { 2067 u8 reserved_0[0xa0]; 2068 2069 u8 reserved_1[0x10]; 2070 u8 rqt_max_size[0x10]; 2071 2072 u8 reserved_2[0x10]; 2073 u8 rqt_actual_size[0x10]; 2074 2075 u8 reserved_3[0x6a0]; 2076 2077 struct mlx5_ifc_rq_num_bits rq_num[0]; 2078 }; 2079 2080 enum { 2081 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2082 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2083 }; 2084 2085 enum { 2086 MLX5_RQC_STATE_RST = 0x0, 2087 MLX5_RQC_STATE_RDY = 0x1, 2088 MLX5_RQC_STATE_ERR = 0x3, 2089 }; 2090 2091 struct mlx5_ifc_rqc_bits { 2092 u8 rlky[0x1]; 2093 u8 reserved_0[0x2]; 2094 u8 vsd[0x1]; 2095 u8 mem_rq_type[0x4]; 2096 u8 state[0x4]; 2097 u8 reserved_1[0x1]; 2098 u8 flush_in_error_en[0x1]; 2099 u8 reserved_2[0x12]; 2100 2101 u8 reserved_3[0x8]; 2102 u8 user_index[0x18]; 2103 2104 u8 reserved_4[0x8]; 2105 u8 cqn[0x18]; 2106 2107 u8 counter_set_id[0x8]; 2108 u8 reserved_5[0x18]; 2109 2110 u8 reserved_6[0x8]; 2111 u8 rmpn[0x18]; 2112 2113 u8 reserved_7[0xe0]; 2114 2115 struct mlx5_ifc_wq_bits wq; 2116 }; 2117 2118 enum { 2119 MLX5_RMPC_STATE_RDY = 0x1, 2120 MLX5_RMPC_STATE_ERR = 0x3, 2121 }; 2122 2123 struct mlx5_ifc_rmpc_bits { 2124 u8 reserved_0[0x8]; 2125 u8 state[0x4]; 2126 u8 reserved_1[0x14]; 2127 2128 u8 basic_cyclic_rcv_wqe[0x1]; 2129 u8 reserved_2[0x1f]; 2130 2131 u8 reserved_3[0x140]; 2132 2133 struct mlx5_ifc_wq_bits wq; 2134 }; 2135 2136 enum { 2137 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2138 }; 2139 2140 struct mlx5_ifc_nic_vport_context_bits { 2141 u8 reserved_0[0x1f]; 2142 u8 roce_en[0x1]; 2143 2144 u8 reserved_1[0x120]; 2145 2146 u8 system_image_guid[0x40]; 2147 u8 port_guid[0x40]; 2148 u8 node_guid[0x40]; 2149 2150 u8 reserved_5[0x140]; 2151 u8 qkey_violation_counter[0x10]; 2152 u8 reserved_6[0x430]; 2153 2154 u8 reserved_2[0x5]; 2155 u8 allowed_list_type[0x3]; 2156 u8 reserved_3[0xc]; 2157 u8 allowed_list_size[0xc]; 2158 2159 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2160 2161 u8 reserved_4[0x20]; 2162 2163 u8 current_uc_mac_address[0][0x40]; 2164 }; 2165 2166 enum { 2167 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2168 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2169 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2170 }; 2171 2172 struct mlx5_ifc_mkc_bits { 2173 u8 reserved_0[0x1]; 2174 u8 free[0x1]; 2175 u8 reserved_1[0xd]; 2176 u8 small_fence_on_rdma_read_response[0x1]; 2177 u8 umr_en[0x1]; 2178 u8 a[0x1]; 2179 u8 rw[0x1]; 2180 u8 rr[0x1]; 2181 u8 lw[0x1]; 2182 u8 lr[0x1]; 2183 u8 access_mode[0x2]; 2184 u8 reserved_2[0x8]; 2185 2186 u8 qpn[0x18]; 2187 u8 mkey_7_0[0x8]; 2188 2189 u8 reserved_3[0x20]; 2190 2191 u8 length64[0x1]; 2192 u8 bsf_en[0x1]; 2193 u8 sync_umr[0x1]; 2194 u8 reserved_4[0x2]; 2195 u8 expected_sigerr_count[0x1]; 2196 u8 reserved_5[0x1]; 2197 u8 en_rinval[0x1]; 2198 u8 pd[0x18]; 2199 2200 u8 start_addr[0x40]; 2201 2202 u8 len[0x40]; 2203 2204 u8 bsf_octword_size[0x20]; 2205 2206 u8 reserved_6[0x80]; 2207 2208 u8 translations_octword_size[0x20]; 2209 2210 u8 reserved_7[0x1b]; 2211 u8 log_page_size[0x5]; 2212 2213 u8 reserved_8[0x20]; 2214 }; 2215 2216 struct mlx5_ifc_pkey_bits { 2217 u8 reserved_0[0x10]; 2218 u8 pkey[0x10]; 2219 }; 2220 2221 struct mlx5_ifc_array128_auto_bits { 2222 u8 array128_auto[16][0x8]; 2223 }; 2224 2225 struct mlx5_ifc_hca_vport_context_bits { 2226 u8 field_select[0x20]; 2227 2228 u8 reserved_0[0xe0]; 2229 2230 u8 sm_virt_aware[0x1]; 2231 u8 has_smi[0x1]; 2232 u8 has_raw[0x1]; 2233 u8 grh_required[0x1]; 2234 u8 reserved_1[0xc]; 2235 u8 port_physical_state[0x4]; 2236 u8 vport_state_policy[0x4]; 2237 u8 port_state[0x4]; 2238 u8 vport_state[0x4]; 2239 2240 u8 reserved_2[0x20]; 2241 2242 u8 system_image_guid[0x40]; 2243 2244 u8 port_guid[0x40]; 2245 2246 u8 node_guid[0x40]; 2247 2248 u8 cap_mask1[0x20]; 2249 2250 u8 cap_mask1_field_select[0x20]; 2251 2252 u8 cap_mask2[0x20]; 2253 2254 u8 cap_mask2_field_select[0x20]; 2255 2256 u8 reserved_3[0x80]; 2257 2258 u8 lid[0x10]; 2259 u8 reserved_4[0x4]; 2260 u8 init_type_reply[0x4]; 2261 u8 lmc[0x3]; 2262 u8 subnet_timeout[0x5]; 2263 2264 u8 sm_lid[0x10]; 2265 u8 sm_sl[0x4]; 2266 u8 reserved_5[0xc]; 2267 2268 u8 qkey_violation_counter[0x10]; 2269 u8 pkey_violation_counter[0x10]; 2270 2271 u8 reserved_6[0xca0]; 2272 }; 2273 2274 enum { 2275 MLX5_EQC_STATUS_OK = 0x0, 2276 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2277 }; 2278 2279 enum { 2280 MLX5_EQC_ST_ARMED = 0x9, 2281 MLX5_EQC_ST_FIRED = 0xa, 2282 }; 2283 2284 struct mlx5_ifc_eqc_bits { 2285 u8 status[0x4]; 2286 u8 reserved_0[0x9]; 2287 u8 ec[0x1]; 2288 u8 oi[0x1]; 2289 u8 reserved_1[0x5]; 2290 u8 st[0x4]; 2291 u8 reserved_2[0x8]; 2292 2293 u8 reserved_3[0x20]; 2294 2295 u8 reserved_4[0x14]; 2296 u8 page_offset[0x6]; 2297 u8 reserved_5[0x6]; 2298 2299 u8 reserved_6[0x3]; 2300 u8 log_eq_size[0x5]; 2301 u8 uar_page[0x18]; 2302 2303 u8 reserved_7[0x20]; 2304 2305 u8 reserved_8[0x18]; 2306 u8 intr[0x8]; 2307 2308 u8 reserved_9[0x3]; 2309 u8 log_page_size[0x5]; 2310 u8 reserved_10[0x18]; 2311 2312 u8 reserved_11[0x60]; 2313 2314 u8 reserved_12[0x8]; 2315 u8 consumer_counter[0x18]; 2316 2317 u8 reserved_13[0x8]; 2318 u8 producer_counter[0x18]; 2319 2320 u8 reserved_14[0x80]; 2321 }; 2322 2323 enum { 2324 MLX5_DCTC_STATE_ACTIVE = 0x0, 2325 MLX5_DCTC_STATE_DRAINING = 0x1, 2326 MLX5_DCTC_STATE_DRAINED = 0x2, 2327 }; 2328 2329 enum { 2330 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2331 MLX5_DCTC_CS_RES_NA = 0x1, 2332 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2333 }; 2334 2335 enum { 2336 MLX5_DCTC_MTU_256_BYTES = 0x1, 2337 MLX5_DCTC_MTU_512_BYTES = 0x2, 2338 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2339 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2340 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2341 }; 2342 2343 struct mlx5_ifc_dctc_bits { 2344 u8 reserved_0[0x4]; 2345 u8 state[0x4]; 2346 u8 reserved_1[0x18]; 2347 2348 u8 reserved_2[0x8]; 2349 u8 user_index[0x18]; 2350 2351 u8 reserved_3[0x8]; 2352 u8 cqn[0x18]; 2353 2354 u8 counter_set_id[0x8]; 2355 u8 atomic_mode[0x4]; 2356 u8 rre[0x1]; 2357 u8 rwe[0x1]; 2358 u8 rae[0x1]; 2359 u8 atomic_like_write_en[0x1]; 2360 u8 latency_sensitive[0x1]; 2361 u8 rlky[0x1]; 2362 u8 free_ar[0x1]; 2363 u8 reserved_4[0xd]; 2364 2365 u8 reserved_5[0x8]; 2366 u8 cs_res[0x8]; 2367 u8 reserved_6[0x3]; 2368 u8 min_rnr_nak[0x5]; 2369 u8 reserved_7[0x8]; 2370 2371 u8 reserved_8[0x8]; 2372 u8 srqn[0x18]; 2373 2374 u8 reserved_9[0x8]; 2375 u8 pd[0x18]; 2376 2377 u8 tclass[0x8]; 2378 u8 reserved_10[0x4]; 2379 u8 flow_label[0x14]; 2380 2381 u8 dc_access_key[0x40]; 2382 2383 u8 reserved_11[0x5]; 2384 u8 mtu[0x3]; 2385 u8 port[0x8]; 2386 u8 pkey_index[0x10]; 2387 2388 u8 reserved_12[0x8]; 2389 u8 my_addr_index[0x8]; 2390 u8 reserved_13[0x8]; 2391 u8 hop_limit[0x8]; 2392 2393 u8 dc_access_key_violation_count[0x20]; 2394 2395 u8 reserved_14[0x14]; 2396 u8 dei_cfi[0x1]; 2397 u8 eth_prio[0x3]; 2398 u8 ecn[0x2]; 2399 u8 dscp[0x6]; 2400 2401 u8 reserved_15[0x40]; 2402 }; 2403 2404 enum { 2405 MLX5_CQC_STATUS_OK = 0x0, 2406 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2407 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2408 }; 2409 2410 enum { 2411 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 2412 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 2413 }; 2414 2415 enum { 2416 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 2417 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 2418 MLX5_CQC_ST_FIRED = 0xa, 2419 }; 2420 2421 struct mlx5_ifc_cqc_bits { 2422 u8 status[0x4]; 2423 u8 reserved_0[0x4]; 2424 u8 cqe_sz[0x3]; 2425 u8 cc[0x1]; 2426 u8 reserved_1[0x1]; 2427 u8 scqe_break_moderation_en[0x1]; 2428 u8 oi[0x1]; 2429 u8 reserved_2[0x2]; 2430 u8 cqe_zip_en[0x1]; 2431 u8 mini_cqe_res_format[0x2]; 2432 u8 st[0x4]; 2433 u8 reserved_3[0x8]; 2434 2435 u8 reserved_4[0x20]; 2436 2437 u8 reserved_5[0x14]; 2438 u8 page_offset[0x6]; 2439 u8 reserved_6[0x6]; 2440 2441 u8 reserved_7[0x3]; 2442 u8 log_cq_size[0x5]; 2443 u8 uar_page[0x18]; 2444 2445 u8 reserved_8[0x4]; 2446 u8 cq_period[0xc]; 2447 u8 cq_max_count[0x10]; 2448 2449 u8 reserved_9[0x18]; 2450 u8 c_eqn[0x8]; 2451 2452 u8 reserved_10[0x3]; 2453 u8 log_page_size[0x5]; 2454 u8 reserved_11[0x18]; 2455 2456 u8 reserved_12[0x20]; 2457 2458 u8 reserved_13[0x8]; 2459 u8 last_notified_index[0x18]; 2460 2461 u8 reserved_14[0x8]; 2462 u8 last_solicit_index[0x18]; 2463 2464 u8 reserved_15[0x8]; 2465 u8 consumer_counter[0x18]; 2466 2467 u8 reserved_16[0x8]; 2468 u8 producer_counter[0x18]; 2469 2470 u8 reserved_17[0x40]; 2471 2472 u8 dbr_addr[0x40]; 2473 }; 2474 2475 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2476 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2477 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2478 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2479 u8 reserved_0[0x800]; 2480 }; 2481 2482 struct mlx5_ifc_query_adapter_param_block_bits { 2483 u8 reserved_0[0xc0]; 2484 2485 u8 reserved_1[0x8]; 2486 u8 ieee_vendor_id[0x18]; 2487 2488 u8 reserved_2[0x10]; 2489 u8 vsd_vendor_id[0x10]; 2490 2491 u8 vsd[208][0x8]; 2492 2493 u8 vsd_contd_psid[16][0x8]; 2494 }; 2495 2496 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2497 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2498 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2499 u8 reserved_0[0x20]; 2500 }; 2501 2502 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2503 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 2504 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 2505 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 2506 u8 reserved_0[0x20]; 2507 }; 2508 2509 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 2510 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 2511 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 2512 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 2513 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 2514 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 2515 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 2516 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 2517 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 2518 u8 reserved_0[0x7c0]; 2519 }; 2520 2521 union mlx5_ifc_event_auto_bits { 2522 struct mlx5_ifc_comp_event_bits comp_event; 2523 struct mlx5_ifc_dct_events_bits dct_events; 2524 struct mlx5_ifc_qp_events_bits qp_events; 2525 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 2526 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 2527 struct mlx5_ifc_cq_error_bits cq_error; 2528 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 2529 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 2530 struct mlx5_ifc_gpio_event_bits gpio_event; 2531 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 2532 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 2533 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 2534 u8 reserved_0[0xe0]; 2535 }; 2536 2537 struct mlx5_ifc_health_buffer_bits { 2538 u8 reserved_0[0x100]; 2539 2540 u8 assert_existptr[0x20]; 2541 2542 u8 assert_callra[0x20]; 2543 2544 u8 reserved_1[0x40]; 2545 2546 u8 fw_version[0x20]; 2547 2548 u8 hw_id[0x20]; 2549 2550 u8 reserved_2[0x20]; 2551 2552 u8 irisc_index[0x8]; 2553 u8 synd[0x8]; 2554 u8 ext_synd[0x10]; 2555 }; 2556 2557 struct mlx5_ifc_register_loopback_control_bits { 2558 u8 no_lb[0x1]; 2559 u8 reserved_0[0x7]; 2560 u8 port[0x8]; 2561 u8 reserved_1[0x10]; 2562 2563 u8 reserved_2[0x60]; 2564 }; 2565 2566 struct mlx5_ifc_teardown_hca_out_bits { 2567 u8 status[0x8]; 2568 u8 reserved_0[0x18]; 2569 2570 u8 syndrome[0x20]; 2571 2572 u8 reserved_1[0x40]; 2573 }; 2574 2575 enum { 2576 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 2577 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1, 2578 }; 2579 2580 struct mlx5_ifc_teardown_hca_in_bits { 2581 u8 opcode[0x10]; 2582 u8 reserved_0[0x10]; 2583 2584 u8 reserved_1[0x10]; 2585 u8 op_mod[0x10]; 2586 2587 u8 reserved_2[0x10]; 2588 u8 profile[0x10]; 2589 2590 u8 reserved_3[0x20]; 2591 }; 2592 2593 struct mlx5_ifc_sqerr2rts_qp_out_bits { 2594 u8 status[0x8]; 2595 u8 reserved_0[0x18]; 2596 2597 u8 syndrome[0x20]; 2598 2599 u8 reserved_1[0x40]; 2600 }; 2601 2602 struct mlx5_ifc_sqerr2rts_qp_in_bits { 2603 u8 opcode[0x10]; 2604 u8 reserved_0[0x10]; 2605 2606 u8 reserved_1[0x10]; 2607 u8 op_mod[0x10]; 2608 2609 u8 reserved_2[0x8]; 2610 u8 qpn[0x18]; 2611 2612 u8 reserved_3[0x20]; 2613 2614 u8 opt_param_mask[0x20]; 2615 2616 u8 reserved_4[0x20]; 2617 2618 struct mlx5_ifc_qpc_bits qpc; 2619 2620 u8 reserved_5[0x80]; 2621 }; 2622 2623 struct mlx5_ifc_sqd2rts_qp_out_bits { 2624 u8 status[0x8]; 2625 u8 reserved_0[0x18]; 2626 2627 u8 syndrome[0x20]; 2628 2629 u8 reserved_1[0x40]; 2630 }; 2631 2632 struct mlx5_ifc_sqd2rts_qp_in_bits { 2633 u8 opcode[0x10]; 2634 u8 reserved_0[0x10]; 2635 2636 u8 reserved_1[0x10]; 2637 u8 op_mod[0x10]; 2638 2639 u8 reserved_2[0x8]; 2640 u8 qpn[0x18]; 2641 2642 u8 reserved_3[0x20]; 2643 2644 u8 opt_param_mask[0x20]; 2645 2646 u8 reserved_4[0x20]; 2647 2648 struct mlx5_ifc_qpc_bits qpc; 2649 2650 u8 reserved_5[0x80]; 2651 }; 2652 2653 struct mlx5_ifc_set_roce_address_out_bits { 2654 u8 status[0x8]; 2655 u8 reserved_0[0x18]; 2656 2657 u8 syndrome[0x20]; 2658 2659 u8 reserved_1[0x40]; 2660 }; 2661 2662 struct mlx5_ifc_set_roce_address_in_bits { 2663 u8 opcode[0x10]; 2664 u8 reserved_0[0x10]; 2665 2666 u8 reserved_1[0x10]; 2667 u8 op_mod[0x10]; 2668 2669 u8 roce_address_index[0x10]; 2670 u8 reserved_2[0x10]; 2671 2672 u8 reserved_3[0x20]; 2673 2674 struct mlx5_ifc_roce_addr_layout_bits roce_address; 2675 }; 2676 2677 struct mlx5_ifc_set_mad_demux_out_bits { 2678 u8 status[0x8]; 2679 u8 reserved_0[0x18]; 2680 2681 u8 syndrome[0x20]; 2682 2683 u8 reserved_1[0x40]; 2684 }; 2685 2686 enum { 2687 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 2688 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 2689 }; 2690 2691 struct mlx5_ifc_set_mad_demux_in_bits { 2692 u8 opcode[0x10]; 2693 u8 reserved_0[0x10]; 2694 2695 u8 reserved_1[0x10]; 2696 u8 op_mod[0x10]; 2697 2698 u8 reserved_2[0x20]; 2699 2700 u8 reserved_3[0x6]; 2701 u8 demux_mode[0x2]; 2702 u8 reserved_4[0x18]; 2703 }; 2704 2705 struct mlx5_ifc_set_l2_table_entry_out_bits { 2706 u8 status[0x8]; 2707 u8 reserved_0[0x18]; 2708 2709 u8 syndrome[0x20]; 2710 2711 u8 reserved_1[0x40]; 2712 }; 2713 2714 struct mlx5_ifc_set_l2_table_entry_in_bits { 2715 u8 opcode[0x10]; 2716 u8 reserved_0[0x10]; 2717 2718 u8 reserved_1[0x10]; 2719 u8 op_mod[0x10]; 2720 2721 u8 reserved_2[0x60]; 2722 2723 u8 reserved_3[0x8]; 2724 u8 table_index[0x18]; 2725 2726 u8 reserved_4[0x20]; 2727 2728 u8 reserved_5[0x13]; 2729 u8 vlan_valid[0x1]; 2730 u8 vlan[0xc]; 2731 2732 struct mlx5_ifc_mac_address_layout_bits mac_address; 2733 2734 u8 reserved_6[0xc0]; 2735 }; 2736 2737 struct mlx5_ifc_set_issi_out_bits { 2738 u8 status[0x8]; 2739 u8 reserved_0[0x18]; 2740 2741 u8 syndrome[0x20]; 2742 2743 u8 reserved_1[0x40]; 2744 }; 2745 2746 struct mlx5_ifc_set_issi_in_bits { 2747 u8 opcode[0x10]; 2748 u8 reserved_0[0x10]; 2749 2750 u8 reserved_1[0x10]; 2751 u8 op_mod[0x10]; 2752 2753 u8 reserved_2[0x10]; 2754 u8 current_issi[0x10]; 2755 2756 u8 reserved_3[0x20]; 2757 }; 2758 2759 struct mlx5_ifc_set_hca_cap_out_bits { 2760 u8 status[0x8]; 2761 u8 reserved_0[0x18]; 2762 2763 u8 syndrome[0x20]; 2764 2765 u8 reserved_1[0x40]; 2766 }; 2767 2768 struct mlx5_ifc_set_hca_cap_in_bits { 2769 u8 opcode[0x10]; 2770 u8 reserved_0[0x10]; 2771 2772 u8 reserved_1[0x10]; 2773 u8 op_mod[0x10]; 2774 2775 u8 reserved_2[0x40]; 2776 2777 union mlx5_ifc_hca_cap_union_bits capability; 2778 }; 2779 2780 struct mlx5_ifc_set_fte_out_bits { 2781 u8 status[0x8]; 2782 u8 reserved_0[0x18]; 2783 2784 u8 syndrome[0x20]; 2785 2786 u8 reserved_1[0x40]; 2787 }; 2788 2789 struct mlx5_ifc_set_fte_in_bits { 2790 u8 opcode[0x10]; 2791 u8 reserved_0[0x10]; 2792 2793 u8 reserved_1[0x10]; 2794 u8 op_mod[0x10]; 2795 2796 u8 reserved_2[0x40]; 2797 2798 u8 table_type[0x8]; 2799 u8 reserved_3[0x18]; 2800 2801 u8 reserved_4[0x8]; 2802 u8 table_id[0x18]; 2803 2804 u8 reserved_5[0x40]; 2805 2806 u8 flow_index[0x20]; 2807 2808 u8 reserved_6[0xe0]; 2809 2810 struct mlx5_ifc_flow_context_bits flow_context; 2811 }; 2812 2813 struct mlx5_ifc_rts2rts_qp_out_bits { 2814 u8 status[0x8]; 2815 u8 reserved_0[0x18]; 2816 2817 u8 syndrome[0x20]; 2818 2819 u8 reserved_1[0x40]; 2820 }; 2821 2822 struct mlx5_ifc_rts2rts_qp_in_bits { 2823 u8 opcode[0x10]; 2824 u8 reserved_0[0x10]; 2825 2826 u8 reserved_1[0x10]; 2827 u8 op_mod[0x10]; 2828 2829 u8 reserved_2[0x8]; 2830 u8 qpn[0x18]; 2831 2832 u8 reserved_3[0x20]; 2833 2834 u8 opt_param_mask[0x20]; 2835 2836 u8 reserved_4[0x20]; 2837 2838 struct mlx5_ifc_qpc_bits qpc; 2839 2840 u8 reserved_5[0x80]; 2841 }; 2842 2843 struct mlx5_ifc_rtr2rts_qp_out_bits { 2844 u8 status[0x8]; 2845 u8 reserved_0[0x18]; 2846 2847 u8 syndrome[0x20]; 2848 2849 u8 reserved_1[0x40]; 2850 }; 2851 2852 struct mlx5_ifc_rtr2rts_qp_in_bits { 2853 u8 opcode[0x10]; 2854 u8 reserved_0[0x10]; 2855 2856 u8 reserved_1[0x10]; 2857 u8 op_mod[0x10]; 2858 2859 u8 reserved_2[0x8]; 2860 u8 qpn[0x18]; 2861 2862 u8 reserved_3[0x20]; 2863 2864 u8 opt_param_mask[0x20]; 2865 2866 u8 reserved_4[0x20]; 2867 2868 struct mlx5_ifc_qpc_bits qpc; 2869 2870 u8 reserved_5[0x80]; 2871 }; 2872 2873 struct mlx5_ifc_rst2init_qp_out_bits { 2874 u8 status[0x8]; 2875 u8 reserved_0[0x18]; 2876 2877 u8 syndrome[0x20]; 2878 2879 u8 reserved_1[0x40]; 2880 }; 2881 2882 struct mlx5_ifc_rst2init_qp_in_bits { 2883 u8 opcode[0x10]; 2884 u8 reserved_0[0x10]; 2885 2886 u8 reserved_1[0x10]; 2887 u8 op_mod[0x10]; 2888 2889 u8 reserved_2[0x8]; 2890 u8 qpn[0x18]; 2891 2892 u8 reserved_3[0x20]; 2893 2894 u8 opt_param_mask[0x20]; 2895 2896 u8 reserved_4[0x20]; 2897 2898 struct mlx5_ifc_qpc_bits qpc; 2899 2900 u8 reserved_5[0x80]; 2901 }; 2902 2903 struct mlx5_ifc_query_xrc_srq_out_bits { 2904 u8 status[0x8]; 2905 u8 reserved_0[0x18]; 2906 2907 u8 syndrome[0x20]; 2908 2909 u8 reserved_1[0x40]; 2910 2911 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 2912 2913 u8 reserved_2[0x600]; 2914 2915 u8 pas[0][0x40]; 2916 }; 2917 2918 struct mlx5_ifc_query_xrc_srq_in_bits { 2919 u8 opcode[0x10]; 2920 u8 reserved_0[0x10]; 2921 2922 u8 reserved_1[0x10]; 2923 u8 op_mod[0x10]; 2924 2925 u8 reserved_2[0x8]; 2926 u8 xrc_srqn[0x18]; 2927 2928 u8 reserved_3[0x20]; 2929 }; 2930 2931 enum { 2932 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 2933 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 2934 }; 2935 2936 struct mlx5_ifc_query_vport_state_out_bits { 2937 u8 status[0x8]; 2938 u8 reserved_0[0x18]; 2939 2940 u8 syndrome[0x20]; 2941 2942 u8 reserved_1[0x20]; 2943 2944 u8 reserved_2[0x18]; 2945 u8 admin_state[0x4]; 2946 u8 state[0x4]; 2947 }; 2948 2949 enum { 2950 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 2951 }; 2952 2953 struct mlx5_ifc_query_vport_state_in_bits { 2954 u8 opcode[0x10]; 2955 u8 reserved_0[0x10]; 2956 2957 u8 reserved_1[0x10]; 2958 u8 op_mod[0x10]; 2959 2960 u8 other_vport[0x1]; 2961 u8 reserved_2[0xf]; 2962 u8 vport_number[0x10]; 2963 2964 u8 reserved_3[0x20]; 2965 }; 2966 2967 struct mlx5_ifc_query_vport_counter_out_bits { 2968 u8 status[0x8]; 2969 u8 reserved_0[0x18]; 2970 2971 u8 syndrome[0x20]; 2972 2973 u8 reserved_1[0x40]; 2974 2975 struct mlx5_ifc_traffic_counter_bits received_errors; 2976 2977 struct mlx5_ifc_traffic_counter_bits transmit_errors; 2978 2979 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 2980 2981 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 2982 2983 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 2984 2985 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 2986 2987 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 2988 2989 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 2990 2991 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 2992 2993 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 2994 2995 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 2996 2997 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 2998 2999 u8 reserved_2[0xa00]; 3000 }; 3001 3002 enum { 3003 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3004 }; 3005 3006 struct mlx5_ifc_query_vport_counter_in_bits { 3007 u8 opcode[0x10]; 3008 u8 reserved_0[0x10]; 3009 3010 u8 reserved_1[0x10]; 3011 u8 op_mod[0x10]; 3012 3013 u8 other_vport[0x1]; 3014 u8 reserved_2[0xf]; 3015 u8 vport_number[0x10]; 3016 3017 u8 reserved_3[0x60]; 3018 3019 u8 clear[0x1]; 3020 u8 reserved_4[0x1f]; 3021 3022 u8 reserved_5[0x20]; 3023 }; 3024 3025 struct mlx5_ifc_query_tis_out_bits { 3026 u8 status[0x8]; 3027 u8 reserved_0[0x18]; 3028 3029 u8 syndrome[0x20]; 3030 3031 u8 reserved_1[0x40]; 3032 3033 struct mlx5_ifc_tisc_bits tis_context; 3034 }; 3035 3036 struct mlx5_ifc_query_tis_in_bits { 3037 u8 opcode[0x10]; 3038 u8 reserved_0[0x10]; 3039 3040 u8 reserved_1[0x10]; 3041 u8 op_mod[0x10]; 3042 3043 u8 reserved_2[0x8]; 3044 u8 tisn[0x18]; 3045 3046 u8 reserved_3[0x20]; 3047 }; 3048 3049 struct mlx5_ifc_query_tir_out_bits { 3050 u8 status[0x8]; 3051 u8 reserved_0[0x18]; 3052 3053 u8 syndrome[0x20]; 3054 3055 u8 reserved_1[0xc0]; 3056 3057 struct mlx5_ifc_tirc_bits tir_context; 3058 }; 3059 3060 struct mlx5_ifc_query_tir_in_bits { 3061 u8 opcode[0x10]; 3062 u8 reserved_0[0x10]; 3063 3064 u8 reserved_1[0x10]; 3065 u8 op_mod[0x10]; 3066 3067 u8 reserved_2[0x8]; 3068 u8 tirn[0x18]; 3069 3070 u8 reserved_3[0x20]; 3071 }; 3072 3073 struct mlx5_ifc_query_srq_out_bits { 3074 u8 status[0x8]; 3075 u8 reserved_0[0x18]; 3076 3077 u8 syndrome[0x20]; 3078 3079 u8 reserved_1[0x40]; 3080 3081 struct mlx5_ifc_srqc_bits srq_context_entry; 3082 3083 u8 reserved_2[0x600]; 3084 3085 u8 pas[0][0x40]; 3086 }; 3087 3088 struct mlx5_ifc_query_srq_in_bits { 3089 u8 opcode[0x10]; 3090 u8 reserved_0[0x10]; 3091 3092 u8 reserved_1[0x10]; 3093 u8 op_mod[0x10]; 3094 3095 u8 reserved_2[0x8]; 3096 u8 srqn[0x18]; 3097 3098 u8 reserved_3[0x20]; 3099 }; 3100 3101 struct mlx5_ifc_query_sq_out_bits { 3102 u8 status[0x8]; 3103 u8 reserved_0[0x18]; 3104 3105 u8 syndrome[0x20]; 3106 3107 u8 reserved_1[0xc0]; 3108 3109 struct mlx5_ifc_sqc_bits sq_context; 3110 }; 3111 3112 struct mlx5_ifc_query_sq_in_bits { 3113 u8 opcode[0x10]; 3114 u8 reserved_0[0x10]; 3115 3116 u8 reserved_1[0x10]; 3117 u8 op_mod[0x10]; 3118 3119 u8 reserved_2[0x8]; 3120 u8 sqn[0x18]; 3121 3122 u8 reserved_3[0x20]; 3123 }; 3124 3125 struct mlx5_ifc_query_special_contexts_out_bits { 3126 u8 status[0x8]; 3127 u8 reserved_0[0x18]; 3128 3129 u8 syndrome[0x20]; 3130 3131 u8 reserved_1[0x20]; 3132 3133 u8 resd_lkey[0x20]; 3134 }; 3135 3136 struct mlx5_ifc_query_special_contexts_in_bits { 3137 u8 opcode[0x10]; 3138 u8 reserved_0[0x10]; 3139 3140 u8 reserved_1[0x10]; 3141 u8 op_mod[0x10]; 3142 3143 u8 reserved_2[0x40]; 3144 }; 3145 3146 struct mlx5_ifc_query_rqt_out_bits { 3147 u8 status[0x8]; 3148 u8 reserved_0[0x18]; 3149 3150 u8 syndrome[0x20]; 3151 3152 u8 reserved_1[0xc0]; 3153 3154 struct mlx5_ifc_rqtc_bits rqt_context; 3155 }; 3156 3157 struct mlx5_ifc_query_rqt_in_bits { 3158 u8 opcode[0x10]; 3159 u8 reserved_0[0x10]; 3160 3161 u8 reserved_1[0x10]; 3162 u8 op_mod[0x10]; 3163 3164 u8 reserved_2[0x8]; 3165 u8 rqtn[0x18]; 3166 3167 u8 reserved_3[0x20]; 3168 }; 3169 3170 struct mlx5_ifc_query_rq_out_bits { 3171 u8 status[0x8]; 3172 u8 reserved_0[0x18]; 3173 3174 u8 syndrome[0x20]; 3175 3176 u8 reserved_1[0xc0]; 3177 3178 struct mlx5_ifc_rqc_bits rq_context; 3179 }; 3180 3181 struct mlx5_ifc_query_rq_in_bits { 3182 u8 opcode[0x10]; 3183 u8 reserved_0[0x10]; 3184 3185 u8 reserved_1[0x10]; 3186 u8 op_mod[0x10]; 3187 3188 u8 reserved_2[0x8]; 3189 u8 rqn[0x18]; 3190 3191 u8 reserved_3[0x20]; 3192 }; 3193 3194 struct mlx5_ifc_query_roce_address_out_bits { 3195 u8 status[0x8]; 3196 u8 reserved_0[0x18]; 3197 3198 u8 syndrome[0x20]; 3199 3200 u8 reserved_1[0x40]; 3201 3202 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3203 }; 3204 3205 struct mlx5_ifc_query_roce_address_in_bits { 3206 u8 opcode[0x10]; 3207 u8 reserved_0[0x10]; 3208 3209 u8 reserved_1[0x10]; 3210 u8 op_mod[0x10]; 3211 3212 u8 roce_address_index[0x10]; 3213 u8 reserved_2[0x10]; 3214 3215 u8 reserved_3[0x20]; 3216 }; 3217 3218 struct mlx5_ifc_query_rmp_out_bits { 3219 u8 status[0x8]; 3220 u8 reserved_0[0x18]; 3221 3222 u8 syndrome[0x20]; 3223 3224 u8 reserved_1[0xc0]; 3225 3226 struct mlx5_ifc_rmpc_bits rmp_context; 3227 }; 3228 3229 struct mlx5_ifc_query_rmp_in_bits { 3230 u8 opcode[0x10]; 3231 u8 reserved_0[0x10]; 3232 3233 u8 reserved_1[0x10]; 3234 u8 op_mod[0x10]; 3235 3236 u8 reserved_2[0x8]; 3237 u8 rmpn[0x18]; 3238 3239 u8 reserved_3[0x20]; 3240 }; 3241 3242 struct mlx5_ifc_query_qp_out_bits { 3243 u8 status[0x8]; 3244 u8 reserved_0[0x18]; 3245 3246 u8 syndrome[0x20]; 3247 3248 u8 reserved_1[0x40]; 3249 3250 u8 opt_param_mask[0x20]; 3251 3252 u8 reserved_2[0x20]; 3253 3254 struct mlx5_ifc_qpc_bits qpc; 3255 3256 u8 reserved_3[0x80]; 3257 3258 u8 pas[0][0x40]; 3259 }; 3260 3261 struct mlx5_ifc_query_qp_in_bits { 3262 u8 opcode[0x10]; 3263 u8 reserved_0[0x10]; 3264 3265 u8 reserved_1[0x10]; 3266 u8 op_mod[0x10]; 3267 3268 u8 reserved_2[0x8]; 3269 u8 qpn[0x18]; 3270 3271 u8 reserved_3[0x20]; 3272 }; 3273 3274 struct mlx5_ifc_query_q_counter_out_bits { 3275 u8 status[0x8]; 3276 u8 reserved_0[0x18]; 3277 3278 u8 syndrome[0x20]; 3279 3280 u8 reserved_1[0x40]; 3281 3282 u8 rx_write_requests[0x20]; 3283 3284 u8 reserved_2[0x20]; 3285 3286 u8 rx_read_requests[0x20]; 3287 3288 u8 reserved_3[0x20]; 3289 3290 u8 rx_atomic_requests[0x20]; 3291 3292 u8 reserved_4[0x20]; 3293 3294 u8 rx_dct_connect[0x20]; 3295 3296 u8 reserved_5[0x20]; 3297 3298 u8 out_of_buffer[0x20]; 3299 3300 u8 reserved_6[0x20]; 3301 3302 u8 out_of_sequence[0x20]; 3303 3304 u8 reserved_7[0x620]; 3305 }; 3306 3307 struct mlx5_ifc_query_q_counter_in_bits { 3308 u8 opcode[0x10]; 3309 u8 reserved_0[0x10]; 3310 3311 u8 reserved_1[0x10]; 3312 u8 op_mod[0x10]; 3313 3314 u8 reserved_2[0x80]; 3315 3316 u8 clear[0x1]; 3317 u8 reserved_3[0x1f]; 3318 3319 u8 reserved_4[0x18]; 3320 u8 counter_set_id[0x8]; 3321 }; 3322 3323 struct mlx5_ifc_query_pages_out_bits { 3324 u8 status[0x8]; 3325 u8 reserved_0[0x18]; 3326 3327 u8 syndrome[0x20]; 3328 3329 u8 reserved_1[0x10]; 3330 u8 function_id[0x10]; 3331 3332 u8 num_pages[0x20]; 3333 }; 3334 3335 enum { 3336 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 3337 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 3338 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 3339 }; 3340 3341 struct mlx5_ifc_query_pages_in_bits { 3342 u8 opcode[0x10]; 3343 u8 reserved_0[0x10]; 3344 3345 u8 reserved_1[0x10]; 3346 u8 op_mod[0x10]; 3347 3348 u8 reserved_2[0x10]; 3349 u8 function_id[0x10]; 3350 3351 u8 reserved_3[0x20]; 3352 }; 3353 3354 struct mlx5_ifc_query_nic_vport_context_out_bits { 3355 u8 status[0x8]; 3356 u8 reserved_0[0x18]; 3357 3358 u8 syndrome[0x20]; 3359 3360 u8 reserved_1[0x40]; 3361 3362 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 3363 }; 3364 3365 struct mlx5_ifc_query_nic_vport_context_in_bits { 3366 u8 opcode[0x10]; 3367 u8 reserved_0[0x10]; 3368 3369 u8 reserved_1[0x10]; 3370 u8 op_mod[0x10]; 3371 3372 u8 other_vport[0x1]; 3373 u8 reserved_2[0xf]; 3374 u8 vport_number[0x10]; 3375 3376 u8 reserved_3[0x5]; 3377 u8 allowed_list_type[0x3]; 3378 u8 reserved_4[0x18]; 3379 }; 3380 3381 struct mlx5_ifc_query_mkey_out_bits { 3382 u8 status[0x8]; 3383 u8 reserved_0[0x18]; 3384 3385 u8 syndrome[0x20]; 3386 3387 u8 reserved_1[0x40]; 3388 3389 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 3390 3391 u8 reserved_2[0x600]; 3392 3393 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 3394 3395 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 3396 }; 3397 3398 struct mlx5_ifc_query_mkey_in_bits { 3399 u8 opcode[0x10]; 3400 u8 reserved_0[0x10]; 3401 3402 u8 reserved_1[0x10]; 3403 u8 op_mod[0x10]; 3404 3405 u8 reserved_2[0x8]; 3406 u8 mkey_index[0x18]; 3407 3408 u8 pg_access[0x1]; 3409 u8 reserved_3[0x1f]; 3410 }; 3411 3412 struct mlx5_ifc_query_mad_demux_out_bits { 3413 u8 status[0x8]; 3414 u8 reserved_0[0x18]; 3415 3416 u8 syndrome[0x20]; 3417 3418 u8 reserved_1[0x40]; 3419 3420 u8 mad_dumux_parameters_block[0x20]; 3421 }; 3422 3423 struct mlx5_ifc_query_mad_demux_in_bits { 3424 u8 opcode[0x10]; 3425 u8 reserved_0[0x10]; 3426 3427 u8 reserved_1[0x10]; 3428 u8 op_mod[0x10]; 3429 3430 u8 reserved_2[0x40]; 3431 }; 3432 3433 struct mlx5_ifc_query_l2_table_entry_out_bits { 3434 u8 status[0x8]; 3435 u8 reserved_0[0x18]; 3436 3437 u8 syndrome[0x20]; 3438 3439 u8 reserved_1[0xa0]; 3440 3441 u8 reserved_2[0x13]; 3442 u8 vlan_valid[0x1]; 3443 u8 vlan[0xc]; 3444 3445 struct mlx5_ifc_mac_address_layout_bits mac_address; 3446 3447 u8 reserved_3[0xc0]; 3448 }; 3449 3450 struct mlx5_ifc_query_l2_table_entry_in_bits { 3451 u8 opcode[0x10]; 3452 u8 reserved_0[0x10]; 3453 3454 u8 reserved_1[0x10]; 3455 u8 op_mod[0x10]; 3456 3457 u8 reserved_2[0x60]; 3458 3459 u8 reserved_3[0x8]; 3460 u8 table_index[0x18]; 3461 3462 u8 reserved_4[0x140]; 3463 }; 3464 3465 struct mlx5_ifc_query_issi_out_bits { 3466 u8 status[0x8]; 3467 u8 reserved_0[0x18]; 3468 3469 u8 syndrome[0x20]; 3470 3471 u8 reserved_1[0x10]; 3472 u8 current_issi[0x10]; 3473 3474 u8 reserved_2[0xa0]; 3475 3476 u8 supported_issi_reserved[76][0x8]; 3477 u8 supported_issi_dw0[0x20]; 3478 }; 3479 3480 struct mlx5_ifc_query_issi_in_bits { 3481 u8 opcode[0x10]; 3482 u8 reserved_0[0x10]; 3483 3484 u8 reserved_1[0x10]; 3485 u8 op_mod[0x10]; 3486 3487 u8 reserved_2[0x40]; 3488 }; 3489 3490 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 3491 u8 status[0x8]; 3492 u8 reserved_0[0x18]; 3493 3494 u8 syndrome[0x20]; 3495 3496 u8 reserved_1[0x40]; 3497 3498 struct mlx5_ifc_pkey_bits pkey[0]; 3499 }; 3500 3501 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 3502 u8 opcode[0x10]; 3503 u8 reserved_0[0x10]; 3504 3505 u8 reserved_1[0x10]; 3506 u8 op_mod[0x10]; 3507 3508 u8 other_vport[0x1]; 3509 u8 reserved_2[0xb]; 3510 u8 port_num[0x4]; 3511 u8 vport_number[0x10]; 3512 3513 u8 reserved_3[0x10]; 3514 u8 pkey_index[0x10]; 3515 }; 3516 3517 struct mlx5_ifc_query_hca_vport_gid_out_bits { 3518 u8 status[0x8]; 3519 u8 reserved_0[0x18]; 3520 3521 u8 syndrome[0x20]; 3522 3523 u8 reserved_1[0x20]; 3524 3525 u8 gids_num[0x10]; 3526 u8 reserved_2[0x10]; 3527 3528 struct mlx5_ifc_array128_auto_bits gid[0]; 3529 }; 3530 3531 struct mlx5_ifc_query_hca_vport_gid_in_bits { 3532 u8 opcode[0x10]; 3533 u8 reserved_0[0x10]; 3534 3535 u8 reserved_1[0x10]; 3536 u8 op_mod[0x10]; 3537 3538 u8 other_vport[0x1]; 3539 u8 reserved_2[0xb]; 3540 u8 port_num[0x4]; 3541 u8 vport_number[0x10]; 3542 3543 u8 reserved_3[0x10]; 3544 u8 gid_index[0x10]; 3545 }; 3546 3547 struct mlx5_ifc_query_hca_vport_context_out_bits { 3548 u8 status[0x8]; 3549 u8 reserved_0[0x18]; 3550 3551 u8 syndrome[0x20]; 3552 3553 u8 reserved_1[0x40]; 3554 3555 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 3556 }; 3557 3558 struct mlx5_ifc_query_hca_vport_context_in_bits { 3559 u8 opcode[0x10]; 3560 u8 reserved_0[0x10]; 3561 3562 u8 reserved_1[0x10]; 3563 u8 op_mod[0x10]; 3564 3565 u8 other_vport[0x1]; 3566 u8 reserved_2[0xb]; 3567 u8 port_num[0x4]; 3568 u8 vport_number[0x10]; 3569 3570 u8 reserved_3[0x20]; 3571 }; 3572 3573 struct mlx5_ifc_query_hca_cap_out_bits { 3574 u8 status[0x8]; 3575 u8 reserved_0[0x18]; 3576 3577 u8 syndrome[0x20]; 3578 3579 u8 reserved_1[0x40]; 3580 3581 union mlx5_ifc_hca_cap_union_bits capability; 3582 }; 3583 3584 struct mlx5_ifc_query_hca_cap_in_bits { 3585 u8 opcode[0x10]; 3586 u8 reserved_0[0x10]; 3587 3588 u8 reserved_1[0x10]; 3589 u8 op_mod[0x10]; 3590 3591 u8 reserved_2[0x40]; 3592 }; 3593 3594 struct mlx5_ifc_query_flow_table_out_bits { 3595 u8 status[0x8]; 3596 u8 reserved_0[0x18]; 3597 3598 u8 syndrome[0x20]; 3599 3600 u8 reserved_1[0x80]; 3601 3602 u8 reserved_2[0x8]; 3603 u8 level[0x8]; 3604 u8 reserved_3[0x8]; 3605 u8 log_size[0x8]; 3606 3607 u8 reserved_4[0x120]; 3608 }; 3609 3610 struct mlx5_ifc_query_flow_table_in_bits { 3611 u8 opcode[0x10]; 3612 u8 reserved_0[0x10]; 3613 3614 u8 reserved_1[0x10]; 3615 u8 op_mod[0x10]; 3616 3617 u8 reserved_2[0x40]; 3618 3619 u8 table_type[0x8]; 3620 u8 reserved_3[0x18]; 3621 3622 u8 reserved_4[0x8]; 3623 u8 table_id[0x18]; 3624 3625 u8 reserved_5[0x140]; 3626 }; 3627 3628 struct mlx5_ifc_query_fte_out_bits { 3629 u8 status[0x8]; 3630 u8 reserved_0[0x18]; 3631 3632 u8 syndrome[0x20]; 3633 3634 u8 reserved_1[0x1c0]; 3635 3636 struct mlx5_ifc_flow_context_bits flow_context; 3637 }; 3638 3639 struct mlx5_ifc_query_fte_in_bits { 3640 u8 opcode[0x10]; 3641 u8 reserved_0[0x10]; 3642 3643 u8 reserved_1[0x10]; 3644 u8 op_mod[0x10]; 3645 3646 u8 reserved_2[0x40]; 3647 3648 u8 table_type[0x8]; 3649 u8 reserved_3[0x18]; 3650 3651 u8 reserved_4[0x8]; 3652 u8 table_id[0x18]; 3653 3654 u8 reserved_5[0x40]; 3655 3656 u8 flow_index[0x20]; 3657 3658 u8 reserved_6[0xe0]; 3659 }; 3660 3661 enum { 3662 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 3663 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 3664 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 3665 }; 3666 3667 struct mlx5_ifc_query_flow_group_out_bits { 3668 u8 status[0x8]; 3669 u8 reserved_0[0x18]; 3670 3671 u8 syndrome[0x20]; 3672 3673 u8 reserved_1[0xa0]; 3674 3675 u8 start_flow_index[0x20]; 3676 3677 u8 reserved_2[0x20]; 3678 3679 u8 end_flow_index[0x20]; 3680 3681 u8 reserved_3[0xa0]; 3682 3683 u8 reserved_4[0x18]; 3684 u8 match_criteria_enable[0x8]; 3685 3686 struct mlx5_ifc_fte_match_param_bits match_criteria; 3687 3688 u8 reserved_5[0xe00]; 3689 }; 3690 3691 struct mlx5_ifc_query_flow_group_in_bits { 3692 u8 opcode[0x10]; 3693 u8 reserved_0[0x10]; 3694 3695 u8 reserved_1[0x10]; 3696 u8 op_mod[0x10]; 3697 3698 u8 reserved_2[0x40]; 3699 3700 u8 table_type[0x8]; 3701 u8 reserved_3[0x18]; 3702 3703 u8 reserved_4[0x8]; 3704 u8 table_id[0x18]; 3705 3706 u8 group_id[0x20]; 3707 3708 u8 reserved_5[0x120]; 3709 }; 3710 3711 struct mlx5_ifc_query_eq_out_bits { 3712 u8 status[0x8]; 3713 u8 reserved_0[0x18]; 3714 3715 u8 syndrome[0x20]; 3716 3717 u8 reserved_1[0x40]; 3718 3719 struct mlx5_ifc_eqc_bits eq_context_entry; 3720 3721 u8 reserved_2[0x40]; 3722 3723 u8 event_bitmask[0x40]; 3724 3725 u8 reserved_3[0x580]; 3726 3727 u8 pas[0][0x40]; 3728 }; 3729 3730 struct mlx5_ifc_query_eq_in_bits { 3731 u8 opcode[0x10]; 3732 u8 reserved_0[0x10]; 3733 3734 u8 reserved_1[0x10]; 3735 u8 op_mod[0x10]; 3736 3737 u8 reserved_2[0x18]; 3738 u8 eq_number[0x8]; 3739 3740 u8 reserved_3[0x20]; 3741 }; 3742 3743 struct mlx5_ifc_query_dct_out_bits { 3744 u8 status[0x8]; 3745 u8 reserved_0[0x18]; 3746 3747 u8 syndrome[0x20]; 3748 3749 u8 reserved_1[0x40]; 3750 3751 struct mlx5_ifc_dctc_bits dct_context_entry; 3752 3753 u8 reserved_2[0x180]; 3754 }; 3755 3756 struct mlx5_ifc_query_dct_in_bits { 3757 u8 opcode[0x10]; 3758 u8 reserved_0[0x10]; 3759 3760 u8 reserved_1[0x10]; 3761 u8 op_mod[0x10]; 3762 3763 u8 reserved_2[0x8]; 3764 u8 dctn[0x18]; 3765 3766 u8 reserved_3[0x20]; 3767 }; 3768 3769 struct mlx5_ifc_query_cq_out_bits { 3770 u8 status[0x8]; 3771 u8 reserved_0[0x18]; 3772 3773 u8 syndrome[0x20]; 3774 3775 u8 reserved_1[0x40]; 3776 3777 struct mlx5_ifc_cqc_bits cq_context; 3778 3779 u8 reserved_2[0x600]; 3780 3781 u8 pas[0][0x40]; 3782 }; 3783 3784 struct mlx5_ifc_query_cq_in_bits { 3785 u8 opcode[0x10]; 3786 u8 reserved_0[0x10]; 3787 3788 u8 reserved_1[0x10]; 3789 u8 op_mod[0x10]; 3790 3791 u8 reserved_2[0x8]; 3792 u8 cqn[0x18]; 3793 3794 u8 reserved_3[0x20]; 3795 }; 3796 3797 struct mlx5_ifc_query_cong_status_out_bits { 3798 u8 status[0x8]; 3799 u8 reserved_0[0x18]; 3800 3801 u8 syndrome[0x20]; 3802 3803 u8 reserved_1[0x20]; 3804 3805 u8 enable[0x1]; 3806 u8 tag_enable[0x1]; 3807 u8 reserved_2[0x1e]; 3808 }; 3809 3810 struct mlx5_ifc_query_cong_status_in_bits { 3811 u8 opcode[0x10]; 3812 u8 reserved_0[0x10]; 3813 3814 u8 reserved_1[0x10]; 3815 u8 op_mod[0x10]; 3816 3817 u8 reserved_2[0x18]; 3818 u8 priority[0x4]; 3819 u8 cong_protocol[0x4]; 3820 3821 u8 reserved_3[0x20]; 3822 }; 3823 3824 struct mlx5_ifc_query_cong_statistics_out_bits { 3825 u8 status[0x8]; 3826 u8 reserved_0[0x18]; 3827 3828 u8 syndrome[0x20]; 3829 3830 u8 reserved_1[0x40]; 3831 3832 u8 cur_flows[0x20]; 3833 3834 u8 sum_flows[0x20]; 3835 3836 u8 cnp_ignored_high[0x20]; 3837 3838 u8 cnp_ignored_low[0x20]; 3839 3840 u8 cnp_handled_high[0x20]; 3841 3842 u8 cnp_handled_low[0x20]; 3843 3844 u8 reserved_2[0x100]; 3845 3846 u8 time_stamp_high[0x20]; 3847 3848 u8 time_stamp_low[0x20]; 3849 3850 u8 accumulators_period[0x20]; 3851 3852 u8 ecn_marked_roce_packets_high[0x20]; 3853 3854 u8 ecn_marked_roce_packets_low[0x20]; 3855 3856 u8 cnps_sent_high[0x20]; 3857 3858 u8 cnps_sent_low[0x20]; 3859 3860 u8 reserved_3[0x560]; 3861 }; 3862 3863 struct mlx5_ifc_query_cong_statistics_in_bits { 3864 u8 opcode[0x10]; 3865 u8 reserved_0[0x10]; 3866 3867 u8 reserved_1[0x10]; 3868 u8 op_mod[0x10]; 3869 3870 u8 clear[0x1]; 3871 u8 reserved_2[0x1f]; 3872 3873 u8 reserved_3[0x20]; 3874 }; 3875 3876 struct mlx5_ifc_query_cong_params_out_bits { 3877 u8 status[0x8]; 3878 u8 reserved_0[0x18]; 3879 3880 u8 syndrome[0x20]; 3881 3882 u8 reserved_1[0x40]; 3883 3884 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 3885 }; 3886 3887 struct mlx5_ifc_query_cong_params_in_bits { 3888 u8 opcode[0x10]; 3889 u8 reserved_0[0x10]; 3890 3891 u8 reserved_1[0x10]; 3892 u8 op_mod[0x10]; 3893 3894 u8 reserved_2[0x1c]; 3895 u8 cong_protocol[0x4]; 3896 3897 u8 reserved_3[0x20]; 3898 }; 3899 3900 struct mlx5_ifc_query_adapter_out_bits { 3901 u8 status[0x8]; 3902 u8 reserved_0[0x18]; 3903 3904 u8 syndrome[0x20]; 3905 3906 u8 reserved_1[0x40]; 3907 3908 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 3909 }; 3910 3911 struct mlx5_ifc_query_adapter_in_bits { 3912 u8 opcode[0x10]; 3913 u8 reserved_0[0x10]; 3914 3915 u8 reserved_1[0x10]; 3916 u8 op_mod[0x10]; 3917 3918 u8 reserved_2[0x40]; 3919 }; 3920 3921 struct mlx5_ifc_qp_2rst_out_bits { 3922 u8 status[0x8]; 3923 u8 reserved_0[0x18]; 3924 3925 u8 syndrome[0x20]; 3926 3927 u8 reserved_1[0x40]; 3928 }; 3929 3930 struct mlx5_ifc_qp_2rst_in_bits { 3931 u8 opcode[0x10]; 3932 u8 reserved_0[0x10]; 3933 3934 u8 reserved_1[0x10]; 3935 u8 op_mod[0x10]; 3936 3937 u8 reserved_2[0x8]; 3938 u8 qpn[0x18]; 3939 3940 u8 reserved_3[0x20]; 3941 }; 3942 3943 struct mlx5_ifc_qp_2err_out_bits { 3944 u8 status[0x8]; 3945 u8 reserved_0[0x18]; 3946 3947 u8 syndrome[0x20]; 3948 3949 u8 reserved_1[0x40]; 3950 }; 3951 3952 struct mlx5_ifc_qp_2err_in_bits { 3953 u8 opcode[0x10]; 3954 u8 reserved_0[0x10]; 3955 3956 u8 reserved_1[0x10]; 3957 u8 op_mod[0x10]; 3958 3959 u8 reserved_2[0x8]; 3960 u8 qpn[0x18]; 3961 3962 u8 reserved_3[0x20]; 3963 }; 3964 3965 struct mlx5_ifc_page_fault_resume_out_bits { 3966 u8 status[0x8]; 3967 u8 reserved_0[0x18]; 3968 3969 u8 syndrome[0x20]; 3970 3971 u8 reserved_1[0x40]; 3972 }; 3973 3974 struct mlx5_ifc_page_fault_resume_in_bits { 3975 u8 opcode[0x10]; 3976 u8 reserved_0[0x10]; 3977 3978 u8 reserved_1[0x10]; 3979 u8 op_mod[0x10]; 3980 3981 u8 error[0x1]; 3982 u8 reserved_2[0x4]; 3983 u8 rdma[0x1]; 3984 u8 read_write[0x1]; 3985 u8 req_res[0x1]; 3986 u8 qpn[0x18]; 3987 3988 u8 reserved_3[0x20]; 3989 }; 3990 3991 struct mlx5_ifc_nop_out_bits { 3992 u8 status[0x8]; 3993 u8 reserved_0[0x18]; 3994 3995 u8 syndrome[0x20]; 3996 3997 u8 reserved_1[0x40]; 3998 }; 3999 4000 struct mlx5_ifc_nop_in_bits { 4001 u8 opcode[0x10]; 4002 u8 reserved_0[0x10]; 4003 4004 u8 reserved_1[0x10]; 4005 u8 op_mod[0x10]; 4006 4007 u8 reserved_2[0x40]; 4008 }; 4009 4010 struct mlx5_ifc_modify_vport_state_out_bits { 4011 u8 status[0x8]; 4012 u8 reserved_0[0x18]; 4013 4014 u8 syndrome[0x20]; 4015 4016 u8 reserved_1[0x40]; 4017 }; 4018 4019 struct mlx5_ifc_modify_vport_state_in_bits { 4020 u8 opcode[0x10]; 4021 u8 reserved_0[0x10]; 4022 4023 u8 reserved_1[0x10]; 4024 u8 op_mod[0x10]; 4025 4026 u8 other_vport[0x1]; 4027 u8 reserved_2[0xf]; 4028 u8 vport_number[0x10]; 4029 4030 u8 reserved_3[0x18]; 4031 u8 admin_state[0x4]; 4032 u8 reserved_4[0x4]; 4033 }; 4034 4035 struct mlx5_ifc_modify_tis_out_bits { 4036 u8 status[0x8]; 4037 u8 reserved_0[0x18]; 4038 4039 u8 syndrome[0x20]; 4040 4041 u8 reserved_1[0x40]; 4042 }; 4043 4044 struct mlx5_ifc_modify_tis_in_bits { 4045 u8 opcode[0x10]; 4046 u8 reserved_0[0x10]; 4047 4048 u8 reserved_1[0x10]; 4049 u8 op_mod[0x10]; 4050 4051 u8 reserved_2[0x8]; 4052 u8 tisn[0x18]; 4053 4054 u8 reserved_3[0x20]; 4055 4056 u8 modify_bitmask[0x40]; 4057 4058 u8 reserved_4[0x40]; 4059 4060 struct mlx5_ifc_tisc_bits ctx; 4061 }; 4062 4063 struct mlx5_ifc_modify_tir_bitmask_bits { 4064 u8 reserved_0[0x20]; 4065 4066 u8 reserved_1[0x1b]; 4067 u8 self_lb_en[0x1]; 4068 u8 reserved_2[0x3]; 4069 u8 lro[0x1]; 4070 }; 4071 4072 struct mlx5_ifc_modify_tir_out_bits { 4073 u8 status[0x8]; 4074 u8 reserved_0[0x18]; 4075 4076 u8 syndrome[0x20]; 4077 4078 u8 reserved_1[0x40]; 4079 }; 4080 4081 struct mlx5_ifc_modify_tir_in_bits { 4082 u8 opcode[0x10]; 4083 u8 reserved_0[0x10]; 4084 4085 u8 reserved_1[0x10]; 4086 u8 op_mod[0x10]; 4087 4088 u8 reserved_2[0x8]; 4089 u8 tirn[0x18]; 4090 4091 u8 reserved_3[0x20]; 4092 4093 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 4094 4095 u8 reserved_4[0x40]; 4096 4097 struct mlx5_ifc_tirc_bits ctx; 4098 }; 4099 4100 struct mlx5_ifc_modify_sq_out_bits { 4101 u8 status[0x8]; 4102 u8 reserved_0[0x18]; 4103 4104 u8 syndrome[0x20]; 4105 4106 u8 reserved_1[0x40]; 4107 }; 4108 4109 struct mlx5_ifc_modify_sq_in_bits { 4110 u8 opcode[0x10]; 4111 u8 reserved_0[0x10]; 4112 4113 u8 reserved_1[0x10]; 4114 u8 op_mod[0x10]; 4115 4116 u8 sq_state[0x4]; 4117 u8 reserved_2[0x4]; 4118 u8 sqn[0x18]; 4119 4120 u8 reserved_3[0x20]; 4121 4122 u8 modify_bitmask[0x40]; 4123 4124 u8 reserved_4[0x40]; 4125 4126 struct mlx5_ifc_sqc_bits ctx; 4127 }; 4128 4129 struct mlx5_ifc_modify_rqt_out_bits { 4130 u8 status[0x8]; 4131 u8 reserved_0[0x18]; 4132 4133 u8 syndrome[0x20]; 4134 4135 u8 reserved_1[0x40]; 4136 }; 4137 4138 struct mlx5_ifc_rqt_bitmask_bits { 4139 u8 reserved[0x20]; 4140 4141 u8 reserved1[0x1f]; 4142 u8 rqn_list[0x1]; 4143 }; 4144 4145 struct mlx5_ifc_modify_rqt_in_bits { 4146 u8 opcode[0x10]; 4147 u8 reserved_0[0x10]; 4148 4149 u8 reserved_1[0x10]; 4150 u8 op_mod[0x10]; 4151 4152 u8 reserved_2[0x8]; 4153 u8 rqtn[0x18]; 4154 4155 u8 reserved_3[0x20]; 4156 4157 struct mlx5_ifc_rqt_bitmask_bits bitmask; 4158 4159 u8 reserved_4[0x40]; 4160 4161 struct mlx5_ifc_rqtc_bits ctx; 4162 }; 4163 4164 struct mlx5_ifc_modify_rq_out_bits { 4165 u8 status[0x8]; 4166 u8 reserved_0[0x18]; 4167 4168 u8 syndrome[0x20]; 4169 4170 u8 reserved_1[0x40]; 4171 }; 4172 4173 struct mlx5_ifc_modify_rq_in_bits { 4174 u8 opcode[0x10]; 4175 u8 reserved_0[0x10]; 4176 4177 u8 reserved_1[0x10]; 4178 u8 op_mod[0x10]; 4179 4180 u8 rq_state[0x4]; 4181 u8 reserved_2[0x4]; 4182 u8 rqn[0x18]; 4183 4184 u8 reserved_3[0x20]; 4185 4186 u8 modify_bitmask[0x40]; 4187 4188 u8 reserved_4[0x40]; 4189 4190 struct mlx5_ifc_rqc_bits ctx; 4191 }; 4192 4193 struct mlx5_ifc_modify_rmp_out_bits { 4194 u8 status[0x8]; 4195 u8 reserved_0[0x18]; 4196 4197 u8 syndrome[0x20]; 4198 4199 u8 reserved_1[0x40]; 4200 }; 4201 4202 struct mlx5_ifc_rmp_bitmask_bits { 4203 u8 reserved[0x20]; 4204 4205 u8 reserved1[0x1f]; 4206 u8 lwm[0x1]; 4207 }; 4208 4209 struct mlx5_ifc_modify_rmp_in_bits { 4210 u8 opcode[0x10]; 4211 u8 reserved_0[0x10]; 4212 4213 u8 reserved_1[0x10]; 4214 u8 op_mod[0x10]; 4215 4216 u8 rmp_state[0x4]; 4217 u8 reserved_2[0x4]; 4218 u8 rmpn[0x18]; 4219 4220 u8 reserved_3[0x20]; 4221 4222 struct mlx5_ifc_rmp_bitmask_bits bitmask; 4223 4224 u8 reserved_4[0x40]; 4225 4226 struct mlx5_ifc_rmpc_bits ctx; 4227 }; 4228 4229 struct mlx5_ifc_modify_nic_vport_context_out_bits { 4230 u8 status[0x8]; 4231 u8 reserved_0[0x18]; 4232 4233 u8 syndrome[0x20]; 4234 4235 u8 reserved_1[0x40]; 4236 }; 4237 4238 struct mlx5_ifc_modify_nic_vport_field_select_bits { 4239 u8 reserved_0[0x1c]; 4240 u8 permanent_address[0x1]; 4241 u8 addresses_list[0x1]; 4242 u8 roce_en[0x1]; 4243 u8 reserved_1[0x1]; 4244 }; 4245 4246 struct mlx5_ifc_modify_nic_vport_context_in_bits { 4247 u8 opcode[0x10]; 4248 u8 reserved_0[0x10]; 4249 4250 u8 reserved_1[0x10]; 4251 u8 op_mod[0x10]; 4252 4253 u8 other_vport[0x1]; 4254 u8 reserved_2[0xf]; 4255 u8 vport_number[0x10]; 4256 4257 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 4258 4259 u8 reserved_3[0x780]; 4260 4261 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4262 }; 4263 4264 struct mlx5_ifc_modify_hca_vport_context_out_bits { 4265 u8 status[0x8]; 4266 u8 reserved_0[0x18]; 4267 4268 u8 syndrome[0x20]; 4269 4270 u8 reserved_1[0x40]; 4271 }; 4272 4273 struct mlx5_ifc_modify_hca_vport_context_in_bits { 4274 u8 opcode[0x10]; 4275 u8 reserved_0[0x10]; 4276 4277 u8 reserved_1[0x10]; 4278 u8 op_mod[0x10]; 4279 4280 u8 other_vport[0x1]; 4281 u8 reserved_2[0xb]; 4282 u8 port_num[0x4]; 4283 u8 vport_number[0x10]; 4284 4285 u8 reserved_3[0x20]; 4286 4287 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4288 }; 4289 4290 struct mlx5_ifc_modify_cq_out_bits { 4291 u8 status[0x8]; 4292 u8 reserved_0[0x18]; 4293 4294 u8 syndrome[0x20]; 4295 4296 u8 reserved_1[0x40]; 4297 }; 4298 4299 enum { 4300 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 4301 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 4302 }; 4303 4304 struct mlx5_ifc_modify_cq_in_bits { 4305 u8 opcode[0x10]; 4306 u8 reserved_0[0x10]; 4307 4308 u8 reserved_1[0x10]; 4309 u8 op_mod[0x10]; 4310 4311 u8 reserved_2[0x8]; 4312 u8 cqn[0x18]; 4313 4314 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 4315 4316 struct mlx5_ifc_cqc_bits cq_context; 4317 4318 u8 reserved_3[0x600]; 4319 4320 u8 pas[0][0x40]; 4321 }; 4322 4323 struct mlx5_ifc_modify_cong_status_out_bits { 4324 u8 status[0x8]; 4325 u8 reserved_0[0x18]; 4326 4327 u8 syndrome[0x20]; 4328 4329 u8 reserved_1[0x40]; 4330 }; 4331 4332 struct mlx5_ifc_modify_cong_status_in_bits { 4333 u8 opcode[0x10]; 4334 u8 reserved_0[0x10]; 4335 4336 u8 reserved_1[0x10]; 4337 u8 op_mod[0x10]; 4338 4339 u8 reserved_2[0x18]; 4340 u8 priority[0x4]; 4341 u8 cong_protocol[0x4]; 4342 4343 u8 enable[0x1]; 4344 u8 tag_enable[0x1]; 4345 u8 reserved_3[0x1e]; 4346 }; 4347 4348 struct mlx5_ifc_modify_cong_params_out_bits { 4349 u8 status[0x8]; 4350 u8 reserved_0[0x18]; 4351 4352 u8 syndrome[0x20]; 4353 4354 u8 reserved_1[0x40]; 4355 }; 4356 4357 struct mlx5_ifc_modify_cong_params_in_bits { 4358 u8 opcode[0x10]; 4359 u8 reserved_0[0x10]; 4360 4361 u8 reserved_1[0x10]; 4362 u8 op_mod[0x10]; 4363 4364 u8 reserved_2[0x1c]; 4365 u8 cong_protocol[0x4]; 4366 4367 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 4368 4369 u8 reserved_3[0x80]; 4370 4371 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4372 }; 4373 4374 struct mlx5_ifc_manage_pages_out_bits { 4375 u8 status[0x8]; 4376 u8 reserved_0[0x18]; 4377 4378 u8 syndrome[0x20]; 4379 4380 u8 output_num_entries[0x20]; 4381 4382 u8 reserved_1[0x20]; 4383 4384 u8 pas[0][0x40]; 4385 }; 4386 4387 enum { 4388 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 4389 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 4390 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 4391 }; 4392 4393 struct mlx5_ifc_manage_pages_in_bits { 4394 u8 opcode[0x10]; 4395 u8 reserved_0[0x10]; 4396 4397 u8 reserved_1[0x10]; 4398 u8 op_mod[0x10]; 4399 4400 u8 reserved_2[0x10]; 4401 u8 function_id[0x10]; 4402 4403 u8 input_num_entries[0x20]; 4404 4405 u8 pas[0][0x40]; 4406 }; 4407 4408 struct mlx5_ifc_mad_ifc_out_bits { 4409 u8 status[0x8]; 4410 u8 reserved_0[0x18]; 4411 4412 u8 syndrome[0x20]; 4413 4414 u8 reserved_1[0x40]; 4415 4416 u8 response_mad_packet[256][0x8]; 4417 }; 4418 4419 struct mlx5_ifc_mad_ifc_in_bits { 4420 u8 opcode[0x10]; 4421 u8 reserved_0[0x10]; 4422 4423 u8 reserved_1[0x10]; 4424 u8 op_mod[0x10]; 4425 4426 u8 remote_lid[0x10]; 4427 u8 reserved_2[0x8]; 4428 u8 port[0x8]; 4429 4430 u8 reserved_3[0x20]; 4431 4432 u8 mad[256][0x8]; 4433 }; 4434 4435 struct mlx5_ifc_init_hca_out_bits { 4436 u8 status[0x8]; 4437 u8 reserved_0[0x18]; 4438 4439 u8 syndrome[0x20]; 4440 4441 u8 reserved_1[0x40]; 4442 }; 4443 4444 struct mlx5_ifc_init_hca_in_bits { 4445 u8 opcode[0x10]; 4446 u8 reserved_0[0x10]; 4447 4448 u8 reserved_1[0x10]; 4449 u8 op_mod[0x10]; 4450 4451 u8 reserved_2[0x40]; 4452 }; 4453 4454 struct mlx5_ifc_init2rtr_qp_out_bits { 4455 u8 status[0x8]; 4456 u8 reserved_0[0x18]; 4457 4458 u8 syndrome[0x20]; 4459 4460 u8 reserved_1[0x40]; 4461 }; 4462 4463 struct mlx5_ifc_init2rtr_qp_in_bits { 4464 u8 opcode[0x10]; 4465 u8 reserved_0[0x10]; 4466 4467 u8 reserved_1[0x10]; 4468 u8 op_mod[0x10]; 4469 4470 u8 reserved_2[0x8]; 4471 u8 qpn[0x18]; 4472 4473 u8 reserved_3[0x20]; 4474 4475 u8 opt_param_mask[0x20]; 4476 4477 u8 reserved_4[0x20]; 4478 4479 struct mlx5_ifc_qpc_bits qpc; 4480 4481 u8 reserved_5[0x80]; 4482 }; 4483 4484 struct mlx5_ifc_init2init_qp_out_bits { 4485 u8 status[0x8]; 4486 u8 reserved_0[0x18]; 4487 4488 u8 syndrome[0x20]; 4489 4490 u8 reserved_1[0x40]; 4491 }; 4492 4493 struct mlx5_ifc_init2init_qp_in_bits { 4494 u8 opcode[0x10]; 4495 u8 reserved_0[0x10]; 4496 4497 u8 reserved_1[0x10]; 4498 u8 op_mod[0x10]; 4499 4500 u8 reserved_2[0x8]; 4501 u8 qpn[0x18]; 4502 4503 u8 reserved_3[0x20]; 4504 4505 u8 opt_param_mask[0x20]; 4506 4507 u8 reserved_4[0x20]; 4508 4509 struct mlx5_ifc_qpc_bits qpc; 4510 4511 u8 reserved_5[0x80]; 4512 }; 4513 4514 struct mlx5_ifc_get_dropped_packet_log_out_bits { 4515 u8 status[0x8]; 4516 u8 reserved_0[0x18]; 4517 4518 u8 syndrome[0x20]; 4519 4520 u8 reserved_1[0x40]; 4521 4522 u8 packet_headers_log[128][0x8]; 4523 4524 u8 packet_syndrome[64][0x8]; 4525 }; 4526 4527 struct mlx5_ifc_get_dropped_packet_log_in_bits { 4528 u8 opcode[0x10]; 4529 u8 reserved_0[0x10]; 4530 4531 u8 reserved_1[0x10]; 4532 u8 op_mod[0x10]; 4533 4534 u8 reserved_2[0x40]; 4535 }; 4536 4537 struct mlx5_ifc_gen_eqe_in_bits { 4538 u8 opcode[0x10]; 4539 u8 reserved_0[0x10]; 4540 4541 u8 reserved_1[0x10]; 4542 u8 op_mod[0x10]; 4543 4544 u8 reserved_2[0x18]; 4545 u8 eq_number[0x8]; 4546 4547 u8 reserved_3[0x20]; 4548 4549 u8 eqe[64][0x8]; 4550 }; 4551 4552 struct mlx5_ifc_gen_eq_out_bits { 4553 u8 status[0x8]; 4554 u8 reserved_0[0x18]; 4555 4556 u8 syndrome[0x20]; 4557 4558 u8 reserved_1[0x40]; 4559 }; 4560 4561 struct mlx5_ifc_enable_hca_out_bits { 4562 u8 status[0x8]; 4563 u8 reserved_0[0x18]; 4564 4565 u8 syndrome[0x20]; 4566 4567 u8 reserved_1[0x20]; 4568 }; 4569 4570 struct mlx5_ifc_enable_hca_in_bits { 4571 u8 opcode[0x10]; 4572 u8 reserved_0[0x10]; 4573 4574 u8 reserved_1[0x10]; 4575 u8 op_mod[0x10]; 4576 4577 u8 reserved_2[0x10]; 4578 u8 function_id[0x10]; 4579 4580 u8 reserved_3[0x20]; 4581 }; 4582 4583 struct mlx5_ifc_drain_dct_out_bits { 4584 u8 status[0x8]; 4585 u8 reserved_0[0x18]; 4586 4587 u8 syndrome[0x20]; 4588 4589 u8 reserved_1[0x40]; 4590 }; 4591 4592 struct mlx5_ifc_drain_dct_in_bits { 4593 u8 opcode[0x10]; 4594 u8 reserved_0[0x10]; 4595 4596 u8 reserved_1[0x10]; 4597 u8 op_mod[0x10]; 4598 4599 u8 reserved_2[0x8]; 4600 u8 dctn[0x18]; 4601 4602 u8 reserved_3[0x20]; 4603 }; 4604 4605 struct mlx5_ifc_disable_hca_out_bits { 4606 u8 status[0x8]; 4607 u8 reserved_0[0x18]; 4608 4609 u8 syndrome[0x20]; 4610 4611 u8 reserved_1[0x20]; 4612 }; 4613 4614 struct mlx5_ifc_disable_hca_in_bits { 4615 u8 opcode[0x10]; 4616 u8 reserved_0[0x10]; 4617 4618 u8 reserved_1[0x10]; 4619 u8 op_mod[0x10]; 4620 4621 u8 reserved_2[0x10]; 4622 u8 function_id[0x10]; 4623 4624 u8 reserved_3[0x20]; 4625 }; 4626 4627 struct mlx5_ifc_detach_from_mcg_out_bits { 4628 u8 status[0x8]; 4629 u8 reserved_0[0x18]; 4630 4631 u8 syndrome[0x20]; 4632 4633 u8 reserved_1[0x40]; 4634 }; 4635 4636 struct mlx5_ifc_detach_from_mcg_in_bits { 4637 u8 opcode[0x10]; 4638 u8 reserved_0[0x10]; 4639 4640 u8 reserved_1[0x10]; 4641 u8 op_mod[0x10]; 4642 4643 u8 reserved_2[0x8]; 4644 u8 qpn[0x18]; 4645 4646 u8 reserved_3[0x20]; 4647 4648 u8 multicast_gid[16][0x8]; 4649 }; 4650 4651 struct mlx5_ifc_destroy_xrc_srq_out_bits { 4652 u8 status[0x8]; 4653 u8 reserved_0[0x18]; 4654 4655 u8 syndrome[0x20]; 4656 4657 u8 reserved_1[0x40]; 4658 }; 4659 4660 struct mlx5_ifc_destroy_xrc_srq_in_bits { 4661 u8 opcode[0x10]; 4662 u8 reserved_0[0x10]; 4663 4664 u8 reserved_1[0x10]; 4665 u8 op_mod[0x10]; 4666 4667 u8 reserved_2[0x8]; 4668 u8 xrc_srqn[0x18]; 4669 4670 u8 reserved_3[0x20]; 4671 }; 4672 4673 struct mlx5_ifc_destroy_tis_out_bits { 4674 u8 status[0x8]; 4675 u8 reserved_0[0x18]; 4676 4677 u8 syndrome[0x20]; 4678 4679 u8 reserved_1[0x40]; 4680 }; 4681 4682 struct mlx5_ifc_destroy_tis_in_bits { 4683 u8 opcode[0x10]; 4684 u8 reserved_0[0x10]; 4685 4686 u8 reserved_1[0x10]; 4687 u8 op_mod[0x10]; 4688 4689 u8 reserved_2[0x8]; 4690 u8 tisn[0x18]; 4691 4692 u8 reserved_3[0x20]; 4693 }; 4694 4695 struct mlx5_ifc_destroy_tir_out_bits { 4696 u8 status[0x8]; 4697 u8 reserved_0[0x18]; 4698 4699 u8 syndrome[0x20]; 4700 4701 u8 reserved_1[0x40]; 4702 }; 4703 4704 struct mlx5_ifc_destroy_tir_in_bits { 4705 u8 opcode[0x10]; 4706 u8 reserved_0[0x10]; 4707 4708 u8 reserved_1[0x10]; 4709 u8 op_mod[0x10]; 4710 4711 u8 reserved_2[0x8]; 4712 u8 tirn[0x18]; 4713 4714 u8 reserved_3[0x20]; 4715 }; 4716 4717 struct mlx5_ifc_destroy_srq_out_bits { 4718 u8 status[0x8]; 4719 u8 reserved_0[0x18]; 4720 4721 u8 syndrome[0x20]; 4722 4723 u8 reserved_1[0x40]; 4724 }; 4725 4726 struct mlx5_ifc_destroy_srq_in_bits { 4727 u8 opcode[0x10]; 4728 u8 reserved_0[0x10]; 4729 4730 u8 reserved_1[0x10]; 4731 u8 op_mod[0x10]; 4732 4733 u8 reserved_2[0x8]; 4734 u8 srqn[0x18]; 4735 4736 u8 reserved_3[0x20]; 4737 }; 4738 4739 struct mlx5_ifc_destroy_sq_out_bits { 4740 u8 status[0x8]; 4741 u8 reserved_0[0x18]; 4742 4743 u8 syndrome[0x20]; 4744 4745 u8 reserved_1[0x40]; 4746 }; 4747 4748 struct mlx5_ifc_destroy_sq_in_bits { 4749 u8 opcode[0x10]; 4750 u8 reserved_0[0x10]; 4751 4752 u8 reserved_1[0x10]; 4753 u8 op_mod[0x10]; 4754 4755 u8 reserved_2[0x8]; 4756 u8 sqn[0x18]; 4757 4758 u8 reserved_3[0x20]; 4759 }; 4760 4761 struct mlx5_ifc_destroy_rqt_out_bits { 4762 u8 status[0x8]; 4763 u8 reserved_0[0x18]; 4764 4765 u8 syndrome[0x20]; 4766 4767 u8 reserved_1[0x40]; 4768 }; 4769 4770 struct mlx5_ifc_destroy_rqt_in_bits { 4771 u8 opcode[0x10]; 4772 u8 reserved_0[0x10]; 4773 4774 u8 reserved_1[0x10]; 4775 u8 op_mod[0x10]; 4776 4777 u8 reserved_2[0x8]; 4778 u8 rqtn[0x18]; 4779 4780 u8 reserved_3[0x20]; 4781 }; 4782 4783 struct mlx5_ifc_destroy_rq_out_bits { 4784 u8 status[0x8]; 4785 u8 reserved_0[0x18]; 4786 4787 u8 syndrome[0x20]; 4788 4789 u8 reserved_1[0x40]; 4790 }; 4791 4792 struct mlx5_ifc_destroy_rq_in_bits { 4793 u8 opcode[0x10]; 4794 u8 reserved_0[0x10]; 4795 4796 u8 reserved_1[0x10]; 4797 u8 op_mod[0x10]; 4798 4799 u8 reserved_2[0x8]; 4800 u8 rqn[0x18]; 4801 4802 u8 reserved_3[0x20]; 4803 }; 4804 4805 struct mlx5_ifc_destroy_rmp_out_bits { 4806 u8 status[0x8]; 4807 u8 reserved_0[0x18]; 4808 4809 u8 syndrome[0x20]; 4810 4811 u8 reserved_1[0x40]; 4812 }; 4813 4814 struct mlx5_ifc_destroy_rmp_in_bits { 4815 u8 opcode[0x10]; 4816 u8 reserved_0[0x10]; 4817 4818 u8 reserved_1[0x10]; 4819 u8 op_mod[0x10]; 4820 4821 u8 reserved_2[0x8]; 4822 u8 rmpn[0x18]; 4823 4824 u8 reserved_3[0x20]; 4825 }; 4826 4827 struct mlx5_ifc_destroy_qp_out_bits { 4828 u8 status[0x8]; 4829 u8 reserved_0[0x18]; 4830 4831 u8 syndrome[0x20]; 4832 4833 u8 reserved_1[0x40]; 4834 }; 4835 4836 struct mlx5_ifc_destroy_qp_in_bits { 4837 u8 opcode[0x10]; 4838 u8 reserved_0[0x10]; 4839 4840 u8 reserved_1[0x10]; 4841 u8 op_mod[0x10]; 4842 4843 u8 reserved_2[0x8]; 4844 u8 qpn[0x18]; 4845 4846 u8 reserved_3[0x20]; 4847 }; 4848 4849 struct mlx5_ifc_destroy_psv_out_bits { 4850 u8 status[0x8]; 4851 u8 reserved_0[0x18]; 4852 4853 u8 syndrome[0x20]; 4854 4855 u8 reserved_1[0x40]; 4856 }; 4857 4858 struct mlx5_ifc_destroy_psv_in_bits { 4859 u8 opcode[0x10]; 4860 u8 reserved_0[0x10]; 4861 4862 u8 reserved_1[0x10]; 4863 u8 op_mod[0x10]; 4864 4865 u8 reserved_2[0x8]; 4866 u8 psvn[0x18]; 4867 4868 u8 reserved_3[0x20]; 4869 }; 4870 4871 struct mlx5_ifc_destroy_mkey_out_bits { 4872 u8 status[0x8]; 4873 u8 reserved_0[0x18]; 4874 4875 u8 syndrome[0x20]; 4876 4877 u8 reserved_1[0x40]; 4878 }; 4879 4880 struct mlx5_ifc_destroy_mkey_in_bits { 4881 u8 opcode[0x10]; 4882 u8 reserved_0[0x10]; 4883 4884 u8 reserved_1[0x10]; 4885 u8 op_mod[0x10]; 4886 4887 u8 reserved_2[0x8]; 4888 u8 mkey_index[0x18]; 4889 4890 u8 reserved_3[0x20]; 4891 }; 4892 4893 struct mlx5_ifc_destroy_flow_table_out_bits { 4894 u8 status[0x8]; 4895 u8 reserved_0[0x18]; 4896 4897 u8 syndrome[0x20]; 4898 4899 u8 reserved_1[0x40]; 4900 }; 4901 4902 struct mlx5_ifc_destroy_flow_table_in_bits { 4903 u8 opcode[0x10]; 4904 u8 reserved_0[0x10]; 4905 4906 u8 reserved_1[0x10]; 4907 u8 op_mod[0x10]; 4908 4909 u8 reserved_2[0x40]; 4910 4911 u8 table_type[0x8]; 4912 u8 reserved_3[0x18]; 4913 4914 u8 reserved_4[0x8]; 4915 u8 table_id[0x18]; 4916 4917 u8 reserved_5[0x140]; 4918 }; 4919 4920 struct mlx5_ifc_destroy_flow_group_out_bits { 4921 u8 status[0x8]; 4922 u8 reserved_0[0x18]; 4923 4924 u8 syndrome[0x20]; 4925 4926 u8 reserved_1[0x40]; 4927 }; 4928 4929 struct mlx5_ifc_destroy_flow_group_in_bits { 4930 u8 opcode[0x10]; 4931 u8 reserved_0[0x10]; 4932 4933 u8 reserved_1[0x10]; 4934 u8 op_mod[0x10]; 4935 4936 u8 reserved_2[0x40]; 4937 4938 u8 table_type[0x8]; 4939 u8 reserved_3[0x18]; 4940 4941 u8 reserved_4[0x8]; 4942 u8 table_id[0x18]; 4943 4944 u8 group_id[0x20]; 4945 4946 u8 reserved_5[0x120]; 4947 }; 4948 4949 struct mlx5_ifc_destroy_eq_out_bits { 4950 u8 status[0x8]; 4951 u8 reserved_0[0x18]; 4952 4953 u8 syndrome[0x20]; 4954 4955 u8 reserved_1[0x40]; 4956 }; 4957 4958 struct mlx5_ifc_destroy_eq_in_bits { 4959 u8 opcode[0x10]; 4960 u8 reserved_0[0x10]; 4961 4962 u8 reserved_1[0x10]; 4963 u8 op_mod[0x10]; 4964 4965 u8 reserved_2[0x18]; 4966 u8 eq_number[0x8]; 4967 4968 u8 reserved_3[0x20]; 4969 }; 4970 4971 struct mlx5_ifc_destroy_dct_out_bits { 4972 u8 status[0x8]; 4973 u8 reserved_0[0x18]; 4974 4975 u8 syndrome[0x20]; 4976 4977 u8 reserved_1[0x40]; 4978 }; 4979 4980 struct mlx5_ifc_destroy_dct_in_bits { 4981 u8 opcode[0x10]; 4982 u8 reserved_0[0x10]; 4983 4984 u8 reserved_1[0x10]; 4985 u8 op_mod[0x10]; 4986 4987 u8 reserved_2[0x8]; 4988 u8 dctn[0x18]; 4989 4990 u8 reserved_3[0x20]; 4991 }; 4992 4993 struct mlx5_ifc_destroy_cq_out_bits { 4994 u8 status[0x8]; 4995 u8 reserved_0[0x18]; 4996 4997 u8 syndrome[0x20]; 4998 4999 u8 reserved_1[0x40]; 5000 }; 5001 5002 struct mlx5_ifc_destroy_cq_in_bits { 5003 u8 opcode[0x10]; 5004 u8 reserved_0[0x10]; 5005 5006 u8 reserved_1[0x10]; 5007 u8 op_mod[0x10]; 5008 5009 u8 reserved_2[0x8]; 5010 u8 cqn[0x18]; 5011 5012 u8 reserved_3[0x20]; 5013 }; 5014 5015 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 5016 u8 status[0x8]; 5017 u8 reserved_0[0x18]; 5018 5019 u8 syndrome[0x20]; 5020 5021 u8 reserved_1[0x40]; 5022 }; 5023 5024 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 5025 u8 opcode[0x10]; 5026 u8 reserved_0[0x10]; 5027 5028 u8 reserved_1[0x10]; 5029 u8 op_mod[0x10]; 5030 5031 u8 reserved_2[0x20]; 5032 5033 u8 reserved_3[0x10]; 5034 u8 vxlan_udp_port[0x10]; 5035 }; 5036 5037 struct mlx5_ifc_delete_l2_table_entry_out_bits { 5038 u8 status[0x8]; 5039 u8 reserved_0[0x18]; 5040 5041 u8 syndrome[0x20]; 5042 5043 u8 reserved_1[0x40]; 5044 }; 5045 5046 struct mlx5_ifc_delete_l2_table_entry_in_bits { 5047 u8 opcode[0x10]; 5048 u8 reserved_0[0x10]; 5049 5050 u8 reserved_1[0x10]; 5051 u8 op_mod[0x10]; 5052 5053 u8 reserved_2[0x60]; 5054 5055 u8 reserved_3[0x8]; 5056 u8 table_index[0x18]; 5057 5058 u8 reserved_4[0x140]; 5059 }; 5060 5061 struct mlx5_ifc_delete_fte_out_bits { 5062 u8 status[0x8]; 5063 u8 reserved_0[0x18]; 5064 5065 u8 syndrome[0x20]; 5066 5067 u8 reserved_1[0x40]; 5068 }; 5069 5070 struct mlx5_ifc_delete_fte_in_bits { 5071 u8 opcode[0x10]; 5072 u8 reserved_0[0x10]; 5073 5074 u8 reserved_1[0x10]; 5075 u8 op_mod[0x10]; 5076 5077 u8 reserved_2[0x40]; 5078 5079 u8 table_type[0x8]; 5080 u8 reserved_3[0x18]; 5081 5082 u8 reserved_4[0x8]; 5083 u8 table_id[0x18]; 5084 5085 u8 reserved_5[0x40]; 5086 5087 u8 flow_index[0x20]; 5088 5089 u8 reserved_6[0xe0]; 5090 }; 5091 5092 struct mlx5_ifc_dealloc_xrcd_out_bits { 5093 u8 status[0x8]; 5094 u8 reserved_0[0x18]; 5095 5096 u8 syndrome[0x20]; 5097 5098 u8 reserved_1[0x40]; 5099 }; 5100 5101 struct mlx5_ifc_dealloc_xrcd_in_bits { 5102 u8 opcode[0x10]; 5103 u8 reserved_0[0x10]; 5104 5105 u8 reserved_1[0x10]; 5106 u8 op_mod[0x10]; 5107 5108 u8 reserved_2[0x8]; 5109 u8 xrcd[0x18]; 5110 5111 u8 reserved_3[0x20]; 5112 }; 5113 5114 struct mlx5_ifc_dealloc_uar_out_bits { 5115 u8 status[0x8]; 5116 u8 reserved_0[0x18]; 5117 5118 u8 syndrome[0x20]; 5119 5120 u8 reserved_1[0x40]; 5121 }; 5122 5123 struct mlx5_ifc_dealloc_uar_in_bits { 5124 u8 opcode[0x10]; 5125 u8 reserved_0[0x10]; 5126 5127 u8 reserved_1[0x10]; 5128 u8 op_mod[0x10]; 5129 5130 u8 reserved_2[0x8]; 5131 u8 uar[0x18]; 5132 5133 u8 reserved_3[0x20]; 5134 }; 5135 5136 struct mlx5_ifc_dealloc_transport_domain_out_bits { 5137 u8 status[0x8]; 5138 u8 reserved_0[0x18]; 5139 5140 u8 syndrome[0x20]; 5141 5142 u8 reserved_1[0x40]; 5143 }; 5144 5145 struct mlx5_ifc_dealloc_transport_domain_in_bits { 5146 u8 opcode[0x10]; 5147 u8 reserved_0[0x10]; 5148 5149 u8 reserved_1[0x10]; 5150 u8 op_mod[0x10]; 5151 5152 u8 reserved_2[0x8]; 5153 u8 transport_domain[0x18]; 5154 5155 u8 reserved_3[0x20]; 5156 }; 5157 5158 struct mlx5_ifc_dealloc_q_counter_out_bits { 5159 u8 status[0x8]; 5160 u8 reserved_0[0x18]; 5161 5162 u8 syndrome[0x20]; 5163 5164 u8 reserved_1[0x40]; 5165 }; 5166 5167 struct mlx5_ifc_dealloc_q_counter_in_bits { 5168 u8 opcode[0x10]; 5169 u8 reserved_0[0x10]; 5170 5171 u8 reserved_1[0x10]; 5172 u8 op_mod[0x10]; 5173 5174 u8 reserved_2[0x18]; 5175 u8 counter_set_id[0x8]; 5176 5177 u8 reserved_3[0x20]; 5178 }; 5179 5180 struct mlx5_ifc_dealloc_pd_out_bits { 5181 u8 status[0x8]; 5182 u8 reserved_0[0x18]; 5183 5184 u8 syndrome[0x20]; 5185 5186 u8 reserved_1[0x40]; 5187 }; 5188 5189 struct mlx5_ifc_dealloc_pd_in_bits { 5190 u8 opcode[0x10]; 5191 u8 reserved_0[0x10]; 5192 5193 u8 reserved_1[0x10]; 5194 u8 op_mod[0x10]; 5195 5196 u8 reserved_2[0x8]; 5197 u8 pd[0x18]; 5198 5199 u8 reserved_3[0x20]; 5200 }; 5201 5202 struct mlx5_ifc_create_xrc_srq_out_bits { 5203 u8 status[0x8]; 5204 u8 reserved_0[0x18]; 5205 5206 u8 syndrome[0x20]; 5207 5208 u8 reserved_1[0x8]; 5209 u8 xrc_srqn[0x18]; 5210 5211 u8 reserved_2[0x20]; 5212 }; 5213 5214 struct mlx5_ifc_create_xrc_srq_in_bits { 5215 u8 opcode[0x10]; 5216 u8 reserved_0[0x10]; 5217 5218 u8 reserved_1[0x10]; 5219 u8 op_mod[0x10]; 5220 5221 u8 reserved_2[0x40]; 5222 5223 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5224 5225 u8 reserved_3[0x600]; 5226 5227 u8 pas[0][0x40]; 5228 }; 5229 5230 struct mlx5_ifc_create_tis_out_bits { 5231 u8 status[0x8]; 5232 u8 reserved_0[0x18]; 5233 5234 u8 syndrome[0x20]; 5235 5236 u8 reserved_1[0x8]; 5237 u8 tisn[0x18]; 5238 5239 u8 reserved_2[0x20]; 5240 }; 5241 5242 struct mlx5_ifc_create_tis_in_bits { 5243 u8 opcode[0x10]; 5244 u8 reserved_0[0x10]; 5245 5246 u8 reserved_1[0x10]; 5247 u8 op_mod[0x10]; 5248 5249 u8 reserved_2[0xc0]; 5250 5251 struct mlx5_ifc_tisc_bits ctx; 5252 }; 5253 5254 struct mlx5_ifc_create_tir_out_bits { 5255 u8 status[0x8]; 5256 u8 reserved_0[0x18]; 5257 5258 u8 syndrome[0x20]; 5259 5260 u8 reserved_1[0x8]; 5261 u8 tirn[0x18]; 5262 5263 u8 reserved_2[0x20]; 5264 }; 5265 5266 struct mlx5_ifc_create_tir_in_bits { 5267 u8 opcode[0x10]; 5268 u8 reserved_0[0x10]; 5269 5270 u8 reserved_1[0x10]; 5271 u8 op_mod[0x10]; 5272 5273 u8 reserved_2[0xc0]; 5274 5275 struct mlx5_ifc_tirc_bits ctx; 5276 }; 5277 5278 struct mlx5_ifc_create_srq_out_bits { 5279 u8 status[0x8]; 5280 u8 reserved_0[0x18]; 5281 5282 u8 syndrome[0x20]; 5283 5284 u8 reserved_1[0x8]; 5285 u8 srqn[0x18]; 5286 5287 u8 reserved_2[0x20]; 5288 }; 5289 5290 struct mlx5_ifc_create_srq_in_bits { 5291 u8 opcode[0x10]; 5292 u8 reserved_0[0x10]; 5293 5294 u8 reserved_1[0x10]; 5295 u8 op_mod[0x10]; 5296 5297 u8 reserved_2[0x40]; 5298 5299 struct mlx5_ifc_srqc_bits srq_context_entry; 5300 5301 u8 reserved_3[0x600]; 5302 5303 u8 pas[0][0x40]; 5304 }; 5305 5306 struct mlx5_ifc_create_sq_out_bits { 5307 u8 status[0x8]; 5308 u8 reserved_0[0x18]; 5309 5310 u8 syndrome[0x20]; 5311 5312 u8 reserved_1[0x8]; 5313 u8 sqn[0x18]; 5314 5315 u8 reserved_2[0x20]; 5316 }; 5317 5318 struct mlx5_ifc_create_sq_in_bits { 5319 u8 opcode[0x10]; 5320 u8 reserved_0[0x10]; 5321 5322 u8 reserved_1[0x10]; 5323 u8 op_mod[0x10]; 5324 5325 u8 reserved_2[0xc0]; 5326 5327 struct mlx5_ifc_sqc_bits ctx; 5328 }; 5329 5330 struct mlx5_ifc_create_rqt_out_bits { 5331 u8 status[0x8]; 5332 u8 reserved_0[0x18]; 5333 5334 u8 syndrome[0x20]; 5335 5336 u8 reserved_1[0x8]; 5337 u8 rqtn[0x18]; 5338 5339 u8 reserved_2[0x20]; 5340 }; 5341 5342 struct mlx5_ifc_create_rqt_in_bits { 5343 u8 opcode[0x10]; 5344 u8 reserved_0[0x10]; 5345 5346 u8 reserved_1[0x10]; 5347 u8 op_mod[0x10]; 5348 5349 u8 reserved_2[0xc0]; 5350 5351 struct mlx5_ifc_rqtc_bits rqt_context; 5352 }; 5353 5354 struct mlx5_ifc_create_rq_out_bits { 5355 u8 status[0x8]; 5356 u8 reserved_0[0x18]; 5357 5358 u8 syndrome[0x20]; 5359 5360 u8 reserved_1[0x8]; 5361 u8 rqn[0x18]; 5362 5363 u8 reserved_2[0x20]; 5364 }; 5365 5366 struct mlx5_ifc_create_rq_in_bits { 5367 u8 opcode[0x10]; 5368 u8 reserved_0[0x10]; 5369 5370 u8 reserved_1[0x10]; 5371 u8 op_mod[0x10]; 5372 5373 u8 reserved_2[0xc0]; 5374 5375 struct mlx5_ifc_rqc_bits ctx; 5376 }; 5377 5378 struct mlx5_ifc_create_rmp_out_bits { 5379 u8 status[0x8]; 5380 u8 reserved_0[0x18]; 5381 5382 u8 syndrome[0x20]; 5383 5384 u8 reserved_1[0x8]; 5385 u8 rmpn[0x18]; 5386 5387 u8 reserved_2[0x20]; 5388 }; 5389 5390 struct mlx5_ifc_create_rmp_in_bits { 5391 u8 opcode[0x10]; 5392 u8 reserved_0[0x10]; 5393 5394 u8 reserved_1[0x10]; 5395 u8 op_mod[0x10]; 5396 5397 u8 reserved_2[0xc0]; 5398 5399 struct mlx5_ifc_rmpc_bits ctx; 5400 }; 5401 5402 struct mlx5_ifc_create_qp_out_bits { 5403 u8 status[0x8]; 5404 u8 reserved_0[0x18]; 5405 5406 u8 syndrome[0x20]; 5407 5408 u8 reserved_1[0x8]; 5409 u8 qpn[0x18]; 5410 5411 u8 reserved_2[0x20]; 5412 }; 5413 5414 struct mlx5_ifc_create_qp_in_bits { 5415 u8 opcode[0x10]; 5416 u8 reserved_0[0x10]; 5417 5418 u8 reserved_1[0x10]; 5419 u8 op_mod[0x10]; 5420 5421 u8 reserved_2[0x40]; 5422 5423 u8 opt_param_mask[0x20]; 5424 5425 u8 reserved_3[0x20]; 5426 5427 struct mlx5_ifc_qpc_bits qpc; 5428 5429 u8 reserved_4[0x80]; 5430 5431 u8 pas[0][0x40]; 5432 }; 5433 5434 struct mlx5_ifc_create_psv_out_bits { 5435 u8 status[0x8]; 5436 u8 reserved_0[0x18]; 5437 5438 u8 syndrome[0x20]; 5439 5440 u8 reserved_1[0x40]; 5441 5442 u8 reserved_2[0x8]; 5443 u8 psv0_index[0x18]; 5444 5445 u8 reserved_3[0x8]; 5446 u8 psv1_index[0x18]; 5447 5448 u8 reserved_4[0x8]; 5449 u8 psv2_index[0x18]; 5450 5451 u8 reserved_5[0x8]; 5452 u8 psv3_index[0x18]; 5453 }; 5454 5455 struct mlx5_ifc_create_psv_in_bits { 5456 u8 opcode[0x10]; 5457 u8 reserved_0[0x10]; 5458 5459 u8 reserved_1[0x10]; 5460 u8 op_mod[0x10]; 5461 5462 u8 num_psv[0x4]; 5463 u8 reserved_2[0x4]; 5464 u8 pd[0x18]; 5465 5466 u8 reserved_3[0x20]; 5467 }; 5468 5469 struct mlx5_ifc_create_mkey_out_bits { 5470 u8 status[0x8]; 5471 u8 reserved_0[0x18]; 5472 5473 u8 syndrome[0x20]; 5474 5475 u8 reserved_1[0x8]; 5476 u8 mkey_index[0x18]; 5477 5478 u8 reserved_2[0x20]; 5479 }; 5480 5481 struct mlx5_ifc_create_mkey_in_bits { 5482 u8 opcode[0x10]; 5483 u8 reserved_0[0x10]; 5484 5485 u8 reserved_1[0x10]; 5486 u8 op_mod[0x10]; 5487 5488 u8 reserved_2[0x20]; 5489 5490 u8 pg_access[0x1]; 5491 u8 reserved_3[0x1f]; 5492 5493 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5494 5495 u8 reserved_4[0x80]; 5496 5497 u8 translations_octword_actual_size[0x20]; 5498 5499 u8 reserved_5[0x560]; 5500 5501 u8 klm_pas_mtt[0][0x20]; 5502 }; 5503 5504 struct mlx5_ifc_create_flow_table_out_bits { 5505 u8 status[0x8]; 5506 u8 reserved_0[0x18]; 5507 5508 u8 syndrome[0x20]; 5509 5510 u8 reserved_1[0x8]; 5511 u8 table_id[0x18]; 5512 5513 u8 reserved_2[0x20]; 5514 }; 5515 5516 struct mlx5_ifc_create_flow_table_in_bits { 5517 u8 opcode[0x10]; 5518 u8 reserved_0[0x10]; 5519 5520 u8 reserved_1[0x10]; 5521 u8 op_mod[0x10]; 5522 5523 u8 reserved_2[0x40]; 5524 5525 u8 table_type[0x8]; 5526 u8 reserved_3[0x18]; 5527 5528 u8 reserved_4[0x20]; 5529 5530 u8 reserved_5[0x8]; 5531 u8 level[0x8]; 5532 u8 reserved_6[0x8]; 5533 u8 log_size[0x8]; 5534 5535 u8 reserved_7[0x120]; 5536 }; 5537 5538 struct mlx5_ifc_create_flow_group_out_bits { 5539 u8 status[0x8]; 5540 u8 reserved_0[0x18]; 5541 5542 u8 syndrome[0x20]; 5543 5544 u8 reserved_1[0x8]; 5545 u8 group_id[0x18]; 5546 5547 u8 reserved_2[0x20]; 5548 }; 5549 5550 enum { 5551 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5552 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5553 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5554 }; 5555 5556 struct mlx5_ifc_create_flow_group_in_bits { 5557 u8 opcode[0x10]; 5558 u8 reserved_0[0x10]; 5559 5560 u8 reserved_1[0x10]; 5561 u8 op_mod[0x10]; 5562 5563 u8 reserved_2[0x40]; 5564 5565 u8 table_type[0x8]; 5566 u8 reserved_3[0x18]; 5567 5568 u8 reserved_4[0x8]; 5569 u8 table_id[0x18]; 5570 5571 u8 reserved_5[0x20]; 5572 5573 u8 start_flow_index[0x20]; 5574 5575 u8 reserved_6[0x20]; 5576 5577 u8 end_flow_index[0x20]; 5578 5579 u8 reserved_7[0xa0]; 5580 5581 u8 reserved_8[0x18]; 5582 u8 match_criteria_enable[0x8]; 5583 5584 struct mlx5_ifc_fte_match_param_bits match_criteria; 5585 5586 u8 reserved_9[0xe00]; 5587 }; 5588 5589 struct mlx5_ifc_create_eq_out_bits { 5590 u8 status[0x8]; 5591 u8 reserved_0[0x18]; 5592 5593 u8 syndrome[0x20]; 5594 5595 u8 reserved_1[0x18]; 5596 u8 eq_number[0x8]; 5597 5598 u8 reserved_2[0x20]; 5599 }; 5600 5601 struct mlx5_ifc_create_eq_in_bits { 5602 u8 opcode[0x10]; 5603 u8 reserved_0[0x10]; 5604 5605 u8 reserved_1[0x10]; 5606 u8 op_mod[0x10]; 5607 5608 u8 reserved_2[0x40]; 5609 5610 struct mlx5_ifc_eqc_bits eq_context_entry; 5611 5612 u8 reserved_3[0x40]; 5613 5614 u8 event_bitmask[0x40]; 5615 5616 u8 reserved_4[0x580]; 5617 5618 u8 pas[0][0x40]; 5619 }; 5620 5621 struct mlx5_ifc_create_dct_out_bits { 5622 u8 status[0x8]; 5623 u8 reserved_0[0x18]; 5624 5625 u8 syndrome[0x20]; 5626 5627 u8 reserved_1[0x8]; 5628 u8 dctn[0x18]; 5629 5630 u8 reserved_2[0x20]; 5631 }; 5632 5633 struct mlx5_ifc_create_dct_in_bits { 5634 u8 opcode[0x10]; 5635 u8 reserved_0[0x10]; 5636 5637 u8 reserved_1[0x10]; 5638 u8 op_mod[0x10]; 5639 5640 u8 reserved_2[0x40]; 5641 5642 struct mlx5_ifc_dctc_bits dct_context_entry; 5643 5644 u8 reserved_3[0x180]; 5645 }; 5646 5647 struct mlx5_ifc_create_cq_out_bits { 5648 u8 status[0x8]; 5649 u8 reserved_0[0x18]; 5650 5651 u8 syndrome[0x20]; 5652 5653 u8 reserved_1[0x8]; 5654 u8 cqn[0x18]; 5655 5656 u8 reserved_2[0x20]; 5657 }; 5658 5659 struct mlx5_ifc_create_cq_in_bits { 5660 u8 opcode[0x10]; 5661 u8 reserved_0[0x10]; 5662 5663 u8 reserved_1[0x10]; 5664 u8 op_mod[0x10]; 5665 5666 u8 reserved_2[0x40]; 5667 5668 struct mlx5_ifc_cqc_bits cq_context; 5669 5670 u8 reserved_3[0x600]; 5671 5672 u8 pas[0][0x40]; 5673 }; 5674 5675 struct mlx5_ifc_config_int_moderation_out_bits { 5676 u8 status[0x8]; 5677 u8 reserved_0[0x18]; 5678 5679 u8 syndrome[0x20]; 5680 5681 u8 reserved_1[0x4]; 5682 u8 min_delay[0xc]; 5683 u8 int_vector[0x10]; 5684 5685 u8 reserved_2[0x20]; 5686 }; 5687 5688 enum { 5689 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 5690 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 5691 }; 5692 5693 struct mlx5_ifc_config_int_moderation_in_bits { 5694 u8 opcode[0x10]; 5695 u8 reserved_0[0x10]; 5696 5697 u8 reserved_1[0x10]; 5698 u8 op_mod[0x10]; 5699 5700 u8 reserved_2[0x4]; 5701 u8 min_delay[0xc]; 5702 u8 int_vector[0x10]; 5703 5704 u8 reserved_3[0x20]; 5705 }; 5706 5707 struct mlx5_ifc_attach_to_mcg_out_bits { 5708 u8 status[0x8]; 5709 u8 reserved_0[0x18]; 5710 5711 u8 syndrome[0x20]; 5712 5713 u8 reserved_1[0x40]; 5714 }; 5715 5716 struct mlx5_ifc_attach_to_mcg_in_bits { 5717 u8 opcode[0x10]; 5718 u8 reserved_0[0x10]; 5719 5720 u8 reserved_1[0x10]; 5721 u8 op_mod[0x10]; 5722 5723 u8 reserved_2[0x8]; 5724 u8 qpn[0x18]; 5725 5726 u8 reserved_3[0x20]; 5727 5728 u8 multicast_gid[16][0x8]; 5729 }; 5730 5731 struct mlx5_ifc_arm_xrc_srq_out_bits { 5732 u8 status[0x8]; 5733 u8 reserved_0[0x18]; 5734 5735 u8 syndrome[0x20]; 5736 5737 u8 reserved_1[0x40]; 5738 }; 5739 5740 enum { 5741 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 5742 }; 5743 5744 struct mlx5_ifc_arm_xrc_srq_in_bits { 5745 u8 opcode[0x10]; 5746 u8 reserved_0[0x10]; 5747 5748 u8 reserved_1[0x10]; 5749 u8 op_mod[0x10]; 5750 5751 u8 reserved_2[0x8]; 5752 u8 xrc_srqn[0x18]; 5753 5754 u8 reserved_3[0x10]; 5755 u8 lwm[0x10]; 5756 }; 5757 5758 struct mlx5_ifc_arm_rq_out_bits { 5759 u8 status[0x8]; 5760 u8 reserved_0[0x18]; 5761 5762 u8 syndrome[0x20]; 5763 5764 u8 reserved_1[0x40]; 5765 }; 5766 5767 enum { 5768 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1, 5769 }; 5770 5771 struct mlx5_ifc_arm_rq_in_bits { 5772 u8 opcode[0x10]; 5773 u8 reserved_0[0x10]; 5774 5775 u8 reserved_1[0x10]; 5776 u8 op_mod[0x10]; 5777 5778 u8 reserved_2[0x8]; 5779 u8 srq_number[0x18]; 5780 5781 u8 reserved_3[0x10]; 5782 u8 lwm[0x10]; 5783 }; 5784 5785 struct mlx5_ifc_arm_dct_out_bits { 5786 u8 status[0x8]; 5787 u8 reserved_0[0x18]; 5788 5789 u8 syndrome[0x20]; 5790 5791 u8 reserved_1[0x40]; 5792 }; 5793 5794 struct mlx5_ifc_arm_dct_in_bits { 5795 u8 opcode[0x10]; 5796 u8 reserved_0[0x10]; 5797 5798 u8 reserved_1[0x10]; 5799 u8 op_mod[0x10]; 5800 5801 u8 reserved_2[0x8]; 5802 u8 dct_number[0x18]; 5803 5804 u8 reserved_3[0x20]; 5805 }; 5806 5807 struct mlx5_ifc_alloc_xrcd_out_bits { 5808 u8 status[0x8]; 5809 u8 reserved_0[0x18]; 5810 5811 u8 syndrome[0x20]; 5812 5813 u8 reserved_1[0x8]; 5814 u8 xrcd[0x18]; 5815 5816 u8 reserved_2[0x20]; 5817 }; 5818 5819 struct mlx5_ifc_alloc_xrcd_in_bits { 5820 u8 opcode[0x10]; 5821 u8 reserved_0[0x10]; 5822 5823 u8 reserved_1[0x10]; 5824 u8 op_mod[0x10]; 5825 5826 u8 reserved_2[0x40]; 5827 }; 5828 5829 struct mlx5_ifc_alloc_uar_out_bits { 5830 u8 status[0x8]; 5831 u8 reserved_0[0x18]; 5832 5833 u8 syndrome[0x20]; 5834 5835 u8 reserved_1[0x8]; 5836 u8 uar[0x18]; 5837 5838 u8 reserved_2[0x20]; 5839 }; 5840 5841 struct mlx5_ifc_alloc_uar_in_bits { 5842 u8 opcode[0x10]; 5843 u8 reserved_0[0x10]; 5844 5845 u8 reserved_1[0x10]; 5846 u8 op_mod[0x10]; 5847 5848 u8 reserved_2[0x40]; 5849 }; 5850 5851 struct mlx5_ifc_alloc_transport_domain_out_bits { 5852 u8 status[0x8]; 5853 u8 reserved_0[0x18]; 5854 5855 u8 syndrome[0x20]; 5856 5857 u8 reserved_1[0x8]; 5858 u8 transport_domain[0x18]; 5859 5860 u8 reserved_2[0x20]; 5861 }; 5862 5863 struct mlx5_ifc_alloc_transport_domain_in_bits { 5864 u8 opcode[0x10]; 5865 u8 reserved_0[0x10]; 5866 5867 u8 reserved_1[0x10]; 5868 u8 op_mod[0x10]; 5869 5870 u8 reserved_2[0x40]; 5871 }; 5872 5873 struct mlx5_ifc_alloc_q_counter_out_bits { 5874 u8 status[0x8]; 5875 u8 reserved_0[0x18]; 5876 5877 u8 syndrome[0x20]; 5878 5879 u8 reserved_1[0x18]; 5880 u8 counter_set_id[0x8]; 5881 5882 u8 reserved_2[0x20]; 5883 }; 5884 5885 struct mlx5_ifc_alloc_q_counter_in_bits { 5886 u8 opcode[0x10]; 5887 u8 reserved_0[0x10]; 5888 5889 u8 reserved_1[0x10]; 5890 u8 op_mod[0x10]; 5891 5892 u8 reserved_2[0x40]; 5893 }; 5894 5895 struct mlx5_ifc_alloc_pd_out_bits { 5896 u8 status[0x8]; 5897 u8 reserved_0[0x18]; 5898 5899 u8 syndrome[0x20]; 5900 5901 u8 reserved_1[0x8]; 5902 u8 pd[0x18]; 5903 5904 u8 reserved_2[0x20]; 5905 }; 5906 5907 struct mlx5_ifc_alloc_pd_in_bits { 5908 u8 opcode[0x10]; 5909 u8 reserved_0[0x10]; 5910 5911 u8 reserved_1[0x10]; 5912 u8 op_mod[0x10]; 5913 5914 u8 reserved_2[0x40]; 5915 }; 5916 5917 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 5918 u8 status[0x8]; 5919 u8 reserved_0[0x18]; 5920 5921 u8 syndrome[0x20]; 5922 5923 u8 reserved_1[0x40]; 5924 }; 5925 5926 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 5927 u8 opcode[0x10]; 5928 u8 reserved_0[0x10]; 5929 5930 u8 reserved_1[0x10]; 5931 u8 op_mod[0x10]; 5932 5933 u8 reserved_2[0x20]; 5934 5935 u8 reserved_3[0x10]; 5936 u8 vxlan_udp_port[0x10]; 5937 }; 5938 5939 struct mlx5_ifc_access_register_out_bits { 5940 u8 status[0x8]; 5941 u8 reserved_0[0x18]; 5942 5943 u8 syndrome[0x20]; 5944 5945 u8 reserved_1[0x40]; 5946 5947 u8 register_data[0][0x20]; 5948 }; 5949 5950 enum { 5951 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 5952 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 5953 }; 5954 5955 struct mlx5_ifc_access_register_in_bits { 5956 u8 opcode[0x10]; 5957 u8 reserved_0[0x10]; 5958 5959 u8 reserved_1[0x10]; 5960 u8 op_mod[0x10]; 5961 5962 u8 reserved_2[0x10]; 5963 u8 register_id[0x10]; 5964 5965 u8 argument[0x20]; 5966 5967 u8 register_data[0][0x20]; 5968 }; 5969 5970 struct mlx5_ifc_sltp_reg_bits { 5971 u8 status[0x4]; 5972 u8 version[0x4]; 5973 u8 local_port[0x8]; 5974 u8 pnat[0x2]; 5975 u8 reserved_0[0x2]; 5976 u8 lane[0x4]; 5977 u8 reserved_1[0x8]; 5978 5979 u8 reserved_2[0x20]; 5980 5981 u8 reserved_3[0x7]; 5982 u8 polarity[0x1]; 5983 u8 ob_tap0[0x8]; 5984 u8 ob_tap1[0x8]; 5985 u8 ob_tap2[0x8]; 5986 5987 u8 reserved_4[0xc]; 5988 u8 ob_preemp_mode[0x4]; 5989 u8 ob_reg[0x8]; 5990 u8 ob_bias[0x8]; 5991 5992 u8 reserved_5[0x20]; 5993 }; 5994 5995 struct mlx5_ifc_slrg_reg_bits { 5996 u8 status[0x4]; 5997 u8 version[0x4]; 5998 u8 local_port[0x8]; 5999 u8 pnat[0x2]; 6000 u8 reserved_0[0x2]; 6001 u8 lane[0x4]; 6002 u8 reserved_1[0x8]; 6003 6004 u8 time_to_link_up[0x10]; 6005 u8 reserved_2[0xc]; 6006 u8 grade_lane_speed[0x4]; 6007 6008 u8 grade_version[0x8]; 6009 u8 grade[0x18]; 6010 6011 u8 reserved_3[0x4]; 6012 u8 height_grade_type[0x4]; 6013 u8 height_grade[0x18]; 6014 6015 u8 height_dz[0x10]; 6016 u8 height_dv[0x10]; 6017 6018 u8 reserved_4[0x10]; 6019 u8 height_sigma[0x10]; 6020 6021 u8 reserved_5[0x20]; 6022 6023 u8 reserved_6[0x4]; 6024 u8 phase_grade_type[0x4]; 6025 u8 phase_grade[0x18]; 6026 6027 u8 reserved_7[0x8]; 6028 u8 phase_eo_pos[0x8]; 6029 u8 reserved_8[0x8]; 6030 u8 phase_eo_neg[0x8]; 6031 6032 u8 ffe_set_tested[0x10]; 6033 u8 test_errors_per_lane[0x10]; 6034 }; 6035 6036 struct mlx5_ifc_pvlc_reg_bits { 6037 u8 reserved_0[0x8]; 6038 u8 local_port[0x8]; 6039 u8 reserved_1[0x10]; 6040 6041 u8 reserved_2[0x1c]; 6042 u8 vl_hw_cap[0x4]; 6043 6044 u8 reserved_3[0x1c]; 6045 u8 vl_admin[0x4]; 6046 6047 u8 reserved_4[0x1c]; 6048 u8 vl_operational[0x4]; 6049 }; 6050 6051 struct mlx5_ifc_pude_reg_bits { 6052 u8 swid[0x8]; 6053 u8 local_port[0x8]; 6054 u8 reserved_0[0x4]; 6055 u8 admin_status[0x4]; 6056 u8 reserved_1[0x4]; 6057 u8 oper_status[0x4]; 6058 6059 u8 reserved_2[0x60]; 6060 }; 6061 6062 struct mlx5_ifc_ptys_reg_bits { 6063 u8 reserved_0[0x8]; 6064 u8 local_port[0x8]; 6065 u8 reserved_1[0xd]; 6066 u8 proto_mask[0x3]; 6067 6068 u8 reserved_2[0x40]; 6069 6070 u8 eth_proto_capability[0x20]; 6071 6072 u8 ib_link_width_capability[0x10]; 6073 u8 ib_proto_capability[0x10]; 6074 6075 u8 reserved_3[0x20]; 6076 6077 u8 eth_proto_admin[0x20]; 6078 6079 u8 ib_link_width_admin[0x10]; 6080 u8 ib_proto_admin[0x10]; 6081 6082 u8 reserved_4[0x20]; 6083 6084 u8 eth_proto_oper[0x20]; 6085 6086 u8 ib_link_width_oper[0x10]; 6087 u8 ib_proto_oper[0x10]; 6088 6089 u8 reserved_5[0x20]; 6090 6091 u8 eth_proto_lp_advertise[0x20]; 6092 6093 u8 reserved_6[0x60]; 6094 }; 6095 6096 struct mlx5_ifc_ptas_reg_bits { 6097 u8 reserved_0[0x20]; 6098 6099 u8 algorithm_options[0x10]; 6100 u8 reserved_1[0x4]; 6101 u8 repetitions_mode[0x4]; 6102 u8 num_of_repetitions[0x8]; 6103 6104 u8 grade_version[0x8]; 6105 u8 height_grade_type[0x4]; 6106 u8 phase_grade_type[0x4]; 6107 u8 height_grade_weight[0x8]; 6108 u8 phase_grade_weight[0x8]; 6109 6110 u8 gisim_measure_bits[0x10]; 6111 u8 adaptive_tap_measure_bits[0x10]; 6112 6113 u8 ber_bath_high_error_threshold[0x10]; 6114 u8 ber_bath_mid_error_threshold[0x10]; 6115 6116 u8 ber_bath_low_error_threshold[0x10]; 6117 u8 one_ratio_high_threshold[0x10]; 6118 6119 u8 one_ratio_high_mid_threshold[0x10]; 6120 u8 one_ratio_low_mid_threshold[0x10]; 6121 6122 u8 one_ratio_low_threshold[0x10]; 6123 u8 ndeo_error_threshold[0x10]; 6124 6125 u8 mixer_offset_step_size[0x10]; 6126 u8 reserved_2[0x8]; 6127 u8 mix90_phase_for_voltage_bath[0x8]; 6128 6129 u8 mixer_offset_start[0x10]; 6130 u8 mixer_offset_end[0x10]; 6131 6132 u8 reserved_3[0x15]; 6133 u8 ber_test_time[0xb]; 6134 }; 6135 6136 struct mlx5_ifc_pspa_reg_bits { 6137 u8 swid[0x8]; 6138 u8 local_port[0x8]; 6139 u8 sub_port[0x8]; 6140 u8 reserved_0[0x8]; 6141 6142 u8 reserved_1[0x20]; 6143 }; 6144 6145 struct mlx5_ifc_pqdr_reg_bits { 6146 u8 reserved_0[0x8]; 6147 u8 local_port[0x8]; 6148 u8 reserved_1[0x5]; 6149 u8 prio[0x3]; 6150 u8 reserved_2[0x6]; 6151 u8 mode[0x2]; 6152 6153 u8 reserved_3[0x20]; 6154 6155 u8 reserved_4[0x10]; 6156 u8 min_threshold[0x10]; 6157 6158 u8 reserved_5[0x10]; 6159 u8 max_threshold[0x10]; 6160 6161 u8 reserved_6[0x10]; 6162 u8 mark_probability_denominator[0x10]; 6163 6164 u8 reserved_7[0x60]; 6165 }; 6166 6167 struct mlx5_ifc_ppsc_reg_bits { 6168 u8 reserved_0[0x8]; 6169 u8 local_port[0x8]; 6170 u8 reserved_1[0x10]; 6171 6172 u8 reserved_2[0x60]; 6173 6174 u8 reserved_3[0x1c]; 6175 u8 wrps_admin[0x4]; 6176 6177 u8 reserved_4[0x1c]; 6178 u8 wrps_status[0x4]; 6179 6180 u8 reserved_5[0x8]; 6181 u8 up_threshold[0x8]; 6182 u8 reserved_6[0x8]; 6183 u8 down_threshold[0x8]; 6184 6185 u8 reserved_7[0x20]; 6186 6187 u8 reserved_8[0x1c]; 6188 u8 srps_admin[0x4]; 6189 6190 u8 reserved_9[0x1c]; 6191 u8 srps_status[0x4]; 6192 6193 u8 reserved_10[0x40]; 6194 }; 6195 6196 struct mlx5_ifc_pplr_reg_bits { 6197 u8 reserved_0[0x8]; 6198 u8 local_port[0x8]; 6199 u8 reserved_1[0x10]; 6200 6201 u8 reserved_2[0x8]; 6202 u8 lb_cap[0x8]; 6203 u8 reserved_3[0x8]; 6204 u8 lb_en[0x8]; 6205 }; 6206 6207 struct mlx5_ifc_pplm_reg_bits { 6208 u8 reserved_0[0x8]; 6209 u8 local_port[0x8]; 6210 u8 reserved_1[0x10]; 6211 6212 u8 reserved_2[0x20]; 6213 6214 u8 port_profile_mode[0x8]; 6215 u8 static_port_profile[0x8]; 6216 u8 active_port_profile[0x8]; 6217 u8 reserved_3[0x8]; 6218 6219 u8 retransmission_active[0x8]; 6220 u8 fec_mode_active[0x18]; 6221 6222 u8 reserved_4[0x20]; 6223 }; 6224 6225 struct mlx5_ifc_ppcnt_reg_bits { 6226 u8 swid[0x8]; 6227 u8 local_port[0x8]; 6228 u8 pnat[0x2]; 6229 u8 reserved_0[0x8]; 6230 u8 grp[0x6]; 6231 6232 u8 clr[0x1]; 6233 u8 reserved_1[0x1c]; 6234 u8 prio_tc[0x3]; 6235 6236 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 6237 }; 6238 6239 struct mlx5_ifc_ppad_reg_bits { 6240 u8 reserved_0[0x3]; 6241 u8 single_mac[0x1]; 6242 u8 reserved_1[0x4]; 6243 u8 local_port[0x8]; 6244 u8 mac_47_32[0x10]; 6245 6246 u8 mac_31_0[0x20]; 6247 6248 u8 reserved_2[0x40]; 6249 }; 6250 6251 struct mlx5_ifc_pmtu_reg_bits { 6252 u8 reserved_0[0x8]; 6253 u8 local_port[0x8]; 6254 u8 reserved_1[0x10]; 6255 6256 u8 max_mtu[0x10]; 6257 u8 reserved_2[0x10]; 6258 6259 u8 admin_mtu[0x10]; 6260 u8 reserved_3[0x10]; 6261 6262 u8 oper_mtu[0x10]; 6263 u8 reserved_4[0x10]; 6264 }; 6265 6266 struct mlx5_ifc_pmpr_reg_bits { 6267 u8 reserved_0[0x8]; 6268 u8 module[0x8]; 6269 u8 reserved_1[0x10]; 6270 6271 u8 reserved_2[0x18]; 6272 u8 attenuation_5g[0x8]; 6273 6274 u8 reserved_3[0x18]; 6275 u8 attenuation_7g[0x8]; 6276 6277 u8 reserved_4[0x18]; 6278 u8 attenuation_12g[0x8]; 6279 }; 6280 6281 struct mlx5_ifc_pmpe_reg_bits { 6282 u8 reserved_0[0x8]; 6283 u8 module[0x8]; 6284 u8 reserved_1[0xc]; 6285 u8 module_status[0x4]; 6286 6287 u8 reserved_2[0x60]; 6288 }; 6289 6290 struct mlx5_ifc_pmpc_reg_bits { 6291 u8 module_state_updated[32][0x8]; 6292 }; 6293 6294 struct mlx5_ifc_pmlpn_reg_bits { 6295 u8 reserved_0[0x4]; 6296 u8 mlpn_status[0x4]; 6297 u8 local_port[0x8]; 6298 u8 reserved_1[0x10]; 6299 6300 u8 e[0x1]; 6301 u8 reserved_2[0x1f]; 6302 }; 6303 6304 struct mlx5_ifc_pmlp_reg_bits { 6305 u8 rxtx[0x1]; 6306 u8 reserved_0[0x7]; 6307 u8 local_port[0x8]; 6308 u8 reserved_1[0x8]; 6309 u8 width[0x8]; 6310 6311 u8 lane0_module_mapping[0x20]; 6312 6313 u8 lane1_module_mapping[0x20]; 6314 6315 u8 lane2_module_mapping[0x20]; 6316 6317 u8 lane3_module_mapping[0x20]; 6318 6319 u8 reserved_2[0x160]; 6320 }; 6321 6322 struct mlx5_ifc_pmaos_reg_bits { 6323 u8 reserved_0[0x8]; 6324 u8 module[0x8]; 6325 u8 reserved_1[0x4]; 6326 u8 admin_status[0x4]; 6327 u8 reserved_2[0x4]; 6328 u8 oper_status[0x4]; 6329 6330 u8 ase[0x1]; 6331 u8 ee[0x1]; 6332 u8 reserved_3[0x1c]; 6333 u8 e[0x2]; 6334 6335 u8 reserved_4[0x40]; 6336 }; 6337 6338 struct mlx5_ifc_plpc_reg_bits { 6339 u8 reserved_0[0x4]; 6340 u8 profile_id[0xc]; 6341 u8 reserved_1[0x4]; 6342 u8 proto_mask[0x4]; 6343 u8 reserved_2[0x8]; 6344 6345 u8 reserved_3[0x10]; 6346 u8 lane_speed[0x10]; 6347 6348 u8 reserved_4[0x17]; 6349 u8 lpbf[0x1]; 6350 u8 fec_mode_policy[0x8]; 6351 6352 u8 retransmission_capability[0x8]; 6353 u8 fec_mode_capability[0x18]; 6354 6355 u8 retransmission_support_admin[0x8]; 6356 u8 fec_mode_support_admin[0x18]; 6357 6358 u8 retransmission_request_admin[0x8]; 6359 u8 fec_mode_request_admin[0x18]; 6360 6361 u8 reserved_5[0x80]; 6362 }; 6363 6364 struct mlx5_ifc_plib_reg_bits { 6365 u8 reserved_0[0x8]; 6366 u8 local_port[0x8]; 6367 u8 reserved_1[0x8]; 6368 u8 ib_port[0x8]; 6369 6370 u8 reserved_2[0x60]; 6371 }; 6372 6373 struct mlx5_ifc_plbf_reg_bits { 6374 u8 reserved_0[0x8]; 6375 u8 local_port[0x8]; 6376 u8 reserved_1[0xd]; 6377 u8 lbf_mode[0x3]; 6378 6379 u8 reserved_2[0x20]; 6380 }; 6381 6382 struct mlx5_ifc_pipg_reg_bits { 6383 u8 reserved_0[0x8]; 6384 u8 local_port[0x8]; 6385 u8 reserved_1[0x10]; 6386 6387 u8 dic[0x1]; 6388 u8 reserved_2[0x19]; 6389 u8 ipg[0x4]; 6390 u8 reserved_3[0x2]; 6391 }; 6392 6393 struct mlx5_ifc_pifr_reg_bits { 6394 u8 reserved_0[0x8]; 6395 u8 local_port[0x8]; 6396 u8 reserved_1[0x10]; 6397 6398 u8 reserved_2[0xe0]; 6399 6400 u8 port_filter[8][0x20]; 6401 6402 u8 port_filter_update_en[8][0x20]; 6403 }; 6404 6405 struct mlx5_ifc_pfcc_reg_bits { 6406 u8 reserved_0[0x8]; 6407 u8 local_port[0x8]; 6408 u8 reserved_1[0x10]; 6409 6410 u8 ppan[0x4]; 6411 u8 reserved_2[0x4]; 6412 u8 prio_mask_tx[0x8]; 6413 u8 reserved_3[0x8]; 6414 u8 prio_mask_rx[0x8]; 6415 6416 u8 pptx[0x1]; 6417 u8 aptx[0x1]; 6418 u8 reserved_4[0x6]; 6419 u8 pfctx[0x8]; 6420 u8 reserved_5[0x10]; 6421 6422 u8 pprx[0x1]; 6423 u8 aprx[0x1]; 6424 u8 reserved_6[0x6]; 6425 u8 pfcrx[0x8]; 6426 u8 reserved_7[0x10]; 6427 6428 u8 reserved_8[0x80]; 6429 }; 6430 6431 struct mlx5_ifc_pelc_reg_bits { 6432 u8 op[0x4]; 6433 u8 reserved_0[0x4]; 6434 u8 local_port[0x8]; 6435 u8 reserved_1[0x10]; 6436 6437 u8 op_admin[0x8]; 6438 u8 op_capability[0x8]; 6439 u8 op_request[0x8]; 6440 u8 op_active[0x8]; 6441 6442 u8 admin[0x40]; 6443 6444 u8 capability[0x40]; 6445 6446 u8 request[0x40]; 6447 6448 u8 active[0x40]; 6449 6450 u8 reserved_2[0x80]; 6451 }; 6452 6453 struct mlx5_ifc_peir_reg_bits { 6454 u8 reserved_0[0x8]; 6455 u8 local_port[0x8]; 6456 u8 reserved_1[0x10]; 6457 6458 u8 reserved_2[0xc]; 6459 u8 error_count[0x4]; 6460 u8 reserved_3[0x10]; 6461 6462 u8 reserved_4[0xc]; 6463 u8 lane[0x4]; 6464 u8 reserved_5[0x8]; 6465 u8 error_type[0x8]; 6466 }; 6467 6468 struct mlx5_ifc_pcap_reg_bits { 6469 u8 reserved_0[0x8]; 6470 u8 local_port[0x8]; 6471 u8 reserved_1[0x10]; 6472 6473 u8 port_capability_mask[4][0x20]; 6474 }; 6475 6476 struct mlx5_ifc_paos_reg_bits { 6477 u8 swid[0x8]; 6478 u8 local_port[0x8]; 6479 u8 reserved_0[0x4]; 6480 u8 admin_status[0x4]; 6481 u8 reserved_1[0x4]; 6482 u8 oper_status[0x4]; 6483 6484 u8 ase[0x1]; 6485 u8 ee[0x1]; 6486 u8 reserved_2[0x1c]; 6487 u8 e[0x2]; 6488 6489 u8 reserved_3[0x40]; 6490 }; 6491 6492 struct mlx5_ifc_pamp_reg_bits { 6493 u8 reserved_0[0x8]; 6494 u8 opamp_group[0x8]; 6495 u8 reserved_1[0xc]; 6496 u8 opamp_group_type[0x4]; 6497 6498 u8 start_index[0x10]; 6499 u8 reserved_2[0x4]; 6500 u8 num_of_indices[0xc]; 6501 6502 u8 index_data[18][0x10]; 6503 }; 6504 6505 struct mlx5_ifc_lane_2_module_mapping_bits { 6506 u8 reserved_0[0x6]; 6507 u8 rx_lane[0x2]; 6508 u8 reserved_1[0x6]; 6509 u8 tx_lane[0x2]; 6510 u8 reserved_2[0x8]; 6511 u8 module[0x8]; 6512 }; 6513 6514 struct mlx5_ifc_bufferx_reg_bits { 6515 u8 reserved_0[0x6]; 6516 u8 lossy[0x1]; 6517 u8 epsb[0x1]; 6518 u8 reserved_1[0xc]; 6519 u8 size[0xc]; 6520 6521 u8 xoff_threshold[0x10]; 6522 u8 xon_threshold[0x10]; 6523 }; 6524 6525 struct mlx5_ifc_set_node_in_bits { 6526 u8 node_description[64][0x8]; 6527 }; 6528 6529 struct mlx5_ifc_register_power_settings_bits { 6530 u8 reserved_0[0x18]; 6531 u8 power_settings_level[0x8]; 6532 6533 u8 reserved_1[0x60]; 6534 }; 6535 6536 struct mlx5_ifc_register_host_endianness_bits { 6537 u8 he[0x1]; 6538 u8 reserved_0[0x1f]; 6539 6540 u8 reserved_1[0x60]; 6541 }; 6542 6543 struct mlx5_ifc_umr_pointer_desc_argument_bits { 6544 u8 reserved_0[0x20]; 6545 6546 u8 mkey[0x20]; 6547 6548 u8 addressh_63_32[0x20]; 6549 6550 u8 addressl_31_0[0x20]; 6551 }; 6552 6553 struct mlx5_ifc_ud_adrs_vector_bits { 6554 u8 dc_key[0x40]; 6555 6556 u8 ext[0x1]; 6557 u8 reserved_0[0x7]; 6558 u8 destination_qp_dct[0x18]; 6559 6560 u8 static_rate[0x4]; 6561 u8 sl_eth_prio[0x4]; 6562 u8 fl[0x1]; 6563 u8 mlid[0x7]; 6564 u8 rlid_udp_sport[0x10]; 6565 6566 u8 reserved_1[0x20]; 6567 6568 u8 rmac_47_16[0x20]; 6569 6570 u8 rmac_15_0[0x10]; 6571 u8 tclass[0x8]; 6572 u8 hop_limit[0x8]; 6573 6574 u8 reserved_2[0x1]; 6575 u8 grh[0x1]; 6576 u8 reserved_3[0x2]; 6577 u8 src_addr_index[0x8]; 6578 u8 flow_label[0x14]; 6579 6580 u8 rgid_rip[16][0x8]; 6581 }; 6582 6583 struct mlx5_ifc_pages_req_event_bits { 6584 u8 reserved_0[0x10]; 6585 u8 function_id[0x10]; 6586 6587 u8 num_pages[0x20]; 6588 6589 u8 reserved_1[0xa0]; 6590 }; 6591 6592 struct mlx5_ifc_eqe_bits { 6593 u8 reserved_0[0x8]; 6594 u8 event_type[0x8]; 6595 u8 reserved_1[0x8]; 6596 u8 event_sub_type[0x8]; 6597 6598 u8 reserved_2[0xe0]; 6599 6600 union mlx5_ifc_event_auto_bits event_data; 6601 6602 u8 reserved_3[0x10]; 6603 u8 signature[0x8]; 6604 u8 reserved_4[0x7]; 6605 u8 owner[0x1]; 6606 }; 6607 6608 enum { 6609 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 6610 }; 6611 6612 struct mlx5_ifc_cmd_queue_entry_bits { 6613 u8 type[0x8]; 6614 u8 reserved_0[0x18]; 6615 6616 u8 input_length[0x20]; 6617 6618 u8 input_mailbox_pointer_63_32[0x20]; 6619 6620 u8 input_mailbox_pointer_31_9[0x17]; 6621 u8 reserved_1[0x9]; 6622 6623 u8 command_input_inline_data[16][0x8]; 6624 6625 u8 command_output_inline_data[16][0x8]; 6626 6627 u8 output_mailbox_pointer_63_32[0x20]; 6628 6629 u8 output_mailbox_pointer_31_9[0x17]; 6630 u8 reserved_2[0x9]; 6631 6632 u8 output_length[0x20]; 6633 6634 u8 token[0x8]; 6635 u8 signature[0x8]; 6636 u8 reserved_3[0x8]; 6637 u8 status[0x7]; 6638 u8 ownership[0x1]; 6639 }; 6640 6641 struct mlx5_ifc_cmd_out_bits { 6642 u8 status[0x8]; 6643 u8 reserved_0[0x18]; 6644 6645 u8 syndrome[0x20]; 6646 6647 u8 command_output[0x20]; 6648 }; 6649 6650 struct mlx5_ifc_cmd_in_bits { 6651 u8 opcode[0x10]; 6652 u8 reserved_0[0x10]; 6653 6654 u8 reserved_1[0x10]; 6655 u8 op_mod[0x10]; 6656 6657 u8 command[0][0x20]; 6658 }; 6659 6660 struct mlx5_ifc_cmd_if_box_bits { 6661 u8 mailbox_data[512][0x8]; 6662 6663 u8 reserved_0[0x180]; 6664 6665 u8 next_pointer_63_32[0x20]; 6666 6667 u8 next_pointer_31_10[0x16]; 6668 u8 reserved_1[0xa]; 6669 6670 u8 block_number[0x20]; 6671 6672 u8 reserved_2[0x8]; 6673 u8 token[0x8]; 6674 u8 ctrl_signature[0x8]; 6675 u8 signature[0x8]; 6676 }; 6677 6678 struct mlx5_ifc_mtt_bits { 6679 u8 ptag_63_32[0x20]; 6680 6681 u8 ptag_31_8[0x18]; 6682 u8 reserved_0[0x6]; 6683 u8 wr_en[0x1]; 6684 u8 rd_en[0x1]; 6685 }; 6686 6687 enum { 6688 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 6689 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 6690 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 6691 }; 6692 6693 enum { 6694 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 6695 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 6696 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 6697 }; 6698 6699 enum { 6700 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 6701 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 6702 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 6703 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 6704 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 6705 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 6706 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 6707 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 6708 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 6709 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 6710 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 6711 }; 6712 6713 struct mlx5_ifc_initial_seg_bits { 6714 u8 fw_rev_minor[0x10]; 6715 u8 fw_rev_major[0x10]; 6716 6717 u8 cmd_interface_rev[0x10]; 6718 u8 fw_rev_subminor[0x10]; 6719 6720 u8 reserved_0[0x40]; 6721 6722 u8 cmdq_phy_addr_63_32[0x20]; 6723 6724 u8 cmdq_phy_addr_31_12[0x14]; 6725 u8 reserved_1[0x2]; 6726 u8 nic_interface[0x2]; 6727 u8 log_cmdq_size[0x4]; 6728 u8 log_cmdq_stride[0x4]; 6729 6730 u8 command_doorbell_vector[0x20]; 6731 6732 u8 reserved_2[0xf00]; 6733 6734 u8 initializing[0x1]; 6735 u8 reserved_3[0x4]; 6736 u8 nic_interface_supported[0x3]; 6737 u8 reserved_4[0x18]; 6738 6739 struct mlx5_ifc_health_buffer_bits health_buffer; 6740 6741 u8 no_dram_nic_offset[0x20]; 6742 6743 u8 reserved_5[0x6e40]; 6744 6745 u8 reserved_6[0x1f]; 6746 u8 clear_int[0x1]; 6747 6748 u8 health_syndrome[0x8]; 6749 u8 health_counter[0x18]; 6750 6751 u8 reserved_7[0x17fc0]; 6752 }; 6753 6754 union mlx5_ifc_ports_control_registers_document_bits { 6755 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 6756 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 6757 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 6758 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 6759 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 6760 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 6761 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 6762 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 6763 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 6764 struct mlx5_ifc_pamp_reg_bits pamp_reg; 6765 struct mlx5_ifc_paos_reg_bits paos_reg; 6766 struct mlx5_ifc_pcap_reg_bits pcap_reg; 6767 struct mlx5_ifc_peir_reg_bits peir_reg; 6768 struct mlx5_ifc_pelc_reg_bits pelc_reg; 6769 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 6770 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 6771 struct mlx5_ifc_pifr_reg_bits pifr_reg; 6772 struct mlx5_ifc_pipg_reg_bits pipg_reg; 6773 struct mlx5_ifc_plbf_reg_bits plbf_reg; 6774 struct mlx5_ifc_plib_reg_bits plib_reg; 6775 struct mlx5_ifc_plpc_reg_bits plpc_reg; 6776 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 6777 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 6778 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 6779 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 6780 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 6781 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 6782 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 6783 struct mlx5_ifc_ppad_reg_bits ppad_reg; 6784 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 6785 struct mlx5_ifc_pplm_reg_bits pplm_reg; 6786 struct mlx5_ifc_pplr_reg_bits pplr_reg; 6787 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 6788 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 6789 struct mlx5_ifc_pspa_reg_bits pspa_reg; 6790 struct mlx5_ifc_ptas_reg_bits ptas_reg; 6791 struct mlx5_ifc_ptys_reg_bits ptys_reg; 6792 struct mlx5_ifc_pude_reg_bits pude_reg; 6793 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 6794 struct mlx5_ifc_slrg_reg_bits slrg_reg; 6795 struct mlx5_ifc_sltp_reg_bits sltp_reg; 6796 u8 reserved_0[0x60e0]; 6797 }; 6798 6799 union mlx5_ifc_debug_enhancements_document_bits { 6800 struct mlx5_ifc_health_buffer_bits health_buffer; 6801 u8 reserved_0[0x200]; 6802 }; 6803 6804 union mlx5_ifc_uplink_pci_interface_document_bits { 6805 struct mlx5_ifc_initial_seg_bits initial_seg; 6806 u8 reserved_0[0x20060]; 6807 }; 6808 6809 #endif /* MLX5_IFC_H */ 6810