1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 84 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 85 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 86 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 87 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 88 MLX5_OBJ_TYPE_STC = 0x0040, 89 MLX5_OBJ_TYPE_RTC = 0x0041, 90 MLX5_OBJ_TYPE_STE = 0x0042, 91 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043, 92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15, 108 }; 109 110 enum { 111 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 112 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 114 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 115 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 116 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 117 }; 118 119 enum { 120 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 121 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 122 MLX5_CMD_OP_INIT_HCA = 0x102, 123 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 124 MLX5_CMD_OP_ENABLE_HCA = 0x104, 125 MLX5_CMD_OP_DISABLE_HCA = 0x105, 126 MLX5_CMD_OP_QUERY_PAGES = 0x107, 127 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 128 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 129 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 130 MLX5_CMD_OP_SET_ISSI = 0x10b, 131 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 132 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 133 MLX5_CMD_OP_ALLOC_SF = 0x113, 134 MLX5_CMD_OP_DEALLOC_SF = 0x114, 135 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 136 MLX5_CMD_OP_RESUME_VHCA = 0x116, 137 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 138 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 139 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 140 MLX5_CMD_OP_CREATE_MKEY = 0x200, 141 MLX5_CMD_OP_QUERY_MKEY = 0x201, 142 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 143 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 144 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 145 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 146 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 147 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 148 MLX5_CMD_OP_CREATE_EQ = 0x301, 149 MLX5_CMD_OP_DESTROY_EQ = 0x302, 150 MLX5_CMD_OP_QUERY_EQ = 0x303, 151 MLX5_CMD_OP_GEN_EQE = 0x304, 152 MLX5_CMD_OP_CREATE_CQ = 0x400, 153 MLX5_CMD_OP_DESTROY_CQ = 0x401, 154 MLX5_CMD_OP_QUERY_CQ = 0x402, 155 MLX5_CMD_OP_MODIFY_CQ = 0x403, 156 MLX5_CMD_OP_CREATE_QP = 0x500, 157 MLX5_CMD_OP_DESTROY_QP = 0x501, 158 MLX5_CMD_OP_RST2INIT_QP = 0x502, 159 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 160 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 161 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 162 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 163 MLX5_CMD_OP_2ERR_QP = 0x507, 164 MLX5_CMD_OP_2RST_QP = 0x50a, 165 MLX5_CMD_OP_QUERY_QP = 0x50b, 166 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 167 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 168 MLX5_CMD_OP_CREATE_PSV = 0x600, 169 MLX5_CMD_OP_DESTROY_PSV = 0x601, 170 MLX5_CMD_OP_CREATE_SRQ = 0x700, 171 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 172 MLX5_CMD_OP_QUERY_SRQ = 0x702, 173 MLX5_CMD_OP_ARM_RQ = 0x703, 174 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 175 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 176 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 177 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 178 MLX5_CMD_OP_CREATE_DCT = 0x710, 179 MLX5_CMD_OP_DESTROY_DCT = 0x711, 180 MLX5_CMD_OP_DRAIN_DCT = 0x712, 181 MLX5_CMD_OP_QUERY_DCT = 0x713, 182 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 183 MLX5_CMD_OP_CREATE_XRQ = 0x717, 184 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 185 MLX5_CMD_OP_QUERY_XRQ = 0x719, 186 MLX5_CMD_OP_ARM_XRQ = 0x71a, 187 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 188 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 189 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 190 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 191 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 192 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 193 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 194 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 195 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 196 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 197 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 198 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 199 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 200 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 202 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 203 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 204 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 205 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 206 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 207 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 208 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 209 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 210 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 211 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 212 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 213 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 214 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 215 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 216 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 217 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 218 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 219 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 220 MLX5_CMD_OP_ALLOC_PD = 0x800, 221 MLX5_CMD_OP_DEALLOC_PD = 0x801, 222 MLX5_CMD_OP_ALLOC_UAR = 0x802, 223 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 224 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 225 MLX5_CMD_OP_ACCESS_REG = 0x805, 226 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 227 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 228 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 229 MLX5_CMD_OP_MAD_IFC = 0x50d, 230 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 231 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 232 MLX5_CMD_OP_NOP = 0x80d, 233 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 234 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 235 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 236 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 237 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 238 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 239 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 240 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 241 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 242 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 243 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 244 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 245 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 246 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 247 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 248 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 249 MLX5_CMD_OP_CREATE_LAG = 0x840, 250 MLX5_CMD_OP_MODIFY_LAG = 0x841, 251 MLX5_CMD_OP_QUERY_LAG = 0x842, 252 MLX5_CMD_OP_DESTROY_LAG = 0x843, 253 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 254 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 255 MLX5_CMD_OP_CREATE_TIR = 0x900, 256 MLX5_CMD_OP_MODIFY_TIR = 0x901, 257 MLX5_CMD_OP_DESTROY_TIR = 0x902, 258 MLX5_CMD_OP_QUERY_TIR = 0x903, 259 MLX5_CMD_OP_CREATE_SQ = 0x904, 260 MLX5_CMD_OP_MODIFY_SQ = 0x905, 261 MLX5_CMD_OP_DESTROY_SQ = 0x906, 262 MLX5_CMD_OP_QUERY_SQ = 0x907, 263 MLX5_CMD_OP_CREATE_RQ = 0x908, 264 MLX5_CMD_OP_MODIFY_RQ = 0x909, 265 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 266 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 267 MLX5_CMD_OP_QUERY_RQ = 0x90b, 268 MLX5_CMD_OP_CREATE_RMP = 0x90c, 269 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 270 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 271 MLX5_CMD_OP_QUERY_RMP = 0x90f, 272 MLX5_CMD_OP_CREATE_TIS = 0x912, 273 MLX5_CMD_OP_MODIFY_TIS = 0x913, 274 MLX5_CMD_OP_DESTROY_TIS = 0x914, 275 MLX5_CMD_OP_QUERY_TIS = 0x915, 276 MLX5_CMD_OP_CREATE_RQT = 0x916, 277 MLX5_CMD_OP_MODIFY_RQT = 0x917, 278 MLX5_CMD_OP_DESTROY_RQT = 0x918, 279 MLX5_CMD_OP_QUERY_RQT = 0x919, 280 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 281 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 282 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 283 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 284 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 285 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 286 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 287 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 288 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 289 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 290 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 291 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 292 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 293 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 294 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 295 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 296 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 297 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 298 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 299 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 300 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 301 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 302 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 303 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 304 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 305 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 306 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 307 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 308 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 309 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 310 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 311 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 312 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 313 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 314 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 315 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 316 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 317 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 318 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 319 MLX5_CMD_OPCODE_QUERY_VUID = 0xb22, 320 MLX5_CMD_OP_MAX 321 }; 322 323 /* Valid range for general commands that don't work over an object */ 324 enum { 325 MLX5_CMD_OP_GENERAL_START = 0xb00, 326 MLX5_CMD_OP_GENERAL_END = 0xd00, 327 }; 328 329 enum { 330 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 331 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 332 }; 333 334 enum { 335 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 336 }; 337 338 struct mlx5_ifc_flow_table_fields_supported_bits { 339 u8 outer_dmac[0x1]; 340 u8 outer_smac[0x1]; 341 u8 outer_ether_type[0x1]; 342 u8 outer_ip_version[0x1]; 343 u8 outer_first_prio[0x1]; 344 u8 outer_first_cfi[0x1]; 345 u8 outer_first_vid[0x1]; 346 u8 outer_ipv4_ttl[0x1]; 347 u8 outer_second_prio[0x1]; 348 u8 outer_second_cfi[0x1]; 349 u8 outer_second_vid[0x1]; 350 u8 reserved_at_b[0x1]; 351 u8 outer_sip[0x1]; 352 u8 outer_dip[0x1]; 353 u8 outer_frag[0x1]; 354 u8 outer_ip_protocol[0x1]; 355 u8 outer_ip_ecn[0x1]; 356 u8 outer_ip_dscp[0x1]; 357 u8 outer_udp_sport[0x1]; 358 u8 outer_udp_dport[0x1]; 359 u8 outer_tcp_sport[0x1]; 360 u8 outer_tcp_dport[0x1]; 361 u8 outer_tcp_flags[0x1]; 362 u8 outer_gre_protocol[0x1]; 363 u8 outer_gre_key[0x1]; 364 u8 outer_vxlan_vni[0x1]; 365 u8 outer_geneve_vni[0x1]; 366 u8 outer_geneve_oam[0x1]; 367 u8 outer_geneve_protocol_type[0x1]; 368 u8 outer_geneve_opt_len[0x1]; 369 u8 source_vhca_port[0x1]; 370 u8 source_eswitch_port[0x1]; 371 372 u8 inner_dmac[0x1]; 373 u8 inner_smac[0x1]; 374 u8 inner_ether_type[0x1]; 375 u8 inner_ip_version[0x1]; 376 u8 inner_first_prio[0x1]; 377 u8 inner_first_cfi[0x1]; 378 u8 inner_first_vid[0x1]; 379 u8 reserved_at_27[0x1]; 380 u8 inner_second_prio[0x1]; 381 u8 inner_second_cfi[0x1]; 382 u8 inner_second_vid[0x1]; 383 u8 reserved_at_2b[0x1]; 384 u8 inner_sip[0x1]; 385 u8 inner_dip[0x1]; 386 u8 inner_frag[0x1]; 387 u8 inner_ip_protocol[0x1]; 388 u8 inner_ip_ecn[0x1]; 389 u8 inner_ip_dscp[0x1]; 390 u8 inner_udp_sport[0x1]; 391 u8 inner_udp_dport[0x1]; 392 u8 inner_tcp_sport[0x1]; 393 u8 inner_tcp_dport[0x1]; 394 u8 inner_tcp_flags[0x1]; 395 u8 reserved_at_37[0x9]; 396 397 u8 geneve_tlv_option_0_data[0x1]; 398 u8 geneve_tlv_option_0_exist[0x1]; 399 u8 reserved_at_42[0x3]; 400 u8 outer_first_mpls_over_udp[0x4]; 401 u8 outer_first_mpls_over_gre[0x4]; 402 u8 inner_first_mpls[0x4]; 403 u8 outer_first_mpls[0x4]; 404 u8 reserved_at_55[0x2]; 405 u8 outer_esp_spi[0x1]; 406 u8 reserved_at_58[0x2]; 407 u8 bth_dst_qp[0x1]; 408 u8 reserved_at_5b[0x5]; 409 410 u8 reserved_at_60[0x18]; 411 u8 metadata_reg_c_7[0x1]; 412 u8 metadata_reg_c_6[0x1]; 413 u8 metadata_reg_c_5[0x1]; 414 u8 metadata_reg_c_4[0x1]; 415 u8 metadata_reg_c_3[0x1]; 416 u8 metadata_reg_c_2[0x1]; 417 u8 metadata_reg_c_1[0x1]; 418 u8 metadata_reg_c_0[0x1]; 419 }; 420 421 /* Table 2170 - Flow Table Fields Supported 2 Format */ 422 struct mlx5_ifc_flow_table_fields_supported_2_bits { 423 u8 reserved_at_0[0x2]; 424 u8 inner_l4_type[0x1]; 425 u8 outer_l4_type[0x1]; 426 u8 reserved_at_4[0xa]; 427 u8 bth_opcode[0x1]; 428 u8 reserved_at_f[0x1]; 429 u8 tunnel_header_0_1[0x1]; 430 u8 reserved_at_11[0xf]; 431 432 u8 reserved_at_20[0x60]; 433 }; 434 435 struct mlx5_ifc_flow_table_prop_layout_bits { 436 u8 ft_support[0x1]; 437 u8 reserved_at_1[0x1]; 438 u8 flow_counter[0x1]; 439 u8 flow_modify_en[0x1]; 440 u8 modify_root[0x1]; 441 u8 identified_miss_table_mode[0x1]; 442 u8 flow_table_modify[0x1]; 443 u8 reformat[0x1]; 444 u8 decap[0x1]; 445 u8 reset_root_to_default[0x1]; 446 u8 pop_vlan[0x1]; 447 u8 push_vlan[0x1]; 448 u8 reserved_at_c[0x1]; 449 u8 pop_vlan_2[0x1]; 450 u8 push_vlan_2[0x1]; 451 u8 reformat_and_vlan_action[0x1]; 452 u8 reserved_at_10[0x1]; 453 u8 sw_owner[0x1]; 454 u8 reformat_l3_tunnel_to_l2[0x1]; 455 u8 reformat_l2_to_l3_tunnel[0x1]; 456 u8 reformat_and_modify_action[0x1]; 457 u8 ignore_flow_level[0x1]; 458 u8 reserved_at_16[0x1]; 459 u8 table_miss_action_domain[0x1]; 460 u8 termination_table[0x1]; 461 u8 reformat_and_fwd_to_table[0x1]; 462 u8 reserved_at_1a[0x2]; 463 u8 ipsec_encrypt[0x1]; 464 u8 ipsec_decrypt[0x1]; 465 u8 sw_owner_v2[0x1]; 466 u8 reserved_at_1f[0x1]; 467 468 u8 termination_table_raw_traffic[0x1]; 469 u8 reserved_at_21[0x1]; 470 u8 log_max_ft_size[0x6]; 471 u8 log_max_modify_header_context[0x8]; 472 u8 max_modify_header_actions[0x8]; 473 u8 max_ft_level[0x8]; 474 475 u8 reformat_add_esp_trasport[0x1]; 476 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 477 u8 reformat_add_esp_transport_over_udp[0x1]; 478 u8 reformat_del_esp_trasport[0x1]; 479 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 480 u8 reformat_del_esp_transport_over_udp[0x1]; 481 u8 execute_aso[0x1]; 482 u8 reserved_at_47[0x19]; 483 484 u8 reserved_at_60[0x2]; 485 u8 reformat_insert[0x1]; 486 u8 reformat_remove[0x1]; 487 u8 macsec_encrypt[0x1]; 488 u8 macsec_decrypt[0x1]; 489 u8 reserved_at_66[0x2]; 490 u8 reformat_add_macsec[0x1]; 491 u8 reformat_remove_macsec[0x1]; 492 u8 reparse[0x1]; 493 u8 reserved_at_6b[0x1]; 494 u8 cross_vhca_object[0x1]; 495 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 496 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 497 u8 ignore_flow_level_rtc_valid[0x1]; 498 u8 reserved_at_70[0x8]; 499 u8 log_max_ft_num[0x8]; 500 501 u8 reserved_at_80[0x10]; 502 u8 log_max_flow_counter[0x8]; 503 u8 log_max_destination[0x8]; 504 505 u8 reserved_at_a0[0x18]; 506 u8 log_max_flow[0x8]; 507 508 u8 reserved_at_c0[0x40]; 509 510 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 511 512 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 513 }; 514 515 struct mlx5_ifc_odp_per_transport_service_cap_bits { 516 u8 send[0x1]; 517 u8 receive[0x1]; 518 u8 write[0x1]; 519 u8 read[0x1]; 520 u8 atomic[0x1]; 521 u8 srq_receive[0x1]; 522 u8 reserved_at_6[0x1a]; 523 }; 524 525 struct mlx5_ifc_ipv4_layout_bits { 526 u8 reserved_at_0[0x60]; 527 528 u8 ipv4[0x20]; 529 }; 530 531 struct mlx5_ifc_ipv6_layout_bits { 532 u8 ipv6[16][0x8]; 533 }; 534 535 struct mlx5_ifc_ipv6_simple_layout_bits { 536 u8 ipv6_127_96[0x20]; 537 u8 ipv6_95_64[0x20]; 538 u8 ipv6_63_32[0x20]; 539 u8 ipv6_31_0[0x20]; 540 }; 541 542 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 543 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout; 544 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 545 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 546 u8 reserved_at_0[0x80]; 547 }; 548 549 enum { 550 MLX5_PACKET_L4_TYPE_NONE, 551 MLX5_PACKET_L4_TYPE_TCP, 552 MLX5_PACKET_L4_TYPE_UDP, 553 }; 554 555 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 556 u8 smac_47_16[0x20]; 557 558 u8 smac_15_0[0x10]; 559 u8 ethertype[0x10]; 560 561 u8 dmac_47_16[0x20]; 562 563 u8 dmac_15_0[0x10]; 564 u8 first_prio[0x3]; 565 u8 first_cfi[0x1]; 566 u8 first_vid[0xc]; 567 568 u8 ip_protocol[0x8]; 569 u8 ip_dscp[0x6]; 570 u8 ip_ecn[0x2]; 571 u8 cvlan_tag[0x1]; 572 u8 svlan_tag[0x1]; 573 u8 frag[0x1]; 574 u8 ip_version[0x4]; 575 u8 tcp_flags[0x9]; 576 577 u8 tcp_sport[0x10]; 578 u8 tcp_dport[0x10]; 579 580 u8 l4_type[0x2]; 581 u8 reserved_at_c2[0xe]; 582 u8 ipv4_ihl[0x4]; 583 u8 reserved_at_c4[0x4]; 584 585 u8 ttl_hoplimit[0x8]; 586 587 u8 udp_sport[0x10]; 588 u8 udp_dport[0x10]; 589 590 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 591 592 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 593 }; 594 595 struct mlx5_ifc_nvgre_key_bits { 596 u8 hi[0x18]; 597 u8 lo[0x8]; 598 }; 599 600 union mlx5_ifc_gre_key_bits { 601 struct mlx5_ifc_nvgre_key_bits nvgre; 602 u8 key[0x20]; 603 }; 604 605 struct mlx5_ifc_fte_match_set_misc_bits { 606 u8 gre_c_present[0x1]; 607 u8 reserved_at_1[0x1]; 608 u8 gre_k_present[0x1]; 609 u8 gre_s_present[0x1]; 610 u8 source_vhca_port[0x4]; 611 u8 source_sqn[0x18]; 612 613 u8 source_eswitch_owner_vhca_id[0x10]; 614 u8 source_port[0x10]; 615 616 u8 outer_second_prio[0x3]; 617 u8 outer_second_cfi[0x1]; 618 u8 outer_second_vid[0xc]; 619 u8 inner_second_prio[0x3]; 620 u8 inner_second_cfi[0x1]; 621 u8 inner_second_vid[0xc]; 622 623 u8 outer_second_cvlan_tag[0x1]; 624 u8 inner_second_cvlan_tag[0x1]; 625 u8 outer_second_svlan_tag[0x1]; 626 u8 inner_second_svlan_tag[0x1]; 627 u8 reserved_at_64[0xc]; 628 u8 gre_protocol[0x10]; 629 630 union mlx5_ifc_gre_key_bits gre_key; 631 632 u8 vxlan_vni[0x18]; 633 u8 bth_opcode[0x8]; 634 635 u8 geneve_vni[0x18]; 636 u8 reserved_at_d8[0x6]; 637 u8 geneve_tlv_option_0_exist[0x1]; 638 u8 geneve_oam[0x1]; 639 640 u8 reserved_at_e0[0xc]; 641 u8 outer_ipv6_flow_label[0x14]; 642 643 u8 reserved_at_100[0xc]; 644 u8 inner_ipv6_flow_label[0x14]; 645 646 u8 reserved_at_120[0xa]; 647 u8 geneve_opt_len[0x6]; 648 u8 geneve_protocol_type[0x10]; 649 650 u8 reserved_at_140[0x8]; 651 u8 bth_dst_qp[0x18]; 652 u8 inner_esp_spi[0x20]; 653 u8 outer_esp_spi[0x20]; 654 u8 reserved_at_1a0[0x60]; 655 }; 656 657 struct mlx5_ifc_fte_match_mpls_bits { 658 u8 mpls_label[0x14]; 659 u8 mpls_exp[0x3]; 660 u8 mpls_s_bos[0x1]; 661 u8 mpls_ttl[0x8]; 662 }; 663 664 struct mlx5_ifc_fte_match_set_misc2_bits { 665 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 666 667 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 668 669 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 670 671 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 672 673 u8 metadata_reg_c_7[0x20]; 674 675 u8 metadata_reg_c_6[0x20]; 676 677 u8 metadata_reg_c_5[0x20]; 678 679 u8 metadata_reg_c_4[0x20]; 680 681 u8 metadata_reg_c_3[0x20]; 682 683 u8 metadata_reg_c_2[0x20]; 684 685 u8 metadata_reg_c_1[0x20]; 686 687 u8 metadata_reg_c_0[0x20]; 688 689 u8 metadata_reg_a[0x20]; 690 691 u8 reserved_at_1a0[0x8]; 692 693 u8 macsec_syndrome[0x8]; 694 u8 ipsec_syndrome[0x8]; 695 u8 reserved_at_1b8[0x8]; 696 697 u8 reserved_at_1c0[0x40]; 698 }; 699 700 struct mlx5_ifc_fte_match_set_misc3_bits { 701 u8 inner_tcp_seq_num[0x20]; 702 703 u8 outer_tcp_seq_num[0x20]; 704 705 u8 inner_tcp_ack_num[0x20]; 706 707 u8 outer_tcp_ack_num[0x20]; 708 709 u8 reserved_at_80[0x8]; 710 u8 outer_vxlan_gpe_vni[0x18]; 711 712 u8 outer_vxlan_gpe_next_protocol[0x8]; 713 u8 outer_vxlan_gpe_flags[0x8]; 714 u8 reserved_at_b0[0x10]; 715 716 u8 icmp_header_data[0x20]; 717 718 u8 icmpv6_header_data[0x20]; 719 720 u8 icmp_type[0x8]; 721 u8 icmp_code[0x8]; 722 u8 icmpv6_type[0x8]; 723 u8 icmpv6_code[0x8]; 724 725 u8 geneve_tlv_option_0_data[0x20]; 726 727 u8 gtpu_teid[0x20]; 728 729 u8 gtpu_msg_type[0x8]; 730 u8 gtpu_msg_flags[0x8]; 731 u8 reserved_at_170[0x10]; 732 733 u8 gtpu_dw_2[0x20]; 734 735 u8 gtpu_first_ext_dw_0[0x20]; 736 737 u8 gtpu_dw_0[0x20]; 738 739 u8 reserved_at_1e0[0x20]; 740 }; 741 742 struct mlx5_ifc_fte_match_set_misc4_bits { 743 u8 prog_sample_field_value_0[0x20]; 744 745 u8 prog_sample_field_id_0[0x20]; 746 747 u8 prog_sample_field_value_1[0x20]; 748 749 u8 prog_sample_field_id_1[0x20]; 750 751 u8 prog_sample_field_value_2[0x20]; 752 753 u8 prog_sample_field_id_2[0x20]; 754 755 u8 prog_sample_field_value_3[0x20]; 756 757 u8 prog_sample_field_id_3[0x20]; 758 759 u8 reserved_at_100[0x100]; 760 }; 761 762 struct mlx5_ifc_fte_match_set_misc5_bits { 763 u8 macsec_tag_0[0x20]; 764 765 u8 macsec_tag_1[0x20]; 766 767 u8 macsec_tag_2[0x20]; 768 769 u8 macsec_tag_3[0x20]; 770 771 u8 tunnel_header_0[0x20]; 772 773 u8 tunnel_header_1[0x20]; 774 775 u8 tunnel_header_2[0x20]; 776 777 u8 tunnel_header_3[0x20]; 778 779 u8 reserved_at_100[0x100]; 780 }; 781 782 struct mlx5_ifc_cmd_pas_bits { 783 u8 pa_h[0x20]; 784 785 u8 pa_l[0x14]; 786 u8 reserved_at_34[0xc]; 787 }; 788 789 struct mlx5_ifc_uint64_bits { 790 u8 hi[0x20]; 791 792 u8 lo[0x20]; 793 }; 794 795 enum { 796 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 797 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 798 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 799 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 800 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 801 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 802 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 803 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 804 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 805 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 806 }; 807 808 struct mlx5_ifc_ads_bits { 809 u8 fl[0x1]; 810 u8 free_ar[0x1]; 811 u8 reserved_at_2[0xe]; 812 u8 pkey_index[0x10]; 813 814 u8 plane_index[0x8]; 815 u8 grh[0x1]; 816 u8 mlid[0x7]; 817 u8 rlid[0x10]; 818 819 u8 ack_timeout[0x5]; 820 u8 reserved_at_45[0x3]; 821 u8 src_addr_index[0x8]; 822 u8 reserved_at_50[0x4]; 823 u8 stat_rate[0x4]; 824 u8 hop_limit[0x8]; 825 826 u8 reserved_at_60[0x4]; 827 u8 tclass[0x8]; 828 u8 flow_label[0x14]; 829 830 u8 rgid_rip[16][0x8]; 831 832 u8 reserved_at_100[0x4]; 833 u8 f_dscp[0x1]; 834 u8 f_ecn[0x1]; 835 u8 reserved_at_106[0x1]; 836 u8 f_eth_prio[0x1]; 837 u8 ecn[0x2]; 838 u8 dscp[0x6]; 839 u8 udp_sport[0x10]; 840 841 u8 dei_cfi[0x1]; 842 u8 eth_prio[0x3]; 843 u8 sl[0x4]; 844 u8 vhca_port_num[0x8]; 845 u8 rmac_47_32[0x10]; 846 847 u8 rmac_31_0[0x20]; 848 }; 849 850 struct mlx5_ifc_flow_table_nic_cap_bits { 851 u8 nic_rx_multi_path_tirs[0x1]; 852 u8 nic_rx_multi_path_tirs_fts[0x1]; 853 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 854 u8 reserved_at_3[0x4]; 855 u8 sw_owner_reformat_supported[0x1]; 856 u8 reserved_at_8[0x18]; 857 858 u8 encap_general_header[0x1]; 859 u8 reserved_at_21[0xa]; 860 u8 log_max_packet_reformat_context[0x5]; 861 u8 reserved_at_30[0x6]; 862 u8 max_encap_header_size[0xa]; 863 u8 reserved_at_40[0x1c0]; 864 865 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 866 867 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 868 869 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 870 871 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 872 873 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 874 875 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 876 877 u8 reserved_at_e00[0x600]; 878 879 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 880 881 u8 reserved_at_1480[0x80]; 882 883 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 884 885 u8 reserved_at_1580[0x280]; 886 887 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 888 889 u8 reserved_at_1880[0x780]; 890 891 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 892 893 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 894 895 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 896 897 u8 reserved_at_20c0[0x5f40]; 898 }; 899 900 struct mlx5_ifc_port_selection_cap_bits { 901 u8 reserved_at_0[0x10]; 902 u8 port_select_flow_table[0x1]; 903 u8 reserved_at_11[0x1]; 904 u8 port_select_flow_table_bypass[0x1]; 905 u8 reserved_at_13[0xd]; 906 907 u8 reserved_at_20[0x1e0]; 908 909 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 910 911 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 912 913 u8 reserved_at_480[0x7b80]; 914 }; 915 916 enum { 917 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 918 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 919 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 920 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 921 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 922 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 923 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 924 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 925 }; 926 927 struct mlx5_ifc_flow_table_eswitch_cap_bits { 928 u8 fdb_to_vport_reg_c_id[0x8]; 929 u8 reserved_at_8[0x5]; 930 u8 fdb_uplink_hairpin[0x1]; 931 u8 fdb_multi_path_any_table_limit_regc[0x1]; 932 u8 reserved_at_f[0x1]; 933 u8 fdb_dynamic_tunnel[0x1]; 934 u8 reserved_at_11[0x1]; 935 u8 fdb_multi_path_any_table[0x1]; 936 u8 reserved_at_13[0x2]; 937 u8 fdb_modify_header_fwd_to_table[0x1]; 938 u8 fdb_ipv4_ttl_modify[0x1]; 939 u8 flow_source[0x1]; 940 u8 reserved_at_18[0x2]; 941 u8 multi_fdb_encap[0x1]; 942 u8 egress_acl_forward_to_vport[0x1]; 943 u8 fdb_multi_path_to_table[0x1]; 944 u8 reserved_at_1d[0x3]; 945 946 u8 reserved_at_20[0x1e0]; 947 948 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 949 950 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 951 952 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 953 954 u8 reserved_at_800[0xC00]; 955 956 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 957 958 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 959 960 u8 reserved_at_1500[0x300]; 961 962 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 963 964 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 965 966 u8 sw_steering_uplink_icm_address_rx[0x40]; 967 968 u8 sw_steering_uplink_icm_address_tx[0x40]; 969 970 u8 reserved_at_1900[0x6700]; 971 }; 972 973 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 974 u8 reserved_at_0[0x3]; 975 u8 log_max_num_ste[0x5]; 976 u8 reserved_at_8[0x3]; 977 u8 log_max_num_stc[0x5]; 978 u8 reserved_at_10[0x3]; 979 u8 log_max_num_rtc[0x5]; 980 u8 reserved_at_18[0x3]; 981 u8 log_max_num_header_modify_pattern[0x5]; 982 983 u8 rtc_hash_split_table[0x1]; 984 u8 rtc_linear_lookup_table[0x1]; 985 u8 reserved_at_22[0x1]; 986 u8 stc_alloc_log_granularity[0x5]; 987 u8 reserved_at_28[0x3]; 988 u8 stc_alloc_log_max[0x5]; 989 u8 reserved_at_30[0x3]; 990 u8 ste_alloc_log_granularity[0x5]; 991 u8 reserved_at_38[0x3]; 992 u8 ste_alloc_log_max[0x5]; 993 994 u8 reserved_at_40[0xb]; 995 u8 rtc_reparse_mode[0x5]; 996 u8 reserved_at_50[0x3]; 997 u8 rtc_index_mode[0x5]; 998 u8 reserved_at_58[0x3]; 999 u8 rtc_log_depth_max[0x5]; 1000 1001 u8 reserved_at_60[0x10]; 1002 u8 ste_format[0x10]; 1003 1004 u8 stc_action_type[0x80]; 1005 1006 u8 header_insert_type[0x10]; 1007 u8 header_remove_type[0x10]; 1008 1009 u8 trivial_match_definer[0x20]; 1010 1011 u8 reserved_at_140[0x1b]; 1012 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 1013 1014 u8 reserved_at_160[0x18]; 1015 u8 access_index_mode[0x8]; 1016 1017 u8 reserved_at_180[0x10]; 1018 u8 ste_format_gen_wqe[0x10]; 1019 1020 u8 linear_match_definer_reg_c3[0x20]; 1021 1022 u8 fdb_jump_to_tir_stc[0x1]; 1023 u8 reserved_at_1c1[0x1f]; 1024 }; 1025 1026 struct mlx5_ifc_esw_cap_bits { 1027 u8 reserved_at_0[0x1d]; 1028 u8 merged_eswitch[0x1]; 1029 u8 reserved_at_1e[0x2]; 1030 1031 u8 reserved_at_20[0x40]; 1032 1033 u8 esw_manager_vport_number_valid[0x1]; 1034 u8 reserved_at_61[0xf]; 1035 u8 esw_manager_vport_number[0x10]; 1036 1037 u8 reserved_at_80[0x780]; 1038 }; 1039 1040 enum { 1041 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 1042 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 1043 }; 1044 1045 struct mlx5_ifc_e_switch_cap_bits { 1046 u8 vport_svlan_strip[0x1]; 1047 u8 vport_cvlan_strip[0x1]; 1048 u8 vport_svlan_insert[0x1]; 1049 u8 vport_cvlan_insert_if_not_exist[0x1]; 1050 u8 vport_cvlan_insert_overwrite[0x1]; 1051 u8 reserved_at_5[0x1]; 1052 u8 vport_cvlan_insert_always[0x1]; 1053 u8 esw_shared_ingress_acl[0x1]; 1054 u8 esw_uplink_ingress_acl[0x1]; 1055 u8 root_ft_on_other_esw[0x1]; 1056 u8 reserved_at_a[0xf]; 1057 u8 esw_functions_changed[0x1]; 1058 u8 reserved_at_1a[0x1]; 1059 u8 ecpf_vport_exists[0x1]; 1060 u8 counter_eswitch_affinity[0x1]; 1061 u8 merged_eswitch[0x1]; 1062 u8 nic_vport_node_guid_modify[0x1]; 1063 u8 nic_vport_port_guid_modify[0x1]; 1064 1065 u8 vxlan_encap_decap[0x1]; 1066 u8 nvgre_encap_decap[0x1]; 1067 u8 reserved_at_22[0x1]; 1068 u8 log_max_fdb_encap_uplink[0x5]; 1069 u8 reserved_at_21[0x3]; 1070 u8 log_max_packet_reformat_context[0x5]; 1071 u8 reserved_2b[0x6]; 1072 u8 max_encap_header_size[0xa]; 1073 1074 u8 reserved_at_40[0xb]; 1075 u8 log_max_esw_sf[0x5]; 1076 u8 esw_sf_base_id[0x10]; 1077 1078 u8 reserved_at_60[0x7a0]; 1079 1080 }; 1081 1082 struct mlx5_ifc_qos_cap_bits { 1083 u8 packet_pacing[0x1]; 1084 u8 esw_scheduling[0x1]; 1085 u8 esw_bw_share[0x1]; 1086 u8 esw_rate_limit[0x1]; 1087 u8 reserved_at_4[0x1]; 1088 u8 packet_pacing_burst_bound[0x1]; 1089 u8 packet_pacing_typical_size[0x1]; 1090 u8 reserved_at_7[0x1]; 1091 u8 nic_sq_scheduling[0x1]; 1092 u8 nic_bw_share[0x1]; 1093 u8 nic_rate_limit[0x1]; 1094 u8 packet_pacing_uid[0x1]; 1095 u8 log_esw_max_sched_depth[0x4]; 1096 u8 reserved_at_10[0x10]; 1097 1098 u8 reserved_at_20[0xb]; 1099 u8 log_max_qos_nic_queue_group[0x5]; 1100 u8 reserved_at_30[0x10]; 1101 1102 u8 packet_pacing_max_rate[0x20]; 1103 1104 u8 packet_pacing_min_rate[0x20]; 1105 1106 u8 reserved_at_80[0x10]; 1107 u8 packet_pacing_rate_table_size[0x10]; 1108 1109 u8 esw_element_type[0x10]; 1110 u8 esw_tsar_type[0x10]; 1111 1112 u8 reserved_at_c0[0x10]; 1113 u8 max_qos_para_vport[0x10]; 1114 1115 u8 max_tsar_bw_share[0x20]; 1116 1117 u8 nic_element_type[0x10]; 1118 u8 nic_tsar_type[0x10]; 1119 1120 u8 reserved_at_120[0x3]; 1121 u8 log_meter_aso_granularity[0x5]; 1122 u8 reserved_at_128[0x3]; 1123 u8 log_meter_aso_max_alloc[0x5]; 1124 u8 reserved_at_130[0x3]; 1125 u8 log_max_num_meter_aso[0x5]; 1126 u8 reserved_at_138[0x8]; 1127 1128 u8 reserved_at_140[0x6c0]; 1129 }; 1130 1131 struct mlx5_ifc_debug_cap_bits { 1132 u8 core_dump_general[0x1]; 1133 u8 core_dump_qp[0x1]; 1134 u8 reserved_at_2[0x7]; 1135 u8 resource_dump[0x1]; 1136 u8 reserved_at_a[0x16]; 1137 1138 u8 reserved_at_20[0x2]; 1139 u8 stall_detect[0x1]; 1140 u8 reserved_at_23[0x1d]; 1141 1142 u8 reserved_at_40[0x7c0]; 1143 }; 1144 1145 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1146 u8 csum_cap[0x1]; 1147 u8 vlan_cap[0x1]; 1148 u8 lro_cap[0x1]; 1149 u8 lro_psh_flag[0x1]; 1150 u8 lro_time_stamp[0x1]; 1151 u8 reserved_at_5[0x2]; 1152 u8 wqe_vlan_insert[0x1]; 1153 u8 self_lb_en_modifiable[0x1]; 1154 u8 reserved_at_9[0x2]; 1155 u8 max_lso_cap[0x5]; 1156 u8 multi_pkt_send_wqe[0x2]; 1157 u8 wqe_inline_mode[0x2]; 1158 u8 rss_ind_tbl_cap[0x4]; 1159 u8 reg_umr_sq[0x1]; 1160 u8 scatter_fcs[0x1]; 1161 u8 enhanced_multi_pkt_send_wqe[0x1]; 1162 u8 tunnel_lso_const_out_ip_id[0x1]; 1163 u8 tunnel_lro_gre[0x1]; 1164 u8 tunnel_lro_vxlan[0x1]; 1165 u8 tunnel_stateless_gre[0x1]; 1166 u8 tunnel_stateless_vxlan[0x1]; 1167 1168 u8 swp[0x1]; 1169 u8 swp_csum[0x1]; 1170 u8 swp_lso[0x1]; 1171 u8 cqe_checksum_full[0x1]; 1172 u8 tunnel_stateless_geneve_tx[0x1]; 1173 u8 tunnel_stateless_mpls_over_udp[0x1]; 1174 u8 tunnel_stateless_mpls_over_gre[0x1]; 1175 u8 tunnel_stateless_vxlan_gpe[0x1]; 1176 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1177 u8 tunnel_stateless_ip_over_ip[0x1]; 1178 u8 insert_trailer[0x1]; 1179 u8 reserved_at_2b[0x1]; 1180 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1181 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1182 u8 reserved_at_2e[0x2]; 1183 u8 max_vxlan_udp_ports[0x8]; 1184 u8 swp_csum_l4_partial[0x1]; 1185 u8 reserved_at_39[0x5]; 1186 u8 max_geneve_opt_len[0x1]; 1187 u8 tunnel_stateless_geneve_rx[0x1]; 1188 1189 u8 reserved_at_40[0x10]; 1190 u8 lro_min_mss_size[0x10]; 1191 1192 u8 reserved_at_60[0x120]; 1193 1194 u8 lro_timer_supported_periods[4][0x20]; 1195 1196 u8 reserved_at_200[0x600]; 1197 }; 1198 1199 enum { 1200 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1201 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1202 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1203 }; 1204 1205 struct mlx5_ifc_roce_cap_bits { 1206 u8 roce_apm[0x1]; 1207 u8 reserved_at_1[0x3]; 1208 u8 sw_r_roce_src_udp_port[0x1]; 1209 u8 fl_rc_qp_when_roce_disabled[0x1]; 1210 u8 fl_rc_qp_when_roce_enabled[0x1]; 1211 u8 roce_cc_general[0x1]; 1212 u8 qp_ooo_transmit_default[0x1]; 1213 u8 reserved_at_9[0x15]; 1214 u8 qp_ts_format[0x2]; 1215 1216 u8 reserved_at_20[0x60]; 1217 1218 u8 reserved_at_80[0xc]; 1219 u8 l3_type[0x4]; 1220 u8 reserved_at_90[0x8]; 1221 u8 roce_version[0x8]; 1222 1223 u8 reserved_at_a0[0x10]; 1224 u8 r_roce_dest_udp_port[0x10]; 1225 1226 u8 r_roce_max_src_udp_port[0x10]; 1227 u8 r_roce_min_src_udp_port[0x10]; 1228 1229 u8 reserved_at_e0[0x10]; 1230 u8 roce_address_table_size[0x10]; 1231 1232 u8 reserved_at_100[0x700]; 1233 }; 1234 1235 struct mlx5_ifc_sync_steering_in_bits { 1236 u8 opcode[0x10]; 1237 u8 uid[0x10]; 1238 1239 u8 reserved_at_20[0x10]; 1240 u8 op_mod[0x10]; 1241 1242 u8 reserved_at_40[0xc0]; 1243 }; 1244 1245 struct mlx5_ifc_sync_steering_out_bits { 1246 u8 status[0x8]; 1247 u8 reserved_at_8[0x18]; 1248 1249 u8 syndrome[0x20]; 1250 1251 u8 reserved_at_40[0x40]; 1252 }; 1253 1254 struct mlx5_ifc_sync_crypto_in_bits { 1255 u8 opcode[0x10]; 1256 u8 uid[0x10]; 1257 1258 u8 reserved_at_20[0x10]; 1259 u8 op_mod[0x10]; 1260 1261 u8 reserved_at_40[0x20]; 1262 1263 u8 reserved_at_60[0x10]; 1264 u8 crypto_type[0x10]; 1265 1266 u8 reserved_at_80[0x80]; 1267 }; 1268 1269 struct mlx5_ifc_sync_crypto_out_bits { 1270 u8 status[0x8]; 1271 u8 reserved_at_8[0x18]; 1272 1273 u8 syndrome[0x20]; 1274 1275 u8 reserved_at_40[0x40]; 1276 }; 1277 1278 struct mlx5_ifc_device_mem_cap_bits { 1279 u8 memic[0x1]; 1280 u8 reserved_at_1[0x1f]; 1281 1282 u8 reserved_at_20[0xb]; 1283 u8 log_min_memic_alloc_size[0x5]; 1284 u8 reserved_at_30[0x8]; 1285 u8 log_max_memic_addr_alignment[0x8]; 1286 1287 u8 memic_bar_start_addr[0x40]; 1288 1289 u8 memic_bar_size[0x20]; 1290 1291 u8 max_memic_size[0x20]; 1292 1293 u8 steering_sw_icm_start_address[0x40]; 1294 1295 u8 reserved_at_100[0x8]; 1296 u8 log_header_modify_sw_icm_size[0x8]; 1297 u8 reserved_at_110[0x2]; 1298 u8 log_sw_icm_alloc_granularity[0x6]; 1299 u8 log_steering_sw_icm_size[0x8]; 1300 1301 u8 log_indirect_encap_sw_icm_size[0x8]; 1302 u8 reserved_at_128[0x10]; 1303 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1304 1305 u8 header_modify_sw_icm_start_address[0x40]; 1306 1307 u8 reserved_at_180[0x40]; 1308 1309 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1310 1311 u8 memic_operations[0x20]; 1312 1313 u8 reserved_at_220[0x20]; 1314 1315 u8 indirect_encap_sw_icm_start_address[0x40]; 1316 1317 u8 reserved_at_280[0x580]; 1318 }; 1319 1320 struct mlx5_ifc_device_event_cap_bits { 1321 u8 user_affiliated_events[4][0x40]; 1322 1323 u8 user_unaffiliated_events[4][0x40]; 1324 }; 1325 1326 struct mlx5_ifc_virtio_emulation_cap_bits { 1327 u8 desc_tunnel_offload_type[0x1]; 1328 u8 eth_frame_offload_type[0x1]; 1329 u8 virtio_version_1_0[0x1]; 1330 u8 device_features_bits_mask[0xd]; 1331 u8 event_mode[0x8]; 1332 u8 virtio_queue_type[0x8]; 1333 1334 u8 max_tunnel_desc[0x10]; 1335 u8 reserved_at_30[0x3]; 1336 u8 log_doorbell_stride[0x5]; 1337 u8 reserved_at_38[0x3]; 1338 u8 log_doorbell_bar_size[0x5]; 1339 1340 u8 doorbell_bar_offset[0x40]; 1341 1342 u8 max_emulated_devices[0x8]; 1343 u8 max_num_virtio_queues[0x18]; 1344 1345 u8 reserved_at_a0[0x20]; 1346 1347 u8 reserved_at_c0[0x13]; 1348 u8 desc_group_mkey_supported[0x1]; 1349 u8 freeze_to_rdy_supported[0x1]; 1350 u8 reserved_at_d5[0xb]; 1351 1352 u8 reserved_at_e0[0x20]; 1353 1354 u8 umem_1_buffer_param_a[0x20]; 1355 1356 u8 umem_1_buffer_param_b[0x20]; 1357 1358 u8 umem_2_buffer_param_a[0x20]; 1359 1360 u8 umem_2_buffer_param_b[0x20]; 1361 1362 u8 umem_3_buffer_param_a[0x20]; 1363 1364 u8 umem_3_buffer_param_b[0x20]; 1365 1366 u8 reserved_at_1c0[0x640]; 1367 }; 1368 1369 enum { 1370 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1371 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1372 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1373 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1374 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1375 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1376 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1377 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1378 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1379 }; 1380 1381 enum { 1382 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1383 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1384 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1385 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1386 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1387 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1388 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1389 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1390 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1391 }; 1392 1393 struct mlx5_ifc_atomic_caps_bits { 1394 u8 reserved_at_0[0x40]; 1395 1396 u8 atomic_req_8B_endianness_mode[0x2]; 1397 u8 reserved_at_42[0x4]; 1398 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1399 1400 u8 reserved_at_47[0x19]; 1401 1402 u8 reserved_at_60[0x20]; 1403 1404 u8 reserved_at_80[0x10]; 1405 u8 atomic_operations[0x10]; 1406 1407 u8 reserved_at_a0[0x10]; 1408 u8 atomic_size_qp[0x10]; 1409 1410 u8 reserved_at_c0[0x10]; 1411 u8 atomic_size_dc[0x10]; 1412 1413 u8 reserved_at_e0[0x720]; 1414 }; 1415 1416 struct mlx5_ifc_odp_scheme_cap_bits { 1417 u8 reserved_at_0[0x40]; 1418 1419 u8 sig[0x1]; 1420 u8 reserved_at_41[0x4]; 1421 u8 page_prefetch[0x1]; 1422 u8 reserved_at_46[0x1a]; 1423 1424 u8 reserved_at_60[0x20]; 1425 1426 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1427 1428 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1429 1430 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1431 1432 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1433 1434 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1435 1436 u8 reserved_at_120[0xe0]; 1437 }; 1438 1439 struct mlx5_ifc_odp_cap_bits { 1440 struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap; 1441 1442 struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap; 1443 1444 u8 reserved_at_400[0x200]; 1445 1446 u8 mem_page_fault[0x1]; 1447 u8 reserved_at_601[0x1f]; 1448 1449 u8 reserved_at_620[0x1e0]; 1450 }; 1451 1452 struct mlx5_ifc_tls_cap_bits { 1453 u8 tls_1_2_aes_gcm_128[0x1]; 1454 u8 tls_1_3_aes_gcm_128[0x1]; 1455 u8 tls_1_2_aes_gcm_256[0x1]; 1456 u8 tls_1_3_aes_gcm_256[0x1]; 1457 u8 reserved_at_4[0x1c]; 1458 1459 u8 reserved_at_20[0x7e0]; 1460 }; 1461 1462 struct mlx5_ifc_ipsec_cap_bits { 1463 u8 ipsec_full_offload[0x1]; 1464 u8 ipsec_crypto_offload[0x1]; 1465 u8 ipsec_esn[0x1]; 1466 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1467 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1468 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1469 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1470 u8 reserved_at_7[0x4]; 1471 u8 log_max_ipsec_offload[0x5]; 1472 u8 reserved_at_10[0x10]; 1473 1474 u8 min_log_ipsec_full_replay_window[0x8]; 1475 u8 max_log_ipsec_full_replay_window[0x8]; 1476 u8 reserved_at_30[0x7d0]; 1477 }; 1478 1479 struct mlx5_ifc_macsec_cap_bits { 1480 u8 macsec_epn[0x1]; 1481 u8 reserved_at_1[0x2]; 1482 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1483 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1484 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1485 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1486 u8 reserved_at_7[0x4]; 1487 u8 log_max_macsec_offload[0x5]; 1488 u8 reserved_at_10[0x10]; 1489 1490 u8 min_log_macsec_full_replay_window[0x8]; 1491 u8 max_log_macsec_full_replay_window[0x8]; 1492 u8 reserved_at_30[0x10]; 1493 1494 u8 reserved_at_40[0x7c0]; 1495 }; 1496 1497 enum { 1498 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1499 MLX5_WQ_TYPE_CYCLIC = 0x1, 1500 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1501 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1502 }; 1503 1504 enum { 1505 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1506 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1507 }; 1508 1509 enum { 1510 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1511 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1512 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1513 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1514 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1515 }; 1516 1517 enum { 1518 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1519 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1520 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1521 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1522 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1523 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1524 }; 1525 1526 enum { 1527 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1528 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1529 }; 1530 1531 enum { 1532 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1533 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1534 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1535 }; 1536 1537 enum { 1538 MLX5_CAP_PORT_TYPE_IB = 0x0, 1539 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1540 }; 1541 1542 enum { 1543 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1544 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1545 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1546 }; 1547 1548 enum { 1549 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0, 1550 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1, 1551 MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2, 1552 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1553 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1554 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1555 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6, 1556 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1557 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1558 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1559 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1560 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1561 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1562 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1563 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1564 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1565 }; 1566 1567 enum { 1568 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1569 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1570 }; 1571 1572 #define MLX5_FC_BULK_SIZE_FACTOR 128 1573 1574 enum mlx5_fc_bulk_alloc_bitmask { 1575 MLX5_FC_BULK_128 = (1 << 0), 1576 MLX5_FC_BULK_256 = (1 << 1), 1577 MLX5_FC_BULK_512 = (1 << 2), 1578 MLX5_FC_BULK_1024 = (1 << 3), 1579 MLX5_FC_BULK_2048 = (1 << 4), 1580 MLX5_FC_BULK_4096 = (1 << 5), 1581 MLX5_FC_BULK_8192 = (1 << 6), 1582 MLX5_FC_BULK_16384 = (1 << 7), 1583 }; 1584 1585 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1586 1587 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1588 1589 enum { 1590 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1591 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1592 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1593 }; 1594 1595 struct mlx5_ifc_cmd_hca_cap_bits { 1596 u8 reserved_at_0[0x6]; 1597 u8 page_request_disable[0x1]; 1598 u8 reserved_at_7[0x9]; 1599 u8 shared_object_to_user_object_allowed[0x1]; 1600 u8 reserved_at_13[0xe]; 1601 u8 vhca_resource_manager[0x1]; 1602 1603 u8 hca_cap_2[0x1]; 1604 u8 create_lag_when_not_master_up[0x1]; 1605 u8 dtor[0x1]; 1606 u8 event_on_vhca_state_teardown_request[0x1]; 1607 u8 event_on_vhca_state_in_use[0x1]; 1608 u8 event_on_vhca_state_active[0x1]; 1609 u8 event_on_vhca_state_allocated[0x1]; 1610 u8 event_on_vhca_state_invalid[0x1]; 1611 u8 reserved_at_28[0x8]; 1612 u8 vhca_id[0x10]; 1613 1614 u8 reserved_at_40[0x40]; 1615 1616 u8 log_max_srq_sz[0x8]; 1617 u8 log_max_qp_sz[0x8]; 1618 u8 event_cap[0x1]; 1619 u8 reserved_at_91[0x2]; 1620 u8 isolate_vl_tc_new[0x1]; 1621 u8 reserved_at_94[0x4]; 1622 u8 prio_tag_required[0x1]; 1623 u8 reserved_at_99[0x2]; 1624 u8 log_max_qp[0x5]; 1625 1626 u8 reserved_at_a0[0x3]; 1627 u8 ece_support[0x1]; 1628 u8 reserved_at_a4[0x5]; 1629 u8 reg_c_preserve[0x1]; 1630 u8 reserved_at_aa[0x1]; 1631 u8 log_max_srq[0x5]; 1632 u8 reserved_at_b0[0x1]; 1633 u8 uplink_follow[0x1]; 1634 u8 ts_cqe_to_dest_cqn[0x1]; 1635 u8 reserved_at_b3[0x6]; 1636 u8 go_back_n[0x1]; 1637 u8 reserved_at_ba[0x6]; 1638 1639 u8 max_sgl_for_optimized_performance[0x8]; 1640 u8 log_max_cq_sz[0x8]; 1641 u8 relaxed_ordering_write_umr[0x1]; 1642 u8 relaxed_ordering_read_umr[0x1]; 1643 u8 reserved_at_d2[0x7]; 1644 u8 virtio_net_device_emualtion_manager[0x1]; 1645 u8 virtio_blk_device_emualtion_manager[0x1]; 1646 u8 log_max_cq[0x5]; 1647 1648 u8 log_max_eq_sz[0x8]; 1649 u8 relaxed_ordering_write[0x1]; 1650 u8 relaxed_ordering_read_pci_enabled[0x1]; 1651 u8 log_max_mkey[0x6]; 1652 u8 reserved_at_f0[0x6]; 1653 u8 terminate_scatter_list_mkey[0x1]; 1654 u8 repeated_mkey[0x1]; 1655 u8 dump_fill_mkey[0x1]; 1656 u8 reserved_at_f9[0x2]; 1657 u8 fast_teardown[0x1]; 1658 u8 log_max_eq[0x4]; 1659 1660 u8 max_indirection[0x8]; 1661 u8 fixed_buffer_size[0x1]; 1662 u8 log_max_mrw_sz[0x7]; 1663 u8 force_teardown[0x1]; 1664 u8 reserved_at_111[0x1]; 1665 u8 log_max_bsf_list_size[0x6]; 1666 u8 umr_extended_translation_offset[0x1]; 1667 u8 null_mkey[0x1]; 1668 u8 log_max_klm_list_size[0x6]; 1669 1670 u8 reserved_at_120[0x2]; 1671 u8 qpc_extension[0x1]; 1672 u8 reserved_at_123[0x7]; 1673 u8 log_max_ra_req_dc[0x6]; 1674 u8 reserved_at_130[0x2]; 1675 u8 eth_wqe_too_small[0x1]; 1676 u8 reserved_at_133[0x6]; 1677 u8 vnic_env_cq_overrun[0x1]; 1678 u8 log_max_ra_res_dc[0x6]; 1679 1680 u8 reserved_at_140[0x5]; 1681 u8 release_all_pages[0x1]; 1682 u8 must_not_use[0x1]; 1683 u8 reserved_at_147[0x2]; 1684 u8 roce_accl[0x1]; 1685 u8 log_max_ra_req_qp[0x6]; 1686 u8 reserved_at_150[0xa]; 1687 u8 log_max_ra_res_qp[0x6]; 1688 1689 u8 end_pad[0x1]; 1690 u8 cc_query_allowed[0x1]; 1691 u8 cc_modify_allowed[0x1]; 1692 u8 start_pad[0x1]; 1693 u8 cache_line_128byte[0x1]; 1694 u8 reserved_at_165[0x4]; 1695 u8 rts2rts_qp_counters_set_id[0x1]; 1696 u8 reserved_at_16a[0x2]; 1697 u8 vnic_env_int_rq_oob[0x1]; 1698 u8 sbcam_reg[0x1]; 1699 u8 reserved_at_16e[0x1]; 1700 u8 qcam_reg[0x1]; 1701 u8 gid_table_size[0x10]; 1702 1703 u8 out_of_seq_cnt[0x1]; 1704 u8 vport_counters[0x1]; 1705 u8 retransmission_q_counters[0x1]; 1706 u8 debug[0x1]; 1707 u8 modify_rq_counter_set_id[0x1]; 1708 u8 rq_delay_drop[0x1]; 1709 u8 max_qp_cnt[0xa]; 1710 u8 pkey_table_size[0x10]; 1711 1712 u8 vport_group_manager[0x1]; 1713 u8 vhca_group_manager[0x1]; 1714 u8 ib_virt[0x1]; 1715 u8 eth_virt[0x1]; 1716 u8 vnic_env_queue_counters[0x1]; 1717 u8 ets[0x1]; 1718 u8 nic_flow_table[0x1]; 1719 u8 eswitch_manager[0x1]; 1720 u8 device_memory[0x1]; 1721 u8 mcam_reg[0x1]; 1722 u8 pcam_reg[0x1]; 1723 u8 local_ca_ack_delay[0x5]; 1724 u8 port_module_event[0x1]; 1725 u8 enhanced_error_q_counters[0x1]; 1726 u8 ports_check[0x1]; 1727 u8 reserved_at_1b3[0x1]; 1728 u8 disable_link_up[0x1]; 1729 u8 beacon_led[0x1]; 1730 u8 port_type[0x2]; 1731 u8 num_ports[0x8]; 1732 1733 u8 reserved_at_1c0[0x1]; 1734 u8 pps[0x1]; 1735 u8 pps_modify[0x1]; 1736 u8 log_max_msg[0x5]; 1737 u8 reserved_at_1c8[0x4]; 1738 u8 max_tc[0x4]; 1739 u8 temp_warn_event[0x1]; 1740 u8 dcbx[0x1]; 1741 u8 general_notification_event[0x1]; 1742 u8 reserved_at_1d3[0x2]; 1743 u8 fpga[0x1]; 1744 u8 rol_s[0x1]; 1745 u8 rol_g[0x1]; 1746 u8 reserved_at_1d8[0x1]; 1747 u8 wol_s[0x1]; 1748 u8 wol_g[0x1]; 1749 u8 wol_a[0x1]; 1750 u8 wol_b[0x1]; 1751 u8 wol_m[0x1]; 1752 u8 wol_u[0x1]; 1753 u8 wol_p[0x1]; 1754 1755 u8 stat_rate_support[0x10]; 1756 u8 reserved_at_1f0[0x1]; 1757 u8 pci_sync_for_fw_update_event[0x1]; 1758 u8 reserved_at_1f2[0x6]; 1759 u8 init2_lag_tx_port_affinity[0x1]; 1760 u8 reserved_at_1fa[0x2]; 1761 u8 wqe_based_flow_table_update_cap[0x1]; 1762 u8 cqe_version[0x4]; 1763 1764 u8 compact_address_vector[0x1]; 1765 u8 striding_rq[0x1]; 1766 u8 reserved_at_202[0x1]; 1767 u8 ipoib_enhanced_offloads[0x1]; 1768 u8 ipoib_basic_offloads[0x1]; 1769 u8 reserved_at_205[0x1]; 1770 u8 repeated_block_disabled[0x1]; 1771 u8 umr_modify_entity_size_disabled[0x1]; 1772 u8 umr_modify_atomic_disabled[0x1]; 1773 u8 umr_indirect_mkey_disabled[0x1]; 1774 u8 umr_fence[0x2]; 1775 u8 dc_req_scat_data_cqe[0x1]; 1776 u8 reserved_at_20d[0x2]; 1777 u8 drain_sigerr[0x1]; 1778 u8 cmdif_checksum[0x2]; 1779 u8 sigerr_cqe[0x1]; 1780 u8 reserved_at_213[0x1]; 1781 u8 wq_signature[0x1]; 1782 u8 sctr_data_cqe[0x1]; 1783 u8 reserved_at_216[0x1]; 1784 u8 sho[0x1]; 1785 u8 tph[0x1]; 1786 u8 rf[0x1]; 1787 u8 dct[0x1]; 1788 u8 qos[0x1]; 1789 u8 eth_net_offloads[0x1]; 1790 u8 roce[0x1]; 1791 u8 atomic[0x1]; 1792 u8 reserved_at_21f[0x1]; 1793 1794 u8 cq_oi[0x1]; 1795 u8 cq_resize[0x1]; 1796 u8 cq_moderation[0x1]; 1797 u8 cq_period_mode_modify[0x1]; 1798 u8 reserved_at_224[0x2]; 1799 u8 cq_eq_remap[0x1]; 1800 u8 pg[0x1]; 1801 u8 block_lb_mc[0x1]; 1802 u8 reserved_at_229[0x1]; 1803 u8 scqe_break_moderation[0x1]; 1804 u8 cq_period_start_from_cqe[0x1]; 1805 u8 cd[0x1]; 1806 u8 reserved_at_22d[0x1]; 1807 u8 apm[0x1]; 1808 u8 vector_calc[0x1]; 1809 u8 umr_ptr_rlky[0x1]; 1810 u8 imaicl[0x1]; 1811 u8 qp_packet_based[0x1]; 1812 u8 reserved_at_233[0x3]; 1813 u8 qkv[0x1]; 1814 u8 pkv[0x1]; 1815 u8 set_deth_sqpn[0x1]; 1816 u8 reserved_at_239[0x3]; 1817 u8 xrc[0x1]; 1818 u8 ud[0x1]; 1819 u8 uc[0x1]; 1820 u8 rc[0x1]; 1821 1822 u8 uar_4k[0x1]; 1823 u8 reserved_at_241[0x7]; 1824 u8 fl_rc_qp_when_roce_disabled[0x1]; 1825 u8 regexp_params[0x1]; 1826 u8 uar_sz[0x6]; 1827 u8 port_selection_cap[0x1]; 1828 u8 reserved_at_251[0x1]; 1829 u8 umem_uid_0[0x1]; 1830 u8 reserved_at_253[0x5]; 1831 u8 log_pg_sz[0x8]; 1832 1833 u8 bf[0x1]; 1834 u8 driver_version[0x1]; 1835 u8 pad_tx_eth_packet[0x1]; 1836 u8 reserved_at_263[0x3]; 1837 u8 mkey_by_name[0x1]; 1838 u8 reserved_at_267[0x4]; 1839 1840 u8 log_bf_reg_size[0x5]; 1841 1842 u8 reserved_at_270[0x3]; 1843 u8 qp_error_syndrome[0x1]; 1844 u8 reserved_at_274[0x2]; 1845 u8 lag_dct[0x2]; 1846 u8 lag_tx_port_affinity[0x1]; 1847 u8 lag_native_fdb_selection[0x1]; 1848 u8 reserved_at_27a[0x1]; 1849 u8 lag_master[0x1]; 1850 u8 num_lag_ports[0x4]; 1851 1852 u8 reserved_at_280[0x10]; 1853 u8 max_wqe_sz_sq[0x10]; 1854 1855 u8 reserved_at_2a0[0xb]; 1856 u8 shampo[0x1]; 1857 u8 reserved_at_2ac[0x4]; 1858 u8 max_wqe_sz_rq[0x10]; 1859 1860 u8 max_flow_counter_31_16[0x10]; 1861 u8 max_wqe_sz_sq_dc[0x10]; 1862 1863 u8 reserved_at_2e0[0x7]; 1864 u8 max_qp_mcg[0x19]; 1865 1866 u8 reserved_at_300[0x10]; 1867 u8 flow_counter_bulk_alloc[0x8]; 1868 u8 log_max_mcg[0x8]; 1869 1870 u8 reserved_at_320[0x3]; 1871 u8 log_max_transport_domain[0x5]; 1872 u8 reserved_at_328[0x2]; 1873 u8 relaxed_ordering_read[0x1]; 1874 u8 log_max_pd[0x5]; 1875 u8 reserved_at_330[0x5]; 1876 u8 pcie_reset_using_hotreset_method[0x1]; 1877 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1878 u8 vnic_env_cnt_steering_fail[0x1]; 1879 u8 vport_counter_local_loopback[0x1]; 1880 u8 q_counter_aggregation[0x1]; 1881 u8 q_counter_other_vport[0x1]; 1882 u8 log_max_xrcd[0x5]; 1883 1884 u8 nic_receive_steering_discard[0x1]; 1885 u8 receive_discard_vport_down[0x1]; 1886 u8 transmit_discard_vport_down[0x1]; 1887 u8 eq_overrun_count[0x1]; 1888 u8 reserved_at_344[0x1]; 1889 u8 invalid_command_count[0x1]; 1890 u8 quota_exceeded_count[0x1]; 1891 u8 reserved_at_347[0x1]; 1892 u8 log_max_flow_counter_bulk[0x8]; 1893 u8 max_flow_counter_15_0[0x10]; 1894 1895 1896 u8 reserved_at_360[0x3]; 1897 u8 log_max_rq[0x5]; 1898 u8 reserved_at_368[0x3]; 1899 u8 log_max_sq[0x5]; 1900 u8 reserved_at_370[0x3]; 1901 u8 log_max_tir[0x5]; 1902 u8 reserved_at_378[0x3]; 1903 u8 log_max_tis[0x5]; 1904 1905 u8 basic_cyclic_rcv_wqe[0x1]; 1906 u8 reserved_at_381[0x2]; 1907 u8 log_max_rmp[0x5]; 1908 u8 reserved_at_388[0x3]; 1909 u8 log_max_rqt[0x5]; 1910 u8 reserved_at_390[0x3]; 1911 u8 log_max_rqt_size[0x5]; 1912 u8 reserved_at_398[0x3]; 1913 u8 log_max_tis_per_sq[0x5]; 1914 1915 u8 ext_stride_num_range[0x1]; 1916 u8 roce_rw_supported[0x1]; 1917 u8 log_max_current_uc_list_wr_supported[0x1]; 1918 u8 log_max_stride_sz_rq[0x5]; 1919 u8 reserved_at_3a8[0x3]; 1920 u8 log_min_stride_sz_rq[0x5]; 1921 u8 reserved_at_3b0[0x3]; 1922 u8 log_max_stride_sz_sq[0x5]; 1923 u8 reserved_at_3b8[0x3]; 1924 u8 log_min_stride_sz_sq[0x5]; 1925 1926 u8 hairpin[0x1]; 1927 u8 reserved_at_3c1[0x2]; 1928 u8 log_max_hairpin_queues[0x5]; 1929 u8 reserved_at_3c8[0x3]; 1930 u8 log_max_hairpin_wq_data_sz[0x5]; 1931 u8 reserved_at_3d0[0x3]; 1932 u8 log_max_hairpin_num_packets[0x5]; 1933 u8 reserved_at_3d8[0x3]; 1934 u8 log_max_wq_sz[0x5]; 1935 1936 u8 nic_vport_change_event[0x1]; 1937 u8 disable_local_lb_uc[0x1]; 1938 u8 disable_local_lb_mc[0x1]; 1939 u8 log_min_hairpin_wq_data_sz[0x5]; 1940 u8 reserved_at_3e8[0x1]; 1941 u8 silent_mode[0x1]; 1942 u8 vhca_state[0x1]; 1943 u8 log_max_vlan_list[0x5]; 1944 u8 reserved_at_3f0[0x3]; 1945 u8 log_max_current_mc_list[0x5]; 1946 u8 reserved_at_3f8[0x3]; 1947 u8 log_max_current_uc_list[0x5]; 1948 1949 u8 general_obj_types[0x40]; 1950 1951 u8 sq_ts_format[0x2]; 1952 u8 rq_ts_format[0x2]; 1953 u8 steering_format_version[0x4]; 1954 u8 create_qp_start_hint[0x18]; 1955 1956 u8 reserved_at_460[0x1]; 1957 u8 ats[0x1]; 1958 u8 cross_vhca_rqt[0x1]; 1959 u8 log_max_uctx[0x5]; 1960 u8 reserved_at_468[0x1]; 1961 u8 crypto[0x1]; 1962 u8 ipsec_offload[0x1]; 1963 u8 log_max_umem[0x5]; 1964 u8 max_num_eqs[0x10]; 1965 1966 u8 reserved_at_480[0x1]; 1967 u8 tls_tx[0x1]; 1968 u8 tls_rx[0x1]; 1969 u8 log_max_l2_table[0x5]; 1970 u8 reserved_at_488[0x8]; 1971 u8 log_uar_page_sz[0x10]; 1972 1973 u8 reserved_at_4a0[0x20]; 1974 u8 device_frequency_mhz[0x20]; 1975 u8 device_frequency_khz[0x20]; 1976 1977 u8 reserved_at_500[0x20]; 1978 u8 num_of_uars_per_page[0x20]; 1979 1980 u8 flex_parser_protocols[0x20]; 1981 1982 u8 max_geneve_tlv_options[0x8]; 1983 u8 reserved_at_568[0x3]; 1984 u8 max_geneve_tlv_option_data_len[0x5]; 1985 u8 reserved_at_570[0x9]; 1986 u8 adv_virtualization[0x1]; 1987 u8 reserved_at_57a[0x6]; 1988 1989 u8 reserved_at_580[0xb]; 1990 u8 log_max_dci_stream_channels[0x5]; 1991 u8 reserved_at_590[0x3]; 1992 u8 log_max_dci_errored_streams[0x5]; 1993 u8 reserved_at_598[0x8]; 1994 1995 u8 reserved_at_5a0[0x10]; 1996 u8 enhanced_cqe_compression[0x1]; 1997 u8 reserved_at_5b1[0x1]; 1998 u8 crossing_vhca_mkey[0x1]; 1999 u8 log_max_dek[0x5]; 2000 u8 reserved_at_5b8[0x4]; 2001 u8 mini_cqe_resp_stride_index[0x1]; 2002 u8 cqe_128_always[0x1]; 2003 u8 cqe_compression_128[0x1]; 2004 u8 cqe_compression[0x1]; 2005 2006 u8 cqe_compression_timeout[0x10]; 2007 u8 cqe_compression_max_num[0x10]; 2008 2009 u8 reserved_at_5e0[0x8]; 2010 u8 flex_parser_id_gtpu_dw_0[0x4]; 2011 u8 reserved_at_5ec[0x4]; 2012 u8 tag_matching[0x1]; 2013 u8 rndv_offload_rc[0x1]; 2014 u8 rndv_offload_dc[0x1]; 2015 u8 log_tag_matching_list_sz[0x5]; 2016 u8 reserved_at_5f8[0x3]; 2017 u8 log_max_xrq[0x5]; 2018 2019 u8 affiliate_nic_vport_criteria[0x8]; 2020 u8 native_port_num[0x8]; 2021 u8 num_vhca_ports[0x8]; 2022 u8 flex_parser_id_gtpu_teid[0x4]; 2023 u8 reserved_at_61c[0x2]; 2024 u8 sw_owner_id[0x1]; 2025 u8 reserved_at_61f[0x1]; 2026 2027 u8 max_num_of_monitor_counters[0x10]; 2028 u8 num_ppcnt_monitor_counters[0x10]; 2029 2030 u8 max_num_sf[0x10]; 2031 u8 num_q_monitor_counters[0x10]; 2032 2033 u8 reserved_at_660[0x20]; 2034 2035 u8 sf[0x1]; 2036 u8 sf_set_partition[0x1]; 2037 u8 reserved_at_682[0x1]; 2038 u8 log_max_sf[0x5]; 2039 u8 apu[0x1]; 2040 u8 reserved_at_689[0x4]; 2041 u8 migration[0x1]; 2042 u8 reserved_at_68e[0x2]; 2043 u8 log_min_sf_size[0x8]; 2044 u8 max_num_sf_partitions[0x8]; 2045 2046 u8 uctx_cap[0x20]; 2047 2048 u8 reserved_at_6c0[0x4]; 2049 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 2050 u8 flex_parser_id_icmp_dw1[0x4]; 2051 u8 flex_parser_id_icmp_dw0[0x4]; 2052 u8 flex_parser_id_icmpv6_dw1[0x4]; 2053 u8 flex_parser_id_icmpv6_dw0[0x4]; 2054 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 2055 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 2056 2057 u8 max_num_match_definer[0x10]; 2058 u8 sf_base_id[0x10]; 2059 2060 u8 flex_parser_id_gtpu_dw_2[0x4]; 2061 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 2062 u8 num_total_dynamic_vf_msix[0x18]; 2063 u8 reserved_at_720[0x14]; 2064 u8 dynamic_msix_table_size[0xc]; 2065 u8 reserved_at_740[0xc]; 2066 u8 min_dynamic_vf_msix_table_size[0x4]; 2067 u8 reserved_at_750[0x2]; 2068 u8 data_direct[0x1]; 2069 u8 reserved_at_753[0x1]; 2070 u8 max_dynamic_vf_msix_table_size[0xc]; 2071 2072 u8 reserved_at_760[0x3]; 2073 u8 log_max_num_header_modify_argument[0x5]; 2074 u8 log_header_modify_argument_granularity_offset[0x4]; 2075 u8 log_header_modify_argument_granularity[0x4]; 2076 u8 reserved_at_770[0x3]; 2077 u8 log_header_modify_argument_max_alloc[0x5]; 2078 u8 reserved_at_778[0x8]; 2079 2080 u8 vhca_tunnel_commands[0x40]; 2081 u8 match_definer_format_supported[0x40]; 2082 }; 2083 2084 enum { 2085 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 2086 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 2087 }; 2088 2089 enum { 2090 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 2091 }; 2092 2093 struct mlx5_ifc_cmd_hca_cap_2_bits { 2094 u8 reserved_at_0[0x80]; 2095 2096 u8 migratable[0x1]; 2097 u8 reserved_at_81[0x11]; 2098 u8 query_vuid[0x1]; 2099 u8 reserved_at_93[0x5]; 2100 u8 umr_log_entity_size_5[0x1]; 2101 u8 reserved_at_99[0x7]; 2102 2103 u8 max_reformat_insert_size[0x8]; 2104 u8 max_reformat_insert_offset[0x8]; 2105 u8 max_reformat_remove_size[0x8]; 2106 u8 max_reformat_remove_offset[0x8]; 2107 2108 u8 reserved_at_c0[0x8]; 2109 u8 migration_multi_load[0x1]; 2110 u8 migration_tracking_state[0x1]; 2111 u8 multiplane_qp_ud[0x1]; 2112 u8 reserved_at_cb[0x5]; 2113 u8 migration_in_chunks[0x1]; 2114 u8 reserved_at_d1[0x1]; 2115 u8 sf_eq_usage[0x1]; 2116 u8 reserved_at_d3[0xd]; 2117 2118 u8 cross_vhca_object_to_object_supported[0x20]; 2119 2120 u8 allowed_object_for_other_vhca_access[0x40]; 2121 2122 u8 reserved_at_140[0x60]; 2123 2124 u8 flow_table_type_2_type[0x8]; 2125 u8 reserved_at_1a8[0x2]; 2126 u8 format_select_dw_8_6_ext[0x1]; 2127 u8 log_min_mkey_entity_size[0x5]; 2128 u8 reserved_at_1b0[0x10]; 2129 2130 u8 reserved_at_1c0[0x60]; 2131 2132 u8 reserved_at_220[0x1]; 2133 u8 sw_vhca_id_valid[0x1]; 2134 u8 sw_vhca_id[0xe]; 2135 u8 reserved_at_230[0x10]; 2136 2137 u8 reserved_at_240[0xb]; 2138 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2139 u8 reserved_at_250[0x10]; 2140 2141 u8 reserved_at_260[0x20]; 2142 2143 u8 format_select_dw_gtpu_dw_0[0x8]; 2144 u8 format_select_dw_gtpu_dw_1[0x8]; 2145 u8 format_select_dw_gtpu_dw_2[0x8]; 2146 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2147 2148 u8 generate_wqe_type[0x20]; 2149 2150 u8 reserved_at_2c0[0xc0]; 2151 2152 u8 reserved_at_380[0xb]; 2153 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2154 u8 ec_vf_vport_base[0x10]; 2155 2156 u8 reserved_at_3a0[0xa]; 2157 u8 max_mkey_log_entity_size_mtt[0x6]; 2158 u8 max_rqt_vhca_id[0x10]; 2159 2160 u8 reserved_at_3c0[0x20]; 2161 2162 u8 reserved_at_3e0[0x10]; 2163 u8 pcc_ifa2[0x1]; 2164 u8 reserved_at_3f1[0xf]; 2165 2166 u8 reserved_at_400[0x1]; 2167 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2168 u8 reserved_at_402[0xe]; 2169 u8 return_reg_id[0x10]; 2170 2171 u8 reserved_at_420[0x1c]; 2172 u8 flow_table_hash_type[0x4]; 2173 2174 u8 reserved_at_440[0x8]; 2175 u8 max_num_eqs_24b[0x18]; 2176 u8 reserved_at_460[0x3a0]; 2177 }; 2178 2179 enum mlx5_ifc_flow_destination_type { 2180 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2181 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2182 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2183 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2184 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2185 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2186 }; 2187 2188 enum mlx5_flow_table_miss_action { 2189 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2190 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2191 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2192 }; 2193 2194 struct mlx5_ifc_dest_format_struct_bits { 2195 u8 destination_type[0x8]; 2196 u8 destination_id[0x18]; 2197 2198 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2199 u8 packet_reformat[0x1]; 2200 u8 reserved_at_22[0x6]; 2201 u8 destination_table_type[0x8]; 2202 u8 destination_eswitch_owner_vhca_id[0x10]; 2203 }; 2204 2205 struct mlx5_ifc_flow_counter_list_bits { 2206 u8 flow_counter_id[0x20]; 2207 2208 u8 reserved_at_20[0x20]; 2209 }; 2210 2211 struct mlx5_ifc_extended_dest_format_bits { 2212 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2213 2214 u8 packet_reformat_id[0x20]; 2215 2216 u8 reserved_at_60[0x20]; 2217 }; 2218 2219 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 2220 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2221 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2222 }; 2223 2224 struct mlx5_ifc_fte_match_param_bits { 2225 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2226 2227 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2228 2229 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2230 2231 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2232 2233 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2234 2235 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2236 2237 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2238 2239 u8 reserved_at_e00[0x200]; 2240 }; 2241 2242 enum { 2243 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2244 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2245 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2246 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2247 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2248 }; 2249 2250 struct mlx5_ifc_rx_hash_field_select_bits { 2251 u8 l3_prot_type[0x1]; 2252 u8 l4_prot_type[0x1]; 2253 u8 selected_fields[0x1e]; 2254 }; 2255 2256 enum { 2257 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2258 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2259 }; 2260 2261 enum { 2262 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2263 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2264 }; 2265 2266 struct mlx5_ifc_wq_bits { 2267 u8 wq_type[0x4]; 2268 u8 wq_signature[0x1]; 2269 u8 end_padding_mode[0x2]; 2270 u8 cd_slave[0x1]; 2271 u8 reserved_at_8[0x18]; 2272 2273 u8 hds_skip_first_sge[0x1]; 2274 u8 log2_hds_buf_size[0x3]; 2275 u8 reserved_at_24[0x7]; 2276 u8 page_offset[0x5]; 2277 u8 lwm[0x10]; 2278 2279 u8 reserved_at_40[0x8]; 2280 u8 pd[0x18]; 2281 2282 u8 reserved_at_60[0x8]; 2283 u8 uar_page[0x18]; 2284 2285 u8 dbr_addr[0x40]; 2286 2287 u8 hw_counter[0x20]; 2288 2289 u8 sw_counter[0x20]; 2290 2291 u8 reserved_at_100[0xc]; 2292 u8 log_wq_stride[0x4]; 2293 u8 reserved_at_110[0x3]; 2294 u8 log_wq_pg_sz[0x5]; 2295 u8 reserved_at_118[0x3]; 2296 u8 log_wq_sz[0x5]; 2297 2298 u8 dbr_umem_valid[0x1]; 2299 u8 wq_umem_valid[0x1]; 2300 u8 reserved_at_122[0x1]; 2301 u8 log_hairpin_num_packets[0x5]; 2302 u8 reserved_at_128[0x3]; 2303 u8 log_hairpin_data_sz[0x5]; 2304 2305 u8 reserved_at_130[0x4]; 2306 u8 log_wqe_num_of_strides[0x4]; 2307 u8 two_byte_shift_en[0x1]; 2308 u8 reserved_at_139[0x4]; 2309 u8 log_wqe_stride_size[0x3]; 2310 2311 u8 dbr_umem_id[0x20]; 2312 u8 wq_umem_id[0x20]; 2313 2314 u8 wq_umem_offset[0x40]; 2315 2316 u8 headers_mkey[0x20]; 2317 2318 u8 shampo_enable[0x1]; 2319 u8 reserved_at_1e1[0x4]; 2320 u8 log_reservation_size[0x3]; 2321 u8 reserved_at_1e8[0x5]; 2322 u8 log_max_num_of_packets_per_reservation[0x3]; 2323 u8 reserved_at_1f0[0x6]; 2324 u8 log_headers_entry_size[0x2]; 2325 u8 reserved_at_1f8[0x4]; 2326 u8 log_headers_buffer_entry_num[0x4]; 2327 2328 u8 reserved_at_200[0x400]; 2329 2330 struct mlx5_ifc_cmd_pas_bits pas[]; 2331 }; 2332 2333 struct mlx5_ifc_rq_num_bits { 2334 u8 reserved_at_0[0x8]; 2335 u8 rq_num[0x18]; 2336 }; 2337 2338 struct mlx5_ifc_rq_vhca_bits { 2339 u8 reserved_at_0[0x8]; 2340 u8 rq_num[0x18]; 2341 u8 reserved_at_20[0x10]; 2342 u8 rq_vhca_id[0x10]; 2343 }; 2344 2345 struct mlx5_ifc_mac_address_layout_bits { 2346 u8 reserved_at_0[0x10]; 2347 u8 mac_addr_47_32[0x10]; 2348 2349 u8 mac_addr_31_0[0x20]; 2350 }; 2351 2352 struct mlx5_ifc_vlan_layout_bits { 2353 u8 reserved_at_0[0x14]; 2354 u8 vlan[0x0c]; 2355 2356 u8 reserved_at_20[0x20]; 2357 }; 2358 2359 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2360 u8 reserved_at_0[0xa0]; 2361 2362 u8 min_time_between_cnps[0x20]; 2363 2364 u8 reserved_at_c0[0x12]; 2365 u8 cnp_dscp[0x6]; 2366 u8 reserved_at_d8[0x4]; 2367 u8 cnp_prio_mode[0x1]; 2368 u8 cnp_802p_prio[0x3]; 2369 2370 u8 reserved_at_e0[0x720]; 2371 }; 2372 2373 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2374 u8 reserved_at_0[0x60]; 2375 2376 u8 reserved_at_60[0x4]; 2377 u8 clamp_tgt_rate[0x1]; 2378 u8 reserved_at_65[0x3]; 2379 u8 clamp_tgt_rate_after_time_inc[0x1]; 2380 u8 reserved_at_69[0x17]; 2381 2382 u8 reserved_at_80[0x20]; 2383 2384 u8 rpg_time_reset[0x20]; 2385 2386 u8 rpg_byte_reset[0x20]; 2387 2388 u8 rpg_threshold[0x20]; 2389 2390 u8 rpg_max_rate[0x20]; 2391 2392 u8 rpg_ai_rate[0x20]; 2393 2394 u8 rpg_hai_rate[0x20]; 2395 2396 u8 rpg_gd[0x20]; 2397 2398 u8 rpg_min_dec_fac[0x20]; 2399 2400 u8 rpg_min_rate[0x20]; 2401 2402 u8 reserved_at_1c0[0xe0]; 2403 2404 u8 rate_to_set_on_first_cnp[0x20]; 2405 2406 u8 dce_tcp_g[0x20]; 2407 2408 u8 dce_tcp_rtt[0x20]; 2409 2410 u8 rate_reduce_monitor_period[0x20]; 2411 2412 u8 reserved_at_320[0x20]; 2413 2414 u8 initial_alpha_value[0x20]; 2415 2416 u8 reserved_at_360[0x4a0]; 2417 }; 2418 2419 struct mlx5_ifc_cong_control_r_roce_general_bits { 2420 u8 reserved_at_0[0x80]; 2421 2422 u8 reserved_at_80[0x10]; 2423 u8 rtt_resp_dscp_valid[0x1]; 2424 u8 reserved_at_91[0x9]; 2425 u8 rtt_resp_dscp[0x6]; 2426 2427 u8 reserved_at_a0[0x760]; 2428 }; 2429 2430 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2431 u8 reserved_at_0[0x80]; 2432 2433 u8 rppp_max_rps[0x20]; 2434 2435 u8 rpg_time_reset[0x20]; 2436 2437 u8 rpg_byte_reset[0x20]; 2438 2439 u8 rpg_threshold[0x20]; 2440 2441 u8 rpg_max_rate[0x20]; 2442 2443 u8 rpg_ai_rate[0x20]; 2444 2445 u8 rpg_hai_rate[0x20]; 2446 2447 u8 rpg_gd[0x20]; 2448 2449 u8 rpg_min_dec_fac[0x20]; 2450 2451 u8 rpg_min_rate[0x20]; 2452 2453 u8 reserved_at_1c0[0x640]; 2454 }; 2455 2456 enum { 2457 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2458 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2459 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2460 }; 2461 2462 struct mlx5_ifc_resize_field_select_bits { 2463 u8 resize_field_select[0x20]; 2464 }; 2465 2466 struct mlx5_ifc_resource_dump_bits { 2467 u8 more_dump[0x1]; 2468 u8 inline_dump[0x1]; 2469 u8 reserved_at_2[0xa]; 2470 u8 seq_num[0x4]; 2471 u8 segment_type[0x10]; 2472 2473 u8 reserved_at_20[0x10]; 2474 u8 vhca_id[0x10]; 2475 2476 u8 index1[0x20]; 2477 2478 u8 index2[0x20]; 2479 2480 u8 num_of_obj1[0x10]; 2481 u8 num_of_obj2[0x10]; 2482 2483 u8 reserved_at_a0[0x20]; 2484 2485 u8 device_opaque[0x40]; 2486 2487 u8 mkey[0x20]; 2488 2489 u8 size[0x20]; 2490 2491 u8 address[0x40]; 2492 2493 u8 inline_data[52][0x20]; 2494 }; 2495 2496 struct mlx5_ifc_resource_dump_menu_record_bits { 2497 u8 reserved_at_0[0x4]; 2498 u8 num_of_obj2_supports_active[0x1]; 2499 u8 num_of_obj2_supports_all[0x1]; 2500 u8 must_have_num_of_obj2[0x1]; 2501 u8 support_num_of_obj2[0x1]; 2502 u8 num_of_obj1_supports_active[0x1]; 2503 u8 num_of_obj1_supports_all[0x1]; 2504 u8 must_have_num_of_obj1[0x1]; 2505 u8 support_num_of_obj1[0x1]; 2506 u8 must_have_index2[0x1]; 2507 u8 support_index2[0x1]; 2508 u8 must_have_index1[0x1]; 2509 u8 support_index1[0x1]; 2510 u8 segment_type[0x10]; 2511 2512 u8 segment_name[4][0x20]; 2513 2514 u8 index1_name[4][0x20]; 2515 2516 u8 index2_name[4][0x20]; 2517 }; 2518 2519 struct mlx5_ifc_resource_dump_segment_header_bits { 2520 u8 length_dw[0x10]; 2521 u8 segment_type[0x10]; 2522 }; 2523 2524 struct mlx5_ifc_resource_dump_command_segment_bits { 2525 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2526 2527 u8 segment_called[0x10]; 2528 u8 vhca_id[0x10]; 2529 2530 u8 index1[0x20]; 2531 2532 u8 index2[0x20]; 2533 2534 u8 num_of_obj1[0x10]; 2535 u8 num_of_obj2[0x10]; 2536 }; 2537 2538 struct mlx5_ifc_resource_dump_error_segment_bits { 2539 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2540 2541 u8 reserved_at_20[0x10]; 2542 u8 syndrome_id[0x10]; 2543 2544 u8 reserved_at_40[0x40]; 2545 2546 u8 error[8][0x20]; 2547 }; 2548 2549 struct mlx5_ifc_resource_dump_info_segment_bits { 2550 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2551 2552 u8 reserved_at_20[0x18]; 2553 u8 dump_version[0x8]; 2554 2555 u8 hw_version[0x20]; 2556 2557 u8 fw_version[0x20]; 2558 }; 2559 2560 struct mlx5_ifc_resource_dump_menu_segment_bits { 2561 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2562 2563 u8 reserved_at_20[0x10]; 2564 u8 num_of_records[0x10]; 2565 2566 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2567 }; 2568 2569 struct mlx5_ifc_resource_dump_resource_segment_bits { 2570 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2571 2572 u8 reserved_at_20[0x20]; 2573 2574 u8 index1[0x20]; 2575 2576 u8 index2[0x20]; 2577 2578 u8 payload[][0x20]; 2579 }; 2580 2581 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2582 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2583 }; 2584 2585 struct mlx5_ifc_menu_resource_dump_response_bits { 2586 struct mlx5_ifc_resource_dump_info_segment_bits info; 2587 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2588 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2589 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2590 }; 2591 2592 enum { 2593 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2594 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2595 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2596 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2597 }; 2598 2599 struct mlx5_ifc_modify_field_select_bits { 2600 u8 modify_field_select[0x20]; 2601 }; 2602 2603 struct mlx5_ifc_field_select_r_roce_np_bits { 2604 u8 field_select_r_roce_np[0x20]; 2605 }; 2606 2607 struct mlx5_ifc_field_select_r_roce_rp_bits { 2608 u8 field_select_r_roce_rp[0x20]; 2609 }; 2610 2611 enum { 2612 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2613 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2614 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2615 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2616 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2617 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2618 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2619 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2620 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2621 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2622 }; 2623 2624 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2625 u8 field_select_8021qaurp[0x20]; 2626 }; 2627 2628 struct mlx5_ifc_phys_layer_cntrs_bits { 2629 u8 time_since_last_clear_high[0x20]; 2630 2631 u8 time_since_last_clear_low[0x20]; 2632 2633 u8 symbol_errors_high[0x20]; 2634 2635 u8 symbol_errors_low[0x20]; 2636 2637 u8 sync_headers_errors_high[0x20]; 2638 2639 u8 sync_headers_errors_low[0x20]; 2640 2641 u8 edpl_bip_errors_lane0_high[0x20]; 2642 2643 u8 edpl_bip_errors_lane0_low[0x20]; 2644 2645 u8 edpl_bip_errors_lane1_high[0x20]; 2646 2647 u8 edpl_bip_errors_lane1_low[0x20]; 2648 2649 u8 edpl_bip_errors_lane2_high[0x20]; 2650 2651 u8 edpl_bip_errors_lane2_low[0x20]; 2652 2653 u8 edpl_bip_errors_lane3_high[0x20]; 2654 2655 u8 edpl_bip_errors_lane3_low[0x20]; 2656 2657 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2658 2659 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2660 2661 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2662 2663 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2664 2665 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2666 2667 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2668 2669 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2670 2671 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2672 2673 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2674 2675 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2676 2677 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2678 2679 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2680 2681 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2682 2683 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2684 2685 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2686 2687 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2688 2689 u8 rs_fec_corrected_blocks_high[0x20]; 2690 2691 u8 rs_fec_corrected_blocks_low[0x20]; 2692 2693 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2694 2695 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2696 2697 u8 rs_fec_no_errors_blocks_high[0x20]; 2698 2699 u8 rs_fec_no_errors_blocks_low[0x20]; 2700 2701 u8 rs_fec_single_error_blocks_high[0x20]; 2702 2703 u8 rs_fec_single_error_blocks_low[0x20]; 2704 2705 u8 rs_fec_corrected_symbols_total_high[0x20]; 2706 2707 u8 rs_fec_corrected_symbols_total_low[0x20]; 2708 2709 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2710 2711 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2712 2713 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2714 2715 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2716 2717 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2718 2719 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2720 2721 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2722 2723 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2724 2725 u8 link_down_events[0x20]; 2726 2727 u8 successful_recovery_events[0x20]; 2728 2729 u8 reserved_at_640[0x180]; 2730 }; 2731 2732 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2733 u8 time_since_last_clear_high[0x20]; 2734 2735 u8 time_since_last_clear_low[0x20]; 2736 2737 u8 phy_received_bits_high[0x20]; 2738 2739 u8 phy_received_bits_low[0x20]; 2740 2741 u8 phy_symbol_errors_high[0x20]; 2742 2743 u8 phy_symbol_errors_low[0x20]; 2744 2745 u8 phy_corrected_bits_high[0x20]; 2746 2747 u8 phy_corrected_bits_low[0x20]; 2748 2749 u8 phy_corrected_bits_lane0_high[0x20]; 2750 2751 u8 phy_corrected_bits_lane0_low[0x20]; 2752 2753 u8 phy_corrected_bits_lane1_high[0x20]; 2754 2755 u8 phy_corrected_bits_lane1_low[0x20]; 2756 2757 u8 phy_corrected_bits_lane2_high[0x20]; 2758 2759 u8 phy_corrected_bits_lane2_low[0x20]; 2760 2761 u8 phy_corrected_bits_lane3_high[0x20]; 2762 2763 u8 phy_corrected_bits_lane3_low[0x20]; 2764 2765 u8 reserved_at_200[0x5c0]; 2766 }; 2767 2768 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2769 u8 symbol_error_counter[0x10]; 2770 2771 u8 link_error_recovery_counter[0x8]; 2772 2773 u8 link_downed_counter[0x8]; 2774 2775 u8 port_rcv_errors[0x10]; 2776 2777 u8 port_rcv_remote_physical_errors[0x10]; 2778 2779 u8 port_rcv_switch_relay_errors[0x10]; 2780 2781 u8 port_xmit_discards[0x10]; 2782 2783 u8 port_xmit_constraint_errors[0x8]; 2784 2785 u8 port_rcv_constraint_errors[0x8]; 2786 2787 u8 reserved_at_70[0x8]; 2788 2789 u8 link_overrun_errors[0x8]; 2790 2791 u8 reserved_at_80[0x10]; 2792 2793 u8 vl_15_dropped[0x10]; 2794 2795 u8 reserved_at_a0[0x80]; 2796 2797 u8 port_xmit_wait[0x20]; 2798 }; 2799 2800 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2801 u8 reserved_at_0[0x300]; 2802 2803 u8 port_xmit_data_high[0x20]; 2804 2805 u8 port_xmit_data_low[0x20]; 2806 2807 u8 port_rcv_data_high[0x20]; 2808 2809 u8 port_rcv_data_low[0x20]; 2810 2811 u8 port_xmit_pkts_high[0x20]; 2812 2813 u8 port_xmit_pkts_low[0x20]; 2814 2815 u8 port_rcv_pkts_high[0x20]; 2816 2817 u8 port_rcv_pkts_low[0x20]; 2818 2819 u8 reserved_at_400[0x80]; 2820 2821 u8 port_unicast_xmit_pkts_high[0x20]; 2822 2823 u8 port_unicast_xmit_pkts_low[0x20]; 2824 2825 u8 port_multicast_xmit_pkts_high[0x20]; 2826 2827 u8 port_multicast_xmit_pkts_low[0x20]; 2828 2829 u8 port_unicast_rcv_pkts_high[0x20]; 2830 2831 u8 port_unicast_rcv_pkts_low[0x20]; 2832 2833 u8 port_multicast_rcv_pkts_high[0x20]; 2834 2835 u8 port_multicast_rcv_pkts_low[0x20]; 2836 2837 u8 reserved_at_580[0x240]; 2838 }; 2839 2840 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2841 u8 transmit_queue_high[0x20]; 2842 2843 u8 transmit_queue_low[0x20]; 2844 2845 u8 no_buffer_discard_uc_high[0x20]; 2846 2847 u8 no_buffer_discard_uc_low[0x20]; 2848 2849 u8 reserved_at_80[0x740]; 2850 }; 2851 2852 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2853 u8 wred_discard_high[0x20]; 2854 2855 u8 wred_discard_low[0x20]; 2856 2857 u8 ecn_marked_tc_high[0x20]; 2858 2859 u8 ecn_marked_tc_low[0x20]; 2860 2861 u8 reserved_at_80[0x740]; 2862 }; 2863 2864 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2865 u8 rx_octets_high[0x20]; 2866 2867 u8 rx_octets_low[0x20]; 2868 2869 u8 reserved_at_40[0xc0]; 2870 2871 u8 rx_frames_high[0x20]; 2872 2873 u8 rx_frames_low[0x20]; 2874 2875 u8 tx_octets_high[0x20]; 2876 2877 u8 tx_octets_low[0x20]; 2878 2879 u8 reserved_at_180[0xc0]; 2880 2881 u8 tx_frames_high[0x20]; 2882 2883 u8 tx_frames_low[0x20]; 2884 2885 u8 rx_pause_high[0x20]; 2886 2887 u8 rx_pause_low[0x20]; 2888 2889 u8 rx_pause_duration_high[0x20]; 2890 2891 u8 rx_pause_duration_low[0x20]; 2892 2893 u8 tx_pause_high[0x20]; 2894 2895 u8 tx_pause_low[0x20]; 2896 2897 u8 tx_pause_duration_high[0x20]; 2898 2899 u8 tx_pause_duration_low[0x20]; 2900 2901 u8 rx_pause_transition_high[0x20]; 2902 2903 u8 rx_pause_transition_low[0x20]; 2904 2905 u8 rx_discards_high[0x20]; 2906 2907 u8 rx_discards_low[0x20]; 2908 2909 u8 device_stall_minor_watermark_cnt_high[0x20]; 2910 2911 u8 device_stall_minor_watermark_cnt_low[0x20]; 2912 2913 u8 device_stall_critical_watermark_cnt_high[0x20]; 2914 2915 u8 device_stall_critical_watermark_cnt_low[0x20]; 2916 2917 u8 reserved_at_480[0x340]; 2918 }; 2919 2920 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2921 u8 port_transmit_wait_high[0x20]; 2922 2923 u8 port_transmit_wait_low[0x20]; 2924 2925 u8 reserved_at_40[0x100]; 2926 2927 u8 rx_buffer_almost_full_high[0x20]; 2928 2929 u8 rx_buffer_almost_full_low[0x20]; 2930 2931 u8 rx_buffer_full_high[0x20]; 2932 2933 u8 rx_buffer_full_low[0x20]; 2934 2935 u8 rx_icrc_encapsulated_high[0x20]; 2936 2937 u8 rx_icrc_encapsulated_low[0x20]; 2938 2939 u8 reserved_at_200[0x5c0]; 2940 }; 2941 2942 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2943 u8 dot3stats_alignment_errors_high[0x20]; 2944 2945 u8 dot3stats_alignment_errors_low[0x20]; 2946 2947 u8 dot3stats_fcs_errors_high[0x20]; 2948 2949 u8 dot3stats_fcs_errors_low[0x20]; 2950 2951 u8 dot3stats_single_collision_frames_high[0x20]; 2952 2953 u8 dot3stats_single_collision_frames_low[0x20]; 2954 2955 u8 dot3stats_multiple_collision_frames_high[0x20]; 2956 2957 u8 dot3stats_multiple_collision_frames_low[0x20]; 2958 2959 u8 dot3stats_sqe_test_errors_high[0x20]; 2960 2961 u8 dot3stats_sqe_test_errors_low[0x20]; 2962 2963 u8 dot3stats_deferred_transmissions_high[0x20]; 2964 2965 u8 dot3stats_deferred_transmissions_low[0x20]; 2966 2967 u8 dot3stats_late_collisions_high[0x20]; 2968 2969 u8 dot3stats_late_collisions_low[0x20]; 2970 2971 u8 dot3stats_excessive_collisions_high[0x20]; 2972 2973 u8 dot3stats_excessive_collisions_low[0x20]; 2974 2975 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2976 2977 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2978 2979 u8 dot3stats_carrier_sense_errors_high[0x20]; 2980 2981 u8 dot3stats_carrier_sense_errors_low[0x20]; 2982 2983 u8 dot3stats_frame_too_longs_high[0x20]; 2984 2985 u8 dot3stats_frame_too_longs_low[0x20]; 2986 2987 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2988 2989 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2990 2991 u8 dot3stats_symbol_errors_high[0x20]; 2992 2993 u8 dot3stats_symbol_errors_low[0x20]; 2994 2995 u8 dot3control_in_unknown_opcodes_high[0x20]; 2996 2997 u8 dot3control_in_unknown_opcodes_low[0x20]; 2998 2999 u8 dot3in_pause_frames_high[0x20]; 3000 3001 u8 dot3in_pause_frames_low[0x20]; 3002 3003 u8 dot3out_pause_frames_high[0x20]; 3004 3005 u8 dot3out_pause_frames_low[0x20]; 3006 3007 u8 reserved_at_400[0x3c0]; 3008 }; 3009 3010 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 3011 u8 ether_stats_drop_events_high[0x20]; 3012 3013 u8 ether_stats_drop_events_low[0x20]; 3014 3015 u8 ether_stats_octets_high[0x20]; 3016 3017 u8 ether_stats_octets_low[0x20]; 3018 3019 u8 ether_stats_pkts_high[0x20]; 3020 3021 u8 ether_stats_pkts_low[0x20]; 3022 3023 u8 ether_stats_broadcast_pkts_high[0x20]; 3024 3025 u8 ether_stats_broadcast_pkts_low[0x20]; 3026 3027 u8 ether_stats_multicast_pkts_high[0x20]; 3028 3029 u8 ether_stats_multicast_pkts_low[0x20]; 3030 3031 u8 ether_stats_crc_align_errors_high[0x20]; 3032 3033 u8 ether_stats_crc_align_errors_low[0x20]; 3034 3035 u8 ether_stats_undersize_pkts_high[0x20]; 3036 3037 u8 ether_stats_undersize_pkts_low[0x20]; 3038 3039 u8 ether_stats_oversize_pkts_high[0x20]; 3040 3041 u8 ether_stats_oversize_pkts_low[0x20]; 3042 3043 u8 ether_stats_fragments_high[0x20]; 3044 3045 u8 ether_stats_fragments_low[0x20]; 3046 3047 u8 ether_stats_jabbers_high[0x20]; 3048 3049 u8 ether_stats_jabbers_low[0x20]; 3050 3051 u8 ether_stats_collisions_high[0x20]; 3052 3053 u8 ether_stats_collisions_low[0x20]; 3054 3055 u8 ether_stats_pkts64octets_high[0x20]; 3056 3057 u8 ether_stats_pkts64octets_low[0x20]; 3058 3059 u8 ether_stats_pkts65to127octets_high[0x20]; 3060 3061 u8 ether_stats_pkts65to127octets_low[0x20]; 3062 3063 u8 ether_stats_pkts128to255octets_high[0x20]; 3064 3065 u8 ether_stats_pkts128to255octets_low[0x20]; 3066 3067 u8 ether_stats_pkts256to511octets_high[0x20]; 3068 3069 u8 ether_stats_pkts256to511octets_low[0x20]; 3070 3071 u8 ether_stats_pkts512to1023octets_high[0x20]; 3072 3073 u8 ether_stats_pkts512to1023octets_low[0x20]; 3074 3075 u8 ether_stats_pkts1024to1518octets_high[0x20]; 3076 3077 u8 ether_stats_pkts1024to1518octets_low[0x20]; 3078 3079 u8 ether_stats_pkts1519to2047octets_high[0x20]; 3080 3081 u8 ether_stats_pkts1519to2047octets_low[0x20]; 3082 3083 u8 ether_stats_pkts2048to4095octets_high[0x20]; 3084 3085 u8 ether_stats_pkts2048to4095octets_low[0x20]; 3086 3087 u8 ether_stats_pkts4096to8191octets_high[0x20]; 3088 3089 u8 ether_stats_pkts4096to8191octets_low[0x20]; 3090 3091 u8 ether_stats_pkts8192to10239octets_high[0x20]; 3092 3093 u8 ether_stats_pkts8192to10239octets_low[0x20]; 3094 3095 u8 reserved_at_540[0x280]; 3096 }; 3097 3098 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 3099 u8 if_in_octets_high[0x20]; 3100 3101 u8 if_in_octets_low[0x20]; 3102 3103 u8 if_in_ucast_pkts_high[0x20]; 3104 3105 u8 if_in_ucast_pkts_low[0x20]; 3106 3107 u8 if_in_discards_high[0x20]; 3108 3109 u8 if_in_discards_low[0x20]; 3110 3111 u8 if_in_errors_high[0x20]; 3112 3113 u8 if_in_errors_low[0x20]; 3114 3115 u8 if_in_unknown_protos_high[0x20]; 3116 3117 u8 if_in_unknown_protos_low[0x20]; 3118 3119 u8 if_out_octets_high[0x20]; 3120 3121 u8 if_out_octets_low[0x20]; 3122 3123 u8 if_out_ucast_pkts_high[0x20]; 3124 3125 u8 if_out_ucast_pkts_low[0x20]; 3126 3127 u8 if_out_discards_high[0x20]; 3128 3129 u8 if_out_discards_low[0x20]; 3130 3131 u8 if_out_errors_high[0x20]; 3132 3133 u8 if_out_errors_low[0x20]; 3134 3135 u8 if_in_multicast_pkts_high[0x20]; 3136 3137 u8 if_in_multicast_pkts_low[0x20]; 3138 3139 u8 if_in_broadcast_pkts_high[0x20]; 3140 3141 u8 if_in_broadcast_pkts_low[0x20]; 3142 3143 u8 if_out_multicast_pkts_high[0x20]; 3144 3145 u8 if_out_multicast_pkts_low[0x20]; 3146 3147 u8 if_out_broadcast_pkts_high[0x20]; 3148 3149 u8 if_out_broadcast_pkts_low[0x20]; 3150 3151 u8 reserved_at_340[0x480]; 3152 }; 3153 3154 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3155 u8 a_frames_transmitted_ok_high[0x20]; 3156 3157 u8 a_frames_transmitted_ok_low[0x20]; 3158 3159 u8 a_frames_received_ok_high[0x20]; 3160 3161 u8 a_frames_received_ok_low[0x20]; 3162 3163 u8 a_frame_check_sequence_errors_high[0x20]; 3164 3165 u8 a_frame_check_sequence_errors_low[0x20]; 3166 3167 u8 a_alignment_errors_high[0x20]; 3168 3169 u8 a_alignment_errors_low[0x20]; 3170 3171 u8 a_octets_transmitted_ok_high[0x20]; 3172 3173 u8 a_octets_transmitted_ok_low[0x20]; 3174 3175 u8 a_octets_received_ok_high[0x20]; 3176 3177 u8 a_octets_received_ok_low[0x20]; 3178 3179 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3180 3181 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3182 3183 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3184 3185 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3186 3187 u8 a_multicast_frames_received_ok_high[0x20]; 3188 3189 u8 a_multicast_frames_received_ok_low[0x20]; 3190 3191 u8 a_broadcast_frames_received_ok_high[0x20]; 3192 3193 u8 a_broadcast_frames_received_ok_low[0x20]; 3194 3195 u8 a_in_range_length_errors_high[0x20]; 3196 3197 u8 a_in_range_length_errors_low[0x20]; 3198 3199 u8 a_out_of_range_length_field_high[0x20]; 3200 3201 u8 a_out_of_range_length_field_low[0x20]; 3202 3203 u8 a_frame_too_long_errors_high[0x20]; 3204 3205 u8 a_frame_too_long_errors_low[0x20]; 3206 3207 u8 a_symbol_error_during_carrier_high[0x20]; 3208 3209 u8 a_symbol_error_during_carrier_low[0x20]; 3210 3211 u8 a_mac_control_frames_transmitted_high[0x20]; 3212 3213 u8 a_mac_control_frames_transmitted_low[0x20]; 3214 3215 u8 a_mac_control_frames_received_high[0x20]; 3216 3217 u8 a_mac_control_frames_received_low[0x20]; 3218 3219 u8 a_unsupported_opcodes_received_high[0x20]; 3220 3221 u8 a_unsupported_opcodes_received_low[0x20]; 3222 3223 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3224 3225 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3226 3227 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3228 3229 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3230 3231 u8 reserved_at_4c0[0x300]; 3232 }; 3233 3234 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3235 u8 life_time_counter_high[0x20]; 3236 3237 u8 life_time_counter_low[0x20]; 3238 3239 u8 rx_errors[0x20]; 3240 3241 u8 tx_errors[0x20]; 3242 3243 u8 l0_to_recovery_eieos[0x20]; 3244 3245 u8 l0_to_recovery_ts[0x20]; 3246 3247 u8 l0_to_recovery_framing[0x20]; 3248 3249 u8 l0_to_recovery_retrain[0x20]; 3250 3251 u8 crc_error_dllp[0x20]; 3252 3253 u8 crc_error_tlp[0x20]; 3254 3255 u8 tx_overflow_buffer_pkt_high[0x20]; 3256 3257 u8 tx_overflow_buffer_pkt_low[0x20]; 3258 3259 u8 outbound_stalled_reads[0x20]; 3260 3261 u8 outbound_stalled_writes[0x20]; 3262 3263 u8 outbound_stalled_reads_events[0x20]; 3264 3265 u8 outbound_stalled_writes_events[0x20]; 3266 3267 u8 reserved_at_200[0x5c0]; 3268 }; 3269 3270 struct mlx5_ifc_cmd_inter_comp_event_bits { 3271 u8 command_completion_vector[0x20]; 3272 3273 u8 reserved_at_20[0xc0]; 3274 }; 3275 3276 struct mlx5_ifc_stall_vl_event_bits { 3277 u8 reserved_at_0[0x18]; 3278 u8 port_num[0x1]; 3279 u8 reserved_at_19[0x3]; 3280 u8 vl[0x4]; 3281 3282 u8 reserved_at_20[0xa0]; 3283 }; 3284 3285 struct mlx5_ifc_db_bf_congestion_event_bits { 3286 u8 event_subtype[0x8]; 3287 u8 reserved_at_8[0x8]; 3288 u8 congestion_level[0x8]; 3289 u8 reserved_at_18[0x8]; 3290 3291 u8 reserved_at_20[0xa0]; 3292 }; 3293 3294 struct mlx5_ifc_gpio_event_bits { 3295 u8 reserved_at_0[0x60]; 3296 3297 u8 gpio_event_hi[0x20]; 3298 3299 u8 gpio_event_lo[0x20]; 3300 3301 u8 reserved_at_a0[0x40]; 3302 }; 3303 3304 struct mlx5_ifc_port_state_change_event_bits { 3305 u8 reserved_at_0[0x40]; 3306 3307 u8 port_num[0x4]; 3308 u8 reserved_at_44[0x1c]; 3309 3310 u8 reserved_at_60[0x80]; 3311 }; 3312 3313 struct mlx5_ifc_dropped_packet_logged_bits { 3314 u8 reserved_at_0[0xe0]; 3315 }; 3316 3317 struct mlx5_ifc_default_timeout_bits { 3318 u8 to_multiplier[0x3]; 3319 u8 reserved_at_3[0x9]; 3320 u8 to_value[0x14]; 3321 }; 3322 3323 struct mlx5_ifc_dtor_reg_bits { 3324 u8 reserved_at_0[0x20]; 3325 3326 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3327 3328 u8 reserved_at_40[0x60]; 3329 3330 struct mlx5_ifc_default_timeout_bits health_poll_to; 3331 3332 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3333 3334 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3335 3336 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3337 3338 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3339 3340 struct mlx5_ifc_default_timeout_bits tear_down_to; 3341 3342 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3343 3344 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3345 3346 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3347 3348 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3349 3350 u8 reserved_at_1c0[0x20]; 3351 }; 3352 3353 enum { 3354 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3355 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3356 }; 3357 3358 struct mlx5_ifc_cq_error_bits { 3359 u8 reserved_at_0[0x8]; 3360 u8 cqn[0x18]; 3361 3362 u8 reserved_at_20[0x20]; 3363 3364 u8 reserved_at_40[0x18]; 3365 u8 syndrome[0x8]; 3366 3367 u8 reserved_at_60[0x80]; 3368 }; 3369 3370 struct mlx5_ifc_rdma_page_fault_event_bits { 3371 u8 bytes_committed[0x20]; 3372 3373 u8 r_key[0x20]; 3374 3375 u8 reserved_at_40[0x10]; 3376 u8 packet_len[0x10]; 3377 3378 u8 rdma_op_len[0x20]; 3379 3380 u8 rdma_va[0x40]; 3381 3382 u8 reserved_at_c0[0x5]; 3383 u8 rdma[0x1]; 3384 u8 write[0x1]; 3385 u8 requestor[0x1]; 3386 u8 qp_number[0x18]; 3387 }; 3388 3389 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3390 u8 bytes_committed[0x20]; 3391 3392 u8 reserved_at_20[0x10]; 3393 u8 wqe_index[0x10]; 3394 3395 u8 reserved_at_40[0x10]; 3396 u8 len[0x10]; 3397 3398 u8 reserved_at_60[0x60]; 3399 3400 u8 reserved_at_c0[0x5]; 3401 u8 rdma[0x1]; 3402 u8 write_read[0x1]; 3403 u8 requestor[0x1]; 3404 u8 qpn[0x18]; 3405 }; 3406 3407 struct mlx5_ifc_qp_events_bits { 3408 u8 reserved_at_0[0xa0]; 3409 3410 u8 type[0x8]; 3411 u8 reserved_at_a8[0x18]; 3412 3413 u8 reserved_at_c0[0x8]; 3414 u8 qpn_rqn_sqn[0x18]; 3415 }; 3416 3417 struct mlx5_ifc_dct_events_bits { 3418 u8 reserved_at_0[0xc0]; 3419 3420 u8 reserved_at_c0[0x8]; 3421 u8 dct_number[0x18]; 3422 }; 3423 3424 struct mlx5_ifc_comp_event_bits { 3425 u8 reserved_at_0[0xc0]; 3426 3427 u8 reserved_at_c0[0x8]; 3428 u8 cq_number[0x18]; 3429 }; 3430 3431 enum { 3432 MLX5_QPC_STATE_RST = 0x0, 3433 MLX5_QPC_STATE_INIT = 0x1, 3434 MLX5_QPC_STATE_RTR = 0x2, 3435 MLX5_QPC_STATE_RTS = 0x3, 3436 MLX5_QPC_STATE_SQER = 0x4, 3437 MLX5_QPC_STATE_ERR = 0x6, 3438 MLX5_QPC_STATE_SQD = 0x7, 3439 MLX5_QPC_STATE_SUSPENDED = 0x9, 3440 }; 3441 3442 enum { 3443 MLX5_QPC_ST_RC = 0x0, 3444 MLX5_QPC_ST_UC = 0x1, 3445 MLX5_QPC_ST_UD = 0x2, 3446 MLX5_QPC_ST_XRC = 0x3, 3447 MLX5_QPC_ST_DCI = 0x5, 3448 MLX5_QPC_ST_QP0 = 0x7, 3449 MLX5_QPC_ST_QP1 = 0x8, 3450 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3451 MLX5_QPC_ST_REG_UMR = 0xc, 3452 }; 3453 3454 enum { 3455 MLX5_QPC_PM_STATE_ARMED = 0x0, 3456 MLX5_QPC_PM_STATE_REARM = 0x1, 3457 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3458 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3459 }; 3460 3461 enum { 3462 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3463 }; 3464 3465 enum { 3466 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3467 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3468 }; 3469 3470 enum { 3471 MLX5_QPC_MTU_256_BYTES = 0x1, 3472 MLX5_QPC_MTU_512_BYTES = 0x2, 3473 MLX5_QPC_MTU_1K_BYTES = 0x3, 3474 MLX5_QPC_MTU_2K_BYTES = 0x4, 3475 MLX5_QPC_MTU_4K_BYTES = 0x5, 3476 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3477 }; 3478 3479 enum { 3480 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3481 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3482 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3483 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3484 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3485 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3486 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3487 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3488 }; 3489 3490 enum { 3491 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3492 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3493 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3494 }; 3495 3496 enum { 3497 MLX5_QPC_CS_RES_DISABLE = 0x0, 3498 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3499 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3500 }; 3501 3502 enum { 3503 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3504 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3505 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3506 }; 3507 3508 struct mlx5_ifc_qpc_bits { 3509 u8 state[0x4]; 3510 u8 lag_tx_port_affinity[0x4]; 3511 u8 st[0x8]; 3512 u8 reserved_at_10[0x2]; 3513 u8 isolate_vl_tc[0x1]; 3514 u8 pm_state[0x2]; 3515 u8 reserved_at_15[0x1]; 3516 u8 req_e2e_credit_mode[0x2]; 3517 u8 offload_type[0x4]; 3518 u8 end_padding_mode[0x2]; 3519 u8 reserved_at_1e[0x2]; 3520 3521 u8 wq_signature[0x1]; 3522 u8 block_lb_mc[0x1]; 3523 u8 atomic_like_write_en[0x1]; 3524 u8 latency_sensitive[0x1]; 3525 u8 reserved_at_24[0x1]; 3526 u8 drain_sigerr[0x1]; 3527 u8 reserved_at_26[0x2]; 3528 u8 pd[0x18]; 3529 3530 u8 mtu[0x3]; 3531 u8 log_msg_max[0x5]; 3532 u8 reserved_at_48[0x1]; 3533 u8 log_rq_size[0x4]; 3534 u8 log_rq_stride[0x3]; 3535 u8 no_sq[0x1]; 3536 u8 log_sq_size[0x4]; 3537 u8 reserved_at_55[0x1]; 3538 u8 retry_mode[0x2]; 3539 u8 ts_format[0x2]; 3540 u8 reserved_at_5a[0x1]; 3541 u8 rlky[0x1]; 3542 u8 ulp_stateless_offload_mode[0x4]; 3543 3544 u8 counter_set_id[0x8]; 3545 u8 uar_page[0x18]; 3546 3547 u8 reserved_at_80[0x8]; 3548 u8 user_index[0x18]; 3549 3550 u8 reserved_at_a0[0x3]; 3551 u8 log_page_size[0x5]; 3552 u8 remote_qpn[0x18]; 3553 3554 struct mlx5_ifc_ads_bits primary_address_path; 3555 3556 struct mlx5_ifc_ads_bits secondary_address_path; 3557 3558 u8 log_ack_req_freq[0x4]; 3559 u8 reserved_at_384[0x4]; 3560 u8 log_sra_max[0x3]; 3561 u8 reserved_at_38b[0x2]; 3562 u8 retry_count[0x3]; 3563 u8 rnr_retry[0x3]; 3564 u8 reserved_at_393[0x1]; 3565 u8 fre[0x1]; 3566 u8 cur_rnr_retry[0x3]; 3567 u8 cur_retry_count[0x3]; 3568 u8 reserved_at_39b[0x5]; 3569 3570 u8 reserved_at_3a0[0x20]; 3571 3572 u8 reserved_at_3c0[0x8]; 3573 u8 next_send_psn[0x18]; 3574 3575 u8 reserved_at_3e0[0x3]; 3576 u8 log_num_dci_stream_channels[0x5]; 3577 u8 cqn_snd[0x18]; 3578 3579 u8 reserved_at_400[0x3]; 3580 u8 log_num_dci_errored_streams[0x5]; 3581 u8 deth_sqpn[0x18]; 3582 3583 u8 reserved_at_420[0x20]; 3584 3585 u8 reserved_at_440[0x8]; 3586 u8 last_acked_psn[0x18]; 3587 3588 u8 reserved_at_460[0x8]; 3589 u8 ssn[0x18]; 3590 3591 u8 reserved_at_480[0x8]; 3592 u8 log_rra_max[0x3]; 3593 u8 reserved_at_48b[0x1]; 3594 u8 atomic_mode[0x4]; 3595 u8 rre[0x1]; 3596 u8 rwe[0x1]; 3597 u8 rae[0x1]; 3598 u8 reserved_at_493[0x1]; 3599 u8 page_offset[0x6]; 3600 u8 reserved_at_49a[0x3]; 3601 u8 cd_slave_receive[0x1]; 3602 u8 cd_slave_send[0x1]; 3603 u8 cd_master[0x1]; 3604 3605 u8 reserved_at_4a0[0x3]; 3606 u8 min_rnr_nak[0x5]; 3607 u8 next_rcv_psn[0x18]; 3608 3609 u8 reserved_at_4c0[0x8]; 3610 u8 xrcd[0x18]; 3611 3612 u8 reserved_at_4e0[0x8]; 3613 u8 cqn_rcv[0x18]; 3614 3615 u8 dbr_addr[0x40]; 3616 3617 u8 q_key[0x20]; 3618 3619 u8 reserved_at_560[0x5]; 3620 u8 rq_type[0x3]; 3621 u8 srqn_rmpn_xrqn[0x18]; 3622 3623 u8 reserved_at_580[0x8]; 3624 u8 rmsn[0x18]; 3625 3626 u8 hw_sq_wqebb_counter[0x10]; 3627 u8 sw_sq_wqebb_counter[0x10]; 3628 3629 u8 hw_rq_counter[0x20]; 3630 3631 u8 sw_rq_counter[0x20]; 3632 3633 u8 reserved_at_600[0x20]; 3634 3635 u8 reserved_at_620[0xf]; 3636 u8 cgs[0x1]; 3637 u8 cs_req[0x8]; 3638 u8 cs_res[0x8]; 3639 3640 u8 dc_access_key[0x40]; 3641 3642 u8 reserved_at_680[0x3]; 3643 u8 dbr_umem_valid[0x1]; 3644 3645 u8 reserved_at_684[0xbc]; 3646 }; 3647 3648 struct mlx5_ifc_roce_addr_layout_bits { 3649 u8 source_l3_address[16][0x8]; 3650 3651 u8 reserved_at_80[0x3]; 3652 u8 vlan_valid[0x1]; 3653 u8 vlan_id[0xc]; 3654 u8 source_mac_47_32[0x10]; 3655 3656 u8 source_mac_31_0[0x20]; 3657 3658 u8 reserved_at_c0[0x14]; 3659 u8 roce_l3_type[0x4]; 3660 u8 roce_version[0x8]; 3661 3662 u8 reserved_at_e0[0x20]; 3663 }; 3664 3665 struct mlx5_ifc_crypto_cap_bits { 3666 u8 reserved_at_0[0x3]; 3667 u8 synchronize_dek[0x1]; 3668 u8 int_kek_manual[0x1]; 3669 u8 int_kek_auto[0x1]; 3670 u8 reserved_at_6[0x1a]; 3671 3672 u8 reserved_at_20[0x3]; 3673 u8 log_dek_max_alloc[0x5]; 3674 u8 reserved_at_28[0x3]; 3675 u8 log_max_num_deks[0x5]; 3676 u8 reserved_at_30[0x10]; 3677 3678 u8 reserved_at_40[0x20]; 3679 3680 u8 reserved_at_60[0x3]; 3681 u8 log_dek_granularity[0x5]; 3682 u8 reserved_at_68[0x3]; 3683 u8 log_max_num_int_kek[0x5]; 3684 u8 sw_wrapped_dek[0x10]; 3685 3686 u8 reserved_at_80[0x780]; 3687 }; 3688 3689 union mlx5_ifc_hca_cap_union_bits { 3690 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3691 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3692 struct mlx5_ifc_odp_cap_bits odp_cap; 3693 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3694 struct mlx5_ifc_roce_cap_bits roce_cap; 3695 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3696 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3697 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3698 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 3699 struct mlx5_ifc_esw_cap_bits esw_cap; 3700 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3701 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3702 struct mlx5_ifc_qos_cap_bits qos_cap; 3703 struct mlx5_ifc_debug_cap_bits debug_cap; 3704 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3705 struct mlx5_ifc_tls_cap_bits tls_cap; 3706 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3707 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3708 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3709 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3710 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3711 u8 reserved_at_0[0x8000]; 3712 }; 3713 3714 enum { 3715 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3716 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3717 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3718 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3719 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3720 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3721 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3722 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3723 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3724 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3725 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3726 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3727 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3728 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3729 }; 3730 3731 enum { 3732 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3733 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3734 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3735 }; 3736 3737 enum { 3738 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3739 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3740 }; 3741 3742 struct mlx5_ifc_vlan_bits { 3743 u8 ethtype[0x10]; 3744 u8 prio[0x3]; 3745 u8 cfi[0x1]; 3746 u8 vid[0xc]; 3747 }; 3748 3749 enum { 3750 MLX5_FLOW_METER_COLOR_RED = 0x0, 3751 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3752 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3753 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3754 }; 3755 3756 enum { 3757 MLX5_EXE_ASO_FLOW_METER = 0x2, 3758 }; 3759 3760 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3761 u8 return_reg_id[0x4]; 3762 u8 aso_type[0x4]; 3763 u8 reserved_at_8[0x14]; 3764 u8 action[0x1]; 3765 u8 init_color[0x2]; 3766 u8 meter_id[0x1]; 3767 }; 3768 3769 union mlx5_ifc_exe_aso_ctrl { 3770 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3771 }; 3772 3773 struct mlx5_ifc_execute_aso_bits { 3774 u8 valid[0x1]; 3775 u8 reserved_at_1[0x7]; 3776 u8 aso_object_id[0x18]; 3777 3778 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3779 }; 3780 3781 struct mlx5_ifc_flow_context_bits { 3782 struct mlx5_ifc_vlan_bits push_vlan; 3783 3784 u8 group_id[0x20]; 3785 3786 u8 reserved_at_40[0x8]; 3787 u8 flow_tag[0x18]; 3788 3789 u8 reserved_at_60[0x10]; 3790 u8 action[0x10]; 3791 3792 u8 extended_destination[0x1]; 3793 u8 uplink_hairpin_en[0x1]; 3794 u8 flow_source[0x2]; 3795 u8 encrypt_decrypt_type[0x4]; 3796 u8 destination_list_size[0x18]; 3797 3798 u8 reserved_at_a0[0x8]; 3799 u8 flow_counter_list_size[0x18]; 3800 3801 u8 packet_reformat_id[0x20]; 3802 3803 u8 modify_header_id[0x20]; 3804 3805 struct mlx5_ifc_vlan_bits push_vlan_2; 3806 3807 u8 encrypt_decrypt_obj_id[0x20]; 3808 u8 reserved_at_140[0xc0]; 3809 3810 struct mlx5_ifc_fte_match_param_bits match_value; 3811 3812 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3813 3814 u8 reserved_at_1300[0x500]; 3815 3816 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 3817 }; 3818 3819 enum { 3820 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3821 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3822 }; 3823 3824 struct mlx5_ifc_xrc_srqc_bits { 3825 u8 state[0x4]; 3826 u8 log_xrc_srq_size[0x4]; 3827 u8 reserved_at_8[0x18]; 3828 3829 u8 wq_signature[0x1]; 3830 u8 cont_srq[0x1]; 3831 u8 reserved_at_22[0x1]; 3832 u8 rlky[0x1]; 3833 u8 basic_cyclic_rcv_wqe[0x1]; 3834 u8 log_rq_stride[0x3]; 3835 u8 xrcd[0x18]; 3836 3837 u8 page_offset[0x6]; 3838 u8 reserved_at_46[0x1]; 3839 u8 dbr_umem_valid[0x1]; 3840 u8 cqn[0x18]; 3841 3842 u8 reserved_at_60[0x20]; 3843 3844 u8 user_index_equal_xrc_srqn[0x1]; 3845 u8 reserved_at_81[0x1]; 3846 u8 log_page_size[0x6]; 3847 u8 user_index[0x18]; 3848 3849 u8 reserved_at_a0[0x20]; 3850 3851 u8 reserved_at_c0[0x8]; 3852 u8 pd[0x18]; 3853 3854 u8 lwm[0x10]; 3855 u8 wqe_cnt[0x10]; 3856 3857 u8 reserved_at_100[0x40]; 3858 3859 u8 db_record_addr_h[0x20]; 3860 3861 u8 db_record_addr_l[0x1e]; 3862 u8 reserved_at_17e[0x2]; 3863 3864 u8 reserved_at_180[0x80]; 3865 }; 3866 3867 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3868 u8 counter_error_queues[0x20]; 3869 3870 u8 total_error_queues[0x20]; 3871 3872 u8 send_queue_priority_update_flow[0x20]; 3873 3874 u8 reserved_at_60[0x20]; 3875 3876 u8 nic_receive_steering_discard[0x40]; 3877 3878 u8 receive_discard_vport_down[0x40]; 3879 3880 u8 transmit_discard_vport_down[0x40]; 3881 3882 u8 async_eq_overrun[0x20]; 3883 3884 u8 comp_eq_overrun[0x20]; 3885 3886 u8 reserved_at_180[0x20]; 3887 3888 u8 invalid_command[0x20]; 3889 3890 u8 quota_exceeded_command[0x20]; 3891 3892 u8 internal_rq_out_of_buffer[0x20]; 3893 3894 u8 cq_overrun[0x20]; 3895 3896 u8 eth_wqe_too_small[0x20]; 3897 3898 u8 reserved_at_220[0xc0]; 3899 3900 u8 generated_pkt_steering_fail[0x40]; 3901 3902 u8 handled_pkt_steering_fail[0x40]; 3903 3904 u8 reserved_at_360[0xc80]; 3905 }; 3906 3907 struct mlx5_ifc_traffic_counter_bits { 3908 u8 packets[0x40]; 3909 3910 u8 octets[0x40]; 3911 }; 3912 3913 struct mlx5_ifc_tisc_bits { 3914 u8 strict_lag_tx_port_affinity[0x1]; 3915 u8 tls_en[0x1]; 3916 u8 reserved_at_2[0x2]; 3917 u8 lag_tx_port_affinity[0x04]; 3918 3919 u8 reserved_at_8[0x4]; 3920 u8 prio[0x4]; 3921 u8 reserved_at_10[0x10]; 3922 3923 u8 reserved_at_20[0x100]; 3924 3925 u8 reserved_at_120[0x8]; 3926 u8 transport_domain[0x18]; 3927 3928 u8 reserved_at_140[0x8]; 3929 u8 underlay_qpn[0x18]; 3930 3931 u8 reserved_at_160[0x8]; 3932 u8 pd[0x18]; 3933 3934 u8 reserved_at_180[0x380]; 3935 }; 3936 3937 enum { 3938 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3939 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3940 }; 3941 3942 enum { 3943 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3944 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3945 }; 3946 3947 enum { 3948 MLX5_RX_HASH_FN_NONE = 0x0, 3949 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3950 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3951 }; 3952 3953 enum { 3954 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3955 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3956 }; 3957 3958 struct mlx5_ifc_tirc_bits { 3959 u8 reserved_at_0[0x20]; 3960 3961 u8 disp_type[0x4]; 3962 u8 tls_en[0x1]; 3963 u8 reserved_at_25[0x1b]; 3964 3965 u8 reserved_at_40[0x40]; 3966 3967 u8 reserved_at_80[0x4]; 3968 u8 lro_timeout_period_usecs[0x10]; 3969 u8 packet_merge_mask[0x4]; 3970 u8 lro_max_ip_payload_size[0x8]; 3971 3972 u8 reserved_at_a0[0x40]; 3973 3974 u8 reserved_at_e0[0x8]; 3975 u8 inline_rqn[0x18]; 3976 3977 u8 rx_hash_symmetric[0x1]; 3978 u8 reserved_at_101[0x1]; 3979 u8 tunneled_offload_en[0x1]; 3980 u8 reserved_at_103[0x5]; 3981 u8 indirect_table[0x18]; 3982 3983 u8 rx_hash_fn[0x4]; 3984 u8 reserved_at_124[0x2]; 3985 u8 self_lb_block[0x2]; 3986 u8 transport_domain[0x18]; 3987 3988 u8 rx_hash_toeplitz_key[10][0x20]; 3989 3990 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3991 3992 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3993 3994 u8 reserved_at_2c0[0x4c0]; 3995 }; 3996 3997 enum { 3998 MLX5_SRQC_STATE_GOOD = 0x0, 3999 MLX5_SRQC_STATE_ERROR = 0x1, 4000 }; 4001 4002 struct mlx5_ifc_srqc_bits { 4003 u8 state[0x4]; 4004 u8 log_srq_size[0x4]; 4005 u8 reserved_at_8[0x18]; 4006 4007 u8 wq_signature[0x1]; 4008 u8 cont_srq[0x1]; 4009 u8 reserved_at_22[0x1]; 4010 u8 rlky[0x1]; 4011 u8 reserved_at_24[0x1]; 4012 u8 log_rq_stride[0x3]; 4013 u8 xrcd[0x18]; 4014 4015 u8 page_offset[0x6]; 4016 u8 reserved_at_46[0x2]; 4017 u8 cqn[0x18]; 4018 4019 u8 reserved_at_60[0x20]; 4020 4021 u8 reserved_at_80[0x2]; 4022 u8 log_page_size[0x6]; 4023 u8 reserved_at_88[0x18]; 4024 4025 u8 reserved_at_a0[0x20]; 4026 4027 u8 reserved_at_c0[0x8]; 4028 u8 pd[0x18]; 4029 4030 u8 lwm[0x10]; 4031 u8 wqe_cnt[0x10]; 4032 4033 u8 reserved_at_100[0x40]; 4034 4035 u8 dbr_addr[0x40]; 4036 4037 u8 reserved_at_180[0x80]; 4038 }; 4039 4040 enum { 4041 MLX5_SQC_STATE_RST = 0x0, 4042 MLX5_SQC_STATE_RDY = 0x1, 4043 MLX5_SQC_STATE_ERR = 0x3, 4044 }; 4045 4046 struct mlx5_ifc_sqc_bits { 4047 u8 rlky[0x1]; 4048 u8 cd_master[0x1]; 4049 u8 fre[0x1]; 4050 u8 flush_in_error_en[0x1]; 4051 u8 allow_multi_pkt_send_wqe[0x1]; 4052 u8 min_wqe_inline_mode[0x3]; 4053 u8 state[0x4]; 4054 u8 reg_umr[0x1]; 4055 u8 allow_swp[0x1]; 4056 u8 hairpin[0x1]; 4057 u8 non_wire[0x1]; 4058 u8 reserved_at_10[0xa]; 4059 u8 ts_format[0x2]; 4060 u8 reserved_at_1c[0x4]; 4061 4062 u8 reserved_at_20[0x8]; 4063 u8 user_index[0x18]; 4064 4065 u8 reserved_at_40[0x8]; 4066 u8 cqn[0x18]; 4067 4068 u8 reserved_at_60[0x8]; 4069 u8 hairpin_peer_rq[0x18]; 4070 4071 u8 reserved_at_80[0x10]; 4072 u8 hairpin_peer_vhca[0x10]; 4073 4074 u8 reserved_at_a0[0x20]; 4075 4076 u8 reserved_at_c0[0x8]; 4077 u8 ts_cqe_to_dest_cqn[0x18]; 4078 4079 u8 reserved_at_e0[0x10]; 4080 u8 packet_pacing_rate_limit_index[0x10]; 4081 u8 tis_lst_sz[0x10]; 4082 u8 qos_queue_group_id[0x10]; 4083 4084 u8 reserved_at_120[0x40]; 4085 4086 u8 reserved_at_160[0x8]; 4087 u8 tis_num_0[0x18]; 4088 4089 struct mlx5_ifc_wq_bits wq; 4090 }; 4091 4092 enum { 4093 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 4094 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 4095 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 4096 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 4097 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 4098 }; 4099 4100 enum { 4101 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 4102 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 4103 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 4104 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 4105 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, 4106 }; 4107 4108 enum { 4109 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4110 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4111 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4112 }; 4113 4114 enum { 4115 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, 4116 TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, 4117 TSAR_TYPE_CAP_MASK_ETS = 1 << 2, 4118 }; 4119 4120 struct mlx5_ifc_tsar_element_bits { 4121 u8 reserved_at_0[0x8]; 4122 u8 tsar_type[0x8]; 4123 u8 reserved_at_10[0x10]; 4124 }; 4125 4126 struct mlx5_ifc_vport_element_bits { 4127 u8 reserved_at_0[0x10]; 4128 u8 vport_number[0x10]; 4129 }; 4130 4131 struct mlx5_ifc_vport_tc_element_bits { 4132 u8 traffic_class[0x4]; 4133 u8 reserved_at_4[0xc]; 4134 u8 vport_number[0x10]; 4135 }; 4136 4137 union mlx5_ifc_element_attributes_bits { 4138 struct mlx5_ifc_tsar_element_bits tsar; 4139 struct mlx5_ifc_vport_element_bits vport; 4140 struct mlx5_ifc_vport_tc_element_bits vport_tc; 4141 u8 reserved_at_0[0x20]; 4142 }; 4143 4144 struct mlx5_ifc_scheduling_context_bits { 4145 u8 element_type[0x8]; 4146 u8 reserved_at_8[0x18]; 4147 4148 union mlx5_ifc_element_attributes_bits element_attributes; 4149 4150 u8 parent_element_id[0x20]; 4151 4152 u8 reserved_at_60[0x40]; 4153 4154 u8 bw_share[0x20]; 4155 4156 u8 max_average_bw[0x20]; 4157 4158 u8 reserved_at_e0[0x120]; 4159 }; 4160 4161 struct mlx5_ifc_rqtc_bits { 4162 u8 reserved_at_0[0xa0]; 4163 4164 u8 reserved_at_a0[0x5]; 4165 u8 list_q_type[0x3]; 4166 u8 reserved_at_a8[0x8]; 4167 u8 rqt_max_size[0x10]; 4168 4169 u8 rq_vhca_id_format[0x1]; 4170 u8 reserved_at_c1[0xf]; 4171 u8 rqt_actual_size[0x10]; 4172 4173 u8 reserved_at_e0[0x6a0]; 4174 4175 union { 4176 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4177 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4178 }; 4179 }; 4180 4181 enum { 4182 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4183 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4184 }; 4185 4186 enum { 4187 MLX5_RQC_STATE_RST = 0x0, 4188 MLX5_RQC_STATE_RDY = 0x1, 4189 MLX5_RQC_STATE_ERR = 0x3, 4190 }; 4191 4192 enum { 4193 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4194 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4195 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4196 }; 4197 4198 enum { 4199 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4200 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4201 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4202 }; 4203 4204 struct mlx5_ifc_rqc_bits { 4205 u8 rlky[0x1]; 4206 u8 delay_drop_en[0x1]; 4207 u8 scatter_fcs[0x1]; 4208 u8 vsd[0x1]; 4209 u8 mem_rq_type[0x4]; 4210 u8 state[0x4]; 4211 u8 reserved_at_c[0x1]; 4212 u8 flush_in_error_en[0x1]; 4213 u8 hairpin[0x1]; 4214 u8 reserved_at_f[0xb]; 4215 u8 ts_format[0x2]; 4216 u8 reserved_at_1c[0x4]; 4217 4218 u8 reserved_at_20[0x8]; 4219 u8 user_index[0x18]; 4220 4221 u8 reserved_at_40[0x8]; 4222 u8 cqn[0x18]; 4223 4224 u8 counter_set_id[0x8]; 4225 u8 reserved_at_68[0x18]; 4226 4227 u8 reserved_at_80[0x8]; 4228 u8 rmpn[0x18]; 4229 4230 u8 reserved_at_a0[0x8]; 4231 u8 hairpin_peer_sq[0x18]; 4232 4233 u8 reserved_at_c0[0x10]; 4234 u8 hairpin_peer_vhca[0x10]; 4235 4236 u8 reserved_at_e0[0x46]; 4237 u8 shampo_no_match_alignment_granularity[0x2]; 4238 u8 reserved_at_128[0x6]; 4239 u8 shampo_match_criteria_type[0x2]; 4240 u8 reservation_timeout[0x10]; 4241 4242 u8 reserved_at_140[0x40]; 4243 4244 struct mlx5_ifc_wq_bits wq; 4245 }; 4246 4247 enum { 4248 MLX5_RMPC_STATE_RDY = 0x1, 4249 MLX5_RMPC_STATE_ERR = 0x3, 4250 }; 4251 4252 struct mlx5_ifc_rmpc_bits { 4253 u8 reserved_at_0[0x8]; 4254 u8 state[0x4]; 4255 u8 reserved_at_c[0x14]; 4256 4257 u8 basic_cyclic_rcv_wqe[0x1]; 4258 u8 reserved_at_21[0x1f]; 4259 4260 u8 reserved_at_40[0x140]; 4261 4262 struct mlx5_ifc_wq_bits wq; 4263 }; 4264 4265 enum { 4266 VHCA_ID_TYPE_HW = 0, 4267 VHCA_ID_TYPE_SW = 1, 4268 }; 4269 4270 struct mlx5_ifc_nic_vport_context_bits { 4271 u8 reserved_at_0[0x5]; 4272 u8 min_wqe_inline_mode[0x3]; 4273 u8 reserved_at_8[0x15]; 4274 u8 disable_mc_local_lb[0x1]; 4275 u8 disable_uc_local_lb[0x1]; 4276 u8 roce_en[0x1]; 4277 4278 u8 arm_change_event[0x1]; 4279 u8 reserved_at_21[0x1a]; 4280 u8 event_on_mtu[0x1]; 4281 u8 event_on_promisc_change[0x1]; 4282 u8 event_on_vlan_change[0x1]; 4283 u8 event_on_mc_address_change[0x1]; 4284 u8 event_on_uc_address_change[0x1]; 4285 4286 u8 vhca_id_type[0x1]; 4287 u8 reserved_at_41[0xb]; 4288 u8 affiliation_criteria[0x4]; 4289 u8 affiliated_vhca_id[0x10]; 4290 4291 u8 reserved_at_60[0xa0]; 4292 4293 u8 reserved_at_100[0x1]; 4294 u8 sd_group[0x3]; 4295 u8 reserved_at_104[0x1c]; 4296 4297 u8 reserved_at_120[0x10]; 4298 u8 mtu[0x10]; 4299 4300 u8 system_image_guid[0x40]; 4301 u8 port_guid[0x40]; 4302 u8 node_guid[0x40]; 4303 4304 u8 reserved_at_200[0x140]; 4305 u8 qkey_violation_counter[0x10]; 4306 u8 reserved_at_350[0x430]; 4307 4308 u8 promisc_uc[0x1]; 4309 u8 promisc_mc[0x1]; 4310 u8 promisc_all[0x1]; 4311 u8 reserved_at_783[0x2]; 4312 u8 allowed_list_type[0x3]; 4313 u8 reserved_at_788[0xc]; 4314 u8 allowed_list_size[0xc]; 4315 4316 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4317 4318 u8 reserved_at_7e0[0x20]; 4319 4320 u8 current_uc_mac_address[][0x40]; 4321 }; 4322 4323 enum { 4324 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4325 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4326 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4327 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4328 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4329 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4330 MLX5_MKC_ACCESS_MODE_CROSSING = 0x6, 4331 }; 4332 4333 struct mlx5_ifc_mkc_bits { 4334 u8 reserved_at_0[0x1]; 4335 u8 free[0x1]; 4336 u8 reserved_at_2[0x1]; 4337 u8 access_mode_4_2[0x3]; 4338 u8 reserved_at_6[0x7]; 4339 u8 relaxed_ordering_write[0x1]; 4340 u8 reserved_at_e[0x1]; 4341 u8 small_fence_on_rdma_read_response[0x1]; 4342 u8 umr_en[0x1]; 4343 u8 a[0x1]; 4344 u8 rw[0x1]; 4345 u8 rr[0x1]; 4346 u8 lw[0x1]; 4347 u8 lr[0x1]; 4348 u8 access_mode_1_0[0x2]; 4349 u8 reserved_at_18[0x2]; 4350 u8 ma_translation_mode[0x2]; 4351 u8 reserved_at_1c[0x4]; 4352 4353 u8 qpn[0x18]; 4354 u8 mkey_7_0[0x8]; 4355 4356 u8 reserved_at_40[0x20]; 4357 4358 u8 length64[0x1]; 4359 u8 bsf_en[0x1]; 4360 u8 sync_umr[0x1]; 4361 u8 reserved_at_63[0x2]; 4362 u8 expected_sigerr_count[0x1]; 4363 u8 reserved_at_66[0x1]; 4364 u8 en_rinval[0x1]; 4365 u8 pd[0x18]; 4366 4367 u8 start_addr[0x40]; 4368 4369 u8 len[0x40]; 4370 4371 u8 bsf_octword_size[0x20]; 4372 4373 u8 reserved_at_120[0x60]; 4374 4375 u8 crossing_target_vhca_id[0x10]; 4376 u8 reserved_at_190[0x10]; 4377 4378 u8 translations_octword_size[0x20]; 4379 4380 u8 reserved_at_1c0[0x19]; 4381 u8 relaxed_ordering_read[0x1]; 4382 u8 log_page_size[0x6]; 4383 4384 u8 reserved_at_1e0[0x20]; 4385 }; 4386 4387 struct mlx5_ifc_pkey_bits { 4388 u8 reserved_at_0[0x10]; 4389 u8 pkey[0x10]; 4390 }; 4391 4392 struct mlx5_ifc_array128_auto_bits { 4393 u8 array128_auto[16][0x8]; 4394 }; 4395 4396 struct mlx5_ifc_hca_vport_context_bits { 4397 u8 field_select[0x20]; 4398 4399 u8 reserved_at_20[0xe0]; 4400 4401 u8 sm_virt_aware[0x1]; 4402 u8 has_smi[0x1]; 4403 u8 has_raw[0x1]; 4404 u8 grh_required[0x1]; 4405 u8 reserved_at_104[0x4]; 4406 u8 num_port_plane[0x8]; 4407 u8 port_physical_state[0x4]; 4408 u8 vport_state_policy[0x4]; 4409 u8 port_state[0x4]; 4410 u8 vport_state[0x4]; 4411 4412 u8 reserved_at_120[0x20]; 4413 4414 u8 system_image_guid[0x40]; 4415 4416 u8 port_guid[0x40]; 4417 4418 u8 node_guid[0x40]; 4419 4420 u8 cap_mask1[0x20]; 4421 4422 u8 cap_mask1_field_select[0x20]; 4423 4424 u8 cap_mask2[0x20]; 4425 4426 u8 cap_mask2_field_select[0x20]; 4427 4428 u8 reserved_at_280[0x80]; 4429 4430 u8 lid[0x10]; 4431 u8 reserved_at_310[0x4]; 4432 u8 init_type_reply[0x4]; 4433 u8 lmc[0x3]; 4434 u8 subnet_timeout[0x5]; 4435 4436 u8 sm_lid[0x10]; 4437 u8 sm_sl[0x4]; 4438 u8 reserved_at_334[0xc]; 4439 4440 u8 qkey_violation_counter[0x10]; 4441 u8 pkey_violation_counter[0x10]; 4442 4443 u8 reserved_at_360[0xca0]; 4444 }; 4445 4446 struct mlx5_ifc_esw_vport_context_bits { 4447 u8 fdb_to_vport_reg_c[0x1]; 4448 u8 reserved_at_1[0x2]; 4449 u8 vport_svlan_strip[0x1]; 4450 u8 vport_cvlan_strip[0x1]; 4451 u8 vport_svlan_insert[0x1]; 4452 u8 vport_cvlan_insert[0x2]; 4453 u8 fdb_to_vport_reg_c_id[0x8]; 4454 u8 reserved_at_10[0x10]; 4455 4456 u8 reserved_at_20[0x20]; 4457 4458 u8 svlan_cfi[0x1]; 4459 u8 svlan_pcp[0x3]; 4460 u8 svlan_id[0xc]; 4461 u8 cvlan_cfi[0x1]; 4462 u8 cvlan_pcp[0x3]; 4463 u8 cvlan_id[0xc]; 4464 4465 u8 reserved_at_60[0x720]; 4466 4467 u8 sw_steering_vport_icm_address_rx[0x40]; 4468 4469 u8 sw_steering_vport_icm_address_tx[0x40]; 4470 }; 4471 4472 enum { 4473 MLX5_EQC_STATUS_OK = 0x0, 4474 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4475 }; 4476 4477 enum { 4478 MLX5_EQC_ST_ARMED = 0x9, 4479 MLX5_EQC_ST_FIRED = 0xa, 4480 }; 4481 4482 struct mlx5_ifc_eqc_bits { 4483 u8 status[0x4]; 4484 u8 reserved_at_4[0x9]; 4485 u8 ec[0x1]; 4486 u8 oi[0x1]; 4487 u8 reserved_at_f[0x5]; 4488 u8 st[0x4]; 4489 u8 reserved_at_18[0x8]; 4490 4491 u8 reserved_at_20[0x20]; 4492 4493 u8 reserved_at_40[0x14]; 4494 u8 page_offset[0x6]; 4495 u8 reserved_at_5a[0x6]; 4496 4497 u8 reserved_at_60[0x3]; 4498 u8 log_eq_size[0x5]; 4499 u8 uar_page[0x18]; 4500 4501 u8 reserved_at_80[0x20]; 4502 4503 u8 reserved_at_a0[0x14]; 4504 u8 intr[0xc]; 4505 4506 u8 reserved_at_c0[0x3]; 4507 u8 log_page_size[0x5]; 4508 u8 reserved_at_c8[0x18]; 4509 4510 u8 reserved_at_e0[0x60]; 4511 4512 u8 reserved_at_140[0x8]; 4513 u8 consumer_counter[0x18]; 4514 4515 u8 reserved_at_160[0x8]; 4516 u8 producer_counter[0x18]; 4517 4518 u8 reserved_at_180[0x80]; 4519 }; 4520 4521 enum { 4522 MLX5_DCTC_STATE_ACTIVE = 0x0, 4523 MLX5_DCTC_STATE_DRAINING = 0x1, 4524 MLX5_DCTC_STATE_DRAINED = 0x2, 4525 }; 4526 4527 enum { 4528 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4529 MLX5_DCTC_CS_RES_NA = 0x1, 4530 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4531 }; 4532 4533 enum { 4534 MLX5_DCTC_MTU_256_BYTES = 0x1, 4535 MLX5_DCTC_MTU_512_BYTES = 0x2, 4536 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4537 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4538 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4539 }; 4540 4541 struct mlx5_ifc_dctc_bits { 4542 u8 reserved_at_0[0x4]; 4543 u8 state[0x4]; 4544 u8 reserved_at_8[0x18]; 4545 4546 u8 reserved_at_20[0x8]; 4547 u8 user_index[0x18]; 4548 4549 u8 reserved_at_40[0x8]; 4550 u8 cqn[0x18]; 4551 4552 u8 counter_set_id[0x8]; 4553 u8 atomic_mode[0x4]; 4554 u8 rre[0x1]; 4555 u8 rwe[0x1]; 4556 u8 rae[0x1]; 4557 u8 atomic_like_write_en[0x1]; 4558 u8 latency_sensitive[0x1]; 4559 u8 rlky[0x1]; 4560 u8 free_ar[0x1]; 4561 u8 reserved_at_73[0xd]; 4562 4563 u8 reserved_at_80[0x8]; 4564 u8 cs_res[0x8]; 4565 u8 reserved_at_90[0x3]; 4566 u8 min_rnr_nak[0x5]; 4567 u8 reserved_at_98[0x8]; 4568 4569 u8 reserved_at_a0[0x8]; 4570 u8 srqn_xrqn[0x18]; 4571 4572 u8 reserved_at_c0[0x8]; 4573 u8 pd[0x18]; 4574 4575 u8 tclass[0x8]; 4576 u8 reserved_at_e8[0x4]; 4577 u8 flow_label[0x14]; 4578 4579 u8 dc_access_key[0x40]; 4580 4581 u8 reserved_at_140[0x5]; 4582 u8 mtu[0x3]; 4583 u8 port[0x8]; 4584 u8 pkey_index[0x10]; 4585 4586 u8 reserved_at_160[0x8]; 4587 u8 my_addr_index[0x8]; 4588 u8 reserved_at_170[0x8]; 4589 u8 hop_limit[0x8]; 4590 4591 u8 dc_access_key_violation_count[0x20]; 4592 4593 u8 reserved_at_1a0[0x14]; 4594 u8 dei_cfi[0x1]; 4595 u8 eth_prio[0x3]; 4596 u8 ecn[0x2]; 4597 u8 dscp[0x6]; 4598 4599 u8 reserved_at_1c0[0x20]; 4600 u8 ece[0x20]; 4601 }; 4602 4603 enum { 4604 MLX5_CQC_STATUS_OK = 0x0, 4605 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4606 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4607 }; 4608 4609 enum { 4610 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4611 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4612 }; 4613 4614 enum { 4615 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4616 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4617 MLX5_CQC_ST_FIRED = 0xa, 4618 }; 4619 4620 enum mlx5_cq_period_mode { 4621 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4622 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4623 MLX5_CQ_PERIOD_NUM_MODES, 4624 }; 4625 4626 struct mlx5_ifc_cqc_bits { 4627 u8 status[0x4]; 4628 u8 reserved_at_4[0x2]; 4629 u8 dbr_umem_valid[0x1]; 4630 u8 apu_cq[0x1]; 4631 u8 cqe_sz[0x3]; 4632 u8 cc[0x1]; 4633 u8 reserved_at_c[0x1]; 4634 u8 scqe_break_moderation_en[0x1]; 4635 u8 oi[0x1]; 4636 u8 cq_period_mode[0x2]; 4637 u8 cqe_comp_en[0x1]; 4638 u8 mini_cqe_res_format[0x2]; 4639 u8 st[0x4]; 4640 u8 reserved_at_18[0x6]; 4641 u8 cqe_compression_layout[0x2]; 4642 4643 u8 reserved_at_20[0x20]; 4644 4645 u8 reserved_at_40[0x14]; 4646 u8 page_offset[0x6]; 4647 u8 reserved_at_5a[0x6]; 4648 4649 u8 reserved_at_60[0x3]; 4650 u8 log_cq_size[0x5]; 4651 u8 uar_page[0x18]; 4652 4653 u8 reserved_at_80[0x4]; 4654 u8 cq_period[0xc]; 4655 u8 cq_max_count[0x10]; 4656 4657 u8 c_eqn_or_apu_element[0x20]; 4658 4659 u8 reserved_at_c0[0x3]; 4660 u8 log_page_size[0x5]; 4661 u8 reserved_at_c8[0x18]; 4662 4663 u8 reserved_at_e0[0x20]; 4664 4665 u8 reserved_at_100[0x8]; 4666 u8 last_notified_index[0x18]; 4667 4668 u8 reserved_at_120[0x8]; 4669 u8 last_solicit_index[0x18]; 4670 4671 u8 reserved_at_140[0x8]; 4672 u8 consumer_counter[0x18]; 4673 4674 u8 reserved_at_160[0x8]; 4675 u8 producer_counter[0x18]; 4676 4677 u8 reserved_at_180[0x40]; 4678 4679 u8 dbr_addr[0x40]; 4680 }; 4681 4682 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4683 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4684 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4685 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4686 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4687 u8 reserved_at_0[0x800]; 4688 }; 4689 4690 struct mlx5_ifc_query_adapter_param_block_bits { 4691 u8 reserved_at_0[0xc0]; 4692 4693 u8 reserved_at_c0[0x8]; 4694 u8 ieee_vendor_id[0x18]; 4695 4696 u8 reserved_at_e0[0x10]; 4697 u8 vsd_vendor_id[0x10]; 4698 4699 u8 vsd[208][0x8]; 4700 4701 u8 vsd_contd_psid[16][0x8]; 4702 }; 4703 4704 enum { 4705 MLX5_XRQC_STATE_GOOD = 0x0, 4706 MLX5_XRQC_STATE_ERROR = 0x1, 4707 }; 4708 4709 enum { 4710 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4711 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4712 }; 4713 4714 enum { 4715 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4716 }; 4717 4718 struct mlx5_ifc_tag_matching_topology_context_bits { 4719 u8 log_matching_list_sz[0x4]; 4720 u8 reserved_at_4[0xc]; 4721 u8 append_next_index[0x10]; 4722 4723 u8 sw_phase_cnt[0x10]; 4724 u8 hw_phase_cnt[0x10]; 4725 4726 u8 reserved_at_40[0x40]; 4727 }; 4728 4729 struct mlx5_ifc_xrqc_bits { 4730 u8 state[0x4]; 4731 u8 rlkey[0x1]; 4732 u8 reserved_at_5[0xf]; 4733 u8 topology[0x4]; 4734 u8 reserved_at_18[0x4]; 4735 u8 offload[0x4]; 4736 4737 u8 reserved_at_20[0x8]; 4738 u8 user_index[0x18]; 4739 4740 u8 reserved_at_40[0x8]; 4741 u8 cqn[0x18]; 4742 4743 u8 reserved_at_60[0xa0]; 4744 4745 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4746 4747 u8 reserved_at_180[0x280]; 4748 4749 struct mlx5_ifc_wq_bits wq; 4750 }; 4751 4752 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4753 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4754 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4755 u8 reserved_at_0[0x20]; 4756 }; 4757 4758 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4759 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4760 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4761 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4762 u8 reserved_at_0[0x20]; 4763 }; 4764 4765 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4766 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4767 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4768 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4769 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4770 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4771 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4772 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4773 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4774 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4775 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4776 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4777 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4778 u8 reserved_at_0[0x7c0]; 4779 }; 4780 4781 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4782 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4783 u8 reserved_at_0[0x7c0]; 4784 }; 4785 4786 union mlx5_ifc_event_auto_bits { 4787 struct mlx5_ifc_comp_event_bits comp_event; 4788 struct mlx5_ifc_dct_events_bits dct_events; 4789 struct mlx5_ifc_qp_events_bits qp_events; 4790 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4791 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4792 struct mlx5_ifc_cq_error_bits cq_error; 4793 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4794 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4795 struct mlx5_ifc_gpio_event_bits gpio_event; 4796 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4797 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4798 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4799 u8 reserved_at_0[0xe0]; 4800 }; 4801 4802 struct mlx5_ifc_health_buffer_bits { 4803 u8 reserved_at_0[0x100]; 4804 4805 u8 assert_existptr[0x20]; 4806 4807 u8 assert_callra[0x20]; 4808 4809 u8 reserved_at_140[0x20]; 4810 4811 u8 time[0x20]; 4812 4813 u8 fw_version[0x20]; 4814 4815 u8 hw_id[0x20]; 4816 4817 u8 rfr[0x1]; 4818 u8 reserved_at_1c1[0x3]; 4819 u8 valid[0x1]; 4820 u8 severity[0x3]; 4821 u8 reserved_at_1c8[0x18]; 4822 4823 u8 irisc_index[0x8]; 4824 u8 synd[0x8]; 4825 u8 ext_synd[0x10]; 4826 }; 4827 4828 struct mlx5_ifc_register_loopback_control_bits { 4829 u8 no_lb[0x1]; 4830 u8 reserved_at_1[0x7]; 4831 u8 port[0x8]; 4832 u8 reserved_at_10[0x10]; 4833 4834 u8 reserved_at_20[0x60]; 4835 }; 4836 4837 enum { 4838 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4839 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4840 }; 4841 4842 struct mlx5_ifc_teardown_hca_out_bits { 4843 u8 status[0x8]; 4844 u8 reserved_at_8[0x18]; 4845 4846 u8 syndrome[0x20]; 4847 4848 u8 reserved_at_40[0x3f]; 4849 4850 u8 state[0x1]; 4851 }; 4852 4853 enum { 4854 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4855 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4856 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4857 }; 4858 4859 struct mlx5_ifc_teardown_hca_in_bits { 4860 u8 opcode[0x10]; 4861 u8 reserved_at_10[0x10]; 4862 4863 u8 reserved_at_20[0x10]; 4864 u8 op_mod[0x10]; 4865 4866 u8 reserved_at_40[0x10]; 4867 u8 profile[0x10]; 4868 4869 u8 reserved_at_60[0x20]; 4870 }; 4871 4872 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4873 u8 status[0x8]; 4874 u8 reserved_at_8[0x18]; 4875 4876 u8 syndrome[0x20]; 4877 4878 u8 reserved_at_40[0x40]; 4879 }; 4880 4881 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4882 u8 opcode[0x10]; 4883 u8 uid[0x10]; 4884 4885 u8 reserved_at_20[0x10]; 4886 u8 op_mod[0x10]; 4887 4888 u8 reserved_at_40[0x8]; 4889 u8 qpn[0x18]; 4890 4891 u8 reserved_at_60[0x20]; 4892 4893 u8 opt_param_mask[0x20]; 4894 4895 u8 reserved_at_a0[0x20]; 4896 4897 struct mlx5_ifc_qpc_bits qpc; 4898 4899 u8 reserved_at_800[0x80]; 4900 }; 4901 4902 struct mlx5_ifc_sqd2rts_qp_out_bits { 4903 u8 status[0x8]; 4904 u8 reserved_at_8[0x18]; 4905 4906 u8 syndrome[0x20]; 4907 4908 u8 reserved_at_40[0x40]; 4909 }; 4910 4911 struct mlx5_ifc_sqd2rts_qp_in_bits { 4912 u8 opcode[0x10]; 4913 u8 uid[0x10]; 4914 4915 u8 reserved_at_20[0x10]; 4916 u8 op_mod[0x10]; 4917 4918 u8 reserved_at_40[0x8]; 4919 u8 qpn[0x18]; 4920 4921 u8 reserved_at_60[0x20]; 4922 4923 u8 opt_param_mask[0x20]; 4924 4925 u8 reserved_at_a0[0x20]; 4926 4927 struct mlx5_ifc_qpc_bits qpc; 4928 4929 u8 reserved_at_800[0x80]; 4930 }; 4931 4932 struct mlx5_ifc_set_roce_address_out_bits { 4933 u8 status[0x8]; 4934 u8 reserved_at_8[0x18]; 4935 4936 u8 syndrome[0x20]; 4937 4938 u8 reserved_at_40[0x40]; 4939 }; 4940 4941 struct mlx5_ifc_set_roce_address_in_bits { 4942 u8 opcode[0x10]; 4943 u8 reserved_at_10[0x10]; 4944 4945 u8 reserved_at_20[0x10]; 4946 u8 op_mod[0x10]; 4947 4948 u8 roce_address_index[0x10]; 4949 u8 reserved_at_50[0xc]; 4950 u8 vhca_port_num[0x4]; 4951 4952 u8 reserved_at_60[0x20]; 4953 4954 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4955 }; 4956 4957 struct mlx5_ifc_set_mad_demux_out_bits { 4958 u8 status[0x8]; 4959 u8 reserved_at_8[0x18]; 4960 4961 u8 syndrome[0x20]; 4962 4963 u8 reserved_at_40[0x40]; 4964 }; 4965 4966 enum { 4967 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4968 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4969 }; 4970 4971 struct mlx5_ifc_set_mad_demux_in_bits { 4972 u8 opcode[0x10]; 4973 u8 reserved_at_10[0x10]; 4974 4975 u8 reserved_at_20[0x10]; 4976 u8 op_mod[0x10]; 4977 4978 u8 reserved_at_40[0x20]; 4979 4980 u8 reserved_at_60[0x6]; 4981 u8 demux_mode[0x2]; 4982 u8 reserved_at_68[0x18]; 4983 }; 4984 4985 struct mlx5_ifc_set_l2_table_entry_out_bits { 4986 u8 status[0x8]; 4987 u8 reserved_at_8[0x18]; 4988 4989 u8 syndrome[0x20]; 4990 4991 u8 reserved_at_40[0x40]; 4992 }; 4993 4994 struct mlx5_ifc_set_l2_table_entry_in_bits { 4995 u8 opcode[0x10]; 4996 u8 reserved_at_10[0x10]; 4997 4998 u8 reserved_at_20[0x10]; 4999 u8 op_mod[0x10]; 5000 5001 u8 reserved_at_40[0x60]; 5002 5003 u8 reserved_at_a0[0x8]; 5004 u8 table_index[0x18]; 5005 5006 u8 reserved_at_c0[0x20]; 5007 5008 u8 reserved_at_e0[0x10]; 5009 u8 silent_mode_valid[0x1]; 5010 u8 silent_mode[0x1]; 5011 u8 reserved_at_f2[0x1]; 5012 u8 vlan_valid[0x1]; 5013 u8 vlan[0xc]; 5014 5015 struct mlx5_ifc_mac_address_layout_bits mac_address; 5016 5017 u8 reserved_at_140[0xc0]; 5018 }; 5019 5020 struct mlx5_ifc_set_issi_out_bits { 5021 u8 status[0x8]; 5022 u8 reserved_at_8[0x18]; 5023 5024 u8 syndrome[0x20]; 5025 5026 u8 reserved_at_40[0x40]; 5027 }; 5028 5029 struct mlx5_ifc_set_issi_in_bits { 5030 u8 opcode[0x10]; 5031 u8 reserved_at_10[0x10]; 5032 5033 u8 reserved_at_20[0x10]; 5034 u8 op_mod[0x10]; 5035 5036 u8 reserved_at_40[0x10]; 5037 u8 current_issi[0x10]; 5038 5039 u8 reserved_at_60[0x20]; 5040 }; 5041 5042 struct mlx5_ifc_set_hca_cap_out_bits { 5043 u8 status[0x8]; 5044 u8 reserved_at_8[0x18]; 5045 5046 u8 syndrome[0x20]; 5047 5048 u8 reserved_at_40[0x40]; 5049 }; 5050 5051 struct mlx5_ifc_set_hca_cap_in_bits { 5052 u8 opcode[0x10]; 5053 u8 reserved_at_10[0x10]; 5054 5055 u8 reserved_at_20[0x10]; 5056 u8 op_mod[0x10]; 5057 5058 u8 other_function[0x1]; 5059 u8 ec_vf_function[0x1]; 5060 u8 reserved_at_42[0xe]; 5061 u8 function_id[0x10]; 5062 5063 u8 reserved_at_60[0x20]; 5064 5065 union mlx5_ifc_hca_cap_union_bits capability; 5066 }; 5067 5068 enum { 5069 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 5070 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 5071 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 5072 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 5073 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 5074 }; 5075 5076 struct mlx5_ifc_set_fte_out_bits { 5077 u8 status[0x8]; 5078 u8 reserved_at_8[0x18]; 5079 5080 u8 syndrome[0x20]; 5081 5082 u8 reserved_at_40[0x40]; 5083 }; 5084 5085 struct mlx5_ifc_set_fte_in_bits { 5086 u8 opcode[0x10]; 5087 u8 reserved_at_10[0x10]; 5088 5089 u8 reserved_at_20[0x10]; 5090 u8 op_mod[0x10]; 5091 5092 u8 other_vport[0x1]; 5093 u8 reserved_at_41[0xf]; 5094 u8 vport_number[0x10]; 5095 5096 u8 reserved_at_60[0x20]; 5097 5098 u8 table_type[0x8]; 5099 u8 reserved_at_88[0x18]; 5100 5101 u8 reserved_at_a0[0x8]; 5102 u8 table_id[0x18]; 5103 5104 u8 ignore_flow_level[0x1]; 5105 u8 reserved_at_c1[0x17]; 5106 u8 modify_enable_mask[0x8]; 5107 5108 u8 reserved_at_e0[0x20]; 5109 5110 u8 flow_index[0x20]; 5111 5112 u8 reserved_at_120[0xe0]; 5113 5114 struct mlx5_ifc_flow_context_bits flow_context; 5115 }; 5116 5117 struct mlx5_ifc_dest_format_bits { 5118 u8 destination_type[0x8]; 5119 u8 destination_id[0x18]; 5120 5121 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5122 u8 packet_reformat[0x1]; 5123 u8 reserved_at_22[0xe]; 5124 u8 destination_eswitch_owner_vhca_id[0x10]; 5125 }; 5126 5127 struct mlx5_ifc_rts2rts_qp_out_bits { 5128 u8 status[0x8]; 5129 u8 reserved_at_8[0x18]; 5130 5131 u8 syndrome[0x20]; 5132 5133 u8 reserved_at_40[0x20]; 5134 u8 ece[0x20]; 5135 }; 5136 5137 struct mlx5_ifc_rts2rts_qp_in_bits { 5138 u8 opcode[0x10]; 5139 u8 uid[0x10]; 5140 5141 u8 reserved_at_20[0x10]; 5142 u8 op_mod[0x10]; 5143 5144 u8 reserved_at_40[0x8]; 5145 u8 qpn[0x18]; 5146 5147 u8 reserved_at_60[0x20]; 5148 5149 u8 opt_param_mask[0x20]; 5150 5151 u8 ece[0x20]; 5152 5153 struct mlx5_ifc_qpc_bits qpc; 5154 5155 u8 reserved_at_800[0x80]; 5156 }; 5157 5158 struct mlx5_ifc_rtr2rts_qp_out_bits { 5159 u8 status[0x8]; 5160 u8 reserved_at_8[0x18]; 5161 5162 u8 syndrome[0x20]; 5163 5164 u8 reserved_at_40[0x20]; 5165 u8 ece[0x20]; 5166 }; 5167 5168 struct mlx5_ifc_rtr2rts_qp_in_bits { 5169 u8 opcode[0x10]; 5170 u8 uid[0x10]; 5171 5172 u8 reserved_at_20[0x10]; 5173 u8 op_mod[0x10]; 5174 5175 u8 reserved_at_40[0x8]; 5176 u8 qpn[0x18]; 5177 5178 u8 reserved_at_60[0x20]; 5179 5180 u8 opt_param_mask[0x20]; 5181 5182 u8 ece[0x20]; 5183 5184 struct mlx5_ifc_qpc_bits qpc; 5185 5186 u8 reserved_at_800[0x80]; 5187 }; 5188 5189 struct mlx5_ifc_rst2init_qp_out_bits { 5190 u8 status[0x8]; 5191 u8 reserved_at_8[0x18]; 5192 5193 u8 syndrome[0x20]; 5194 5195 u8 reserved_at_40[0x20]; 5196 u8 ece[0x20]; 5197 }; 5198 5199 struct mlx5_ifc_rst2init_qp_in_bits { 5200 u8 opcode[0x10]; 5201 u8 uid[0x10]; 5202 5203 u8 reserved_at_20[0x10]; 5204 u8 op_mod[0x10]; 5205 5206 u8 reserved_at_40[0x8]; 5207 u8 qpn[0x18]; 5208 5209 u8 reserved_at_60[0x20]; 5210 5211 u8 opt_param_mask[0x20]; 5212 5213 u8 ece[0x20]; 5214 5215 struct mlx5_ifc_qpc_bits qpc; 5216 5217 u8 reserved_at_800[0x80]; 5218 }; 5219 5220 struct mlx5_ifc_query_xrq_out_bits { 5221 u8 status[0x8]; 5222 u8 reserved_at_8[0x18]; 5223 5224 u8 syndrome[0x20]; 5225 5226 u8 reserved_at_40[0x40]; 5227 5228 struct mlx5_ifc_xrqc_bits xrq_context; 5229 }; 5230 5231 struct mlx5_ifc_query_xrq_in_bits { 5232 u8 opcode[0x10]; 5233 u8 reserved_at_10[0x10]; 5234 5235 u8 reserved_at_20[0x10]; 5236 u8 op_mod[0x10]; 5237 5238 u8 reserved_at_40[0x8]; 5239 u8 xrqn[0x18]; 5240 5241 u8 reserved_at_60[0x20]; 5242 }; 5243 5244 struct mlx5_ifc_query_xrc_srq_out_bits { 5245 u8 status[0x8]; 5246 u8 reserved_at_8[0x18]; 5247 5248 u8 syndrome[0x20]; 5249 5250 u8 reserved_at_40[0x40]; 5251 5252 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5253 5254 u8 reserved_at_280[0x600]; 5255 5256 u8 pas[][0x40]; 5257 }; 5258 5259 struct mlx5_ifc_query_xrc_srq_in_bits { 5260 u8 opcode[0x10]; 5261 u8 reserved_at_10[0x10]; 5262 5263 u8 reserved_at_20[0x10]; 5264 u8 op_mod[0x10]; 5265 5266 u8 reserved_at_40[0x8]; 5267 u8 xrc_srqn[0x18]; 5268 5269 u8 reserved_at_60[0x20]; 5270 }; 5271 5272 enum { 5273 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5274 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5275 }; 5276 5277 struct mlx5_ifc_query_vport_state_out_bits { 5278 u8 status[0x8]; 5279 u8 reserved_at_8[0x18]; 5280 5281 u8 syndrome[0x20]; 5282 5283 u8 reserved_at_40[0x20]; 5284 5285 u8 reserved_at_60[0x18]; 5286 u8 admin_state[0x4]; 5287 u8 state[0x4]; 5288 }; 5289 5290 struct mlx5_ifc_array1024_auto_bits { 5291 u8 array1024_auto[32][0x20]; 5292 }; 5293 5294 struct mlx5_ifc_query_vuid_in_bits { 5295 u8 opcode[0x10]; 5296 u8 uid[0x10]; 5297 5298 u8 reserved_at_20[0x40]; 5299 5300 u8 query_vfs_vuid[0x1]; 5301 u8 data_direct[0x1]; 5302 u8 reserved_at_62[0xe]; 5303 u8 vhca_id[0x10]; 5304 }; 5305 5306 struct mlx5_ifc_query_vuid_out_bits { 5307 u8 status[0x8]; 5308 u8 reserved_at_8[0x18]; 5309 5310 u8 syndrome[0x20]; 5311 5312 u8 reserved_at_40[0x1a0]; 5313 5314 u8 reserved_at_1e0[0x10]; 5315 u8 num_of_entries[0x10]; 5316 5317 struct mlx5_ifc_array1024_auto_bits vuid[]; 5318 }; 5319 5320 enum { 5321 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5322 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5323 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5324 }; 5325 5326 struct mlx5_ifc_arm_monitor_counter_in_bits { 5327 u8 opcode[0x10]; 5328 u8 uid[0x10]; 5329 5330 u8 reserved_at_20[0x10]; 5331 u8 op_mod[0x10]; 5332 5333 u8 reserved_at_40[0x20]; 5334 5335 u8 reserved_at_60[0x20]; 5336 }; 5337 5338 struct mlx5_ifc_arm_monitor_counter_out_bits { 5339 u8 status[0x8]; 5340 u8 reserved_at_8[0x18]; 5341 5342 u8 syndrome[0x20]; 5343 5344 u8 reserved_at_40[0x40]; 5345 }; 5346 5347 enum { 5348 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5349 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5350 }; 5351 5352 enum mlx5_monitor_counter_ppcnt { 5353 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5354 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5355 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5356 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5357 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5358 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5359 }; 5360 5361 enum { 5362 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5363 }; 5364 5365 struct mlx5_ifc_monitor_counter_output_bits { 5366 u8 reserved_at_0[0x4]; 5367 u8 type[0x4]; 5368 u8 reserved_at_8[0x8]; 5369 u8 counter[0x10]; 5370 5371 u8 counter_group_id[0x20]; 5372 }; 5373 5374 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5375 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5376 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5377 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5378 5379 struct mlx5_ifc_set_monitor_counter_in_bits { 5380 u8 opcode[0x10]; 5381 u8 uid[0x10]; 5382 5383 u8 reserved_at_20[0x10]; 5384 u8 op_mod[0x10]; 5385 5386 u8 reserved_at_40[0x10]; 5387 u8 num_of_counters[0x10]; 5388 5389 u8 reserved_at_60[0x20]; 5390 5391 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5392 }; 5393 5394 struct mlx5_ifc_set_monitor_counter_out_bits { 5395 u8 status[0x8]; 5396 u8 reserved_at_8[0x18]; 5397 5398 u8 syndrome[0x20]; 5399 5400 u8 reserved_at_40[0x40]; 5401 }; 5402 5403 struct mlx5_ifc_query_vport_state_in_bits { 5404 u8 opcode[0x10]; 5405 u8 reserved_at_10[0x10]; 5406 5407 u8 reserved_at_20[0x10]; 5408 u8 op_mod[0x10]; 5409 5410 u8 other_vport[0x1]; 5411 u8 reserved_at_41[0xf]; 5412 u8 vport_number[0x10]; 5413 5414 u8 reserved_at_60[0x20]; 5415 }; 5416 5417 struct mlx5_ifc_query_vnic_env_out_bits { 5418 u8 status[0x8]; 5419 u8 reserved_at_8[0x18]; 5420 5421 u8 syndrome[0x20]; 5422 5423 u8 reserved_at_40[0x40]; 5424 5425 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5426 }; 5427 5428 enum { 5429 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5430 }; 5431 5432 struct mlx5_ifc_query_vnic_env_in_bits { 5433 u8 opcode[0x10]; 5434 u8 reserved_at_10[0x10]; 5435 5436 u8 reserved_at_20[0x10]; 5437 u8 op_mod[0x10]; 5438 5439 u8 other_vport[0x1]; 5440 u8 reserved_at_41[0xf]; 5441 u8 vport_number[0x10]; 5442 5443 u8 reserved_at_60[0x20]; 5444 }; 5445 5446 struct mlx5_ifc_query_vport_counter_out_bits { 5447 u8 status[0x8]; 5448 u8 reserved_at_8[0x18]; 5449 5450 u8 syndrome[0x20]; 5451 5452 u8 reserved_at_40[0x40]; 5453 5454 struct mlx5_ifc_traffic_counter_bits received_errors; 5455 5456 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5457 5458 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5459 5460 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5461 5462 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5463 5464 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5465 5466 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5467 5468 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5469 5470 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5471 5472 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5473 5474 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5475 5476 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5477 5478 struct mlx5_ifc_traffic_counter_bits local_loopback; 5479 5480 u8 reserved_at_700[0x980]; 5481 }; 5482 5483 enum { 5484 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5485 }; 5486 5487 struct mlx5_ifc_query_vport_counter_in_bits { 5488 u8 opcode[0x10]; 5489 u8 reserved_at_10[0x10]; 5490 5491 u8 reserved_at_20[0x10]; 5492 u8 op_mod[0x10]; 5493 5494 u8 other_vport[0x1]; 5495 u8 reserved_at_41[0xb]; 5496 u8 port_num[0x4]; 5497 u8 vport_number[0x10]; 5498 5499 u8 reserved_at_60[0x60]; 5500 5501 u8 clear[0x1]; 5502 u8 reserved_at_c1[0x1f]; 5503 5504 u8 reserved_at_e0[0x20]; 5505 }; 5506 5507 struct mlx5_ifc_query_tis_out_bits { 5508 u8 status[0x8]; 5509 u8 reserved_at_8[0x18]; 5510 5511 u8 syndrome[0x20]; 5512 5513 u8 reserved_at_40[0x40]; 5514 5515 struct mlx5_ifc_tisc_bits tis_context; 5516 }; 5517 5518 struct mlx5_ifc_query_tis_in_bits { 5519 u8 opcode[0x10]; 5520 u8 reserved_at_10[0x10]; 5521 5522 u8 reserved_at_20[0x10]; 5523 u8 op_mod[0x10]; 5524 5525 u8 reserved_at_40[0x8]; 5526 u8 tisn[0x18]; 5527 5528 u8 reserved_at_60[0x20]; 5529 }; 5530 5531 struct mlx5_ifc_query_tir_out_bits { 5532 u8 status[0x8]; 5533 u8 reserved_at_8[0x18]; 5534 5535 u8 syndrome[0x20]; 5536 5537 u8 reserved_at_40[0xc0]; 5538 5539 struct mlx5_ifc_tirc_bits tir_context; 5540 }; 5541 5542 struct mlx5_ifc_query_tir_in_bits { 5543 u8 opcode[0x10]; 5544 u8 reserved_at_10[0x10]; 5545 5546 u8 reserved_at_20[0x10]; 5547 u8 op_mod[0x10]; 5548 5549 u8 reserved_at_40[0x8]; 5550 u8 tirn[0x18]; 5551 5552 u8 reserved_at_60[0x20]; 5553 }; 5554 5555 struct mlx5_ifc_query_srq_out_bits { 5556 u8 status[0x8]; 5557 u8 reserved_at_8[0x18]; 5558 5559 u8 syndrome[0x20]; 5560 5561 u8 reserved_at_40[0x40]; 5562 5563 struct mlx5_ifc_srqc_bits srq_context_entry; 5564 5565 u8 reserved_at_280[0x600]; 5566 5567 u8 pas[][0x40]; 5568 }; 5569 5570 struct mlx5_ifc_query_srq_in_bits { 5571 u8 opcode[0x10]; 5572 u8 reserved_at_10[0x10]; 5573 5574 u8 reserved_at_20[0x10]; 5575 u8 op_mod[0x10]; 5576 5577 u8 reserved_at_40[0x8]; 5578 u8 srqn[0x18]; 5579 5580 u8 reserved_at_60[0x20]; 5581 }; 5582 5583 struct mlx5_ifc_query_sq_out_bits { 5584 u8 status[0x8]; 5585 u8 reserved_at_8[0x18]; 5586 5587 u8 syndrome[0x20]; 5588 5589 u8 reserved_at_40[0xc0]; 5590 5591 struct mlx5_ifc_sqc_bits sq_context; 5592 }; 5593 5594 struct mlx5_ifc_query_sq_in_bits { 5595 u8 opcode[0x10]; 5596 u8 reserved_at_10[0x10]; 5597 5598 u8 reserved_at_20[0x10]; 5599 u8 op_mod[0x10]; 5600 5601 u8 reserved_at_40[0x8]; 5602 u8 sqn[0x18]; 5603 5604 u8 reserved_at_60[0x20]; 5605 }; 5606 5607 struct mlx5_ifc_query_special_contexts_out_bits { 5608 u8 status[0x8]; 5609 u8 reserved_at_8[0x18]; 5610 5611 u8 syndrome[0x20]; 5612 5613 u8 dump_fill_mkey[0x20]; 5614 5615 u8 resd_lkey[0x20]; 5616 5617 u8 null_mkey[0x20]; 5618 5619 u8 terminate_scatter_list_mkey[0x20]; 5620 5621 u8 repeated_mkey[0x20]; 5622 5623 u8 reserved_at_a0[0x20]; 5624 }; 5625 5626 struct mlx5_ifc_query_special_contexts_in_bits { 5627 u8 opcode[0x10]; 5628 u8 reserved_at_10[0x10]; 5629 5630 u8 reserved_at_20[0x10]; 5631 u8 op_mod[0x10]; 5632 5633 u8 reserved_at_40[0x40]; 5634 }; 5635 5636 struct mlx5_ifc_query_scheduling_element_out_bits { 5637 u8 opcode[0x10]; 5638 u8 reserved_at_10[0x10]; 5639 5640 u8 reserved_at_20[0x10]; 5641 u8 op_mod[0x10]; 5642 5643 u8 reserved_at_40[0xc0]; 5644 5645 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5646 5647 u8 reserved_at_300[0x100]; 5648 }; 5649 5650 enum { 5651 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5652 SCHEDULING_HIERARCHY_NIC = 0x3, 5653 }; 5654 5655 struct mlx5_ifc_query_scheduling_element_in_bits { 5656 u8 opcode[0x10]; 5657 u8 reserved_at_10[0x10]; 5658 5659 u8 reserved_at_20[0x10]; 5660 u8 op_mod[0x10]; 5661 5662 u8 scheduling_hierarchy[0x8]; 5663 u8 reserved_at_48[0x18]; 5664 5665 u8 scheduling_element_id[0x20]; 5666 5667 u8 reserved_at_80[0x180]; 5668 }; 5669 5670 struct mlx5_ifc_query_rqt_out_bits { 5671 u8 status[0x8]; 5672 u8 reserved_at_8[0x18]; 5673 5674 u8 syndrome[0x20]; 5675 5676 u8 reserved_at_40[0xc0]; 5677 5678 struct mlx5_ifc_rqtc_bits rqt_context; 5679 }; 5680 5681 struct mlx5_ifc_query_rqt_in_bits { 5682 u8 opcode[0x10]; 5683 u8 reserved_at_10[0x10]; 5684 5685 u8 reserved_at_20[0x10]; 5686 u8 op_mod[0x10]; 5687 5688 u8 reserved_at_40[0x8]; 5689 u8 rqtn[0x18]; 5690 5691 u8 reserved_at_60[0x20]; 5692 }; 5693 5694 struct mlx5_ifc_query_rq_out_bits { 5695 u8 status[0x8]; 5696 u8 reserved_at_8[0x18]; 5697 5698 u8 syndrome[0x20]; 5699 5700 u8 reserved_at_40[0xc0]; 5701 5702 struct mlx5_ifc_rqc_bits rq_context; 5703 }; 5704 5705 struct mlx5_ifc_query_rq_in_bits { 5706 u8 opcode[0x10]; 5707 u8 reserved_at_10[0x10]; 5708 5709 u8 reserved_at_20[0x10]; 5710 u8 op_mod[0x10]; 5711 5712 u8 reserved_at_40[0x8]; 5713 u8 rqn[0x18]; 5714 5715 u8 reserved_at_60[0x20]; 5716 }; 5717 5718 struct mlx5_ifc_query_roce_address_out_bits { 5719 u8 status[0x8]; 5720 u8 reserved_at_8[0x18]; 5721 5722 u8 syndrome[0x20]; 5723 5724 u8 reserved_at_40[0x40]; 5725 5726 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5727 }; 5728 5729 struct mlx5_ifc_query_roce_address_in_bits { 5730 u8 opcode[0x10]; 5731 u8 reserved_at_10[0x10]; 5732 5733 u8 reserved_at_20[0x10]; 5734 u8 op_mod[0x10]; 5735 5736 u8 roce_address_index[0x10]; 5737 u8 reserved_at_50[0xc]; 5738 u8 vhca_port_num[0x4]; 5739 5740 u8 reserved_at_60[0x20]; 5741 }; 5742 5743 struct mlx5_ifc_query_rmp_out_bits { 5744 u8 status[0x8]; 5745 u8 reserved_at_8[0x18]; 5746 5747 u8 syndrome[0x20]; 5748 5749 u8 reserved_at_40[0xc0]; 5750 5751 struct mlx5_ifc_rmpc_bits rmp_context; 5752 }; 5753 5754 struct mlx5_ifc_query_rmp_in_bits { 5755 u8 opcode[0x10]; 5756 u8 reserved_at_10[0x10]; 5757 5758 u8 reserved_at_20[0x10]; 5759 u8 op_mod[0x10]; 5760 5761 u8 reserved_at_40[0x8]; 5762 u8 rmpn[0x18]; 5763 5764 u8 reserved_at_60[0x20]; 5765 }; 5766 5767 struct mlx5_ifc_cqe_error_syndrome_bits { 5768 u8 hw_error_syndrome[0x8]; 5769 u8 hw_syndrome_type[0x4]; 5770 u8 reserved_at_c[0x4]; 5771 u8 vendor_error_syndrome[0x8]; 5772 u8 syndrome[0x8]; 5773 }; 5774 5775 struct mlx5_ifc_qp_context_extension_bits { 5776 u8 reserved_at_0[0x60]; 5777 5778 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5779 5780 u8 reserved_at_80[0x580]; 5781 }; 5782 5783 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5784 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5785 5786 u8 pas[0][0x40]; 5787 }; 5788 5789 struct mlx5_ifc_qp_pas_list_in_bits { 5790 struct mlx5_ifc_cmd_pas_bits pas[0]; 5791 }; 5792 5793 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5794 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5795 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5796 }; 5797 5798 struct mlx5_ifc_query_qp_out_bits { 5799 u8 status[0x8]; 5800 u8 reserved_at_8[0x18]; 5801 5802 u8 syndrome[0x20]; 5803 5804 u8 reserved_at_40[0x40]; 5805 5806 u8 opt_param_mask[0x20]; 5807 5808 u8 ece[0x20]; 5809 5810 struct mlx5_ifc_qpc_bits qpc; 5811 5812 u8 reserved_at_800[0x80]; 5813 5814 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5815 }; 5816 5817 struct mlx5_ifc_query_qp_in_bits { 5818 u8 opcode[0x10]; 5819 u8 reserved_at_10[0x10]; 5820 5821 u8 reserved_at_20[0x10]; 5822 u8 op_mod[0x10]; 5823 5824 u8 qpc_ext[0x1]; 5825 u8 reserved_at_41[0x7]; 5826 u8 qpn[0x18]; 5827 5828 u8 reserved_at_60[0x20]; 5829 }; 5830 5831 struct mlx5_ifc_query_q_counter_out_bits { 5832 u8 status[0x8]; 5833 u8 reserved_at_8[0x18]; 5834 5835 u8 syndrome[0x20]; 5836 5837 u8 reserved_at_40[0x40]; 5838 5839 u8 rx_write_requests[0x20]; 5840 5841 u8 reserved_at_a0[0x20]; 5842 5843 u8 rx_read_requests[0x20]; 5844 5845 u8 reserved_at_e0[0x20]; 5846 5847 u8 rx_atomic_requests[0x20]; 5848 5849 u8 reserved_at_120[0x20]; 5850 5851 u8 rx_dct_connect[0x20]; 5852 5853 u8 reserved_at_160[0x20]; 5854 5855 u8 out_of_buffer[0x20]; 5856 5857 u8 reserved_at_1a0[0x20]; 5858 5859 u8 out_of_sequence[0x20]; 5860 5861 u8 reserved_at_1e0[0x20]; 5862 5863 u8 duplicate_request[0x20]; 5864 5865 u8 reserved_at_220[0x20]; 5866 5867 u8 rnr_nak_retry_err[0x20]; 5868 5869 u8 reserved_at_260[0x20]; 5870 5871 u8 packet_seq_err[0x20]; 5872 5873 u8 reserved_at_2a0[0x20]; 5874 5875 u8 implied_nak_seq_err[0x20]; 5876 5877 u8 reserved_at_2e0[0x20]; 5878 5879 u8 local_ack_timeout_err[0x20]; 5880 5881 u8 reserved_at_320[0x60]; 5882 5883 u8 req_rnr_retries_exceeded[0x20]; 5884 5885 u8 reserved_at_3a0[0x20]; 5886 5887 u8 resp_local_length_error[0x20]; 5888 5889 u8 req_local_length_error[0x20]; 5890 5891 u8 resp_local_qp_error[0x20]; 5892 5893 u8 local_operation_error[0x20]; 5894 5895 u8 resp_local_protection[0x20]; 5896 5897 u8 req_local_protection[0x20]; 5898 5899 u8 resp_cqe_error[0x20]; 5900 5901 u8 req_cqe_error[0x20]; 5902 5903 u8 req_mw_binding[0x20]; 5904 5905 u8 req_bad_response[0x20]; 5906 5907 u8 req_remote_invalid_request[0x20]; 5908 5909 u8 resp_remote_invalid_request[0x20]; 5910 5911 u8 req_remote_access_errors[0x20]; 5912 5913 u8 resp_remote_access_errors[0x20]; 5914 5915 u8 req_remote_operation_errors[0x20]; 5916 5917 u8 req_transport_retries_exceeded[0x20]; 5918 5919 u8 cq_overflow[0x20]; 5920 5921 u8 resp_cqe_flush_error[0x20]; 5922 5923 u8 req_cqe_flush_error[0x20]; 5924 5925 u8 reserved_at_620[0x20]; 5926 5927 u8 roce_adp_retrans[0x20]; 5928 5929 u8 roce_adp_retrans_to[0x20]; 5930 5931 u8 roce_slow_restart[0x20]; 5932 5933 u8 roce_slow_restart_cnps[0x20]; 5934 5935 u8 roce_slow_restart_trans[0x20]; 5936 5937 u8 reserved_at_6e0[0x120]; 5938 }; 5939 5940 struct mlx5_ifc_query_q_counter_in_bits { 5941 u8 opcode[0x10]; 5942 u8 reserved_at_10[0x10]; 5943 5944 u8 reserved_at_20[0x10]; 5945 u8 op_mod[0x10]; 5946 5947 u8 other_vport[0x1]; 5948 u8 reserved_at_41[0xf]; 5949 u8 vport_number[0x10]; 5950 5951 u8 reserved_at_60[0x60]; 5952 5953 u8 clear[0x1]; 5954 u8 aggregate[0x1]; 5955 u8 reserved_at_c2[0x1e]; 5956 5957 u8 reserved_at_e0[0x18]; 5958 u8 counter_set_id[0x8]; 5959 }; 5960 5961 struct mlx5_ifc_query_pages_out_bits { 5962 u8 status[0x8]; 5963 u8 reserved_at_8[0x18]; 5964 5965 u8 syndrome[0x20]; 5966 5967 u8 embedded_cpu_function[0x1]; 5968 u8 reserved_at_41[0xf]; 5969 u8 function_id[0x10]; 5970 5971 u8 num_pages[0x20]; 5972 }; 5973 5974 enum { 5975 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5976 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5977 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5978 }; 5979 5980 struct mlx5_ifc_query_pages_in_bits { 5981 u8 opcode[0x10]; 5982 u8 reserved_at_10[0x10]; 5983 5984 u8 reserved_at_20[0x10]; 5985 u8 op_mod[0x10]; 5986 5987 u8 embedded_cpu_function[0x1]; 5988 u8 reserved_at_41[0xf]; 5989 u8 function_id[0x10]; 5990 5991 u8 reserved_at_60[0x20]; 5992 }; 5993 5994 struct mlx5_ifc_query_nic_vport_context_out_bits { 5995 u8 status[0x8]; 5996 u8 reserved_at_8[0x18]; 5997 5998 u8 syndrome[0x20]; 5999 6000 u8 reserved_at_40[0x40]; 6001 6002 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6003 }; 6004 6005 struct mlx5_ifc_query_nic_vport_context_in_bits { 6006 u8 opcode[0x10]; 6007 u8 reserved_at_10[0x10]; 6008 6009 u8 reserved_at_20[0x10]; 6010 u8 op_mod[0x10]; 6011 6012 u8 other_vport[0x1]; 6013 u8 reserved_at_41[0xf]; 6014 u8 vport_number[0x10]; 6015 6016 u8 reserved_at_60[0x5]; 6017 u8 allowed_list_type[0x3]; 6018 u8 reserved_at_68[0x18]; 6019 }; 6020 6021 struct mlx5_ifc_query_mkey_out_bits { 6022 u8 status[0x8]; 6023 u8 reserved_at_8[0x18]; 6024 6025 u8 syndrome[0x20]; 6026 6027 u8 reserved_at_40[0x40]; 6028 6029 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6030 6031 u8 reserved_at_280[0x600]; 6032 6033 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 6034 6035 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 6036 }; 6037 6038 struct mlx5_ifc_query_mkey_in_bits { 6039 u8 opcode[0x10]; 6040 u8 reserved_at_10[0x10]; 6041 6042 u8 reserved_at_20[0x10]; 6043 u8 op_mod[0x10]; 6044 6045 u8 reserved_at_40[0x8]; 6046 u8 mkey_index[0x18]; 6047 6048 u8 pg_access[0x1]; 6049 u8 reserved_at_61[0x1f]; 6050 }; 6051 6052 struct mlx5_ifc_query_mad_demux_out_bits { 6053 u8 status[0x8]; 6054 u8 reserved_at_8[0x18]; 6055 6056 u8 syndrome[0x20]; 6057 6058 u8 reserved_at_40[0x40]; 6059 6060 u8 mad_dumux_parameters_block[0x20]; 6061 }; 6062 6063 struct mlx5_ifc_query_mad_demux_in_bits { 6064 u8 opcode[0x10]; 6065 u8 reserved_at_10[0x10]; 6066 6067 u8 reserved_at_20[0x10]; 6068 u8 op_mod[0x10]; 6069 6070 u8 reserved_at_40[0x40]; 6071 }; 6072 6073 struct mlx5_ifc_query_l2_table_entry_out_bits { 6074 u8 status[0x8]; 6075 u8 reserved_at_8[0x18]; 6076 6077 u8 syndrome[0x20]; 6078 6079 u8 reserved_at_40[0xa0]; 6080 6081 u8 reserved_at_e0[0x13]; 6082 u8 vlan_valid[0x1]; 6083 u8 vlan[0xc]; 6084 6085 struct mlx5_ifc_mac_address_layout_bits mac_address; 6086 6087 u8 reserved_at_140[0xc0]; 6088 }; 6089 6090 struct mlx5_ifc_query_l2_table_entry_in_bits { 6091 u8 opcode[0x10]; 6092 u8 reserved_at_10[0x10]; 6093 6094 u8 reserved_at_20[0x10]; 6095 u8 op_mod[0x10]; 6096 6097 u8 reserved_at_40[0x60]; 6098 6099 u8 reserved_at_a0[0x8]; 6100 u8 table_index[0x18]; 6101 6102 u8 reserved_at_c0[0x140]; 6103 }; 6104 6105 struct mlx5_ifc_query_issi_out_bits { 6106 u8 status[0x8]; 6107 u8 reserved_at_8[0x18]; 6108 6109 u8 syndrome[0x20]; 6110 6111 u8 reserved_at_40[0x10]; 6112 u8 current_issi[0x10]; 6113 6114 u8 reserved_at_60[0xa0]; 6115 6116 u8 reserved_at_100[76][0x8]; 6117 u8 supported_issi_dw0[0x20]; 6118 }; 6119 6120 struct mlx5_ifc_query_issi_in_bits { 6121 u8 opcode[0x10]; 6122 u8 reserved_at_10[0x10]; 6123 6124 u8 reserved_at_20[0x10]; 6125 u8 op_mod[0x10]; 6126 6127 u8 reserved_at_40[0x40]; 6128 }; 6129 6130 struct mlx5_ifc_set_driver_version_out_bits { 6131 u8 status[0x8]; 6132 u8 reserved_0[0x18]; 6133 6134 u8 syndrome[0x20]; 6135 u8 reserved_1[0x40]; 6136 }; 6137 6138 struct mlx5_ifc_set_driver_version_in_bits { 6139 u8 opcode[0x10]; 6140 u8 reserved_0[0x10]; 6141 6142 u8 reserved_1[0x10]; 6143 u8 op_mod[0x10]; 6144 6145 u8 reserved_2[0x40]; 6146 u8 driver_version[64][0x8]; 6147 }; 6148 6149 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 6150 u8 status[0x8]; 6151 u8 reserved_at_8[0x18]; 6152 6153 u8 syndrome[0x20]; 6154 6155 u8 reserved_at_40[0x40]; 6156 6157 struct mlx5_ifc_pkey_bits pkey[]; 6158 }; 6159 6160 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 6161 u8 opcode[0x10]; 6162 u8 reserved_at_10[0x10]; 6163 6164 u8 reserved_at_20[0x10]; 6165 u8 op_mod[0x10]; 6166 6167 u8 other_vport[0x1]; 6168 u8 reserved_at_41[0xb]; 6169 u8 port_num[0x4]; 6170 u8 vport_number[0x10]; 6171 6172 u8 reserved_at_60[0x10]; 6173 u8 pkey_index[0x10]; 6174 }; 6175 6176 enum { 6177 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 6178 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 6179 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 6180 }; 6181 6182 struct mlx5_ifc_query_hca_vport_gid_out_bits { 6183 u8 status[0x8]; 6184 u8 reserved_at_8[0x18]; 6185 6186 u8 syndrome[0x20]; 6187 6188 u8 reserved_at_40[0x20]; 6189 6190 u8 gids_num[0x10]; 6191 u8 reserved_at_70[0x10]; 6192 6193 struct mlx5_ifc_array128_auto_bits gid[]; 6194 }; 6195 6196 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6197 u8 opcode[0x10]; 6198 u8 reserved_at_10[0x10]; 6199 6200 u8 reserved_at_20[0x10]; 6201 u8 op_mod[0x10]; 6202 6203 u8 other_vport[0x1]; 6204 u8 reserved_at_41[0xb]; 6205 u8 port_num[0x4]; 6206 u8 vport_number[0x10]; 6207 6208 u8 reserved_at_60[0x10]; 6209 u8 gid_index[0x10]; 6210 }; 6211 6212 struct mlx5_ifc_query_hca_vport_context_out_bits { 6213 u8 status[0x8]; 6214 u8 reserved_at_8[0x18]; 6215 6216 u8 syndrome[0x20]; 6217 6218 u8 reserved_at_40[0x40]; 6219 6220 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6221 }; 6222 6223 struct mlx5_ifc_query_hca_vport_context_in_bits { 6224 u8 opcode[0x10]; 6225 u8 reserved_at_10[0x10]; 6226 6227 u8 reserved_at_20[0x10]; 6228 u8 op_mod[0x10]; 6229 6230 u8 other_vport[0x1]; 6231 u8 reserved_at_41[0xb]; 6232 u8 port_num[0x4]; 6233 u8 vport_number[0x10]; 6234 6235 u8 reserved_at_60[0x20]; 6236 }; 6237 6238 struct mlx5_ifc_query_hca_cap_out_bits { 6239 u8 status[0x8]; 6240 u8 reserved_at_8[0x18]; 6241 6242 u8 syndrome[0x20]; 6243 6244 u8 reserved_at_40[0x40]; 6245 6246 union mlx5_ifc_hca_cap_union_bits capability; 6247 }; 6248 6249 struct mlx5_ifc_query_hca_cap_in_bits { 6250 u8 opcode[0x10]; 6251 u8 reserved_at_10[0x10]; 6252 6253 u8 reserved_at_20[0x10]; 6254 u8 op_mod[0x10]; 6255 6256 u8 other_function[0x1]; 6257 u8 ec_vf_function[0x1]; 6258 u8 reserved_at_42[0xe]; 6259 u8 function_id[0x10]; 6260 6261 u8 reserved_at_60[0x20]; 6262 }; 6263 6264 struct mlx5_ifc_other_hca_cap_bits { 6265 u8 roce[0x1]; 6266 u8 reserved_at_1[0x27f]; 6267 }; 6268 6269 struct mlx5_ifc_query_other_hca_cap_out_bits { 6270 u8 status[0x8]; 6271 u8 reserved_at_8[0x18]; 6272 6273 u8 syndrome[0x20]; 6274 6275 u8 reserved_at_40[0x40]; 6276 6277 struct mlx5_ifc_other_hca_cap_bits other_capability; 6278 }; 6279 6280 struct mlx5_ifc_query_other_hca_cap_in_bits { 6281 u8 opcode[0x10]; 6282 u8 reserved_at_10[0x10]; 6283 6284 u8 reserved_at_20[0x10]; 6285 u8 op_mod[0x10]; 6286 6287 u8 reserved_at_40[0x10]; 6288 u8 function_id[0x10]; 6289 6290 u8 reserved_at_60[0x20]; 6291 }; 6292 6293 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6294 u8 status[0x8]; 6295 u8 reserved_at_8[0x18]; 6296 6297 u8 syndrome[0x20]; 6298 6299 u8 reserved_at_40[0x40]; 6300 }; 6301 6302 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6303 u8 opcode[0x10]; 6304 u8 reserved_at_10[0x10]; 6305 6306 u8 reserved_at_20[0x10]; 6307 u8 op_mod[0x10]; 6308 6309 u8 reserved_at_40[0x10]; 6310 u8 function_id[0x10]; 6311 u8 field_select[0x20]; 6312 6313 struct mlx5_ifc_other_hca_cap_bits other_capability; 6314 }; 6315 6316 struct mlx5_ifc_flow_table_context_bits { 6317 u8 reformat_en[0x1]; 6318 u8 decap_en[0x1]; 6319 u8 sw_owner[0x1]; 6320 u8 termination_table[0x1]; 6321 u8 table_miss_action[0x4]; 6322 u8 level[0x8]; 6323 u8 rtc_valid[0x1]; 6324 u8 reserved_at_11[0x7]; 6325 u8 log_size[0x8]; 6326 6327 u8 reserved_at_20[0x8]; 6328 u8 table_miss_id[0x18]; 6329 6330 u8 reserved_at_40[0x8]; 6331 u8 lag_master_next_table_id[0x18]; 6332 6333 u8 reserved_at_60[0x60]; 6334 union { 6335 struct { 6336 u8 sw_owner_icm_root_1[0x40]; 6337 6338 u8 sw_owner_icm_root_0[0x40]; 6339 } sws; 6340 struct { 6341 u8 rtc_id_0[0x20]; 6342 6343 u8 rtc_id_1[0x20]; 6344 6345 u8 reserved_at_100[0x40]; 6346 6347 } hws; 6348 }; 6349 }; 6350 6351 struct mlx5_ifc_query_flow_table_out_bits { 6352 u8 status[0x8]; 6353 u8 reserved_at_8[0x18]; 6354 6355 u8 syndrome[0x20]; 6356 6357 u8 reserved_at_40[0x80]; 6358 6359 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6360 }; 6361 6362 struct mlx5_ifc_query_flow_table_in_bits { 6363 u8 opcode[0x10]; 6364 u8 reserved_at_10[0x10]; 6365 6366 u8 reserved_at_20[0x10]; 6367 u8 op_mod[0x10]; 6368 6369 u8 reserved_at_40[0x40]; 6370 6371 u8 table_type[0x8]; 6372 u8 reserved_at_88[0x18]; 6373 6374 u8 reserved_at_a0[0x8]; 6375 u8 table_id[0x18]; 6376 6377 u8 reserved_at_c0[0x140]; 6378 }; 6379 6380 struct mlx5_ifc_query_fte_out_bits { 6381 u8 status[0x8]; 6382 u8 reserved_at_8[0x18]; 6383 6384 u8 syndrome[0x20]; 6385 6386 u8 reserved_at_40[0x1c0]; 6387 6388 struct mlx5_ifc_flow_context_bits flow_context; 6389 }; 6390 6391 struct mlx5_ifc_query_fte_in_bits { 6392 u8 opcode[0x10]; 6393 u8 reserved_at_10[0x10]; 6394 6395 u8 reserved_at_20[0x10]; 6396 u8 op_mod[0x10]; 6397 6398 u8 reserved_at_40[0x40]; 6399 6400 u8 table_type[0x8]; 6401 u8 reserved_at_88[0x18]; 6402 6403 u8 reserved_at_a0[0x8]; 6404 u8 table_id[0x18]; 6405 6406 u8 reserved_at_c0[0x40]; 6407 6408 u8 flow_index[0x20]; 6409 6410 u8 reserved_at_120[0xe0]; 6411 }; 6412 6413 struct mlx5_ifc_match_definer_format_0_bits { 6414 u8 reserved_at_0[0x100]; 6415 6416 u8 metadata_reg_c_0[0x20]; 6417 6418 u8 metadata_reg_c_1[0x20]; 6419 6420 u8 outer_dmac_47_16[0x20]; 6421 6422 u8 outer_dmac_15_0[0x10]; 6423 u8 outer_ethertype[0x10]; 6424 6425 u8 reserved_at_180[0x1]; 6426 u8 sx_sniffer[0x1]; 6427 u8 functional_lb[0x1]; 6428 u8 outer_ip_frag[0x1]; 6429 u8 outer_qp_type[0x2]; 6430 u8 outer_encap_type[0x2]; 6431 u8 port_number[0x2]; 6432 u8 outer_l3_type[0x2]; 6433 u8 outer_l4_type[0x2]; 6434 u8 outer_first_vlan_type[0x2]; 6435 u8 outer_first_vlan_prio[0x3]; 6436 u8 outer_first_vlan_cfi[0x1]; 6437 u8 outer_first_vlan_vid[0xc]; 6438 6439 u8 outer_l4_type_ext[0x4]; 6440 u8 reserved_at_1a4[0x2]; 6441 u8 outer_ipsec_layer[0x2]; 6442 u8 outer_l2_type[0x2]; 6443 u8 force_lb[0x1]; 6444 u8 outer_l2_ok[0x1]; 6445 u8 outer_l3_ok[0x1]; 6446 u8 outer_l4_ok[0x1]; 6447 u8 outer_second_vlan_type[0x2]; 6448 u8 outer_second_vlan_prio[0x3]; 6449 u8 outer_second_vlan_cfi[0x1]; 6450 u8 outer_second_vlan_vid[0xc]; 6451 6452 u8 outer_smac_47_16[0x20]; 6453 6454 u8 outer_smac_15_0[0x10]; 6455 u8 inner_ipv4_checksum_ok[0x1]; 6456 u8 inner_l4_checksum_ok[0x1]; 6457 u8 outer_ipv4_checksum_ok[0x1]; 6458 u8 outer_l4_checksum_ok[0x1]; 6459 u8 inner_l3_ok[0x1]; 6460 u8 inner_l4_ok[0x1]; 6461 u8 outer_l3_ok_duplicate[0x1]; 6462 u8 outer_l4_ok_duplicate[0x1]; 6463 u8 outer_tcp_cwr[0x1]; 6464 u8 outer_tcp_ece[0x1]; 6465 u8 outer_tcp_urg[0x1]; 6466 u8 outer_tcp_ack[0x1]; 6467 u8 outer_tcp_psh[0x1]; 6468 u8 outer_tcp_rst[0x1]; 6469 u8 outer_tcp_syn[0x1]; 6470 u8 outer_tcp_fin[0x1]; 6471 }; 6472 6473 struct mlx5_ifc_match_definer_format_22_bits { 6474 u8 reserved_at_0[0x100]; 6475 6476 u8 outer_ip_src_addr[0x20]; 6477 6478 u8 outer_ip_dest_addr[0x20]; 6479 6480 u8 outer_l4_sport[0x10]; 6481 u8 outer_l4_dport[0x10]; 6482 6483 u8 reserved_at_160[0x1]; 6484 u8 sx_sniffer[0x1]; 6485 u8 functional_lb[0x1]; 6486 u8 outer_ip_frag[0x1]; 6487 u8 outer_qp_type[0x2]; 6488 u8 outer_encap_type[0x2]; 6489 u8 port_number[0x2]; 6490 u8 outer_l3_type[0x2]; 6491 u8 outer_l4_type[0x2]; 6492 u8 outer_first_vlan_type[0x2]; 6493 u8 outer_first_vlan_prio[0x3]; 6494 u8 outer_first_vlan_cfi[0x1]; 6495 u8 outer_first_vlan_vid[0xc]; 6496 6497 u8 metadata_reg_c_0[0x20]; 6498 6499 u8 outer_dmac_47_16[0x20]; 6500 6501 u8 outer_smac_47_16[0x20]; 6502 6503 u8 outer_smac_15_0[0x10]; 6504 u8 outer_dmac_15_0[0x10]; 6505 }; 6506 6507 struct mlx5_ifc_match_definer_format_23_bits { 6508 u8 reserved_at_0[0x100]; 6509 6510 u8 inner_ip_src_addr[0x20]; 6511 6512 u8 inner_ip_dest_addr[0x20]; 6513 6514 u8 inner_l4_sport[0x10]; 6515 u8 inner_l4_dport[0x10]; 6516 6517 u8 reserved_at_160[0x1]; 6518 u8 sx_sniffer[0x1]; 6519 u8 functional_lb[0x1]; 6520 u8 inner_ip_frag[0x1]; 6521 u8 inner_qp_type[0x2]; 6522 u8 inner_encap_type[0x2]; 6523 u8 port_number[0x2]; 6524 u8 inner_l3_type[0x2]; 6525 u8 inner_l4_type[0x2]; 6526 u8 inner_first_vlan_type[0x2]; 6527 u8 inner_first_vlan_prio[0x3]; 6528 u8 inner_first_vlan_cfi[0x1]; 6529 u8 inner_first_vlan_vid[0xc]; 6530 6531 u8 tunnel_header_0[0x20]; 6532 6533 u8 inner_dmac_47_16[0x20]; 6534 6535 u8 inner_smac_47_16[0x20]; 6536 6537 u8 inner_smac_15_0[0x10]; 6538 u8 inner_dmac_15_0[0x10]; 6539 }; 6540 6541 struct mlx5_ifc_match_definer_format_29_bits { 6542 u8 reserved_at_0[0xc0]; 6543 6544 u8 outer_ip_dest_addr[0x80]; 6545 6546 u8 outer_ip_src_addr[0x80]; 6547 6548 u8 outer_l4_sport[0x10]; 6549 u8 outer_l4_dport[0x10]; 6550 6551 u8 reserved_at_1e0[0x20]; 6552 }; 6553 6554 struct mlx5_ifc_match_definer_format_30_bits { 6555 u8 reserved_at_0[0xa0]; 6556 6557 u8 outer_ip_dest_addr[0x80]; 6558 6559 u8 outer_ip_src_addr[0x80]; 6560 6561 u8 outer_dmac_47_16[0x20]; 6562 6563 u8 outer_smac_47_16[0x20]; 6564 6565 u8 outer_smac_15_0[0x10]; 6566 u8 outer_dmac_15_0[0x10]; 6567 }; 6568 6569 struct mlx5_ifc_match_definer_format_31_bits { 6570 u8 reserved_at_0[0xc0]; 6571 6572 u8 inner_ip_dest_addr[0x80]; 6573 6574 u8 inner_ip_src_addr[0x80]; 6575 6576 u8 inner_l4_sport[0x10]; 6577 u8 inner_l4_dport[0x10]; 6578 6579 u8 reserved_at_1e0[0x20]; 6580 }; 6581 6582 struct mlx5_ifc_match_definer_format_32_bits { 6583 u8 reserved_at_0[0xa0]; 6584 6585 u8 inner_ip_dest_addr[0x80]; 6586 6587 u8 inner_ip_src_addr[0x80]; 6588 6589 u8 inner_dmac_47_16[0x20]; 6590 6591 u8 inner_smac_47_16[0x20]; 6592 6593 u8 inner_smac_15_0[0x10]; 6594 u8 inner_dmac_15_0[0x10]; 6595 }; 6596 6597 enum { 6598 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6599 }; 6600 6601 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6602 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6603 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6604 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6605 6606 struct mlx5_ifc_match_definer_match_mask_bits { 6607 u8 reserved_at_1c0[5][0x20]; 6608 u8 match_dw_8[0x20]; 6609 u8 match_dw_7[0x20]; 6610 u8 match_dw_6[0x20]; 6611 u8 match_dw_5[0x20]; 6612 u8 match_dw_4[0x20]; 6613 u8 match_dw_3[0x20]; 6614 u8 match_dw_2[0x20]; 6615 u8 match_dw_1[0x20]; 6616 u8 match_dw_0[0x20]; 6617 6618 u8 match_byte_7[0x8]; 6619 u8 match_byte_6[0x8]; 6620 u8 match_byte_5[0x8]; 6621 u8 match_byte_4[0x8]; 6622 6623 u8 match_byte_3[0x8]; 6624 u8 match_byte_2[0x8]; 6625 u8 match_byte_1[0x8]; 6626 u8 match_byte_0[0x8]; 6627 }; 6628 6629 struct mlx5_ifc_match_definer_bits { 6630 u8 modify_field_select[0x40]; 6631 6632 u8 reserved_at_40[0x40]; 6633 6634 u8 reserved_at_80[0x10]; 6635 u8 format_id[0x10]; 6636 6637 u8 reserved_at_a0[0x60]; 6638 6639 u8 format_select_dw3[0x8]; 6640 u8 format_select_dw2[0x8]; 6641 u8 format_select_dw1[0x8]; 6642 u8 format_select_dw0[0x8]; 6643 6644 u8 format_select_dw7[0x8]; 6645 u8 format_select_dw6[0x8]; 6646 u8 format_select_dw5[0x8]; 6647 u8 format_select_dw4[0x8]; 6648 6649 u8 reserved_at_100[0x18]; 6650 u8 format_select_dw8[0x8]; 6651 6652 u8 reserved_at_120[0x20]; 6653 6654 u8 format_select_byte3[0x8]; 6655 u8 format_select_byte2[0x8]; 6656 u8 format_select_byte1[0x8]; 6657 u8 format_select_byte0[0x8]; 6658 6659 u8 format_select_byte7[0x8]; 6660 u8 format_select_byte6[0x8]; 6661 u8 format_select_byte5[0x8]; 6662 u8 format_select_byte4[0x8]; 6663 6664 u8 reserved_at_180[0x40]; 6665 6666 union { 6667 struct { 6668 u8 match_mask[16][0x20]; 6669 }; 6670 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6671 }; 6672 }; 6673 6674 struct mlx5_ifc_general_obj_create_param_bits { 6675 u8 alias_object[0x1]; 6676 u8 reserved_at_1[0x2]; 6677 u8 log_obj_range[0x5]; 6678 u8 reserved_at_8[0x18]; 6679 }; 6680 6681 struct mlx5_ifc_general_obj_query_param_bits { 6682 u8 alias_object[0x1]; 6683 u8 obj_offset[0x1f]; 6684 }; 6685 6686 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6687 u8 opcode[0x10]; 6688 u8 uid[0x10]; 6689 6690 u8 vhca_tunnel_id[0x10]; 6691 u8 obj_type[0x10]; 6692 6693 u8 obj_id[0x20]; 6694 6695 union { 6696 struct mlx5_ifc_general_obj_create_param_bits create; 6697 struct mlx5_ifc_general_obj_query_param_bits query; 6698 } op_param; 6699 }; 6700 6701 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6702 u8 status[0x8]; 6703 u8 reserved_at_8[0x18]; 6704 6705 u8 syndrome[0x20]; 6706 6707 u8 obj_id[0x20]; 6708 6709 u8 reserved_at_60[0x20]; 6710 }; 6711 6712 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6713 u8 opcode[0x10]; 6714 u8 uid[0x10]; 6715 u8 reserved_at_20[0x10]; 6716 u8 op_mod[0x10]; 6717 u8 reserved_at_40[0x50]; 6718 u8 object_type_to_be_accessed[0x10]; 6719 u8 object_id_to_be_accessed[0x20]; 6720 u8 reserved_at_c0[0x40]; 6721 union { 6722 u8 access_key_raw[0x100]; 6723 u8 access_key[8][0x20]; 6724 }; 6725 }; 6726 6727 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6728 u8 status[0x8]; 6729 u8 reserved_at_8[0x18]; 6730 u8 syndrome[0x20]; 6731 u8 reserved_at_40[0x40]; 6732 }; 6733 6734 struct mlx5_ifc_modify_header_arg_bits { 6735 u8 reserved_at_0[0x80]; 6736 6737 u8 reserved_at_80[0x8]; 6738 u8 access_pd[0x18]; 6739 }; 6740 6741 struct mlx5_ifc_create_modify_header_arg_in_bits { 6742 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6743 struct mlx5_ifc_modify_header_arg_bits arg; 6744 }; 6745 6746 struct mlx5_ifc_create_match_definer_in_bits { 6747 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6748 6749 struct mlx5_ifc_match_definer_bits obj_context; 6750 }; 6751 6752 struct mlx5_ifc_create_match_definer_out_bits { 6753 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6754 }; 6755 6756 struct mlx5_ifc_alias_context_bits { 6757 u8 vhca_id_to_be_accessed[0x10]; 6758 u8 reserved_at_10[0xd]; 6759 u8 status[0x3]; 6760 u8 object_id_to_be_accessed[0x20]; 6761 u8 reserved_at_40[0x40]; 6762 union { 6763 u8 access_key_raw[0x100]; 6764 u8 access_key[8][0x20]; 6765 }; 6766 u8 metadata[0x80]; 6767 }; 6768 6769 struct mlx5_ifc_create_alias_obj_in_bits { 6770 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6771 struct mlx5_ifc_alias_context_bits alias_ctx; 6772 }; 6773 6774 enum { 6775 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6776 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6777 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6778 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6779 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6780 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6781 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6782 }; 6783 6784 struct mlx5_ifc_query_flow_group_out_bits { 6785 u8 status[0x8]; 6786 u8 reserved_at_8[0x18]; 6787 6788 u8 syndrome[0x20]; 6789 6790 u8 reserved_at_40[0xa0]; 6791 6792 u8 start_flow_index[0x20]; 6793 6794 u8 reserved_at_100[0x20]; 6795 6796 u8 end_flow_index[0x20]; 6797 6798 u8 reserved_at_140[0xa0]; 6799 6800 u8 reserved_at_1e0[0x18]; 6801 u8 match_criteria_enable[0x8]; 6802 6803 struct mlx5_ifc_fte_match_param_bits match_criteria; 6804 6805 u8 reserved_at_1200[0xe00]; 6806 }; 6807 6808 struct mlx5_ifc_query_flow_group_in_bits { 6809 u8 opcode[0x10]; 6810 u8 reserved_at_10[0x10]; 6811 6812 u8 reserved_at_20[0x10]; 6813 u8 op_mod[0x10]; 6814 6815 u8 reserved_at_40[0x40]; 6816 6817 u8 table_type[0x8]; 6818 u8 reserved_at_88[0x18]; 6819 6820 u8 reserved_at_a0[0x8]; 6821 u8 table_id[0x18]; 6822 6823 u8 group_id[0x20]; 6824 6825 u8 reserved_at_e0[0x120]; 6826 }; 6827 6828 struct mlx5_ifc_query_flow_counter_out_bits { 6829 u8 status[0x8]; 6830 u8 reserved_at_8[0x18]; 6831 6832 u8 syndrome[0x20]; 6833 6834 u8 reserved_at_40[0x40]; 6835 6836 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6837 }; 6838 6839 struct mlx5_ifc_query_flow_counter_in_bits { 6840 u8 opcode[0x10]; 6841 u8 reserved_at_10[0x10]; 6842 6843 u8 reserved_at_20[0x10]; 6844 u8 op_mod[0x10]; 6845 6846 u8 reserved_at_40[0x80]; 6847 6848 u8 clear[0x1]; 6849 u8 reserved_at_c1[0xf]; 6850 u8 num_of_counters[0x10]; 6851 6852 u8 flow_counter_id[0x20]; 6853 }; 6854 6855 struct mlx5_ifc_query_esw_vport_context_out_bits { 6856 u8 status[0x8]; 6857 u8 reserved_at_8[0x18]; 6858 6859 u8 syndrome[0x20]; 6860 6861 u8 reserved_at_40[0x40]; 6862 6863 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6864 }; 6865 6866 struct mlx5_ifc_query_esw_vport_context_in_bits { 6867 u8 opcode[0x10]; 6868 u8 reserved_at_10[0x10]; 6869 6870 u8 reserved_at_20[0x10]; 6871 u8 op_mod[0x10]; 6872 6873 u8 other_vport[0x1]; 6874 u8 reserved_at_41[0xf]; 6875 u8 vport_number[0x10]; 6876 6877 u8 reserved_at_60[0x20]; 6878 }; 6879 6880 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6881 u8 status[0x8]; 6882 u8 reserved_at_8[0x18]; 6883 6884 u8 syndrome[0x20]; 6885 6886 u8 reserved_at_40[0x40]; 6887 }; 6888 6889 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6890 u8 reserved_at_0[0x1b]; 6891 u8 fdb_to_vport_reg_c_id[0x1]; 6892 u8 vport_cvlan_insert[0x1]; 6893 u8 vport_svlan_insert[0x1]; 6894 u8 vport_cvlan_strip[0x1]; 6895 u8 vport_svlan_strip[0x1]; 6896 }; 6897 6898 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6899 u8 opcode[0x10]; 6900 u8 reserved_at_10[0x10]; 6901 6902 u8 reserved_at_20[0x10]; 6903 u8 op_mod[0x10]; 6904 6905 u8 other_vport[0x1]; 6906 u8 reserved_at_41[0xf]; 6907 u8 vport_number[0x10]; 6908 6909 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6910 6911 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6912 }; 6913 6914 struct mlx5_ifc_query_eq_out_bits { 6915 u8 status[0x8]; 6916 u8 reserved_at_8[0x18]; 6917 6918 u8 syndrome[0x20]; 6919 6920 u8 reserved_at_40[0x40]; 6921 6922 struct mlx5_ifc_eqc_bits eq_context_entry; 6923 6924 u8 reserved_at_280[0x40]; 6925 6926 u8 event_bitmask[0x40]; 6927 6928 u8 reserved_at_300[0x580]; 6929 6930 u8 pas[][0x40]; 6931 }; 6932 6933 struct mlx5_ifc_query_eq_in_bits { 6934 u8 opcode[0x10]; 6935 u8 reserved_at_10[0x10]; 6936 6937 u8 reserved_at_20[0x10]; 6938 u8 op_mod[0x10]; 6939 6940 u8 reserved_at_40[0x18]; 6941 u8 eq_number[0x8]; 6942 6943 u8 reserved_at_60[0x20]; 6944 }; 6945 6946 struct mlx5_ifc_packet_reformat_context_in_bits { 6947 u8 reformat_type[0x8]; 6948 u8 reserved_at_8[0x4]; 6949 u8 reformat_param_0[0x4]; 6950 u8 reserved_at_10[0x6]; 6951 u8 reformat_data_size[0xa]; 6952 6953 u8 reformat_param_1[0x8]; 6954 u8 reserved_at_28[0x8]; 6955 u8 reformat_data[2][0x8]; 6956 6957 u8 more_reformat_data[][0x8]; 6958 }; 6959 6960 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6961 u8 status[0x8]; 6962 u8 reserved_at_8[0x18]; 6963 6964 u8 syndrome[0x20]; 6965 6966 u8 reserved_at_40[0xa0]; 6967 6968 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6969 }; 6970 6971 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6972 u8 opcode[0x10]; 6973 u8 reserved_at_10[0x10]; 6974 6975 u8 reserved_at_20[0x10]; 6976 u8 op_mod[0x10]; 6977 6978 u8 packet_reformat_id[0x20]; 6979 6980 u8 reserved_at_60[0xa0]; 6981 }; 6982 6983 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6984 u8 status[0x8]; 6985 u8 reserved_at_8[0x18]; 6986 6987 u8 syndrome[0x20]; 6988 6989 u8 packet_reformat_id[0x20]; 6990 6991 u8 reserved_at_60[0x20]; 6992 }; 6993 6994 enum { 6995 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6996 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6997 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6998 }; 6999 7000 enum mlx5_reformat_ctx_type { 7001 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 7002 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 7003 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 7004 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 7005 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 7006 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 7007 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 7008 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 7009 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 7010 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 7011 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 7012 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 7013 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 7014 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 7015 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 7016 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 7017 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 7018 }; 7019 7020 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 7021 u8 opcode[0x10]; 7022 u8 reserved_at_10[0x10]; 7023 7024 u8 reserved_at_20[0x10]; 7025 u8 op_mod[0x10]; 7026 7027 u8 reserved_at_40[0xa0]; 7028 7029 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 7030 }; 7031 7032 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 7033 u8 status[0x8]; 7034 u8 reserved_at_8[0x18]; 7035 7036 u8 syndrome[0x20]; 7037 7038 u8 reserved_at_40[0x40]; 7039 }; 7040 7041 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 7042 u8 opcode[0x10]; 7043 u8 reserved_at_10[0x10]; 7044 7045 u8 reserved_20[0x10]; 7046 u8 op_mod[0x10]; 7047 7048 u8 packet_reformat_id[0x20]; 7049 7050 u8 reserved_60[0x20]; 7051 }; 7052 7053 struct mlx5_ifc_set_action_in_bits { 7054 u8 action_type[0x4]; 7055 u8 field[0xc]; 7056 u8 reserved_at_10[0x3]; 7057 u8 offset[0x5]; 7058 u8 reserved_at_18[0x3]; 7059 u8 length[0x5]; 7060 7061 u8 data[0x20]; 7062 }; 7063 7064 struct mlx5_ifc_add_action_in_bits { 7065 u8 action_type[0x4]; 7066 u8 field[0xc]; 7067 u8 reserved_at_10[0x10]; 7068 7069 u8 data[0x20]; 7070 }; 7071 7072 struct mlx5_ifc_copy_action_in_bits { 7073 u8 action_type[0x4]; 7074 u8 src_field[0xc]; 7075 u8 reserved_at_10[0x3]; 7076 u8 src_offset[0x5]; 7077 u8 reserved_at_18[0x3]; 7078 u8 length[0x5]; 7079 7080 u8 reserved_at_20[0x4]; 7081 u8 dst_field[0xc]; 7082 u8 reserved_at_30[0x3]; 7083 u8 dst_offset[0x5]; 7084 u8 reserved_at_38[0x8]; 7085 }; 7086 7087 union mlx5_ifc_set_add_copy_action_in_auto_bits { 7088 struct mlx5_ifc_set_action_in_bits set_action_in; 7089 struct mlx5_ifc_add_action_in_bits add_action_in; 7090 struct mlx5_ifc_copy_action_in_bits copy_action_in; 7091 u8 reserved_at_0[0x40]; 7092 }; 7093 7094 enum { 7095 MLX5_ACTION_TYPE_SET = 0x1, 7096 MLX5_ACTION_TYPE_ADD = 0x2, 7097 MLX5_ACTION_TYPE_COPY = 0x3, 7098 }; 7099 7100 enum { 7101 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 7102 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 7103 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 7104 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 7105 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 7106 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 7107 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 7108 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 7109 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 7110 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 7111 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 7112 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 7113 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 7114 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 7115 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 7116 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 7117 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 7118 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 7119 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 7120 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 7121 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 7122 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 7123 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 7124 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 7125 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 7126 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 7127 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 7128 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 7129 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 7130 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 7131 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 7132 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 7133 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 7134 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 7135 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 7136 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 7137 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 7138 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 7139 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 7140 }; 7141 7142 struct mlx5_ifc_alloc_modify_header_context_out_bits { 7143 u8 status[0x8]; 7144 u8 reserved_at_8[0x18]; 7145 7146 u8 syndrome[0x20]; 7147 7148 u8 modify_header_id[0x20]; 7149 7150 u8 reserved_at_60[0x20]; 7151 }; 7152 7153 struct mlx5_ifc_alloc_modify_header_context_in_bits { 7154 u8 opcode[0x10]; 7155 u8 reserved_at_10[0x10]; 7156 7157 u8 reserved_at_20[0x10]; 7158 u8 op_mod[0x10]; 7159 7160 u8 reserved_at_40[0x20]; 7161 7162 u8 table_type[0x8]; 7163 u8 reserved_at_68[0x10]; 7164 u8 num_of_actions[0x8]; 7165 7166 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 7167 }; 7168 7169 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 7170 u8 status[0x8]; 7171 u8 reserved_at_8[0x18]; 7172 7173 u8 syndrome[0x20]; 7174 7175 u8 reserved_at_40[0x40]; 7176 }; 7177 7178 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 7179 u8 opcode[0x10]; 7180 u8 reserved_at_10[0x10]; 7181 7182 u8 reserved_at_20[0x10]; 7183 u8 op_mod[0x10]; 7184 7185 u8 modify_header_id[0x20]; 7186 7187 u8 reserved_at_60[0x20]; 7188 }; 7189 7190 struct mlx5_ifc_query_modify_header_context_in_bits { 7191 u8 opcode[0x10]; 7192 u8 uid[0x10]; 7193 7194 u8 reserved_at_20[0x10]; 7195 u8 op_mod[0x10]; 7196 7197 u8 modify_header_id[0x20]; 7198 7199 u8 reserved_at_60[0xa0]; 7200 }; 7201 7202 struct mlx5_ifc_query_dct_out_bits { 7203 u8 status[0x8]; 7204 u8 reserved_at_8[0x18]; 7205 7206 u8 syndrome[0x20]; 7207 7208 u8 reserved_at_40[0x40]; 7209 7210 struct mlx5_ifc_dctc_bits dct_context_entry; 7211 7212 u8 reserved_at_280[0x180]; 7213 }; 7214 7215 struct mlx5_ifc_query_dct_in_bits { 7216 u8 opcode[0x10]; 7217 u8 reserved_at_10[0x10]; 7218 7219 u8 reserved_at_20[0x10]; 7220 u8 op_mod[0x10]; 7221 7222 u8 reserved_at_40[0x8]; 7223 u8 dctn[0x18]; 7224 7225 u8 reserved_at_60[0x20]; 7226 }; 7227 7228 struct mlx5_ifc_query_cq_out_bits { 7229 u8 status[0x8]; 7230 u8 reserved_at_8[0x18]; 7231 7232 u8 syndrome[0x20]; 7233 7234 u8 reserved_at_40[0x40]; 7235 7236 struct mlx5_ifc_cqc_bits cq_context; 7237 7238 u8 reserved_at_280[0x600]; 7239 7240 u8 pas[][0x40]; 7241 }; 7242 7243 struct mlx5_ifc_query_cq_in_bits { 7244 u8 opcode[0x10]; 7245 u8 reserved_at_10[0x10]; 7246 7247 u8 reserved_at_20[0x10]; 7248 u8 op_mod[0x10]; 7249 7250 u8 reserved_at_40[0x8]; 7251 u8 cqn[0x18]; 7252 7253 u8 reserved_at_60[0x20]; 7254 }; 7255 7256 struct mlx5_ifc_query_cong_status_out_bits { 7257 u8 status[0x8]; 7258 u8 reserved_at_8[0x18]; 7259 7260 u8 syndrome[0x20]; 7261 7262 u8 reserved_at_40[0x20]; 7263 7264 u8 enable[0x1]; 7265 u8 tag_enable[0x1]; 7266 u8 reserved_at_62[0x1e]; 7267 }; 7268 7269 struct mlx5_ifc_query_cong_status_in_bits { 7270 u8 opcode[0x10]; 7271 u8 reserved_at_10[0x10]; 7272 7273 u8 reserved_at_20[0x10]; 7274 u8 op_mod[0x10]; 7275 7276 u8 reserved_at_40[0x18]; 7277 u8 priority[0x4]; 7278 u8 cong_protocol[0x4]; 7279 7280 u8 reserved_at_60[0x20]; 7281 }; 7282 7283 struct mlx5_ifc_query_cong_statistics_out_bits { 7284 u8 status[0x8]; 7285 u8 reserved_at_8[0x18]; 7286 7287 u8 syndrome[0x20]; 7288 7289 u8 reserved_at_40[0x40]; 7290 7291 u8 rp_cur_flows[0x20]; 7292 7293 u8 sum_flows[0x20]; 7294 7295 u8 rp_cnp_ignored_high[0x20]; 7296 7297 u8 rp_cnp_ignored_low[0x20]; 7298 7299 u8 rp_cnp_handled_high[0x20]; 7300 7301 u8 rp_cnp_handled_low[0x20]; 7302 7303 u8 reserved_at_140[0x100]; 7304 7305 u8 time_stamp_high[0x20]; 7306 7307 u8 time_stamp_low[0x20]; 7308 7309 u8 accumulators_period[0x20]; 7310 7311 u8 np_ecn_marked_roce_packets_high[0x20]; 7312 7313 u8 np_ecn_marked_roce_packets_low[0x20]; 7314 7315 u8 np_cnp_sent_high[0x20]; 7316 7317 u8 np_cnp_sent_low[0x20]; 7318 7319 u8 reserved_at_320[0x560]; 7320 }; 7321 7322 struct mlx5_ifc_query_cong_statistics_in_bits { 7323 u8 opcode[0x10]; 7324 u8 reserved_at_10[0x10]; 7325 7326 u8 reserved_at_20[0x10]; 7327 u8 op_mod[0x10]; 7328 7329 u8 clear[0x1]; 7330 u8 reserved_at_41[0x1f]; 7331 7332 u8 reserved_at_60[0x20]; 7333 }; 7334 7335 struct mlx5_ifc_query_cong_params_out_bits { 7336 u8 status[0x8]; 7337 u8 reserved_at_8[0x18]; 7338 7339 u8 syndrome[0x20]; 7340 7341 u8 reserved_at_40[0x40]; 7342 7343 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7344 }; 7345 7346 struct mlx5_ifc_query_cong_params_in_bits { 7347 u8 opcode[0x10]; 7348 u8 reserved_at_10[0x10]; 7349 7350 u8 reserved_at_20[0x10]; 7351 u8 op_mod[0x10]; 7352 7353 u8 reserved_at_40[0x1c]; 7354 u8 cong_protocol[0x4]; 7355 7356 u8 reserved_at_60[0x20]; 7357 }; 7358 7359 struct mlx5_ifc_query_adapter_out_bits { 7360 u8 status[0x8]; 7361 u8 reserved_at_8[0x18]; 7362 7363 u8 syndrome[0x20]; 7364 7365 u8 reserved_at_40[0x40]; 7366 7367 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7368 }; 7369 7370 struct mlx5_ifc_query_adapter_in_bits { 7371 u8 opcode[0x10]; 7372 u8 reserved_at_10[0x10]; 7373 7374 u8 reserved_at_20[0x10]; 7375 u8 op_mod[0x10]; 7376 7377 u8 reserved_at_40[0x40]; 7378 }; 7379 7380 struct mlx5_ifc_qp_2rst_out_bits { 7381 u8 status[0x8]; 7382 u8 reserved_at_8[0x18]; 7383 7384 u8 syndrome[0x20]; 7385 7386 u8 reserved_at_40[0x40]; 7387 }; 7388 7389 struct mlx5_ifc_qp_2rst_in_bits { 7390 u8 opcode[0x10]; 7391 u8 uid[0x10]; 7392 7393 u8 reserved_at_20[0x10]; 7394 u8 op_mod[0x10]; 7395 7396 u8 reserved_at_40[0x8]; 7397 u8 qpn[0x18]; 7398 7399 u8 reserved_at_60[0x20]; 7400 }; 7401 7402 struct mlx5_ifc_qp_2err_out_bits { 7403 u8 status[0x8]; 7404 u8 reserved_at_8[0x18]; 7405 7406 u8 syndrome[0x20]; 7407 7408 u8 reserved_at_40[0x40]; 7409 }; 7410 7411 struct mlx5_ifc_qp_2err_in_bits { 7412 u8 opcode[0x10]; 7413 u8 uid[0x10]; 7414 7415 u8 reserved_at_20[0x10]; 7416 u8 op_mod[0x10]; 7417 7418 u8 reserved_at_40[0x8]; 7419 u8 qpn[0x18]; 7420 7421 u8 reserved_at_60[0x20]; 7422 }; 7423 7424 struct mlx5_ifc_trans_page_fault_info_bits { 7425 u8 error[0x1]; 7426 u8 reserved_at_1[0x4]; 7427 u8 page_fault_type[0x3]; 7428 u8 wq_number[0x18]; 7429 7430 u8 reserved_at_20[0x8]; 7431 u8 fault_token[0x18]; 7432 }; 7433 7434 struct mlx5_ifc_mem_page_fault_info_bits { 7435 u8 error[0x1]; 7436 u8 reserved_at_1[0xf]; 7437 u8 fault_token_47_32[0x10]; 7438 7439 u8 fault_token_31_0[0x20]; 7440 }; 7441 7442 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits { 7443 struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info; 7444 struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info; 7445 u8 reserved_at_0[0x40]; 7446 }; 7447 7448 struct mlx5_ifc_page_fault_resume_out_bits { 7449 u8 status[0x8]; 7450 u8 reserved_at_8[0x18]; 7451 7452 u8 syndrome[0x20]; 7453 7454 u8 reserved_at_40[0x40]; 7455 }; 7456 7457 struct mlx5_ifc_page_fault_resume_in_bits { 7458 u8 opcode[0x10]; 7459 u8 reserved_at_10[0x10]; 7460 7461 u8 reserved_at_20[0x10]; 7462 u8 op_mod[0x10]; 7463 7464 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits 7465 page_fault_info; 7466 }; 7467 7468 struct mlx5_ifc_nop_out_bits { 7469 u8 status[0x8]; 7470 u8 reserved_at_8[0x18]; 7471 7472 u8 syndrome[0x20]; 7473 7474 u8 reserved_at_40[0x40]; 7475 }; 7476 7477 struct mlx5_ifc_nop_in_bits { 7478 u8 opcode[0x10]; 7479 u8 reserved_at_10[0x10]; 7480 7481 u8 reserved_at_20[0x10]; 7482 u8 op_mod[0x10]; 7483 7484 u8 reserved_at_40[0x40]; 7485 }; 7486 7487 struct mlx5_ifc_modify_vport_state_out_bits { 7488 u8 status[0x8]; 7489 u8 reserved_at_8[0x18]; 7490 7491 u8 syndrome[0x20]; 7492 7493 u8 reserved_at_40[0x40]; 7494 }; 7495 7496 struct mlx5_ifc_modify_vport_state_in_bits { 7497 u8 opcode[0x10]; 7498 u8 reserved_at_10[0x10]; 7499 7500 u8 reserved_at_20[0x10]; 7501 u8 op_mod[0x10]; 7502 7503 u8 other_vport[0x1]; 7504 u8 reserved_at_41[0xf]; 7505 u8 vport_number[0x10]; 7506 7507 u8 reserved_at_60[0x18]; 7508 u8 admin_state[0x4]; 7509 u8 reserved_at_7c[0x4]; 7510 }; 7511 7512 struct mlx5_ifc_modify_tis_out_bits { 7513 u8 status[0x8]; 7514 u8 reserved_at_8[0x18]; 7515 7516 u8 syndrome[0x20]; 7517 7518 u8 reserved_at_40[0x40]; 7519 }; 7520 7521 struct mlx5_ifc_modify_tis_bitmask_bits { 7522 u8 reserved_at_0[0x20]; 7523 7524 u8 reserved_at_20[0x1d]; 7525 u8 lag_tx_port_affinity[0x1]; 7526 u8 strict_lag_tx_port_affinity[0x1]; 7527 u8 prio[0x1]; 7528 }; 7529 7530 struct mlx5_ifc_modify_tis_in_bits { 7531 u8 opcode[0x10]; 7532 u8 uid[0x10]; 7533 7534 u8 reserved_at_20[0x10]; 7535 u8 op_mod[0x10]; 7536 7537 u8 reserved_at_40[0x8]; 7538 u8 tisn[0x18]; 7539 7540 u8 reserved_at_60[0x20]; 7541 7542 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7543 7544 u8 reserved_at_c0[0x40]; 7545 7546 struct mlx5_ifc_tisc_bits ctx; 7547 }; 7548 7549 struct mlx5_ifc_modify_tir_bitmask_bits { 7550 u8 reserved_at_0[0x20]; 7551 7552 u8 reserved_at_20[0x1b]; 7553 u8 self_lb_en[0x1]; 7554 u8 reserved_at_3c[0x1]; 7555 u8 hash[0x1]; 7556 u8 reserved_at_3e[0x1]; 7557 u8 packet_merge[0x1]; 7558 }; 7559 7560 struct mlx5_ifc_modify_tir_out_bits { 7561 u8 status[0x8]; 7562 u8 reserved_at_8[0x18]; 7563 7564 u8 syndrome[0x20]; 7565 7566 u8 reserved_at_40[0x40]; 7567 }; 7568 7569 struct mlx5_ifc_modify_tir_in_bits { 7570 u8 opcode[0x10]; 7571 u8 uid[0x10]; 7572 7573 u8 reserved_at_20[0x10]; 7574 u8 op_mod[0x10]; 7575 7576 u8 reserved_at_40[0x8]; 7577 u8 tirn[0x18]; 7578 7579 u8 reserved_at_60[0x20]; 7580 7581 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7582 7583 u8 reserved_at_c0[0x40]; 7584 7585 struct mlx5_ifc_tirc_bits ctx; 7586 }; 7587 7588 struct mlx5_ifc_modify_sq_out_bits { 7589 u8 status[0x8]; 7590 u8 reserved_at_8[0x18]; 7591 7592 u8 syndrome[0x20]; 7593 7594 u8 reserved_at_40[0x40]; 7595 }; 7596 7597 struct mlx5_ifc_modify_sq_in_bits { 7598 u8 opcode[0x10]; 7599 u8 uid[0x10]; 7600 7601 u8 reserved_at_20[0x10]; 7602 u8 op_mod[0x10]; 7603 7604 u8 sq_state[0x4]; 7605 u8 reserved_at_44[0x4]; 7606 u8 sqn[0x18]; 7607 7608 u8 reserved_at_60[0x20]; 7609 7610 u8 modify_bitmask[0x40]; 7611 7612 u8 reserved_at_c0[0x40]; 7613 7614 struct mlx5_ifc_sqc_bits ctx; 7615 }; 7616 7617 struct mlx5_ifc_modify_scheduling_element_out_bits { 7618 u8 status[0x8]; 7619 u8 reserved_at_8[0x18]; 7620 7621 u8 syndrome[0x20]; 7622 7623 u8 reserved_at_40[0x1c0]; 7624 }; 7625 7626 enum { 7627 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7628 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7629 }; 7630 7631 struct mlx5_ifc_modify_scheduling_element_in_bits { 7632 u8 opcode[0x10]; 7633 u8 reserved_at_10[0x10]; 7634 7635 u8 reserved_at_20[0x10]; 7636 u8 op_mod[0x10]; 7637 7638 u8 scheduling_hierarchy[0x8]; 7639 u8 reserved_at_48[0x18]; 7640 7641 u8 scheduling_element_id[0x20]; 7642 7643 u8 reserved_at_80[0x20]; 7644 7645 u8 modify_bitmask[0x20]; 7646 7647 u8 reserved_at_c0[0x40]; 7648 7649 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7650 7651 u8 reserved_at_300[0x100]; 7652 }; 7653 7654 struct mlx5_ifc_modify_rqt_out_bits { 7655 u8 status[0x8]; 7656 u8 reserved_at_8[0x18]; 7657 7658 u8 syndrome[0x20]; 7659 7660 u8 reserved_at_40[0x40]; 7661 }; 7662 7663 struct mlx5_ifc_rqt_bitmask_bits { 7664 u8 reserved_at_0[0x20]; 7665 7666 u8 reserved_at_20[0x1f]; 7667 u8 rqn_list[0x1]; 7668 }; 7669 7670 struct mlx5_ifc_modify_rqt_in_bits { 7671 u8 opcode[0x10]; 7672 u8 uid[0x10]; 7673 7674 u8 reserved_at_20[0x10]; 7675 u8 op_mod[0x10]; 7676 7677 u8 reserved_at_40[0x8]; 7678 u8 rqtn[0x18]; 7679 7680 u8 reserved_at_60[0x20]; 7681 7682 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7683 7684 u8 reserved_at_c0[0x40]; 7685 7686 struct mlx5_ifc_rqtc_bits ctx; 7687 }; 7688 7689 struct mlx5_ifc_modify_rq_out_bits { 7690 u8 status[0x8]; 7691 u8 reserved_at_8[0x18]; 7692 7693 u8 syndrome[0x20]; 7694 7695 u8 reserved_at_40[0x40]; 7696 }; 7697 7698 enum { 7699 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7700 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7701 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7702 }; 7703 7704 struct mlx5_ifc_modify_rq_in_bits { 7705 u8 opcode[0x10]; 7706 u8 uid[0x10]; 7707 7708 u8 reserved_at_20[0x10]; 7709 u8 op_mod[0x10]; 7710 7711 u8 rq_state[0x4]; 7712 u8 reserved_at_44[0x4]; 7713 u8 rqn[0x18]; 7714 7715 u8 reserved_at_60[0x20]; 7716 7717 u8 modify_bitmask[0x40]; 7718 7719 u8 reserved_at_c0[0x40]; 7720 7721 struct mlx5_ifc_rqc_bits ctx; 7722 }; 7723 7724 struct mlx5_ifc_modify_rmp_out_bits { 7725 u8 status[0x8]; 7726 u8 reserved_at_8[0x18]; 7727 7728 u8 syndrome[0x20]; 7729 7730 u8 reserved_at_40[0x40]; 7731 }; 7732 7733 struct mlx5_ifc_rmp_bitmask_bits { 7734 u8 reserved_at_0[0x20]; 7735 7736 u8 reserved_at_20[0x1f]; 7737 u8 lwm[0x1]; 7738 }; 7739 7740 struct mlx5_ifc_modify_rmp_in_bits { 7741 u8 opcode[0x10]; 7742 u8 uid[0x10]; 7743 7744 u8 reserved_at_20[0x10]; 7745 u8 op_mod[0x10]; 7746 7747 u8 rmp_state[0x4]; 7748 u8 reserved_at_44[0x4]; 7749 u8 rmpn[0x18]; 7750 7751 u8 reserved_at_60[0x20]; 7752 7753 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7754 7755 u8 reserved_at_c0[0x40]; 7756 7757 struct mlx5_ifc_rmpc_bits ctx; 7758 }; 7759 7760 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7761 u8 status[0x8]; 7762 u8 reserved_at_8[0x18]; 7763 7764 u8 syndrome[0x20]; 7765 7766 u8 reserved_at_40[0x40]; 7767 }; 7768 7769 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7770 u8 reserved_at_0[0x12]; 7771 u8 affiliation[0x1]; 7772 u8 reserved_at_13[0x1]; 7773 u8 disable_uc_local_lb[0x1]; 7774 u8 disable_mc_local_lb[0x1]; 7775 u8 node_guid[0x1]; 7776 u8 port_guid[0x1]; 7777 u8 min_inline[0x1]; 7778 u8 mtu[0x1]; 7779 u8 change_event[0x1]; 7780 u8 promisc[0x1]; 7781 u8 permanent_address[0x1]; 7782 u8 addresses_list[0x1]; 7783 u8 roce_en[0x1]; 7784 u8 reserved_at_1f[0x1]; 7785 }; 7786 7787 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7788 u8 opcode[0x10]; 7789 u8 reserved_at_10[0x10]; 7790 7791 u8 reserved_at_20[0x10]; 7792 u8 op_mod[0x10]; 7793 7794 u8 other_vport[0x1]; 7795 u8 reserved_at_41[0xf]; 7796 u8 vport_number[0x10]; 7797 7798 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7799 7800 u8 reserved_at_80[0x780]; 7801 7802 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7803 }; 7804 7805 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7806 u8 status[0x8]; 7807 u8 reserved_at_8[0x18]; 7808 7809 u8 syndrome[0x20]; 7810 7811 u8 reserved_at_40[0x40]; 7812 }; 7813 7814 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7815 u8 opcode[0x10]; 7816 u8 reserved_at_10[0x10]; 7817 7818 u8 reserved_at_20[0x10]; 7819 u8 op_mod[0x10]; 7820 7821 u8 other_vport[0x1]; 7822 u8 reserved_at_41[0xb]; 7823 u8 port_num[0x4]; 7824 u8 vport_number[0x10]; 7825 7826 u8 reserved_at_60[0x20]; 7827 7828 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7829 }; 7830 7831 struct mlx5_ifc_modify_cq_out_bits { 7832 u8 status[0x8]; 7833 u8 reserved_at_8[0x18]; 7834 7835 u8 syndrome[0x20]; 7836 7837 u8 reserved_at_40[0x40]; 7838 }; 7839 7840 enum { 7841 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7842 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7843 }; 7844 7845 struct mlx5_ifc_modify_cq_in_bits { 7846 u8 opcode[0x10]; 7847 u8 uid[0x10]; 7848 7849 u8 reserved_at_20[0x10]; 7850 u8 op_mod[0x10]; 7851 7852 u8 reserved_at_40[0x8]; 7853 u8 cqn[0x18]; 7854 7855 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7856 7857 struct mlx5_ifc_cqc_bits cq_context; 7858 7859 u8 reserved_at_280[0x60]; 7860 7861 u8 cq_umem_valid[0x1]; 7862 u8 reserved_at_2e1[0x1f]; 7863 7864 u8 reserved_at_300[0x580]; 7865 7866 u8 pas[][0x40]; 7867 }; 7868 7869 struct mlx5_ifc_modify_cong_status_out_bits { 7870 u8 status[0x8]; 7871 u8 reserved_at_8[0x18]; 7872 7873 u8 syndrome[0x20]; 7874 7875 u8 reserved_at_40[0x40]; 7876 }; 7877 7878 struct mlx5_ifc_modify_cong_status_in_bits { 7879 u8 opcode[0x10]; 7880 u8 reserved_at_10[0x10]; 7881 7882 u8 reserved_at_20[0x10]; 7883 u8 op_mod[0x10]; 7884 7885 u8 reserved_at_40[0x18]; 7886 u8 priority[0x4]; 7887 u8 cong_protocol[0x4]; 7888 7889 u8 enable[0x1]; 7890 u8 tag_enable[0x1]; 7891 u8 reserved_at_62[0x1e]; 7892 }; 7893 7894 struct mlx5_ifc_modify_cong_params_out_bits { 7895 u8 status[0x8]; 7896 u8 reserved_at_8[0x18]; 7897 7898 u8 syndrome[0x20]; 7899 7900 u8 reserved_at_40[0x40]; 7901 }; 7902 7903 struct mlx5_ifc_modify_cong_params_in_bits { 7904 u8 opcode[0x10]; 7905 u8 reserved_at_10[0x10]; 7906 7907 u8 reserved_at_20[0x10]; 7908 u8 op_mod[0x10]; 7909 7910 u8 reserved_at_40[0x1c]; 7911 u8 cong_protocol[0x4]; 7912 7913 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7914 7915 u8 reserved_at_80[0x80]; 7916 7917 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7918 }; 7919 7920 struct mlx5_ifc_manage_pages_out_bits { 7921 u8 status[0x8]; 7922 u8 reserved_at_8[0x18]; 7923 7924 u8 syndrome[0x20]; 7925 7926 u8 output_num_entries[0x20]; 7927 7928 u8 reserved_at_60[0x20]; 7929 7930 u8 pas[][0x40]; 7931 }; 7932 7933 enum { 7934 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7935 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7936 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7937 }; 7938 7939 struct mlx5_ifc_manage_pages_in_bits { 7940 u8 opcode[0x10]; 7941 u8 reserved_at_10[0x10]; 7942 7943 u8 reserved_at_20[0x10]; 7944 u8 op_mod[0x10]; 7945 7946 u8 embedded_cpu_function[0x1]; 7947 u8 reserved_at_41[0xf]; 7948 u8 function_id[0x10]; 7949 7950 u8 input_num_entries[0x20]; 7951 7952 u8 pas[][0x40]; 7953 }; 7954 7955 struct mlx5_ifc_mad_ifc_out_bits { 7956 u8 status[0x8]; 7957 u8 reserved_at_8[0x18]; 7958 7959 u8 syndrome[0x20]; 7960 7961 u8 reserved_at_40[0x40]; 7962 7963 u8 response_mad_packet[256][0x8]; 7964 }; 7965 7966 struct mlx5_ifc_mad_ifc_in_bits { 7967 u8 opcode[0x10]; 7968 u8 reserved_at_10[0x10]; 7969 7970 u8 reserved_at_20[0x10]; 7971 u8 op_mod[0x10]; 7972 7973 u8 remote_lid[0x10]; 7974 u8 plane_index[0x8]; 7975 u8 port[0x8]; 7976 7977 u8 reserved_at_60[0x20]; 7978 7979 u8 mad[256][0x8]; 7980 }; 7981 7982 struct mlx5_ifc_init_hca_out_bits { 7983 u8 status[0x8]; 7984 u8 reserved_at_8[0x18]; 7985 7986 u8 syndrome[0x20]; 7987 7988 u8 reserved_at_40[0x40]; 7989 }; 7990 7991 struct mlx5_ifc_init_hca_in_bits { 7992 u8 opcode[0x10]; 7993 u8 reserved_at_10[0x10]; 7994 7995 u8 reserved_at_20[0x10]; 7996 u8 op_mod[0x10]; 7997 7998 u8 reserved_at_40[0x20]; 7999 8000 u8 reserved_at_60[0x2]; 8001 u8 sw_vhca_id[0xe]; 8002 u8 reserved_at_70[0x10]; 8003 8004 u8 sw_owner_id[4][0x20]; 8005 }; 8006 8007 struct mlx5_ifc_init2rtr_qp_out_bits { 8008 u8 status[0x8]; 8009 u8 reserved_at_8[0x18]; 8010 8011 u8 syndrome[0x20]; 8012 8013 u8 reserved_at_40[0x20]; 8014 u8 ece[0x20]; 8015 }; 8016 8017 struct mlx5_ifc_init2rtr_qp_in_bits { 8018 u8 opcode[0x10]; 8019 u8 uid[0x10]; 8020 8021 u8 reserved_at_20[0x10]; 8022 u8 op_mod[0x10]; 8023 8024 u8 reserved_at_40[0x8]; 8025 u8 qpn[0x18]; 8026 8027 u8 reserved_at_60[0x20]; 8028 8029 u8 opt_param_mask[0x20]; 8030 8031 u8 ece[0x20]; 8032 8033 struct mlx5_ifc_qpc_bits qpc; 8034 8035 u8 reserved_at_800[0x80]; 8036 }; 8037 8038 struct mlx5_ifc_init2init_qp_out_bits { 8039 u8 status[0x8]; 8040 u8 reserved_at_8[0x18]; 8041 8042 u8 syndrome[0x20]; 8043 8044 u8 reserved_at_40[0x20]; 8045 u8 ece[0x20]; 8046 }; 8047 8048 struct mlx5_ifc_init2init_qp_in_bits { 8049 u8 opcode[0x10]; 8050 u8 uid[0x10]; 8051 8052 u8 reserved_at_20[0x10]; 8053 u8 op_mod[0x10]; 8054 8055 u8 reserved_at_40[0x8]; 8056 u8 qpn[0x18]; 8057 8058 u8 reserved_at_60[0x20]; 8059 8060 u8 opt_param_mask[0x20]; 8061 8062 u8 ece[0x20]; 8063 8064 struct mlx5_ifc_qpc_bits qpc; 8065 8066 u8 reserved_at_800[0x80]; 8067 }; 8068 8069 struct mlx5_ifc_get_dropped_packet_log_out_bits { 8070 u8 status[0x8]; 8071 u8 reserved_at_8[0x18]; 8072 8073 u8 syndrome[0x20]; 8074 8075 u8 reserved_at_40[0x40]; 8076 8077 u8 packet_headers_log[128][0x8]; 8078 8079 u8 packet_syndrome[64][0x8]; 8080 }; 8081 8082 struct mlx5_ifc_get_dropped_packet_log_in_bits { 8083 u8 opcode[0x10]; 8084 u8 reserved_at_10[0x10]; 8085 8086 u8 reserved_at_20[0x10]; 8087 u8 op_mod[0x10]; 8088 8089 u8 reserved_at_40[0x40]; 8090 }; 8091 8092 struct mlx5_ifc_gen_eqe_in_bits { 8093 u8 opcode[0x10]; 8094 u8 reserved_at_10[0x10]; 8095 8096 u8 reserved_at_20[0x10]; 8097 u8 op_mod[0x10]; 8098 8099 u8 reserved_at_40[0x18]; 8100 u8 eq_number[0x8]; 8101 8102 u8 reserved_at_60[0x20]; 8103 8104 u8 eqe[64][0x8]; 8105 }; 8106 8107 struct mlx5_ifc_gen_eq_out_bits { 8108 u8 status[0x8]; 8109 u8 reserved_at_8[0x18]; 8110 8111 u8 syndrome[0x20]; 8112 8113 u8 reserved_at_40[0x40]; 8114 }; 8115 8116 struct mlx5_ifc_enable_hca_out_bits { 8117 u8 status[0x8]; 8118 u8 reserved_at_8[0x18]; 8119 8120 u8 syndrome[0x20]; 8121 8122 u8 reserved_at_40[0x20]; 8123 }; 8124 8125 struct mlx5_ifc_enable_hca_in_bits { 8126 u8 opcode[0x10]; 8127 u8 reserved_at_10[0x10]; 8128 8129 u8 reserved_at_20[0x10]; 8130 u8 op_mod[0x10]; 8131 8132 u8 embedded_cpu_function[0x1]; 8133 u8 reserved_at_41[0xf]; 8134 u8 function_id[0x10]; 8135 8136 u8 reserved_at_60[0x20]; 8137 }; 8138 8139 struct mlx5_ifc_drain_dct_out_bits { 8140 u8 status[0x8]; 8141 u8 reserved_at_8[0x18]; 8142 8143 u8 syndrome[0x20]; 8144 8145 u8 reserved_at_40[0x40]; 8146 }; 8147 8148 struct mlx5_ifc_drain_dct_in_bits { 8149 u8 opcode[0x10]; 8150 u8 uid[0x10]; 8151 8152 u8 reserved_at_20[0x10]; 8153 u8 op_mod[0x10]; 8154 8155 u8 reserved_at_40[0x8]; 8156 u8 dctn[0x18]; 8157 8158 u8 reserved_at_60[0x20]; 8159 }; 8160 8161 struct mlx5_ifc_disable_hca_out_bits { 8162 u8 status[0x8]; 8163 u8 reserved_at_8[0x18]; 8164 8165 u8 syndrome[0x20]; 8166 8167 u8 reserved_at_40[0x20]; 8168 }; 8169 8170 struct mlx5_ifc_disable_hca_in_bits { 8171 u8 opcode[0x10]; 8172 u8 reserved_at_10[0x10]; 8173 8174 u8 reserved_at_20[0x10]; 8175 u8 op_mod[0x10]; 8176 8177 u8 embedded_cpu_function[0x1]; 8178 u8 reserved_at_41[0xf]; 8179 u8 function_id[0x10]; 8180 8181 u8 reserved_at_60[0x20]; 8182 }; 8183 8184 struct mlx5_ifc_detach_from_mcg_out_bits { 8185 u8 status[0x8]; 8186 u8 reserved_at_8[0x18]; 8187 8188 u8 syndrome[0x20]; 8189 8190 u8 reserved_at_40[0x40]; 8191 }; 8192 8193 struct mlx5_ifc_detach_from_mcg_in_bits { 8194 u8 opcode[0x10]; 8195 u8 uid[0x10]; 8196 8197 u8 reserved_at_20[0x10]; 8198 u8 op_mod[0x10]; 8199 8200 u8 reserved_at_40[0x8]; 8201 u8 qpn[0x18]; 8202 8203 u8 reserved_at_60[0x20]; 8204 8205 u8 multicast_gid[16][0x8]; 8206 }; 8207 8208 struct mlx5_ifc_destroy_xrq_out_bits { 8209 u8 status[0x8]; 8210 u8 reserved_at_8[0x18]; 8211 8212 u8 syndrome[0x20]; 8213 8214 u8 reserved_at_40[0x40]; 8215 }; 8216 8217 struct mlx5_ifc_destroy_xrq_in_bits { 8218 u8 opcode[0x10]; 8219 u8 uid[0x10]; 8220 8221 u8 reserved_at_20[0x10]; 8222 u8 op_mod[0x10]; 8223 8224 u8 reserved_at_40[0x8]; 8225 u8 xrqn[0x18]; 8226 8227 u8 reserved_at_60[0x20]; 8228 }; 8229 8230 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8231 u8 status[0x8]; 8232 u8 reserved_at_8[0x18]; 8233 8234 u8 syndrome[0x20]; 8235 8236 u8 reserved_at_40[0x40]; 8237 }; 8238 8239 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8240 u8 opcode[0x10]; 8241 u8 uid[0x10]; 8242 8243 u8 reserved_at_20[0x10]; 8244 u8 op_mod[0x10]; 8245 8246 u8 reserved_at_40[0x8]; 8247 u8 xrc_srqn[0x18]; 8248 8249 u8 reserved_at_60[0x20]; 8250 }; 8251 8252 struct mlx5_ifc_destroy_tis_out_bits { 8253 u8 status[0x8]; 8254 u8 reserved_at_8[0x18]; 8255 8256 u8 syndrome[0x20]; 8257 8258 u8 reserved_at_40[0x40]; 8259 }; 8260 8261 struct mlx5_ifc_destroy_tis_in_bits { 8262 u8 opcode[0x10]; 8263 u8 uid[0x10]; 8264 8265 u8 reserved_at_20[0x10]; 8266 u8 op_mod[0x10]; 8267 8268 u8 reserved_at_40[0x8]; 8269 u8 tisn[0x18]; 8270 8271 u8 reserved_at_60[0x20]; 8272 }; 8273 8274 struct mlx5_ifc_destroy_tir_out_bits { 8275 u8 status[0x8]; 8276 u8 reserved_at_8[0x18]; 8277 8278 u8 syndrome[0x20]; 8279 8280 u8 reserved_at_40[0x40]; 8281 }; 8282 8283 struct mlx5_ifc_destroy_tir_in_bits { 8284 u8 opcode[0x10]; 8285 u8 uid[0x10]; 8286 8287 u8 reserved_at_20[0x10]; 8288 u8 op_mod[0x10]; 8289 8290 u8 reserved_at_40[0x8]; 8291 u8 tirn[0x18]; 8292 8293 u8 reserved_at_60[0x20]; 8294 }; 8295 8296 struct mlx5_ifc_destroy_srq_out_bits { 8297 u8 status[0x8]; 8298 u8 reserved_at_8[0x18]; 8299 8300 u8 syndrome[0x20]; 8301 8302 u8 reserved_at_40[0x40]; 8303 }; 8304 8305 struct mlx5_ifc_destroy_srq_in_bits { 8306 u8 opcode[0x10]; 8307 u8 uid[0x10]; 8308 8309 u8 reserved_at_20[0x10]; 8310 u8 op_mod[0x10]; 8311 8312 u8 reserved_at_40[0x8]; 8313 u8 srqn[0x18]; 8314 8315 u8 reserved_at_60[0x20]; 8316 }; 8317 8318 struct mlx5_ifc_destroy_sq_out_bits { 8319 u8 status[0x8]; 8320 u8 reserved_at_8[0x18]; 8321 8322 u8 syndrome[0x20]; 8323 8324 u8 reserved_at_40[0x40]; 8325 }; 8326 8327 struct mlx5_ifc_destroy_sq_in_bits { 8328 u8 opcode[0x10]; 8329 u8 uid[0x10]; 8330 8331 u8 reserved_at_20[0x10]; 8332 u8 op_mod[0x10]; 8333 8334 u8 reserved_at_40[0x8]; 8335 u8 sqn[0x18]; 8336 8337 u8 reserved_at_60[0x20]; 8338 }; 8339 8340 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8341 u8 status[0x8]; 8342 u8 reserved_at_8[0x18]; 8343 8344 u8 syndrome[0x20]; 8345 8346 u8 reserved_at_40[0x1c0]; 8347 }; 8348 8349 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8350 u8 opcode[0x10]; 8351 u8 reserved_at_10[0x10]; 8352 8353 u8 reserved_at_20[0x10]; 8354 u8 op_mod[0x10]; 8355 8356 u8 scheduling_hierarchy[0x8]; 8357 u8 reserved_at_48[0x18]; 8358 8359 u8 scheduling_element_id[0x20]; 8360 8361 u8 reserved_at_80[0x180]; 8362 }; 8363 8364 struct mlx5_ifc_destroy_rqt_out_bits { 8365 u8 status[0x8]; 8366 u8 reserved_at_8[0x18]; 8367 8368 u8 syndrome[0x20]; 8369 8370 u8 reserved_at_40[0x40]; 8371 }; 8372 8373 struct mlx5_ifc_destroy_rqt_in_bits { 8374 u8 opcode[0x10]; 8375 u8 uid[0x10]; 8376 8377 u8 reserved_at_20[0x10]; 8378 u8 op_mod[0x10]; 8379 8380 u8 reserved_at_40[0x8]; 8381 u8 rqtn[0x18]; 8382 8383 u8 reserved_at_60[0x20]; 8384 }; 8385 8386 struct mlx5_ifc_destroy_rq_out_bits { 8387 u8 status[0x8]; 8388 u8 reserved_at_8[0x18]; 8389 8390 u8 syndrome[0x20]; 8391 8392 u8 reserved_at_40[0x40]; 8393 }; 8394 8395 struct mlx5_ifc_destroy_rq_in_bits { 8396 u8 opcode[0x10]; 8397 u8 uid[0x10]; 8398 8399 u8 reserved_at_20[0x10]; 8400 u8 op_mod[0x10]; 8401 8402 u8 reserved_at_40[0x8]; 8403 u8 rqn[0x18]; 8404 8405 u8 reserved_at_60[0x20]; 8406 }; 8407 8408 struct mlx5_ifc_set_delay_drop_params_in_bits { 8409 u8 opcode[0x10]; 8410 u8 reserved_at_10[0x10]; 8411 8412 u8 reserved_at_20[0x10]; 8413 u8 op_mod[0x10]; 8414 8415 u8 reserved_at_40[0x20]; 8416 8417 u8 reserved_at_60[0x10]; 8418 u8 delay_drop_timeout[0x10]; 8419 }; 8420 8421 struct mlx5_ifc_set_delay_drop_params_out_bits { 8422 u8 status[0x8]; 8423 u8 reserved_at_8[0x18]; 8424 8425 u8 syndrome[0x20]; 8426 8427 u8 reserved_at_40[0x40]; 8428 }; 8429 8430 struct mlx5_ifc_destroy_rmp_out_bits { 8431 u8 status[0x8]; 8432 u8 reserved_at_8[0x18]; 8433 8434 u8 syndrome[0x20]; 8435 8436 u8 reserved_at_40[0x40]; 8437 }; 8438 8439 struct mlx5_ifc_destroy_rmp_in_bits { 8440 u8 opcode[0x10]; 8441 u8 uid[0x10]; 8442 8443 u8 reserved_at_20[0x10]; 8444 u8 op_mod[0x10]; 8445 8446 u8 reserved_at_40[0x8]; 8447 u8 rmpn[0x18]; 8448 8449 u8 reserved_at_60[0x20]; 8450 }; 8451 8452 struct mlx5_ifc_destroy_qp_out_bits { 8453 u8 status[0x8]; 8454 u8 reserved_at_8[0x18]; 8455 8456 u8 syndrome[0x20]; 8457 8458 u8 reserved_at_40[0x40]; 8459 }; 8460 8461 struct mlx5_ifc_destroy_qp_in_bits { 8462 u8 opcode[0x10]; 8463 u8 uid[0x10]; 8464 8465 u8 reserved_at_20[0x10]; 8466 u8 op_mod[0x10]; 8467 8468 u8 reserved_at_40[0x8]; 8469 u8 qpn[0x18]; 8470 8471 u8 reserved_at_60[0x20]; 8472 }; 8473 8474 struct mlx5_ifc_destroy_psv_out_bits { 8475 u8 status[0x8]; 8476 u8 reserved_at_8[0x18]; 8477 8478 u8 syndrome[0x20]; 8479 8480 u8 reserved_at_40[0x40]; 8481 }; 8482 8483 struct mlx5_ifc_destroy_psv_in_bits { 8484 u8 opcode[0x10]; 8485 u8 reserved_at_10[0x10]; 8486 8487 u8 reserved_at_20[0x10]; 8488 u8 op_mod[0x10]; 8489 8490 u8 reserved_at_40[0x8]; 8491 u8 psvn[0x18]; 8492 8493 u8 reserved_at_60[0x20]; 8494 }; 8495 8496 struct mlx5_ifc_destroy_mkey_out_bits { 8497 u8 status[0x8]; 8498 u8 reserved_at_8[0x18]; 8499 8500 u8 syndrome[0x20]; 8501 8502 u8 reserved_at_40[0x40]; 8503 }; 8504 8505 struct mlx5_ifc_destroy_mkey_in_bits { 8506 u8 opcode[0x10]; 8507 u8 uid[0x10]; 8508 8509 u8 reserved_at_20[0x10]; 8510 u8 op_mod[0x10]; 8511 8512 u8 reserved_at_40[0x8]; 8513 u8 mkey_index[0x18]; 8514 8515 u8 reserved_at_60[0x20]; 8516 }; 8517 8518 struct mlx5_ifc_destroy_flow_table_out_bits { 8519 u8 status[0x8]; 8520 u8 reserved_at_8[0x18]; 8521 8522 u8 syndrome[0x20]; 8523 8524 u8 reserved_at_40[0x40]; 8525 }; 8526 8527 struct mlx5_ifc_destroy_flow_table_in_bits { 8528 u8 opcode[0x10]; 8529 u8 reserved_at_10[0x10]; 8530 8531 u8 reserved_at_20[0x10]; 8532 u8 op_mod[0x10]; 8533 8534 u8 other_vport[0x1]; 8535 u8 reserved_at_41[0xf]; 8536 u8 vport_number[0x10]; 8537 8538 u8 reserved_at_60[0x20]; 8539 8540 u8 table_type[0x8]; 8541 u8 reserved_at_88[0x18]; 8542 8543 u8 reserved_at_a0[0x8]; 8544 u8 table_id[0x18]; 8545 8546 u8 reserved_at_c0[0x140]; 8547 }; 8548 8549 struct mlx5_ifc_destroy_flow_group_out_bits { 8550 u8 status[0x8]; 8551 u8 reserved_at_8[0x18]; 8552 8553 u8 syndrome[0x20]; 8554 8555 u8 reserved_at_40[0x40]; 8556 }; 8557 8558 struct mlx5_ifc_destroy_flow_group_in_bits { 8559 u8 opcode[0x10]; 8560 u8 reserved_at_10[0x10]; 8561 8562 u8 reserved_at_20[0x10]; 8563 u8 op_mod[0x10]; 8564 8565 u8 other_vport[0x1]; 8566 u8 reserved_at_41[0xf]; 8567 u8 vport_number[0x10]; 8568 8569 u8 reserved_at_60[0x20]; 8570 8571 u8 table_type[0x8]; 8572 u8 reserved_at_88[0x18]; 8573 8574 u8 reserved_at_a0[0x8]; 8575 u8 table_id[0x18]; 8576 8577 u8 group_id[0x20]; 8578 8579 u8 reserved_at_e0[0x120]; 8580 }; 8581 8582 struct mlx5_ifc_destroy_eq_out_bits { 8583 u8 status[0x8]; 8584 u8 reserved_at_8[0x18]; 8585 8586 u8 syndrome[0x20]; 8587 8588 u8 reserved_at_40[0x40]; 8589 }; 8590 8591 struct mlx5_ifc_destroy_eq_in_bits { 8592 u8 opcode[0x10]; 8593 u8 reserved_at_10[0x10]; 8594 8595 u8 reserved_at_20[0x10]; 8596 u8 op_mod[0x10]; 8597 8598 u8 reserved_at_40[0x18]; 8599 u8 eq_number[0x8]; 8600 8601 u8 reserved_at_60[0x20]; 8602 }; 8603 8604 struct mlx5_ifc_destroy_dct_out_bits { 8605 u8 status[0x8]; 8606 u8 reserved_at_8[0x18]; 8607 8608 u8 syndrome[0x20]; 8609 8610 u8 reserved_at_40[0x40]; 8611 }; 8612 8613 struct mlx5_ifc_destroy_dct_in_bits { 8614 u8 opcode[0x10]; 8615 u8 uid[0x10]; 8616 8617 u8 reserved_at_20[0x10]; 8618 u8 op_mod[0x10]; 8619 8620 u8 reserved_at_40[0x8]; 8621 u8 dctn[0x18]; 8622 8623 u8 reserved_at_60[0x20]; 8624 }; 8625 8626 struct mlx5_ifc_destroy_cq_out_bits { 8627 u8 status[0x8]; 8628 u8 reserved_at_8[0x18]; 8629 8630 u8 syndrome[0x20]; 8631 8632 u8 reserved_at_40[0x40]; 8633 }; 8634 8635 struct mlx5_ifc_destroy_cq_in_bits { 8636 u8 opcode[0x10]; 8637 u8 uid[0x10]; 8638 8639 u8 reserved_at_20[0x10]; 8640 u8 op_mod[0x10]; 8641 8642 u8 reserved_at_40[0x8]; 8643 u8 cqn[0x18]; 8644 8645 u8 reserved_at_60[0x20]; 8646 }; 8647 8648 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8649 u8 status[0x8]; 8650 u8 reserved_at_8[0x18]; 8651 8652 u8 syndrome[0x20]; 8653 8654 u8 reserved_at_40[0x40]; 8655 }; 8656 8657 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8658 u8 opcode[0x10]; 8659 u8 reserved_at_10[0x10]; 8660 8661 u8 reserved_at_20[0x10]; 8662 u8 op_mod[0x10]; 8663 8664 u8 reserved_at_40[0x20]; 8665 8666 u8 reserved_at_60[0x10]; 8667 u8 vxlan_udp_port[0x10]; 8668 }; 8669 8670 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8671 u8 status[0x8]; 8672 u8 reserved_at_8[0x18]; 8673 8674 u8 syndrome[0x20]; 8675 8676 u8 reserved_at_40[0x40]; 8677 }; 8678 8679 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8680 u8 opcode[0x10]; 8681 u8 reserved_at_10[0x10]; 8682 8683 u8 reserved_at_20[0x10]; 8684 u8 op_mod[0x10]; 8685 8686 u8 reserved_at_40[0x60]; 8687 8688 u8 reserved_at_a0[0x8]; 8689 u8 table_index[0x18]; 8690 8691 u8 reserved_at_c0[0x140]; 8692 }; 8693 8694 struct mlx5_ifc_delete_fte_out_bits { 8695 u8 status[0x8]; 8696 u8 reserved_at_8[0x18]; 8697 8698 u8 syndrome[0x20]; 8699 8700 u8 reserved_at_40[0x40]; 8701 }; 8702 8703 struct mlx5_ifc_delete_fte_in_bits { 8704 u8 opcode[0x10]; 8705 u8 reserved_at_10[0x10]; 8706 8707 u8 reserved_at_20[0x10]; 8708 u8 op_mod[0x10]; 8709 8710 u8 other_vport[0x1]; 8711 u8 reserved_at_41[0xf]; 8712 u8 vport_number[0x10]; 8713 8714 u8 reserved_at_60[0x20]; 8715 8716 u8 table_type[0x8]; 8717 u8 reserved_at_88[0x18]; 8718 8719 u8 reserved_at_a0[0x8]; 8720 u8 table_id[0x18]; 8721 8722 u8 reserved_at_c0[0x40]; 8723 8724 u8 flow_index[0x20]; 8725 8726 u8 reserved_at_120[0xe0]; 8727 }; 8728 8729 struct mlx5_ifc_dealloc_xrcd_out_bits { 8730 u8 status[0x8]; 8731 u8 reserved_at_8[0x18]; 8732 8733 u8 syndrome[0x20]; 8734 8735 u8 reserved_at_40[0x40]; 8736 }; 8737 8738 struct mlx5_ifc_dealloc_xrcd_in_bits { 8739 u8 opcode[0x10]; 8740 u8 uid[0x10]; 8741 8742 u8 reserved_at_20[0x10]; 8743 u8 op_mod[0x10]; 8744 8745 u8 reserved_at_40[0x8]; 8746 u8 xrcd[0x18]; 8747 8748 u8 reserved_at_60[0x20]; 8749 }; 8750 8751 struct mlx5_ifc_dealloc_uar_out_bits { 8752 u8 status[0x8]; 8753 u8 reserved_at_8[0x18]; 8754 8755 u8 syndrome[0x20]; 8756 8757 u8 reserved_at_40[0x40]; 8758 }; 8759 8760 struct mlx5_ifc_dealloc_uar_in_bits { 8761 u8 opcode[0x10]; 8762 u8 uid[0x10]; 8763 8764 u8 reserved_at_20[0x10]; 8765 u8 op_mod[0x10]; 8766 8767 u8 reserved_at_40[0x8]; 8768 u8 uar[0x18]; 8769 8770 u8 reserved_at_60[0x20]; 8771 }; 8772 8773 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8774 u8 status[0x8]; 8775 u8 reserved_at_8[0x18]; 8776 8777 u8 syndrome[0x20]; 8778 8779 u8 reserved_at_40[0x40]; 8780 }; 8781 8782 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8783 u8 opcode[0x10]; 8784 u8 uid[0x10]; 8785 8786 u8 reserved_at_20[0x10]; 8787 u8 op_mod[0x10]; 8788 8789 u8 reserved_at_40[0x8]; 8790 u8 transport_domain[0x18]; 8791 8792 u8 reserved_at_60[0x20]; 8793 }; 8794 8795 struct mlx5_ifc_dealloc_q_counter_out_bits { 8796 u8 status[0x8]; 8797 u8 reserved_at_8[0x18]; 8798 8799 u8 syndrome[0x20]; 8800 8801 u8 reserved_at_40[0x40]; 8802 }; 8803 8804 struct mlx5_ifc_dealloc_q_counter_in_bits { 8805 u8 opcode[0x10]; 8806 u8 reserved_at_10[0x10]; 8807 8808 u8 reserved_at_20[0x10]; 8809 u8 op_mod[0x10]; 8810 8811 u8 reserved_at_40[0x18]; 8812 u8 counter_set_id[0x8]; 8813 8814 u8 reserved_at_60[0x20]; 8815 }; 8816 8817 struct mlx5_ifc_dealloc_pd_out_bits { 8818 u8 status[0x8]; 8819 u8 reserved_at_8[0x18]; 8820 8821 u8 syndrome[0x20]; 8822 8823 u8 reserved_at_40[0x40]; 8824 }; 8825 8826 struct mlx5_ifc_dealloc_pd_in_bits { 8827 u8 opcode[0x10]; 8828 u8 uid[0x10]; 8829 8830 u8 reserved_at_20[0x10]; 8831 u8 op_mod[0x10]; 8832 8833 u8 reserved_at_40[0x8]; 8834 u8 pd[0x18]; 8835 8836 u8 reserved_at_60[0x20]; 8837 }; 8838 8839 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8840 u8 status[0x8]; 8841 u8 reserved_at_8[0x18]; 8842 8843 u8 syndrome[0x20]; 8844 8845 u8 reserved_at_40[0x40]; 8846 }; 8847 8848 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8849 u8 opcode[0x10]; 8850 u8 reserved_at_10[0x10]; 8851 8852 u8 reserved_at_20[0x10]; 8853 u8 op_mod[0x10]; 8854 8855 u8 flow_counter_id[0x20]; 8856 8857 u8 reserved_at_60[0x20]; 8858 }; 8859 8860 struct mlx5_ifc_create_xrq_out_bits { 8861 u8 status[0x8]; 8862 u8 reserved_at_8[0x18]; 8863 8864 u8 syndrome[0x20]; 8865 8866 u8 reserved_at_40[0x8]; 8867 u8 xrqn[0x18]; 8868 8869 u8 reserved_at_60[0x20]; 8870 }; 8871 8872 struct mlx5_ifc_create_xrq_in_bits { 8873 u8 opcode[0x10]; 8874 u8 uid[0x10]; 8875 8876 u8 reserved_at_20[0x10]; 8877 u8 op_mod[0x10]; 8878 8879 u8 reserved_at_40[0x40]; 8880 8881 struct mlx5_ifc_xrqc_bits xrq_context; 8882 }; 8883 8884 struct mlx5_ifc_create_xrc_srq_out_bits { 8885 u8 status[0x8]; 8886 u8 reserved_at_8[0x18]; 8887 8888 u8 syndrome[0x20]; 8889 8890 u8 reserved_at_40[0x8]; 8891 u8 xrc_srqn[0x18]; 8892 8893 u8 reserved_at_60[0x20]; 8894 }; 8895 8896 struct mlx5_ifc_create_xrc_srq_in_bits { 8897 u8 opcode[0x10]; 8898 u8 uid[0x10]; 8899 8900 u8 reserved_at_20[0x10]; 8901 u8 op_mod[0x10]; 8902 8903 u8 reserved_at_40[0x40]; 8904 8905 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8906 8907 u8 reserved_at_280[0x60]; 8908 8909 u8 xrc_srq_umem_valid[0x1]; 8910 u8 reserved_at_2e1[0x1f]; 8911 8912 u8 reserved_at_300[0x580]; 8913 8914 u8 pas[][0x40]; 8915 }; 8916 8917 struct mlx5_ifc_create_tis_out_bits { 8918 u8 status[0x8]; 8919 u8 reserved_at_8[0x18]; 8920 8921 u8 syndrome[0x20]; 8922 8923 u8 reserved_at_40[0x8]; 8924 u8 tisn[0x18]; 8925 8926 u8 reserved_at_60[0x20]; 8927 }; 8928 8929 struct mlx5_ifc_create_tis_in_bits { 8930 u8 opcode[0x10]; 8931 u8 uid[0x10]; 8932 8933 u8 reserved_at_20[0x10]; 8934 u8 op_mod[0x10]; 8935 8936 u8 reserved_at_40[0xc0]; 8937 8938 struct mlx5_ifc_tisc_bits ctx; 8939 }; 8940 8941 struct mlx5_ifc_create_tir_out_bits { 8942 u8 status[0x8]; 8943 u8 icm_address_63_40[0x18]; 8944 8945 u8 syndrome[0x20]; 8946 8947 u8 icm_address_39_32[0x8]; 8948 u8 tirn[0x18]; 8949 8950 u8 icm_address_31_0[0x20]; 8951 }; 8952 8953 struct mlx5_ifc_create_tir_in_bits { 8954 u8 opcode[0x10]; 8955 u8 uid[0x10]; 8956 8957 u8 reserved_at_20[0x10]; 8958 u8 op_mod[0x10]; 8959 8960 u8 reserved_at_40[0xc0]; 8961 8962 struct mlx5_ifc_tirc_bits ctx; 8963 }; 8964 8965 struct mlx5_ifc_create_srq_out_bits { 8966 u8 status[0x8]; 8967 u8 reserved_at_8[0x18]; 8968 8969 u8 syndrome[0x20]; 8970 8971 u8 reserved_at_40[0x8]; 8972 u8 srqn[0x18]; 8973 8974 u8 reserved_at_60[0x20]; 8975 }; 8976 8977 struct mlx5_ifc_create_srq_in_bits { 8978 u8 opcode[0x10]; 8979 u8 uid[0x10]; 8980 8981 u8 reserved_at_20[0x10]; 8982 u8 op_mod[0x10]; 8983 8984 u8 reserved_at_40[0x40]; 8985 8986 struct mlx5_ifc_srqc_bits srq_context_entry; 8987 8988 u8 reserved_at_280[0x600]; 8989 8990 u8 pas[][0x40]; 8991 }; 8992 8993 struct mlx5_ifc_create_sq_out_bits { 8994 u8 status[0x8]; 8995 u8 reserved_at_8[0x18]; 8996 8997 u8 syndrome[0x20]; 8998 8999 u8 reserved_at_40[0x8]; 9000 u8 sqn[0x18]; 9001 9002 u8 reserved_at_60[0x20]; 9003 }; 9004 9005 struct mlx5_ifc_create_sq_in_bits { 9006 u8 opcode[0x10]; 9007 u8 uid[0x10]; 9008 9009 u8 reserved_at_20[0x10]; 9010 u8 op_mod[0x10]; 9011 9012 u8 reserved_at_40[0xc0]; 9013 9014 struct mlx5_ifc_sqc_bits ctx; 9015 }; 9016 9017 struct mlx5_ifc_create_scheduling_element_out_bits { 9018 u8 status[0x8]; 9019 u8 reserved_at_8[0x18]; 9020 9021 u8 syndrome[0x20]; 9022 9023 u8 reserved_at_40[0x40]; 9024 9025 u8 scheduling_element_id[0x20]; 9026 9027 u8 reserved_at_a0[0x160]; 9028 }; 9029 9030 struct mlx5_ifc_create_scheduling_element_in_bits { 9031 u8 opcode[0x10]; 9032 u8 reserved_at_10[0x10]; 9033 9034 u8 reserved_at_20[0x10]; 9035 u8 op_mod[0x10]; 9036 9037 u8 scheduling_hierarchy[0x8]; 9038 u8 reserved_at_48[0x18]; 9039 9040 u8 reserved_at_60[0xa0]; 9041 9042 struct mlx5_ifc_scheduling_context_bits scheduling_context; 9043 9044 u8 reserved_at_300[0x100]; 9045 }; 9046 9047 struct mlx5_ifc_create_rqt_out_bits { 9048 u8 status[0x8]; 9049 u8 reserved_at_8[0x18]; 9050 9051 u8 syndrome[0x20]; 9052 9053 u8 reserved_at_40[0x8]; 9054 u8 rqtn[0x18]; 9055 9056 u8 reserved_at_60[0x20]; 9057 }; 9058 9059 struct mlx5_ifc_create_rqt_in_bits { 9060 u8 opcode[0x10]; 9061 u8 uid[0x10]; 9062 9063 u8 reserved_at_20[0x10]; 9064 u8 op_mod[0x10]; 9065 9066 u8 reserved_at_40[0xc0]; 9067 9068 struct mlx5_ifc_rqtc_bits rqt_context; 9069 }; 9070 9071 struct mlx5_ifc_create_rq_out_bits { 9072 u8 status[0x8]; 9073 u8 reserved_at_8[0x18]; 9074 9075 u8 syndrome[0x20]; 9076 9077 u8 reserved_at_40[0x8]; 9078 u8 rqn[0x18]; 9079 9080 u8 reserved_at_60[0x20]; 9081 }; 9082 9083 struct mlx5_ifc_create_rq_in_bits { 9084 u8 opcode[0x10]; 9085 u8 uid[0x10]; 9086 9087 u8 reserved_at_20[0x10]; 9088 u8 op_mod[0x10]; 9089 9090 u8 reserved_at_40[0xc0]; 9091 9092 struct mlx5_ifc_rqc_bits ctx; 9093 }; 9094 9095 struct mlx5_ifc_create_rmp_out_bits { 9096 u8 status[0x8]; 9097 u8 reserved_at_8[0x18]; 9098 9099 u8 syndrome[0x20]; 9100 9101 u8 reserved_at_40[0x8]; 9102 u8 rmpn[0x18]; 9103 9104 u8 reserved_at_60[0x20]; 9105 }; 9106 9107 struct mlx5_ifc_create_rmp_in_bits { 9108 u8 opcode[0x10]; 9109 u8 uid[0x10]; 9110 9111 u8 reserved_at_20[0x10]; 9112 u8 op_mod[0x10]; 9113 9114 u8 reserved_at_40[0xc0]; 9115 9116 struct mlx5_ifc_rmpc_bits ctx; 9117 }; 9118 9119 struct mlx5_ifc_create_qp_out_bits { 9120 u8 status[0x8]; 9121 u8 reserved_at_8[0x18]; 9122 9123 u8 syndrome[0x20]; 9124 9125 u8 reserved_at_40[0x8]; 9126 u8 qpn[0x18]; 9127 9128 u8 ece[0x20]; 9129 }; 9130 9131 struct mlx5_ifc_create_qp_in_bits { 9132 u8 opcode[0x10]; 9133 u8 uid[0x10]; 9134 9135 u8 reserved_at_20[0x10]; 9136 u8 op_mod[0x10]; 9137 9138 u8 qpc_ext[0x1]; 9139 u8 reserved_at_41[0x7]; 9140 u8 input_qpn[0x18]; 9141 9142 u8 reserved_at_60[0x20]; 9143 u8 opt_param_mask[0x20]; 9144 9145 u8 ece[0x20]; 9146 9147 struct mlx5_ifc_qpc_bits qpc; 9148 9149 u8 wq_umem_offset[0x40]; 9150 9151 u8 wq_umem_id[0x20]; 9152 9153 u8 wq_umem_valid[0x1]; 9154 u8 reserved_at_861[0x1f]; 9155 9156 u8 pas[][0x40]; 9157 }; 9158 9159 struct mlx5_ifc_create_psv_out_bits { 9160 u8 status[0x8]; 9161 u8 reserved_at_8[0x18]; 9162 9163 u8 syndrome[0x20]; 9164 9165 u8 reserved_at_40[0x40]; 9166 9167 u8 reserved_at_80[0x8]; 9168 u8 psv0_index[0x18]; 9169 9170 u8 reserved_at_a0[0x8]; 9171 u8 psv1_index[0x18]; 9172 9173 u8 reserved_at_c0[0x8]; 9174 u8 psv2_index[0x18]; 9175 9176 u8 reserved_at_e0[0x8]; 9177 u8 psv3_index[0x18]; 9178 }; 9179 9180 struct mlx5_ifc_create_psv_in_bits { 9181 u8 opcode[0x10]; 9182 u8 reserved_at_10[0x10]; 9183 9184 u8 reserved_at_20[0x10]; 9185 u8 op_mod[0x10]; 9186 9187 u8 num_psv[0x4]; 9188 u8 reserved_at_44[0x4]; 9189 u8 pd[0x18]; 9190 9191 u8 reserved_at_60[0x20]; 9192 }; 9193 9194 struct mlx5_ifc_create_mkey_out_bits { 9195 u8 status[0x8]; 9196 u8 reserved_at_8[0x18]; 9197 9198 u8 syndrome[0x20]; 9199 9200 u8 reserved_at_40[0x8]; 9201 u8 mkey_index[0x18]; 9202 9203 u8 reserved_at_60[0x20]; 9204 }; 9205 9206 struct mlx5_ifc_create_mkey_in_bits { 9207 u8 opcode[0x10]; 9208 u8 uid[0x10]; 9209 9210 u8 reserved_at_20[0x10]; 9211 u8 op_mod[0x10]; 9212 9213 u8 reserved_at_40[0x20]; 9214 9215 u8 pg_access[0x1]; 9216 u8 mkey_umem_valid[0x1]; 9217 u8 data_direct[0x1]; 9218 u8 reserved_at_63[0x1d]; 9219 9220 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 9221 9222 u8 reserved_at_280[0x80]; 9223 9224 u8 translations_octword_actual_size[0x20]; 9225 9226 u8 reserved_at_320[0x560]; 9227 9228 u8 klm_pas_mtt[][0x20]; 9229 }; 9230 9231 enum { 9232 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9233 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9234 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9235 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9236 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9237 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9238 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9239 }; 9240 9241 struct mlx5_ifc_create_flow_table_out_bits { 9242 u8 status[0x8]; 9243 u8 icm_address_63_40[0x18]; 9244 9245 u8 syndrome[0x20]; 9246 9247 u8 icm_address_39_32[0x8]; 9248 u8 table_id[0x18]; 9249 9250 u8 icm_address_31_0[0x20]; 9251 }; 9252 9253 struct mlx5_ifc_create_flow_table_in_bits { 9254 u8 opcode[0x10]; 9255 u8 uid[0x10]; 9256 9257 u8 reserved_at_20[0x10]; 9258 u8 op_mod[0x10]; 9259 9260 u8 other_vport[0x1]; 9261 u8 reserved_at_41[0xf]; 9262 u8 vport_number[0x10]; 9263 9264 u8 reserved_at_60[0x20]; 9265 9266 u8 table_type[0x8]; 9267 u8 reserved_at_88[0x18]; 9268 9269 u8 reserved_at_a0[0x20]; 9270 9271 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9272 }; 9273 9274 struct mlx5_ifc_create_flow_group_out_bits { 9275 u8 status[0x8]; 9276 u8 reserved_at_8[0x18]; 9277 9278 u8 syndrome[0x20]; 9279 9280 u8 reserved_at_40[0x8]; 9281 u8 group_id[0x18]; 9282 9283 u8 reserved_at_60[0x20]; 9284 }; 9285 9286 enum { 9287 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9288 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9289 }; 9290 9291 enum { 9292 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9293 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9294 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9295 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9296 }; 9297 9298 struct mlx5_ifc_create_flow_group_in_bits { 9299 u8 opcode[0x10]; 9300 u8 reserved_at_10[0x10]; 9301 9302 u8 reserved_at_20[0x10]; 9303 u8 op_mod[0x10]; 9304 9305 u8 other_vport[0x1]; 9306 u8 reserved_at_41[0xf]; 9307 u8 vport_number[0x10]; 9308 9309 u8 reserved_at_60[0x20]; 9310 9311 u8 table_type[0x8]; 9312 u8 reserved_at_88[0x4]; 9313 u8 group_type[0x4]; 9314 u8 reserved_at_90[0x10]; 9315 9316 u8 reserved_at_a0[0x8]; 9317 u8 table_id[0x18]; 9318 9319 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9320 9321 u8 reserved_at_c1[0x1f]; 9322 9323 u8 start_flow_index[0x20]; 9324 9325 u8 reserved_at_100[0x20]; 9326 9327 u8 end_flow_index[0x20]; 9328 9329 u8 reserved_at_140[0x10]; 9330 u8 match_definer_id[0x10]; 9331 9332 u8 reserved_at_160[0x80]; 9333 9334 u8 reserved_at_1e0[0x18]; 9335 u8 match_criteria_enable[0x8]; 9336 9337 struct mlx5_ifc_fte_match_param_bits match_criteria; 9338 9339 u8 reserved_at_1200[0xe00]; 9340 }; 9341 9342 struct mlx5_ifc_create_eq_out_bits { 9343 u8 status[0x8]; 9344 u8 reserved_at_8[0x18]; 9345 9346 u8 syndrome[0x20]; 9347 9348 u8 reserved_at_40[0x18]; 9349 u8 eq_number[0x8]; 9350 9351 u8 reserved_at_60[0x20]; 9352 }; 9353 9354 struct mlx5_ifc_create_eq_in_bits { 9355 u8 opcode[0x10]; 9356 u8 uid[0x10]; 9357 9358 u8 reserved_at_20[0x10]; 9359 u8 op_mod[0x10]; 9360 9361 u8 reserved_at_40[0x40]; 9362 9363 struct mlx5_ifc_eqc_bits eq_context_entry; 9364 9365 u8 reserved_at_280[0x40]; 9366 9367 u8 event_bitmask[4][0x40]; 9368 9369 u8 reserved_at_3c0[0x4c0]; 9370 9371 u8 pas[][0x40]; 9372 }; 9373 9374 struct mlx5_ifc_create_dct_out_bits { 9375 u8 status[0x8]; 9376 u8 reserved_at_8[0x18]; 9377 9378 u8 syndrome[0x20]; 9379 9380 u8 reserved_at_40[0x8]; 9381 u8 dctn[0x18]; 9382 9383 u8 ece[0x20]; 9384 }; 9385 9386 struct mlx5_ifc_create_dct_in_bits { 9387 u8 opcode[0x10]; 9388 u8 uid[0x10]; 9389 9390 u8 reserved_at_20[0x10]; 9391 u8 op_mod[0x10]; 9392 9393 u8 reserved_at_40[0x40]; 9394 9395 struct mlx5_ifc_dctc_bits dct_context_entry; 9396 9397 u8 reserved_at_280[0x180]; 9398 }; 9399 9400 struct mlx5_ifc_create_cq_out_bits { 9401 u8 status[0x8]; 9402 u8 reserved_at_8[0x18]; 9403 9404 u8 syndrome[0x20]; 9405 9406 u8 reserved_at_40[0x8]; 9407 u8 cqn[0x18]; 9408 9409 u8 reserved_at_60[0x20]; 9410 }; 9411 9412 struct mlx5_ifc_create_cq_in_bits { 9413 u8 opcode[0x10]; 9414 u8 uid[0x10]; 9415 9416 u8 reserved_at_20[0x10]; 9417 u8 op_mod[0x10]; 9418 9419 u8 reserved_at_40[0x40]; 9420 9421 struct mlx5_ifc_cqc_bits cq_context; 9422 9423 u8 reserved_at_280[0x60]; 9424 9425 u8 cq_umem_valid[0x1]; 9426 u8 reserved_at_2e1[0x59f]; 9427 9428 u8 pas[][0x40]; 9429 }; 9430 9431 struct mlx5_ifc_config_int_moderation_out_bits { 9432 u8 status[0x8]; 9433 u8 reserved_at_8[0x18]; 9434 9435 u8 syndrome[0x20]; 9436 9437 u8 reserved_at_40[0x4]; 9438 u8 min_delay[0xc]; 9439 u8 int_vector[0x10]; 9440 9441 u8 reserved_at_60[0x20]; 9442 }; 9443 9444 enum { 9445 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9446 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9447 }; 9448 9449 struct mlx5_ifc_config_int_moderation_in_bits { 9450 u8 opcode[0x10]; 9451 u8 reserved_at_10[0x10]; 9452 9453 u8 reserved_at_20[0x10]; 9454 u8 op_mod[0x10]; 9455 9456 u8 reserved_at_40[0x4]; 9457 u8 min_delay[0xc]; 9458 u8 int_vector[0x10]; 9459 9460 u8 reserved_at_60[0x20]; 9461 }; 9462 9463 struct mlx5_ifc_attach_to_mcg_out_bits { 9464 u8 status[0x8]; 9465 u8 reserved_at_8[0x18]; 9466 9467 u8 syndrome[0x20]; 9468 9469 u8 reserved_at_40[0x40]; 9470 }; 9471 9472 struct mlx5_ifc_attach_to_mcg_in_bits { 9473 u8 opcode[0x10]; 9474 u8 uid[0x10]; 9475 9476 u8 reserved_at_20[0x10]; 9477 u8 op_mod[0x10]; 9478 9479 u8 reserved_at_40[0x8]; 9480 u8 qpn[0x18]; 9481 9482 u8 reserved_at_60[0x20]; 9483 9484 u8 multicast_gid[16][0x8]; 9485 }; 9486 9487 struct mlx5_ifc_arm_xrq_out_bits { 9488 u8 status[0x8]; 9489 u8 reserved_at_8[0x18]; 9490 9491 u8 syndrome[0x20]; 9492 9493 u8 reserved_at_40[0x40]; 9494 }; 9495 9496 struct mlx5_ifc_arm_xrq_in_bits { 9497 u8 opcode[0x10]; 9498 u8 reserved_at_10[0x10]; 9499 9500 u8 reserved_at_20[0x10]; 9501 u8 op_mod[0x10]; 9502 9503 u8 reserved_at_40[0x8]; 9504 u8 xrqn[0x18]; 9505 9506 u8 reserved_at_60[0x10]; 9507 u8 lwm[0x10]; 9508 }; 9509 9510 struct mlx5_ifc_arm_xrc_srq_out_bits { 9511 u8 status[0x8]; 9512 u8 reserved_at_8[0x18]; 9513 9514 u8 syndrome[0x20]; 9515 9516 u8 reserved_at_40[0x40]; 9517 }; 9518 9519 enum { 9520 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9521 }; 9522 9523 struct mlx5_ifc_arm_xrc_srq_in_bits { 9524 u8 opcode[0x10]; 9525 u8 uid[0x10]; 9526 9527 u8 reserved_at_20[0x10]; 9528 u8 op_mod[0x10]; 9529 9530 u8 reserved_at_40[0x8]; 9531 u8 xrc_srqn[0x18]; 9532 9533 u8 reserved_at_60[0x10]; 9534 u8 lwm[0x10]; 9535 }; 9536 9537 struct mlx5_ifc_arm_rq_out_bits { 9538 u8 status[0x8]; 9539 u8 reserved_at_8[0x18]; 9540 9541 u8 syndrome[0x20]; 9542 9543 u8 reserved_at_40[0x40]; 9544 }; 9545 9546 enum { 9547 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9548 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9549 }; 9550 9551 struct mlx5_ifc_arm_rq_in_bits { 9552 u8 opcode[0x10]; 9553 u8 uid[0x10]; 9554 9555 u8 reserved_at_20[0x10]; 9556 u8 op_mod[0x10]; 9557 9558 u8 reserved_at_40[0x8]; 9559 u8 srq_number[0x18]; 9560 9561 u8 reserved_at_60[0x10]; 9562 u8 lwm[0x10]; 9563 }; 9564 9565 struct mlx5_ifc_arm_dct_out_bits { 9566 u8 status[0x8]; 9567 u8 reserved_at_8[0x18]; 9568 9569 u8 syndrome[0x20]; 9570 9571 u8 reserved_at_40[0x40]; 9572 }; 9573 9574 struct mlx5_ifc_arm_dct_in_bits { 9575 u8 opcode[0x10]; 9576 u8 reserved_at_10[0x10]; 9577 9578 u8 reserved_at_20[0x10]; 9579 u8 op_mod[0x10]; 9580 9581 u8 reserved_at_40[0x8]; 9582 u8 dct_number[0x18]; 9583 9584 u8 reserved_at_60[0x20]; 9585 }; 9586 9587 struct mlx5_ifc_alloc_xrcd_out_bits { 9588 u8 status[0x8]; 9589 u8 reserved_at_8[0x18]; 9590 9591 u8 syndrome[0x20]; 9592 9593 u8 reserved_at_40[0x8]; 9594 u8 xrcd[0x18]; 9595 9596 u8 reserved_at_60[0x20]; 9597 }; 9598 9599 struct mlx5_ifc_alloc_xrcd_in_bits { 9600 u8 opcode[0x10]; 9601 u8 uid[0x10]; 9602 9603 u8 reserved_at_20[0x10]; 9604 u8 op_mod[0x10]; 9605 9606 u8 reserved_at_40[0x40]; 9607 }; 9608 9609 struct mlx5_ifc_alloc_uar_out_bits { 9610 u8 status[0x8]; 9611 u8 reserved_at_8[0x18]; 9612 9613 u8 syndrome[0x20]; 9614 9615 u8 reserved_at_40[0x8]; 9616 u8 uar[0x18]; 9617 9618 u8 reserved_at_60[0x20]; 9619 }; 9620 9621 struct mlx5_ifc_alloc_uar_in_bits { 9622 u8 opcode[0x10]; 9623 u8 uid[0x10]; 9624 9625 u8 reserved_at_20[0x10]; 9626 u8 op_mod[0x10]; 9627 9628 u8 reserved_at_40[0x40]; 9629 }; 9630 9631 struct mlx5_ifc_alloc_transport_domain_out_bits { 9632 u8 status[0x8]; 9633 u8 reserved_at_8[0x18]; 9634 9635 u8 syndrome[0x20]; 9636 9637 u8 reserved_at_40[0x8]; 9638 u8 transport_domain[0x18]; 9639 9640 u8 reserved_at_60[0x20]; 9641 }; 9642 9643 struct mlx5_ifc_alloc_transport_domain_in_bits { 9644 u8 opcode[0x10]; 9645 u8 uid[0x10]; 9646 9647 u8 reserved_at_20[0x10]; 9648 u8 op_mod[0x10]; 9649 9650 u8 reserved_at_40[0x40]; 9651 }; 9652 9653 struct mlx5_ifc_alloc_q_counter_out_bits { 9654 u8 status[0x8]; 9655 u8 reserved_at_8[0x18]; 9656 9657 u8 syndrome[0x20]; 9658 9659 u8 reserved_at_40[0x18]; 9660 u8 counter_set_id[0x8]; 9661 9662 u8 reserved_at_60[0x20]; 9663 }; 9664 9665 struct mlx5_ifc_alloc_q_counter_in_bits { 9666 u8 opcode[0x10]; 9667 u8 uid[0x10]; 9668 9669 u8 reserved_at_20[0x10]; 9670 u8 op_mod[0x10]; 9671 9672 u8 reserved_at_40[0x40]; 9673 }; 9674 9675 struct mlx5_ifc_alloc_pd_out_bits { 9676 u8 status[0x8]; 9677 u8 reserved_at_8[0x18]; 9678 9679 u8 syndrome[0x20]; 9680 9681 u8 reserved_at_40[0x8]; 9682 u8 pd[0x18]; 9683 9684 u8 reserved_at_60[0x20]; 9685 }; 9686 9687 struct mlx5_ifc_alloc_pd_in_bits { 9688 u8 opcode[0x10]; 9689 u8 uid[0x10]; 9690 9691 u8 reserved_at_20[0x10]; 9692 u8 op_mod[0x10]; 9693 9694 u8 reserved_at_40[0x40]; 9695 }; 9696 9697 struct mlx5_ifc_alloc_flow_counter_out_bits { 9698 u8 status[0x8]; 9699 u8 reserved_at_8[0x18]; 9700 9701 u8 syndrome[0x20]; 9702 9703 u8 flow_counter_id[0x20]; 9704 9705 u8 reserved_at_60[0x20]; 9706 }; 9707 9708 struct mlx5_ifc_alloc_flow_counter_in_bits { 9709 u8 opcode[0x10]; 9710 u8 reserved_at_10[0x10]; 9711 9712 u8 reserved_at_20[0x10]; 9713 u8 op_mod[0x10]; 9714 9715 u8 reserved_at_40[0x33]; 9716 u8 flow_counter_bulk_log_size[0x5]; 9717 u8 flow_counter_bulk[0x8]; 9718 }; 9719 9720 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9721 u8 status[0x8]; 9722 u8 reserved_at_8[0x18]; 9723 9724 u8 syndrome[0x20]; 9725 9726 u8 reserved_at_40[0x40]; 9727 }; 9728 9729 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9730 u8 opcode[0x10]; 9731 u8 reserved_at_10[0x10]; 9732 9733 u8 reserved_at_20[0x10]; 9734 u8 op_mod[0x10]; 9735 9736 u8 reserved_at_40[0x20]; 9737 9738 u8 reserved_at_60[0x10]; 9739 u8 vxlan_udp_port[0x10]; 9740 }; 9741 9742 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9743 u8 status[0x8]; 9744 u8 reserved_at_8[0x18]; 9745 9746 u8 syndrome[0x20]; 9747 9748 u8 reserved_at_40[0x40]; 9749 }; 9750 9751 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9752 u8 rate_limit[0x20]; 9753 9754 u8 burst_upper_bound[0x20]; 9755 9756 u8 reserved_at_40[0x10]; 9757 u8 typical_packet_size[0x10]; 9758 9759 u8 reserved_at_60[0x120]; 9760 }; 9761 9762 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9763 u8 opcode[0x10]; 9764 u8 uid[0x10]; 9765 9766 u8 reserved_at_20[0x10]; 9767 u8 op_mod[0x10]; 9768 9769 u8 reserved_at_40[0x10]; 9770 u8 rate_limit_index[0x10]; 9771 9772 u8 reserved_at_60[0x20]; 9773 9774 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9775 }; 9776 9777 struct mlx5_ifc_access_register_out_bits { 9778 u8 status[0x8]; 9779 u8 reserved_at_8[0x18]; 9780 9781 u8 syndrome[0x20]; 9782 9783 u8 reserved_at_40[0x40]; 9784 9785 u8 register_data[][0x20]; 9786 }; 9787 9788 enum { 9789 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9790 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9791 }; 9792 9793 struct mlx5_ifc_access_register_in_bits { 9794 u8 opcode[0x10]; 9795 u8 reserved_at_10[0x10]; 9796 9797 u8 reserved_at_20[0x10]; 9798 u8 op_mod[0x10]; 9799 9800 u8 reserved_at_40[0x10]; 9801 u8 register_id[0x10]; 9802 9803 u8 argument[0x20]; 9804 9805 u8 register_data[][0x20]; 9806 }; 9807 9808 struct mlx5_ifc_sltp_reg_bits { 9809 u8 status[0x4]; 9810 u8 version[0x4]; 9811 u8 local_port[0x8]; 9812 u8 pnat[0x2]; 9813 u8 reserved_at_12[0x2]; 9814 u8 lane[0x4]; 9815 u8 reserved_at_18[0x8]; 9816 9817 u8 reserved_at_20[0x20]; 9818 9819 u8 reserved_at_40[0x7]; 9820 u8 polarity[0x1]; 9821 u8 ob_tap0[0x8]; 9822 u8 ob_tap1[0x8]; 9823 u8 ob_tap2[0x8]; 9824 9825 u8 reserved_at_60[0xc]; 9826 u8 ob_preemp_mode[0x4]; 9827 u8 ob_reg[0x8]; 9828 u8 ob_bias[0x8]; 9829 9830 u8 reserved_at_80[0x20]; 9831 }; 9832 9833 struct mlx5_ifc_slrg_reg_bits { 9834 u8 status[0x4]; 9835 u8 version[0x4]; 9836 u8 local_port[0x8]; 9837 u8 pnat[0x2]; 9838 u8 reserved_at_12[0x2]; 9839 u8 lane[0x4]; 9840 u8 reserved_at_18[0x8]; 9841 9842 u8 time_to_link_up[0x10]; 9843 u8 reserved_at_30[0xc]; 9844 u8 grade_lane_speed[0x4]; 9845 9846 u8 grade_version[0x8]; 9847 u8 grade[0x18]; 9848 9849 u8 reserved_at_60[0x4]; 9850 u8 height_grade_type[0x4]; 9851 u8 height_grade[0x18]; 9852 9853 u8 height_dz[0x10]; 9854 u8 height_dv[0x10]; 9855 9856 u8 reserved_at_a0[0x10]; 9857 u8 height_sigma[0x10]; 9858 9859 u8 reserved_at_c0[0x20]; 9860 9861 u8 reserved_at_e0[0x4]; 9862 u8 phase_grade_type[0x4]; 9863 u8 phase_grade[0x18]; 9864 9865 u8 reserved_at_100[0x8]; 9866 u8 phase_eo_pos[0x8]; 9867 u8 reserved_at_110[0x8]; 9868 u8 phase_eo_neg[0x8]; 9869 9870 u8 ffe_set_tested[0x10]; 9871 u8 test_errors_per_lane[0x10]; 9872 }; 9873 9874 struct mlx5_ifc_pvlc_reg_bits { 9875 u8 reserved_at_0[0x8]; 9876 u8 local_port[0x8]; 9877 u8 reserved_at_10[0x10]; 9878 9879 u8 reserved_at_20[0x1c]; 9880 u8 vl_hw_cap[0x4]; 9881 9882 u8 reserved_at_40[0x1c]; 9883 u8 vl_admin[0x4]; 9884 9885 u8 reserved_at_60[0x1c]; 9886 u8 vl_operational[0x4]; 9887 }; 9888 9889 struct mlx5_ifc_pude_reg_bits { 9890 u8 swid[0x8]; 9891 u8 local_port[0x8]; 9892 u8 reserved_at_10[0x4]; 9893 u8 admin_status[0x4]; 9894 u8 reserved_at_18[0x4]; 9895 u8 oper_status[0x4]; 9896 9897 u8 reserved_at_20[0x60]; 9898 }; 9899 9900 struct mlx5_ifc_ptys_reg_bits { 9901 u8 reserved_at_0[0x1]; 9902 u8 an_disable_admin[0x1]; 9903 u8 an_disable_cap[0x1]; 9904 u8 reserved_at_3[0x5]; 9905 u8 local_port[0x8]; 9906 u8 reserved_at_10[0x8]; 9907 u8 plane_ind[0x4]; 9908 u8 reserved_at_1c[0x1]; 9909 u8 proto_mask[0x3]; 9910 9911 u8 an_status[0x4]; 9912 u8 reserved_at_24[0xc]; 9913 u8 data_rate_oper[0x10]; 9914 9915 u8 ext_eth_proto_capability[0x20]; 9916 9917 u8 eth_proto_capability[0x20]; 9918 9919 u8 ib_link_width_capability[0x10]; 9920 u8 ib_proto_capability[0x10]; 9921 9922 u8 ext_eth_proto_admin[0x20]; 9923 9924 u8 eth_proto_admin[0x20]; 9925 9926 u8 ib_link_width_admin[0x10]; 9927 u8 ib_proto_admin[0x10]; 9928 9929 u8 ext_eth_proto_oper[0x20]; 9930 9931 u8 eth_proto_oper[0x20]; 9932 9933 u8 ib_link_width_oper[0x10]; 9934 u8 ib_proto_oper[0x10]; 9935 9936 u8 reserved_at_160[0x1c]; 9937 u8 connector_type[0x4]; 9938 9939 u8 eth_proto_lp_advertise[0x20]; 9940 9941 u8 reserved_at_1a0[0x60]; 9942 }; 9943 9944 struct mlx5_ifc_mlcr_reg_bits { 9945 u8 reserved_at_0[0x8]; 9946 u8 local_port[0x8]; 9947 u8 reserved_at_10[0x20]; 9948 9949 u8 beacon_duration[0x10]; 9950 u8 reserved_at_40[0x10]; 9951 9952 u8 beacon_remain[0x10]; 9953 }; 9954 9955 struct mlx5_ifc_ptas_reg_bits { 9956 u8 reserved_at_0[0x20]; 9957 9958 u8 algorithm_options[0x10]; 9959 u8 reserved_at_30[0x4]; 9960 u8 repetitions_mode[0x4]; 9961 u8 num_of_repetitions[0x8]; 9962 9963 u8 grade_version[0x8]; 9964 u8 height_grade_type[0x4]; 9965 u8 phase_grade_type[0x4]; 9966 u8 height_grade_weight[0x8]; 9967 u8 phase_grade_weight[0x8]; 9968 9969 u8 gisim_measure_bits[0x10]; 9970 u8 adaptive_tap_measure_bits[0x10]; 9971 9972 u8 ber_bath_high_error_threshold[0x10]; 9973 u8 ber_bath_mid_error_threshold[0x10]; 9974 9975 u8 ber_bath_low_error_threshold[0x10]; 9976 u8 one_ratio_high_threshold[0x10]; 9977 9978 u8 one_ratio_high_mid_threshold[0x10]; 9979 u8 one_ratio_low_mid_threshold[0x10]; 9980 9981 u8 one_ratio_low_threshold[0x10]; 9982 u8 ndeo_error_threshold[0x10]; 9983 9984 u8 mixer_offset_step_size[0x10]; 9985 u8 reserved_at_110[0x8]; 9986 u8 mix90_phase_for_voltage_bath[0x8]; 9987 9988 u8 mixer_offset_start[0x10]; 9989 u8 mixer_offset_end[0x10]; 9990 9991 u8 reserved_at_140[0x15]; 9992 u8 ber_test_time[0xb]; 9993 }; 9994 9995 struct mlx5_ifc_pspa_reg_bits { 9996 u8 swid[0x8]; 9997 u8 local_port[0x8]; 9998 u8 sub_port[0x8]; 9999 u8 reserved_at_18[0x8]; 10000 10001 u8 reserved_at_20[0x20]; 10002 }; 10003 10004 struct mlx5_ifc_pqdr_reg_bits { 10005 u8 reserved_at_0[0x8]; 10006 u8 local_port[0x8]; 10007 u8 reserved_at_10[0x5]; 10008 u8 prio[0x3]; 10009 u8 reserved_at_18[0x6]; 10010 u8 mode[0x2]; 10011 10012 u8 reserved_at_20[0x20]; 10013 10014 u8 reserved_at_40[0x10]; 10015 u8 min_threshold[0x10]; 10016 10017 u8 reserved_at_60[0x10]; 10018 u8 max_threshold[0x10]; 10019 10020 u8 reserved_at_80[0x10]; 10021 u8 mark_probability_denominator[0x10]; 10022 10023 u8 reserved_at_a0[0x60]; 10024 }; 10025 10026 struct mlx5_ifc_ppsc_reg_bits { 10027 u8 reserved_at_0[0x8]; 10028 u8 local_port[0x8]; 10029 u8 reserved_at_10[0x10]; 10030 10031 u8 reserved_at_20[0x60]; 10032 10033 u8 reserved_at_80[0x1c]; 10034 u8 wrps_admin[0x4]; 10035 10036 u8 reserved_at_a0[0x1c]; 10037 u8 wrps_status[0x4]; 10038 10039 u8 reserved_at_c0[0x8]; 10040 u8 up_threshold[0x8]; 10041 u8 reserved_at_d0[0x8]; 10042 u8 down_threshold[0x8]; 10043 10044 u8 reserved_at_e0[0x20]; 10045 10046 u8 reserved_at_100[0x1c]; 10047 u8 srps_admin[0x4]; 10048 10049 u8 reserved_at_120[0x1c]; 10050 u8 srps_status[0x4]; 10051 10052 u8 reserved_at_140[0x40]; 10053 }; 10054 10055 struct mlx5_ifc_pplr_reg_bits { 10056 u8 reserved_at_0[0x8]; 10057 u8 local_port[0x8]; 10058 u8 reserved_at_10[0x10]; 10059 10060 u8 reserved_at_20[0x8]; 10061 u8 lb_cap[0x8]; 10062 u8 reserved_at_30[0x8]; 10063 u8 lb_en[0x8]; 10064 }; 10065 10066 struct mlx5_ifc_pplm_reg_bits { 10067 u8 reserved_at_0[0x8]; 10068 u8 local_port[0x8]; 10069 u8 reserved_at_10[0x10]; 10070 10071 u8 reserved_at_20[0x20]; 10072 10073 u8 port_profile_mode[0x8]; 10074 u8 static_port_profile[0x8]; 10075 u8 active_port_profile[0x8]; 10076 u8 reserved_at_58[0x8]; 10077 10078 u8 retransmission_active[0x8]; 10079 u8 fec_mode_active[0x18]; 10080 10081 u8 rs_fec_correction_bypass_cap[0x4]; 10082 u8 reserved_at_84[0x8]; 10083 u8 fec_override_cap_56g[0x4]; 10084 u8 fec_override_cap_100g[0x4]; 10085 u8 fec_override_cap_50g[0x4]; 10086 u8 fec_override_cap_25g[0x4]; 10087 u8 fec_override_cap_10g_40g[0x4]; 10088 10089 u8 rs_fec_correction_bypass_admin[0x4]; 10090 u8 reserved_at_a4[0x8]; 10091 u8 fec_override_admin_56g[0x4]; 10092 u8 fec_override_admin_100g[0x4]; 10093 u8 fec_override_admin_50g[0x4]; 10094 u8 fec_override_admin_25g[0x4]; 10095 u8 fec_override_admin_10g_40g[0x4]; 10096 10097 u8 fec_override_cap_400g_8x[0x10]; 10098 u8 fec_override_cap_200g_4x[0x10]; 10099 10100 u8 fec_override_cap_100g_2x[0x10]; 10101 u8 fec_override_cap_50g_1x[0x10]; 10102 10103 u8 fec_override_admin_400g_8x[0x10]; 10104 u8 fec_override_admin_200g_4x[0x10]; 10105 10106 u8 fec_override_admin_100g_2x[0x10]; 10107 u8 fec_override_admin_50g_1x[0x10]; 10108 10109 u8 fec_override_cap_800g_8x[0x10]; 10110 u8 fec_override_cap_400g_4x[0x10]; 10111 10112 u8 fec_override_cap_200g_2x[0x10]; 10113 u8 fec_override_cap_100g_1x[0x10]; 10114 10115 u8 reserved_at_180[0xa0]; 10116 10117 u8 fec_override_admin_800g_8x[0x10]; 10118 u8 fec_override_admin_400g_4x[0x10]; 10119 10120 u8 fec_override_admin_200g_2x[0x10]; 10121 u8 fec_override_admin_100g_1x[0x10]; 10122 10123 u8 reserved_at_260[0x20]; 10124 }; 10125 10126 struct mlx5_ifc_ppcnt_reg_bits { 10127 u8 swid[0x8]; 10128 u8 local_port[0x8]; 10129 u8 pnat[0x2]; 10130 u8 reserved_at_12[0x8]; 10131 u8 grp[0x6]; 10132 10133 u8 clr[0x1]; 10134 u8 reserved_at_21[0x13]; 10135 u8 plane_ind[0x4]; 10136 u8 reserved_at_38[0x3]; 10137 u8 prio_tc[0x5]; 10138 10139 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10140 }; 10141 10142 struct mlx5_ifc_mpein_reg_bits { 10143 u8 reserved_at_0[0x2]; 10144 u8 depth[0x6]; 10145 u8 pcie_index[0x8]; 10146 u8 node[0x8]; 10147 u8 reserved_at_18[0x8]; 10148 10149 u8 capability_mask[0x20]; 10150 10151 u8 reserved_at_40[0x8]; 10152 u8 link_width_enabled[0x8]; 10153 u8 link_speed_enabled[0x10]; 10154 10155 u8 lane0_physical_position[0x8]; 10156 u8 link_width_active[0x8]; 10157 u8 link_speed_active[0x10]; 10158 10159 u8 num_of_pfs[0x10]; 10160 u8 num_of_vfs[0x10]; 10161 10162 u8 bdf0[0x10]; 10163 u8 reserved_at_b0[0x10]; 10164 10165 u8 max_read_request_size[0x4]; 10166 u8 max_payload_size[0x4]; 10167 u8 reserved_at_c8[0x5]; 10168 u8 pwr_status[0x3]; 10169 u8 port_type[0x4]; 10170 u8 reserved_at_d4[0xb]; 10171 u8 lane_reversal[0x1]; 10172 10173 u8 reserved_at_e0[0x14]; 10174 u8 pci_power[0xc]; 10175 10176 u8 reserved_at_100[0x20]; 10177 10178 u8 device_status[0x10]; 10179 u8 port_state[0x8]; 10180 u8 reserved_at_138[0x8]; 10181 10182 u8 reserved_at_140[0x10]; 10183 u8 receiver_detect_result[0x10]; 10184 10185 u8 reserved_at_160[0x20]; 10186 }; 10187 10188 struct mlx5_ifc_mpcnt_reg_bits { 10189 u8 reserved_at_0[0x8]; 10190 u8 pcie_index[0x8]; 10191 u8 reserved_at_10[0xa]; 10192 u8 grp[0x6]; 10193 10194 u8 clr[0x1]; 10195 u8 reserved_at_21[0x1f]; 10196 10197 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 10198 }; 10199 10200 struct mlx5_ifc_ppad_reg_bits { 10201 u8 reserved_at_0[0x3]; 10202 u8 single_mac[0x1]; 10203 u8 reserved_at_4[0x4]; 10204 u8 local_port[0x8]; 10205 u8 mac_47_32[0x10]; 10206 10207 u8 mac_31_0[0x20]; 10208 10209 u8 reserved_at_40[0x40]; 10210 }; 10211 10212 struct mlx5_ifc_pmtu_reg_bits { 10213 u8 reserved_at_0[0x8]; 10214 u8 local_port[0x8]; 10215 u8 reserved_at_10[0x10]; 10216 10217 u8 max_mtu[0x10]; 10218 u8 reserved_at_30[0x10]; 10219 10220 u8 admin_mtu[0x10]; 10221 u8 reserved_at_50[0x10]; 10222 10223 u8 oper_mtu[0x10]; 10224 u8 reserved_at_70[0x10]; 10225 }; 10226 10227 struct mlx5_ifc_pmpr_reg_bits { 10228 u8 reserved_at_0[0x8]; 10229 u8 module[0x8]; 10230 u8 reserved_at_10[0x10]; 10231 10232 u8 reserved_at_20[0x18]; 10233 u8 attenuation_5g[0x8]; 10234 10235 u8 reserved_at_40[0x18]; 10236 u8 attenuation_7g[0x8]; 10237 10238 u8 reserved_at_60[0x18]; 10239 u8 attenuation_12g[0x8]; 10240 }; 10241 10242 struct mlx5_ifc_pmpe_reg_bits { 10243 u8 reserved_at_0[0x8]; 10244 u8 module[0x8]; 10245 u8 reserved_at_10[0xc]; 10246 u8 module_status[0x4]; 10247 10248 u8 reserved_at_20[0x60]; 10249 }; 10250 10251 struct mlx5_ifc_pmpc_reg_bits { 10252 u8 module_state_updated[32][0x8]; 10253 }; 10254 10255 struct mlx5_ifc_pmlpn_reg_bits { 10256 u8 reserved_at_0[0x4]; 10257 u8 mlpn_status[0x4]; 10258 u8 local_port[0x8]; 10259 u8 reserved_at_10[0x10]; 10260 10261 u8 e[0x1]; 10262 u8 reserved_at_21[0x1f]; 10263 }; 10264 10265 struct mlx5_ifc_pmlp_reg_bits { 10266 u8 rxtx[0x1]; 10267 u8 reserved_at_1[0x7]; 10268 u8 local_port[0x8]; 10269 u8 reserved_at_10[0x8]; 10270 u8 width[0x8]; 10271 10272 u8 lane0_module_mapping[0x20]; 10273 10274 u8 lane1_module_mapping[0x20]; 10275 10276 u8 lane2_module_mapping[0x20]; 10277 10278 u8 lane3_module_mapping[0x20]; 10279 10280 u8 reserved_at_a0[0x160]; 10281 }; 10282 10283 struct mlx5_ifc_pmaos_reg_bits { 10284 u8 reserved_at_0[0x8]; 10285 u8 module[0x8]; 10286 u8 reserved_at_10[0x4]; 10287 u8 admin_status[0x4]; 10288 u8 reserved_at_18[0x4]; 10289 u8 oper_status[0x4]; 10290 10291 u8 ase[0x1]; 10292 u8 ee[0x1]; 10293 u8 reserved_at_22[0x1c]; 10294 u8 e[0x2]; 10295 10296 u8 reserved_at_40[0x40]; 10297 }; 10298 10299 struct mlx5_ifc_plpc_reg_bits { 10300 u8 reserved_at_0[0x4]; 10301 u8 profile_id[0xc]; 10302 u8 reserved_at_10[0x4]; 10303 u8 proto_mask[0x4]; 10304 u8 reserved_at_18[0x8]; 10305 10306 u8 reserved_at_20[0x10]; 10307 u8 lane_speed[0x10]; 10308 10309 u8 reserved_at_40[0x17]; 10310 u8 lpbf[0x1]; 10311 u8 fec_mode_policy[0x8]; 10312 10313 u8 retransmission_capability[0x8]; 10314 u8 fec_mode_capability[0x18]; 10315 10316 u8 retransmission_support_admin[0x8]; 10317 u8 fec_mode_support_admin[0x18]; 10318 10319 u8 retransmission_request_admin[0x8]; 10320 u8 fec_mode_request_admin[0x18]; 10321 10322 u8 reserved_at_c0[0x80]; 10323 }; 10324 10325 struct mlx5_ifc_plib_reg_bits { 10326 u8 reserved_at_0[0x8]; 10327 u8 local_port[0x8]; 10328 u8 reserved_at_10[0x8]; 10329 u8 ib_port[0x8]; 10330 10331 u8 reserved_at_20[0x60]; 10332 }; 10333 10334 struct mlx5_ifc_plbf_reg_bits { 10335 u8 reserved_at_0[0x8]; 10336 u8 local_port[0x8]; 10337 u8 reserved_at_10[0xd]; 10338 u8 lbf_mode[0x3]; 10339 10340 u8 reserved_at_20[0x20]; 10341 }; 10342 10343 struct mlx5_ifc_pipg_reg_bits { 10344 u8 reserved_at_0[0x8]; 10345 u8 local_port[0x8]; 10346 u8 reserved_at_10[0x10]; 10347 10348 u8 dic[0x1]; 10349 u8 reserved_at_21[0x19]; 10350 u8 ipg[0x4]; 10351 u8 reserved_at_3e[0x2]; 10352 }; 10353 10354 struct mlx5_ifc_pifr_reg_bits { 10355 u8 reserved_at_0[0x8]; 10356 u8 local_port[0x8]; 10357 u8 reserved_at_10[0x10]; 10358 10359 u8 reserved_at_20[0xe0]; 10360 10361 u8 port_filter[8][0x20]; 10362 10363 u8 port_filter_update_en[8][0x20]; 10364 }; 10365 10366 struct mlx5_ifc_pfcc_reg_bits { 10367 u8 reserved_at_0[0x8]; 10368 u8 local_port[0x8]; 10369 u8 reserved_at_10[0xb]; 10370 u8 ppan_mask_n[0x1]; 10371 u8 minor_stall_mask[0x1]; 10372 u8 critical_stall_mask[0x1]; 10373 u8 reserved_at_1e[0x2]; 10374 10375 u8 ppan[0x4]; 10376 u8 reserved_at_24[0x4]; 10377 u8 prio_mask_tx[0x8]; 10378 u8 reserved_at_30[0x8]; 10379 u8 prio_mask_rx[0x8]; 10380 10381 u8 pptx[0x1]; 10382 u8 aptx[0x1]; 10383 u8 pptx_mask_n[0x1]; 10384 u8 reserved_at_43[0x5]; 10385 u8 pfctx[0x8]; 10386 u8 reserved_at_50[0x10]; 10387 10388 u8 pprx[0x1]; 10389 u8 aprx[0x1]; 10390 u8 pprx_mask_n[0x1]; 10391 u8 reserved_at_63[0x5]; 10392 u8 pfcrx[0x8]; 10393 u8 reserved_at_70[0x10]; 10394 10395 u8 device_stall_minor_watermark[0x10]; 10396 u8 device_stall_critical_watermark[0x10]; 10397 10398 u8 reserved_at_a0[0x60]; 10399 }; 10400 10401 struct mlx5_ifc_pelc_reg_bits { 10402 u8 op[0x4]; 10403 u8 reserved_at_4[0x4]; 10404 u8 local_port[0x8]; 10405 u8 reserved_at_10[0x10]; 10406 10407 u8 op_admin[0x8]; 10408 u8 op_capability[0x8]; 10409 u8 op_request[0x8]; 10410 u8 op_active[0x8]; 10411 10412 u8 admin[0x40]; 10413 10414 u8 capability[0x40]; 10415 10416 u8 request[0x40]; 10417 10418 u8 active[0x40]; 10419 10420 u8 reserved_at_140[0x80]; 10421 }; 10422 10423 struct mlx5_ifc_peir_reg_bits { 10424 u8 reserved_at_0[0x8]; 10425 u8 local_port[0x8]; 10426 u8 reserved_at_10[0x10]; 10427 10428 u8 reserved_at_20[0xc]; 10429 u8 error_count[0x4]; 10430 u8 reserved_at_30[0x10]; 10431 10432 u8 reserved_at_40[0xc]; 10433 u8 lane[0x4]; 10434 u8 reserved_at_50[0x8]; 10435 u8 error_type[0x8]; 10436 }; 10437 10438 struct mlx5_ifc_mpegc_reg_bits { 10439 u8 reserved_at_0[0x30]; 10440 u8 field_select[0x10]; 10441 10442 u8 tx_overflow_sense[0x1]; 10443 u8 mark_cqe[0x1]; 10444 u8 mark_cnp[0x1]; 10445 u8 reserved_at_43[0x1b]; 10446 u8 tx_lossy_overflow_oper[0x2]; 10447 10448 u8 reserved_at_60[0x100]; 10449 }; 10450 10451 struct mlx5_ifc_mpir_reg_bits { 10452 u8 sdm[0x1]; 10453 u8 reserved_at_1[0x1b]; 10454 u8 host_buses[0x4]; 10455 10456 u8 reserved_at_20[0x20]; 10457 10458 u8 local_port[0x8]; 10459 u8 reserved_at_28[0x18]; 10460 10461 u8 reserved_at_60[0x20]; 10462 }; 10463 10464 enum { 10465 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10466 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10467 }; 10468 10469 enum { 10470 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10471 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10472 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10473 }; 10474 10475 struct mlx5_ifc_mtutc_reg_bits { 10476 u8 reserved_at_0[0x5]; 10477 u8 freq_adj_units[0x3]; 10478 u8 reserved_at_8[0x3]; 10479 u8 log_max_freq_adjustment[0x5]; 10480 10481 u8 reserved_at_10[0xc]; 10482 u8 operation[0x4]; 10483 10484 u8 freq_adjustment[0x20]; 10485 10486 u8 reserved_at_40[0x40]; 10487 10488 u8 utc_sec[0x20]; 10489 10490 u8 reserved_at_a0[0x2]; 10491 u8 utc_nsec[0x1e]; 10492 10493 u8 time_adjustment[0x20]; 10494 }; 10495 10496 struct mlx5_ifc_pcam_enhanced_features_bits { 10497 u8 reserved_at_0[0x48]; 10498 u8 fec_100G_per_lane_in_pplm[0x1]; 10499 u8 reserved_at_49[0x1f]; 10500 u8 fec_50G_per_lane_in_pplm[0x1]; 10501 u8 reserved_at_69[0x4]; 10502 u8 rx_icrc_encapsulated_counter[0x1]; 10503 u8 reserved_at_6e[0x4]; 10504 u8 ptys_extended_ethernet[0x1]; 10505 u8 reserved_at_73[0x3]; 10506 u8 pfcc_mask[0x1]; 10507 u8 reserved_at_77[0x3]; 10508 u8 per_lane_error_counters[0x1]; 10509 u8 rx_buffer_fullness_counters[0x1]; 10510 u8 ptys_connector_type[0x1]; 10511 u8 reserved_at_7d[0x1]; 10512 u8 ppcnt_discard_group[0x1]; 10513 u8 ppcnt_statistical_group[0x1]; 10514 }; 10515 10516 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10517 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10518 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10519 10520 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10521 u8 pplm[0x1]; 10522 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10523 10524 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10525 u8 pbmc[0x1]; 10526 u8 pptb[0x1]; 10527 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10528 u8 ppcnt[0x1]; 10529 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10530 }; 10531 10532 struct mlx5_ifc_pcam_reg_bits { 10533 u8 reserved_at_0[0x8]; 10534 u8 feature_group[0x8]; 10535 u8 reserved_at_10[0x8]; 10536 u8 access_reg_group[0x8]; 10537 10538 u8 reserved_at_20[0x20]; 10539 10540 union { 10541 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10542 u8 reserved_at_0[0x80]; 10543 } port_access_reg_cap_mask; 10544 10545 u8 reserved_at_c0[0x80]; 10546 10547 union { 10548 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10549 u8 reserved_at_0[0x80]; 10550 } feature_cap_mask; 10551 10552 u8 reserved_at_1c0[0xc0]; 10553 }; 10554 10555 struct mlx5_ifc_mcam_enhanced_features_bits { 10556 u8 reserved_at_0[0x50]; 10557 u8 mtutc_freq_adj_units[0x1]; 10558 u8 mtutc_time_adjustment_extended_range[0x1]; 10559 u8 reserved_at_52[0xb]; 10560 u8 mcia_32dwords[0x1]; 10561 u8 out_pulse_duration_ns[0x1]; 10562 u8 npps_period[0x1]; 10563 u8 reserved_at_60[0xa]; 10564 u8 reset_state[0x1]; 10565 u8 ptpcyc2realtime_modify[0x1]; 10566 u8 reserved_at_6c[0x2]; 10567 u8 pci_status_and_power[0x1]; 10568 u8 reserved_at_6f[0x5]; 10569 u8 mark_tx_action_cnp[0x1]; 10570 u8 mark_tx_action_cqe[0x1]; 10571 u8 dynamic_tx_overflow[0x1]; 10572 u8 reserved_at_77[0x4]; 10573 u8 pcie_outbound_stalled[0x1]; 10574 u8 tx_overflow_buffer_pkt[0x1]; 10575 u8 mtpps_enh_out_per_adj[0x1]; 10576 u8 mtpps_fs[0x1]; 10577 u8 pcie_performance_group[0x1]; 10578 }; 10579 10580 struct mlx5_ifc_mcam_access_reg_bits { 10581 u8 reserved_at_0[0x1c]; 10582 u8 mcda[0x1]; 10583 u8 mcc[0x1]; 10584 u8 mcqi[0x1]; 10585 u8 mcqs[0x1]; 10586 10587 u8 regs_95_to_90[0x6]; 10588 u8 mpir[0x1]; 10589 u8 regs_88_to_87[0x2]; 10590 u8 mpegc[0x1]; 10591 u8 mtutc[0x1]; 10592 u8 regs_84_to_68[0x11]; 10593 u8 tracer_registers[0x4]; 10594 10595 u8 regs_63_to_46[0x12]; 10596 u8 mrtc[0x1]; 10597 u8 regs_44_to_41[0x4]; 10598 u8 mfrl[0x1]; 10599 u8 regs_39_to_32[0x8]; 10600 10601 u8 regs_31_to_11[0x15]; 10602 u8 mtmp[0x1]; 10603 u8 regs_9_to_0[0xa]; 10604 }; 10605 10606 struct mlx5_ifc_mcam_access_reg_bits1 { 10607 u8 regs_127_to_96[0x20]; 10608 10609 u8 regs_95_to_64[0x20]; 10610 10611 u8 regs_63_to_32[0x20]; 10612 10613 u8 regs_31_to_0[0x20]; 10614 }; 10615 10616 struct mlx5_ifc_mcam_access_reg_bits2 { 10617 u8 regs_127_to_99[0x1d]; 10618 u8 mirc[0x1]; 10619 u8 regs_97_to_96[0x2]; 10620 10621 u8 regs_95_to_87[0x09]; 10622 u8 synce_registers[0x2]; 10623 u8 regs_84_to_64[0x15]; 10624 10625 u8 regs_63_to_32[0x20]; 10626 10627 u8 regs_31_to_0[0x20]; 10628 }; 10629 10630 struct mlx5_ifc_mcam_access_reg_bits3 { 10631 u8 regs_127_to_96[0x20]; 10632 10633 u8 regs_95_to_64[0x20]; 10634 10635 u8 regs_63_to_32[0x20]; 10636 10637 u8 regs_31_to_2[0x1e]; 10638 u8 mtctr[0x1]; 10639 u8 mtptm[0x1]; 10640 }; 10641 10642 struct mlx5_ifc_mcam_reg_bits { 10643 u8 reserved_at_0[0x8]; 10644 u8 feature_group[0x8]; 10645 u8 reserved_at_10[0x8]; 10646 u8 access_reg_group[0x8]; 10647 10648 u8 reserved_at_20[0x20]; 10649 10650 union { 10651 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10652 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10653 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10654 struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; 10655 u8 reserved_at_0[0x80]; 10656 } mng_access_reg_cap_mask; 10657 10658 u8 reserved_at_c0[0x80]; 10659 10660 union { 10661 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10662 u8 reserved_at_0[0x80]; 10663 } mng_feature_cap_mask; 10664 10665 u8 reserved_at_1c0[0x80]; 10666 }; 10667 10668 struct mlx5_ifc_qcam_access_reg_cap_mask { 10669 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10670 u8 qpdpm[0x1]; 10671 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10672 u8 qdpm[0x1]; 10673 u8 qpts[0x1]; 10674 u8 qcap[0x1]; 10675 u8 qcam_access_reg_cap_mask_0[0x1]; 10676 }; 10677 10678 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10679 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10680 u8 qpts_trust_both[0x1]; 10681 }; 10682 10683 struct mlx5_ifc_qcam_reg_bits { 10684 u8 reserved_at_0[0x8]; 10685 u8 feature_group[0x8]; 10686 u8 reserved_at_10[0x8]; 10687 u8 access_reg_group[0x8]; 10688 u8 reserved_at_20[0x20]; 10689 10690 union { 10691 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10692 u8 reserved_at_0[0x80]; 10693 } qos_access_reg_cap_mask; 10694 10695 u8 reserved_at_c0[0x80]; 10696 10697 union { 10698 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10699 u8 reserved_at_0[0x80]; 10700 } qos_feature_cap_mask; 10701 10702 u8 reserved_at_1c0[0x80]; 10703 }; 10704 10705 struct mlx5_ifc_core_dump_reg_bits { 10706 u8 reserved_at_0[0x18]; 10707 u8 core_dump_type[0x8]; 10708 10709 u8 reserved_at_20[0x30]; 10710 u8 vhca_id[0x10]; 10711 10712 u8 reserved_at_60[0x8]; 10713 u8 qpn[0x18]; 10714 u8 reserved_at_80[0x180]; 10715 }; 10716 10717 struct mlx5_ifc_pcap_reg_bits { 10718 u8 reserved_at_0[0x8]; 10719 u8 local_port[0x8]; 10720 u8 reserved_at_10[0x10]; 10721 10722 u8 port_capability_mask[4][0x20]; 10723 }; 10724 10725 struct mlx5_ifc_paos_reg_bits { 10726 u8 swid[0x8]; 10727 u8 local_port[0x8]; 10728 u8 reserved_at_10[0x4]; 10729 u8 admin_status[0x4]; 10730 u8 reserved_at_18[0x4]; 10731 u8 oper_status[0x4]; 10732 10733 u8 ase[0x1]; 10734 u8 ee[0x1]; 10735 u8 reserved_at_22[0x1c]; 10736 u8 e[0x2]; 10737 10738 u8 reserved_at_40[0x40]; 10739 }; 10740 10741 struct mlx5_ifc_pamp_reg_bits { 10742 u8 reserved_at_0[0x8]; 10743 u8 opamp_group[0x8]; 10744 u8 reserved_at_10[0xc]; 10745 u8 opamp_group_type[0x4]; 10746 10747 u8 start_index[0x10]; 10748 u8 reserved_at_30[0x4]; 10749 u8 num_of_indices[0xc]; 10750 10751 u8 index_data[18][0x10]; 10752 }; 10753 10754 struct mlx5_ifc_pcmr_reg_bits { 10755 u8 reserved_at_0[0x8]; 10756 u8 local_port[0x8]; 10757 u8 reserved_at_10[0x10]; 10758 10759 u8 entropy_force_cap[0x1]; 10760 u8 entropy_calc_cap[0x1]; 10761 u8 entropy_gre_calc_cap[0x1]; 10762 u8 reserved_at_23[0xf]; 10763 u8 rx_ts_over_crc_cap[0x1]; 10764 u8 reserved_at_33[0xb]; 10765 u8 fcs_cap[0x1]; 10766 u8 reserved_at_3f[0x1]; 10767 10768 u8 entropy_force[0x1]; 10769 u8 entropy_calc[0x1]; 10770 u8 entropy_gre_calc[0x1]; 10771 u8 reserved_at_43[0xf]; 10772 u8 rx_ts_over_crc[0x1]; 10773 u8 reserved_at_53[0xb]; 10774 u8 fcs_chk[0x1]; 10775 u8 reserved_at_5f[0x1]; 10776 }; 10777 10778 struct mlx5_ifc_lane_2_module_mapping_bits { 10779 u8 reserved_at_0[0x4]; 10780 u8 rx_lane[0x4]; 10781 u8 reserved_at_8[0x4]; 10782 u8 tx_lane[0x4]; 10783 u8 reserved_at_10[0x8]; 10784 u8 module[0x8]; 10785 }; 10786 10787 struct mlx5_ifc_bufferx_reg_bits { 10788 u8 reserved_at_0[0x6]; 10789 u8 lossy[0x1]; 10790 u8 epsb[0x1]; 10791 u8 reserved_at_8[0x8]; 10792 u8 size[0x10]; 10793 10794 u8 xoff_threshold[0x10]; 10795 u8 xon_threshold[0x10]; 10796 }; 10797 10798 struct mlx5_ifc_set_node_in_bits { 10799 u8 node_description[64][0x8]; 10800 }; 10801 10802 struct mlx5_ifc_register_power_settings_bits { 10803 u8 reserved_at_0[0x18]; 10804 u8 power_settings_level[0x8]; 10805 10806 u8 reserved_at_20[0x60]; 10807 }; 10808 10809 struct mlx5_ifc_register_host_endianness_bits { 10810 u8 he[0x1]; 10811 u8 reserved_at_1[0x1f]; 10812 10813 u8 reserved_at_20[0x60]; 10814 }; 10815 10816 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10817 u8 reserved_at_0[0x20]; 10818 10819 u8 mkey[0x20]; 10820 10821 u8 addressh_63_32[0x20]; 10822 10823 u8 addressl_31_0[0x20]; 10824 }; 10825 10826 struct mlx5_ifc_ud_adrs_vector_bits { 10827 u8 dc_key[0x40]; 10828 10829 u8 ext[0x1]; 10830 u8 reserved_at_41[0x7]; 10831 u8 destination_qp_dct[0x18]; 10832 10833 u8 static_rate[0x4]; 10834 u8 sl_eth_prio[0x4]; 10835 u8 fl[0x1]; 10836 u8 mlid[0x7]; 10837 u8 rlid_udp_sport[0x10]; 10838 10839 u8 reserved_at_80[0x20]; 10840 10841 u8 rmac_47_16[0x20]; 10842 10843 u8 rmac_15_0[0x10]; 10844 u8 tclass[0x8]; 10845 u8 hop_limit[0x8]; 10846 10847 u8 reserved_at_e0[0x1]; 10848 u8 grh[0x1]; 10849 u8 reserved_at_e2[0x2]; 10850 u8 src_addr_index[0x8]; 10851 u8 flow_label[0x14]; 10852 10853 u8 rgid_rip[16][0x8]; 10854 }; 10855 10856 struct mlx5_ifc_pages_req_event_bits { 10857 u8 reserved_at_0[0x10]; 10858 u8 function_id[0x10]; 10859 10860 u8 num_pages[0x20]; 10861 10862 u8 reserved_at_40[0xa0]; 10863 }; 10864 10865 struct mlx5_ifc_eqe_bits { 10866 u8 reserved_at_0[0x8]; 10867 u8 event_type[0x8]; 10868 u8 reserved_at_10[0x8]; 10869 u8 event_sub_type[0x8]; 10870 10871 u8 reserved_at_20[0xe0]; 10872 10873 union mlx5_ifc_event_auto_bits event_data; 10874 10875 u8 reserved_at_1e0[0x10]; 10876 u8 signature[0x8]; 10877 u8 reserved_at_1f8[0x7]; 10878 u8 owner[0x1]; 10879 }; 10880 10881 enum { 10882 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10883 }; 10884 10885 struct mlx5_ifc_cmd_queue_entry_bits { 10886 u8 type[0x8]; 10887 u8 reserved_at_8[0x18]; 10888 10889 u8 input_length[0x20]; 10890 10891 u8 input_mailbox_pointer_63_32[0x20]; 10892 10893 u8 input_mailbox_pointer_31_9[0x17]; 10894 u8 reserved_at_77[0x9]; 10895 10896 u8 command_input_inline_data[16][0x8]; 10897 10898 u8 command_output_inline_data[16][0x8]; 10899 10900 u8 output_mailbox_pointer_63_32[0x20]; 10901 10902 u8 output_mailbox_pointer_31_9[0x17]; 10903 u8 reserved_at_1b7[0x9]; 10904 10905 u8 output_length[0x20]; 10906 10907 u8 token[0x8]; 10908 u8 signature[0x8]; 10909 u8 reserved_at_1f0[0x8]; 10910 u8 status[0x7]; 10911 u8 ownership[0x1]; 10912 }; 10913 10914 struct mlx5_ifc_cmd_out_bits { 10915 u8 status[0x8]; 10916 u8 reserved_at_8[0x18]; 10917 10918 u8 syndrome[0x20]; 10919 10920 u8 command_output[0x20]; 10921 }; 10922 10923 struct mlx5_ifc_cmd_in_bits { 10924 u8 opcode[0x10]; 10925 u8 reserved_at_10[0x10]; 10926 10927 u8 reserved_at_20[0x10]; 10928 u8 op_mod[0x10]; 10929 10930 u8 command[][0x20]; 10931 }; 10932 10933 struct mlx5_ifc_cmd_if_box_bits { 10934 u8 mailbox_data[512][0x8]; 10935 10936 u8 reserved_at_1000[0x180]; 10937 10938 u8 next_pointer_63_32[0x20]; 10939 10940 u8 next_pointer_31_10[0x16]; 10941 u8 reserved_at_11b6[0xa]; 10942 10943 u8 block_number[0x20]; 10944 10945 u8 reserved_at_11e0[0x8]; 10946 u8 token[0x8]; 10947 u8 ctrl_signature[0x8]; 10948 u8 signature[0x8]; 10949 }; 10950 10951 struct mlx5_ifc_mtt_bits { 10952 u8 ptag_63_32[0x20]; 10953 10954 u8 ptag_31_8[0x18]; 10955 u8 reserved_at_38[0x6]; 10956 u8 wr_en[0x1]; 10957 u8 rd_en[0x1]; 10958 }; 10959 10960 struct mlx5_ifc_query_wol_rol_out_bits { 10961 u8 status[0x8]; 10962 u8 reserved_at_8[0x18]; 10963 10964 u8 syndrome[0x20]; 10965 10966 u8 reserved_at_40[0x10]; 10967 u8 rol_mode[0x8]; 10968 u8 wol_mode[0x8]; 10969 10970 u8 reserved_at_60[0x20]; 10971 }; 10972 10973 struct mlx5_ifc_query_wol_rol_in_bits { 10974 u8 opcode[0x10]; 10975 u8 reserved_at_10[0x10]; 10976 10977 u8 reserved_at_20[0x10]; 10978 u8 op_mod[0x10]; 10979 10980 u8 reserved_at_40[0x40]; 10981 }; 10982 10983 struct mlx5_ifc_set_wol_rol_out_bits { 10984 u8 status[0x8]; 10985 u8 reserved_at_8[0x18]; 10986 10987 u8 syndrome[0x20]; 10988 10989 u8 reserved_at_40[0x40]; 10990 }; 10991 10992 struct mlx5_ifc_set_wol_rol_in_bits { 10993 u8 opcode[0x10]; 10994 u8 reserved_at_10[0x10]; 10995 10996 u8 reserved_at_20[0x10]; 10997 u8 op_mod[0x10]; 10998 10999 u8 rol_mode_valid[0x1]; 11000 u8 wol_mode_valid[0x1]; 11001 u8 reserved_at_42[0xe]; 11002 u8 rol_mode[0x8]; 11003 u8 wol_mode[0x8]; 11004 11005 u8 reserved_at_60[0x20]; 11006 }; 11007 11008 enum { 11009 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 11010 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 11011 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 11012 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 11013 }; 11014 11015 enum { 11016 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 11017 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 11018 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 11019 }; 11020 11021 enum { 11022 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 11023 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 11024 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 11025 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 11026 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 11027 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 11028 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 11029 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 11030 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 11031 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 11032 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 11033 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 11034 }; 11035 11036 struct mlx5_ifc_initial_seg_bits { 11037 u8 fw_rev_minor[0x10]; 11038 u8 fw_rev_major[0x10]; 11039 11040 u8 cmd_interface_rev[0x10]; 11041 u8 fw_rev_subminor[0x10]; 11042 11043 u8 reserved_at_40[0x40]; 11044 11045 u8 cmdq_phy_addr_63_32[0x20]; 11046 11047 u8 cmdq_phy_addr_31_12[0x14]; 11048 u8 reserved_at_b4[0x2]; 11049 u8 nic_interface[0x2]; 11050 u8 log_cmdq_size[0x4]; 11051 u8 log_cmdq_stride[0x4]; 11052 11053 u8 command_doorbell_vector[0x20]; 11054 11055 u8 reserved_at_e0[0xf00]; 11056 11057 u8 initializing[0x1]; 11058 u8 reserved_at_fe1[0x4]; 11059 u8 nic_interface_supported[0x3]; 11060 u8 embedded_cpu[0x1]; 11061 u8 reserved_at_fe9[0x17]; 11062 11063 struct mlx5_ifc_health_buffer_bits health_buffer; 11064 11065 u8 no_dram_nic_offset[0x20]; 11066 11067 u8 reserved_at_1220[0x6e40]; 11068 11069 u8 reserved_at_8060[0x1f]; 11070 u8 clear_int[0x1]; 11071 11072 u8 health_syndrome[0x8]; 11073 u8 health_counter[0x18]; 11074 11075 u8 reserved_at_80a0[0x17fc0]; 11076 }; 11077 11078 struct mlx5_ifc_mtpps_reg_bits { 11079 u8 reserved_at_0[0xc]; 11080 u8 cap_number_of_pps_pins[0x4]; 11081 u8 reserved_at_10[0x4]; 11082 u8 cap_max_num_of_pps_in_pins[0x4]; 11083 u8 reserved_at_18[0x4]; 11084 u8 cap_max_num_of_pps_out_pins[0x4]; 11085 11086 u8 reserved_at_20[0x13]; 11087 u8 cap_log_min_npps_period[0x5]; 11088 u8 reserved_at_38[0x3]; 11089 u8 cap_log_min_out_pulse_duration_ns[0x5]; 11090 11091 u8 reserved_at_40[0x4]; 11092 u8 cap_pin_3_mode[0x4]; 11093 u8 reserved_at_48[0x4]; 11094 u8 cap_pin_2_mode[0x4]; 11095 u8 reserved_at_50[0x4]; 11096 u8 cap_pin_1_mode[0x4]; 11097 u8 reserved_at_58[0x4]; 11098 u8 cap_pin_0_mode[0x4]; 11099 11100 u8 reserved_at_60[0x4]; 11101 u8 cap_pin_7_mode[0x4]; 11102 u8 reserved_at_68[0x4]; 11103 u8 cap_pin_6_mode[0x4]; 11104 u8 reserved_at_70[0x4]; 11105 u8 cap_pin_5_mode[0x4]; 11106 u8 reserved_at_78[0x4]; 11107 u8 cap_pin_4_mode[0x4]; 11108 11109 u8 field_select[0x20]; 11110 u8 reserved_at_a0[0x20]; 11111 11112 u8 npps_period[0x40]; 11113 11114 u8 enable[0x1]; 11115 u8 reserved_at_101[0xb]; 11116 u8 pattern[0x4]; 11117 u8 reserved_at_110[0x4]; 11118 u8 pin_mode[0x4]; 11119 u8 pin[0x8]; 11120 11121 u8 reserved_at_120[0x2]; 11122 u8 out_pulse_duration_ns[0x1e]; 11123 11124 u8 time_stamp[0x40]; 11125 11126 u8 out_pulse_duration[0x10]; 11127 u8 out_periodic_adjustment[0x10]; 11128 u8 enhanced_out_periodic_adjustment[0x20]; 11129 11130 u8 reserved_at_1c0[0x20]; 11131 }; 11132 11133 struct mlx5_ifc_mtppse_reg_bits { 11134 u8 reserved_at_0[0x18]; 11135 u8 pin[0x8]; 11136 u8 event_arm[0x1]; 11137 u8 reserved_at_21[0x1b]; 11138 u8 event_generation_mode[0x4]; 11139 u8 reserved_at_40[0x40]; 11140 }; 11141 11142 struct mlx5_ifc_mcqs_reg_bits { 11143 u8 last_index_flag[0x1]; 11144 u8 reserved_at_1[0x7]; 11145 u8 fw_device[0x8]; 11146 u8 component_index[0x10]; 11147 11148 u8 reserved_at_20[0x10]; 11149 u8 identifier[0x10]; 11150 11151 u8 reserved_at_40[0x17]; 11152 u8 component_status[0x5]; 11153 u8 component_update_state[0x4]; 11154 11155 u8 last_update_state_changer_type[0x4]; 11156 u8 last_update_state_changer_host_id[0x4]; 11157 u8 reserved_at_68[0x18]; 11158 }; 11159 11160 struct mlx5_ifc_mcqi_cap_bits { 11161 u8 supported_info_bitmask[0x20]; 11162 11163 u8 component_size[0x20]; 11164 11165 u8 max_component_size[0x20]; 11166 11167 u8 log_mcda_word_size[0x4]; 11168 u8 reserved_at_64[0xc]; 11169 u8 mcda_max_write_size[0x10]; 11170 11171 u8 rd_en[0x1]; 11172 u8 reserved_at_81[0x1]; 11173 u8 match_chip_id[0x1]; 11174 u8 match_psid[0x1]; 11175 u8 check_user_timestamp[0x1]; 11176 u8 match_base_guid_mac[0x1]; 11177 u8 reserved_at_86[0x1a]; 11178 }; 11179 11180 struct mlx5_ifc_mcqi_version_bits { 11181 u8 reserved_at_0[0x2]; 11182 u8 build_time_valid[0x1]; 11183 u8 user_defined_time_valid[0x1]; 11184 u8 reserved_at_4[0x14]; 11185 u8 version_string_length[0x8]; 11186 11187 u8 version[0x20]; 11188 11189 u8 build_time[0x40]; 11190 11191 u8 user_defined_time[0x40]; 11192 11193 u8 build_tool_version[0x20]; 11194 11195 u8 reserved_at_e0[0x20]; 11196 11197 u8 version_string[92][0x8]; 11198 }; 11199 11200 struct mlx5_ifc_mcqi_activation_method_bits { 11201 u8 pending_server_ac_power_cycle[0x1]; 11202 u8 pending_server_dc_power_cycle[0x1]; 11203 u8 pending_server_reboot[0x1]; 11204 u8 pending_fw_reset[0x1]; 11205 u8 auto_activate[0x1]; 11206 u8 all_hosts_sync[0x1]; 11207 u8 device_hw_reset[0x1]; 11208 u8 reserved_at_7[0x19]; 11209 }; 11210 11211 union mlx5_ifc_mcqi_reg_data_bits { 11212 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 11213 struct mlx5_ifc_mcqi_version_bits mcqi_version; 11214 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 11215 }; 11216 11217 struct mlx5_ifc_mcqi_reg_bits { 11218 u8 read_pending_component[0x1]; 11219 u8 reserved_at_1[0xf]; 11220 u8 component_index[0x10]; 11221 11222 u8 reserved_at_20[0x20]; 11223 11224 u8 reserved_at_40[0x1b]; 11225 u8 info_type[0x5]; 11226 11227 u8 info_size[0x20]; 11228 11229 u8 offset[0x20]; 11230 11231 u8 reserved_at_a0[0x10]; 11232 u8 data_size[0x10]; 11233 11234 union mlx5_ifc_mcqi_reg_data_bits data[]; 11235 }; 11236 11237 struct mlx5_ifc_mcc_reg_bits { 11238 u8 reserved_at_0[0x4]; 11239 u8 time_elapsed_since_last_cmd[0xc]; 11240 u8 reserved_at_10[0x8]; 11241 u8 instruction[0x8]; 11242 11243 u8 reserved_at_20[0x10]; 11244 u8 component_index[0x10]; 11245 11246 u8 reserved_at_40[0x8]; 11247 u8 update_handle[0x18]; 11248 11249 u8 handle_owner_type[0x4]; 11250 u8 handle_owner_host_id[0x4]; 11251 u8 reserved_at_68[0x1]; 11252 u8 control_progress[0x7]; 11253 u8 error_code[0x8]; 11254 u8 reserved_at_78[0x4]; 11255 u8 control_state[0x4]; 11256 11257 u8 component_size[0x20]; 11258 11259 u8 reserved_at_a0[0x60]; 11260 }; 11261 11262 struct mlx5_ifc_mcda_reg_bits { 11263 u8 reserved_at_0[0x8]; 11264 u8 update_handle[0x18]; 11265 11266 u8 offset[0x20]; 11267 11268 u8 reserved_at_40[0x10]; 11269 u8 size[0x10]; 11270 11271 u8 reserved_at_60[0x20]; 11272 11273 u8 data[][0x20]; 11274 }; 11275 11276 enum { 11277 MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0, 11278 MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1, 11279 }; 11280 11281 enum { 11282 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11283 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11284 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11285 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11286 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11287 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11288 }; 11289 11290 enum { 11291 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11292 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11293 }; 11294 11295 enum { 11296 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11297 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11298 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11299 }; 11300 11301 struct mlx5_ifc_mfrl_reg_bits { 11302 u8 reserved_at_0[0x20]; 11303 11304 u8 reserved_at_20[0x2]; 11305 u8 pci_sync_for_fw_update_start[0x1]; 11306 u8 pci_sync_for_fw_update_resp[0x2]; 11307 u8 rst_type_sel[0x3]; 11308 u8 pci_reset_req_method[0x3]; 11309 u8 reserved_at_2b[0x1]; 11310 u8 reset_state[0x4]; 11311 u8 reset_type[0x8]; 11312 u8 reset_level[0x8]; 11313 }; 11314 11315 struct mlx5_ifc_mirc_reg_bits { 11316 u8 reserved_at_0[0x18]; 11317 u8 status_code[0x8]; 11318 11319 u8 reserved_at_20[0x20]; 11320 }; 11321 11322 struct mlx5_ifc_pddr_monitor_opcode_bits { 11323 u8 reserved_at_0[0x10]; 11324 u8 monitor_opcode[0x10]; 11325 }; 11326 11327 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11328 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11329 u8 reserved_at_0[0x20]; 11330 }; 11331 11332 enum { 11333 /* Monitor opcodes */ 11334 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11335 }; 11336 11337 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11338 u8 reserved_at_0[0x10]; 11339 u8 group_opcode[0x10]; 11340 11341 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11342 11343 u8 reserved_at_40[0x20]; 11344 11345 u8 status_message[59][0x20]; 11346 }; 11347 11348 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11349 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11350 u8 reserved_at_0[0x7c0]; 11351 }; 11352 11353 enum { 11354 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11355 }; 11356 11357 struct mlx5_ifc_pddr_reg_bits { 11358 u8 reserved_at_0[0x8]; 11359 u8 local_port[0x8]; 11360 u8 pnat[0x2]; 11361 u8 reserved_at_12[0xe]; 11362 11363 u8 reserved_at_20[0x18]; 11364 u8 page_select[0x8]; 11365 11366 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11367 }; 11368 11369 struct mlx5_ifc_mrtc_reg_bits { 11370 u8 time_synced[0x1]; 11371 u8 reserved_at_1[0x1f]; 11372 11373 u8 reserved_at_20[0x20]; 11374 11375 u8 time_h[0x20]; 11376 11377 u8 time_l[0x20]; 11378 }; 11379 11380 struct mlx5_ifc_mtcap_reg_bits { 11381 u8 reserved_at_0[0x19]; 11382 u8 sensor_count[0x7]; 11383 11384 u8 reserved_at_20[0x20]; 11385 11386 u8 sensor_map[0x40]; 11387 }; 11388 11389 struct mlx5_ifc_mtmp_reg_bits { 11390 u8 reserved_at_0[0x14]; 11391 u8 sensor_index[0xc]; 11392 11393 u8 reserved_at_20[0x10]; 11394 u8 temperature[0x10]; 11395 11396 u8 mte[0x1]; 11397 u8 mtr[0x1]; 11398 u8 reserved_at_42[0xe]; 11399 u8 max_temperature[0x10]; 11400 11401 u8 tee[0x2]; 11402 u8 reserved_at_62[0xe]; 11403 u8 temp_threshold_hi[0x10]; 11404 11405 u8 reserved_at_80[0x10]; 11406 u8 temp_threshold_lo[0x10]; 11407 11408 u8 reserved_at_a0[0x20]; 11409 11410 u8 sensor_name_hi[0x20]; 11411 u8 sensor_name_lo[0x20]; 11412 }; 11413 11414 struct mlx5_ifc_mtptm_reg_bits { 11415 u8 reserved_at_0[0x10]; 11416 u8 psta[0x1]; 11417 u8 reserved_at_11[0xf]; 11418 11419 u8 reserved_at_20[0x60]; 11420 }; 11421 11422 enum { 11423 MLX5_MTCTR_REQUEST_NOP = 0x0, 11424 MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, 11425 MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, 11426 MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, 11427 }; 11428 11429 struct mlx5_ifc_mtctr_reg_bits { 11430 u8 first_clock_timestamp_request[0x8]; 11431 u8 second_clock_timestamp_request[0x8]; 11432 u8 reserved_at_10[0x10]; 11433 11434 u8 first_clock_valid[0x1]; 11435 u8 second_clock_valid[0x1]; 11436 u8 reserved_at_22[0x1e]; 11437 11438 u8 first_clock_timestamp[0x40]; 11439 u8 second_clock_timestamp[0x40]; 11440 }; 11441 11442 union mlx5_ifc_ports_control_registers_document_bits { 11443 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11444 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11445 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11446 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11447 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11448 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11449 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11450 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11451 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11452 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11453 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11454 struct mlx5_ifc_paos_reg_bits paos_reg; 11455 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11456 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11457 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11458 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11459 struct mlx5_ifc_peir_reg_bits peir_reg; 11460 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11461 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11462 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11463 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11464 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11465 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11466 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11467 struct mlx5_ifc_plib_reg_bits plib_reg; 11468 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11469 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11470 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11471 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11472 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11473 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11474 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11475 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11476 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11477 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11478 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11479 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11480 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11481 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11482 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11483 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11484 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11485 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11486 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11487 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11488 struct mlx5_ifc_pude_reg_bits pude_reg; 11489 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11490 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11491 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11492 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11493 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11494 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11495 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11496 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11497 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11498 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11499 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11500 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11501 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11502 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11503 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11504 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11505 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11506 struct mlx5_ifc_mtptm_reg_bits mtptm_reg; 11507 struct mlx5_ifc_mtctr_reg_bits mtctr_reg; 11508 u8 reserved_at_0[0x60e0]; 11509 }; 11510 11511 union mlx5_ifc_debug_enhancements_document_bits { 11512 struct mlx5_ifc_health_buffer_bits health_buffer; 11513 u8 reserved_at_0[0x200]; 11514 }; 11515 11516 union mlx5_ifc_uplink_pci_interface_document_bits { 11517 struct mlx5_ifc_initial_seg_bits initial_seg; 11518 u8 reserved_at_0[0x20060]; 11519 }; 11520 11521 struct mlx5_ifc_set_flow_table_root_out_bits { 11522 u8 status[0x8]; 11523 u8 reserved_at_8[0x18]; 11524 11525 u8 syndrome[0x20]; 11526 11527 u8 reserved_at_40[0x40]; 11528 }; 11529 11530 struct mlx5_ifc_set_flow_table_root_in_bits { 11531 u8 opcode[0x10]; 11532 u8 reserved_at_10[0x10]; 11533 11534 u8 reserved_at_20[0x10]; 11535 u8 op_mod[0x10]; 11536 11537 u8 other_vport[0x1]; 11538 u8 reserved_at_41[0xf]; 11539 u8 vport_number[0x10]; 11540 11541 u8 reserved_at_60[0x20]; 11542 11543 u8 table_type[0x8]; 11544 u8 reserved_at_88[0x7]; 11545 u8 table_of_other_vport[0x1]; 11546 u8 table_vport_number[0x10]; 11547 11548 u8 reserved_at_a0[0x8]; 11549 u8 table_id[0x18]; 11550 11551 u8 reserved_at_c0[0x8]; 11552 u8 underlay_qpn[0x18]; 11553 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11554 u8 reserved_at_e1[0xf]; 11555 u8 table_eswitch_owner_vhca_id[0x10]; 11556 u8 reserved_at_100[0x100]; 11557 }; 11558 11559 enum { 11560 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11561 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11562 }; 11563 11564 struct mlx5_ifc_modify_flow_table_out_bits { 11565 u8 status[0x8]; 11566 u8 reserved_at_8[0x18]; 11567 11568 u8 syndrome[0x20]; 11569 11570 u8 reserved_at_40[0x40]; 11571 }; 11572 11573 struct mlx5_ifc_modify_flow_table_in_bits { 11574 u8 opcode[0x10]; 11575 u8 reserved_at_10[0x10]; 11576 11577 u8 reserved_at_20[0x10]; 11578 u8 op_mod[0x10]; 11579 11580 u8 other_vport[0x1]; 11581 u8 reserved_at_41[0xf]; 11582 u8 vport_number[0x10]; 11583 11584 u8 reserved_at_60[0x10]; 11585 u8 modify_field_select[0x10]; 11586 11587 u8 table_type[0x8]; 11588 u8 reserved_at_88[0x18]; 11589 11590 u8 reserved_at_a0[0x8]; 11591 u8 table_id[0x18]; 11592 11593 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11594 }; 11595 11596 struct mlx5_ifc_ets_tcn_config_reg_bits { 11597 u8 g[0x1]; 11598 u8 b[0x1]; 11599 u8 r[0x1]; 11600 u8 reserved_at_3[0x9]; 11601 u8 group[0x4]; 11602 u8 reserved_at_10[0x9]; 11603 u8 bw_allocation[0x7]; 11604 11605 u8 reserved_at_20[0xc]; 11606 u8 max_bw_units[0x4]; 11607 u8 reserved_at_30[0x8]; 11608 u8 max_bw_value[0x8]; 11609 }; 11610 11611 struct mlx5_ifc_ets_global_config_reg_bits { 11612 u8 reserved_at_0[0x2]; 11613 u8 r[0x1]; 11614 u8 reserved_at_3[0x1d]; 11615 11616 u8 reserved_at_20[0xc]; 11617 u8 max_bw_units[0x4]; 11618 u8 reserved_at_30[0x8]; 11619 u8 max_bw_value[0x8]; 11620 }; 11621 11622 struct mlx5_ifc_qetc_reg_bits { 11623 u8 reserved_at_0[0x8]; 11624 u8 port_number[0x8]; 11625 u8 reserved_at_10[0x30]; 11626 11627 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11628 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11629 }; 11630 11631 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11632 u8 e[0x1]; 11633 u8 reserved_at_01[0x0b]; 11634 u8 prio[0x04]; 11635 }; 11636 11637 struct mlx5_ifc_qpdpm_reg_bits { 11638 u8 reserved_at_0[0x8]; 11639 u8 local_port[0x8]; 11640 u8 reserved_at_10[0x10]; 11641 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11642 }; 11643 11644 struct mlx5_ifc_qpts_reg_bits { 11645 u8 reserved_at_0[0x8]; 11646 u8 local_port[0x8]; 11647 u8 reserved_at_10[0x2d]; 11648 u8 trust_state[0x3]; 11649 }; 11650 11651 struct mlx5_ifc_pptb_reg_bits { 11652 u8 reserved_at_0[0x2]; 11653 u8 mm[0x2]; 11654 u8 reserved_at_4[0x4]; 11655 u8 local_port[0x8]; 11656 u8 reserved_at_10[0x6]; 11657 u8 cm[0x1]; 11658 u8 um[0x1]; 11659 u8 pm[0x8]; 11660 11661 u8 prio_x_buff[0x20]; 11662 11663 u8 pm_msb[0x8]; 11664 u8 reserved_at_48[0x10]; 11665 u8 ctrl_buff[0x4]; 11666 u8 untagged_buff[0x4]; 11667 }; 11668 11669 struct mlx5_ifc_sbcam_reg_bits { 11670 u8 reserved_at_0[0x8]; 11671 u8 feature_group[0x8]; 11672 u8 reserved_at_10[0x8]; 11673 u8 access_reg_group[0x8]; 11674 11675 u8 reserved_at_20[0x20]; 11676 11677 u8 sb_access_reg_cap_mask[4][0x20]; 11678 11679 u8 reserved_at_c0[0x80]; 11680 11681 u8 sb_feature_cap_mask[4][0x20]; 11682 11683 u8 reserved_at_1c0[0x40]; 11684 11685 u8 cap_total_buffer_size[0x20]; 11686 11687 u8 cap_cell_size[0x10]; 11688 u8 cap_max_pg_buffers[0x8]; 11689 u8 cap_num_pool_supported[0x8]; 11690 11691 u8 reserved_at_240[0x8]; 11692 u8 cap_sbsr_stat_size[0x8]; 11693 u8 cap_max_tclass_data[0x8]; 11694 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11695 }; 11696 11697 struct mlx5_ifc_pbmc_reg_bits { 11698 u8 reserved_at_0[0x8]; 11699 u8 local_port[0x8]; 11700 u8 reserved_at_10[0x10]; 11701 11702 u8 xoff_timer_value[0x10]; 11703 u8 xoff_refresh[0x10]; 11704 11705 u8 reserved_at_40[0x9]; 11706 u8 fullness_threshold[0x7]; 11707 u8 port_buffer_size[0x10]; 11708 11709 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11710 11711 u8 reserved_at_2e0[0x80]; 11712 }; 11713 11714 struct mlx5_ifc_sbpr_reg_bits { 11715 u8 desc[0x1]; 11716 u8 snap[0x1]; 11717 u8 reserved_at_2[0x4]; 11718 u8 dir[0x2]; 11719 u8 reserved_at_8[0x14]; 11720 u8 pool[0x4]; 11721 11722 u8 infi_size[0x1]; 11723 u8 reserved_at_21[0x7]; 11724 u8 size[0x18]; 11725 11726 u8 reserved_at_40[0x1c]; 11727 u8 mode[0x4]; 11728 11729 u8 reserved_at_60[0x8]; 11730 u8 buff_occupancy[0x18]; 11731 11732 u8 clr[0x1]; 11733 u8 reserved_at_81[0x7]; 11734 u8 max_buff_occupancy[0x18]; 11735 11736 u8 reserved_at_a0[0x8]; 11737 u8 ext_buff_occupancy[0x18]; 11738 }; 11739 11740 struct mlx5_ifc_sbcm_reg_bits { 11741 u8 desc[0x1]; 11742 u8 snap[0x1]; 11743 u8 reserved_at_2[0x6]; 11744 u8 local_port[0x8]; 11745 u8 pnat[0x2]; 11746 u8 pg_buff[0x6]; 11747 u8 reserved_at_18[0x6]; 11748 u8 dir[0x2]; 11749 11750 u8 reserved_at_20[0x1f]; 11751 u8 exc[0x1]; 11752 11753 u8 reserved_at_40[0x40]; 11754 11755 u8 reserved_at_80[0x8]; 11756 u8 buff_occupancy[0x18]; 11757 11758 u8 clr[0x1]; 11759 u8 reserved_at_a1[0x7]; 11760 u8 max_buff_occupancy[0x18]; 11761 11762 u8 reserved_at_c0[0x8]; 11763 u8 min_buff[0x18]; 11764 11765 u8 infi_max[0x1]; 11766 u8 reserved_at_e1[0x7]; 11767 u8 max_buff[0x18]; 11768 11769 u8 reserved_at_100[0x20]; 11770 11771 u8 reserved_at_120[0x1c]; 11772 u8 pool[0x4]; 11773 }; 11774 11775 struct mlx5_ifc_qtct_reg_bits { 11776 u8 reserved_at_0[0x8]; 11777 u8 port_number[0x8]; 11778 u8 reserved_at_10[0xd]; 11779 u8 prio[0x3]; 11780 11781 u8 reserved_at_20[0x1d]; 11782 u8 tclass[0x3]; 11783 }; 11784 11785 struct mlx5_ifc_mcia_reg_bits { 11786 u8 l[0x1]; 11787 u8 reserved_at_1[0x7]; 11788 u8 module[0x8]; 11789 u8 reserved_at_10[0x8]; 11790 u8 status[0x8]; 11791 11792 u8 i2c_device_address[0x8]; 11793 u8 page_number[0x8]; 11794 u8 device_address[0x10]; 11795 11796 u8 reserved_at_40[0x10]; 11797 u8 size[0x10]; 11798 11799 u8 reserved_at_60[0x20]; 11800 11801 u8 dword_0[0x20]; 11802 u8 dword_1[0x20]; 11803 u8 dword_2[0x20]; 11804 u8 dword_3[0x20]; 11805 u8 dword_4[0x20]; 11806 u8 dword_5[0x20]; 11807 u8 dword_6[0x20]; 11808 u8 dword_7[0x20]; 11809 u8 dword_8[0x20]; 11810 u8 dword_9[0x20]; 11811 u8 dword_10[0x20]; 11812 u8 dword_11[0x20]; 11813 }; 11814 11815 struct mlx5_ifc_dcbx_param_bits { 11816 u8 dcbx_cee_cap[0x1]; 11817 u8 dcbx_ieee_cap[0x1]; 11818 u8 dcbx_standby_cap[0x1]; 11819 u8 reserved_at_3[0x5]; 11820 u8 port_number[0x8]; 11821 u8 reserved_at_10[0xa]; 11822 u8 max_application_table_size[6]; 11823 u8 reserved_at_20[0x15]; 11824 u8 version_oper[0x3]; 11825 u8 reserved_at_38[5]; 11826 u8 version_admin[0x3]; 11827 u8 willing_admin[0x1]; 11828 u8 reserved_at_41[0x3]; 11829 u8 pfc_cap_oper[0x4]; 11830 u8 reserved_at_48[0x4]; 11831 u8 pfc_cap_admin[0x4]; 11832 u8 reserved_at_50[0x4]; 11833 u8 num_of_tc_oper[0x4]; 11834 u8 reserved_at_58[0x4]; 11835 u8 num_of_tc_admin[0x4]; 11836 u8 remote_willing[0x1]; 11837 u8 reserved_at_61[3]; 11838 u8 remote_pfc_cap[4]; 11839 u8 reserved_at_68[0x14]; 11840 u8 remote_num_of_tc[0x4]; 11841 u8 reserved_at_80[0x18]; 11842 u8 error[0x8]; 11843 u8 reserved_at_a0[0x160]; 11844 }; 11845 11846 enum { 11847 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11848 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11849 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11850 }; 11851 11852 struct mlx5_ifc_lagc_bits { 11853 u8 fdb_selection_mode[0x1]; 11854 u8 reserved_at_1[0x14]; 11855 u8 port_select_mode[0x3]; 11856 u8 reserved_at_18[0x5]; 11857 u8 lag_state[0x3]; 11858 11859 u8 reserved_at_20[0xc]; 11860 u8 active_port[0x4]; 11861 u8 reserved_at_30[0x4]; 11862 u8 tx_remap_affinity_2[0x4]; 11863 u8 reserved_at_38[0x4]; 11864 u8 tx_remap_affinity_1[0x4]; 11865 }; 11866 11867 struct mlx5_ifc_create_lag_out_bits { 11868 u8 status[0x8]; 11869 u8 reserved_at_8[0x18]; 11870 11871 u8 syndrome[0x20]; 11872 11873 u8 reserved_at_40[0x40]; 11874 }; 11875 11876 struct mlx5_ifc_create_lag_in_bits { 11877 u8 opcode[0x10]; 11878 u8 reserved_at_10[0x10]; 11879 11880 u8 reserved_at_20[0x10]; 11881 u8 op_mod[0x10]; 11882 11883 struct mlx5_ifc_lagc_bits ctx; 11884 }; 11885 11886 struct mlx5_ifc_modify_lag_out_bits { 11887 u8 status[0x8]; 11888 u8 reserved_at_8[0x18]; 11889 11890 u8 syndrome[0x20]; 11891 11892 u8 reserved_at_40[0x40]; 11893 }; 11894 11895 struct mlx5_ifc_modify_lag_in_bits { 11896 u8 opcode[0x10]; 11897 u8 reserved_at_10[0x10]; 11898 11899 u8 reserved_at_20[0x10]; 11900 u8 op_mod[0x10]; 11901 11902 u8 reserved_at_40[0x20]; 11903 u8 field_select[0x20]; 11904 11905 struct mlx5_ifc_lagc_bits ctx; 11906 }; 11907 11908 struct mlx5_ifc_query_lag_out_bits { 11909 u8 status[0x8]; 11910 u8 reserved_at_8[0x18]; 11911 11912 u8 syndrome[0x20]; 11913 11914 struct mlx5_ifc_lagc_bits ctx; 11915 }; 11916 11917 struct mlx5_ifc_query_lag_in_bits { 11918 u8 opcode[0x10]; 11919 u8 reserved_at_10[0x10]; 11920 11921 u8 reserved_at_20[0x10]; 11922 u8 op_mod[0x10]; 11923 11924 u8 reserved_at_40[0x40]; 11925 }; 11926 11927 struct mlx5_ifc_destroy_lag_out_bits { 11928 u8 status[0x8]; 11929 u8 reserved_at_8[0x18]; 11930 11931 u8 syndrome[0x20]; 11932 11933 u8 reserved_at_40[0x40]; 11934 }; 11935 11936 struct mlx5_ifc_destroy_lag_in_bits { 11937 u8 opcode[0x10]; 11938 u8 reserved_at_10[0x10]; 11939 11940 u8 reserved_at_20[0x10]; 11941 u8 op_mod[0x10]; 11942 11943 u8 reserved_at_40[0x40]; 11944 }; 11945 11946 struct mlx5_ifc_create_vport_lag_out_bits { 11947 u8 status[0x8]; 11948 u8 reserved_at_8[0x18]; 11949 11950 u8 syndrome[0x20]; 11951 11952 u8 reserved_at_40[0x40]; 11953 }; 11954 11955 struct mlx5_ifc_create_vport_lag_in_bits { 11956 u8 opcode[0x10]; 11957 u8 reserved_at_10[0x10]; 11958 11959 u8 reserved_at_20[0x10]; 11960 u8 op_mod[0x10]; 11961 11962 u8 reserved_at_40[0x40]; 11963 }; 11964 11965 struct mlx5_ifc_destroy_vport_lag_out_bits { 11966 u8 status[0x8]; 11967 u8 reserved_at_8[0x18]; 11968 11969 u8 syndrome[0x20]; 11970 11971 u8 reserved_at_40[0x40]; 11972 }; 11973 11974 struct mlx5_ifc_destroy_vport_lag_in_bits { 11975 u8 opcode[0x10]; 11976 u8 reserved_at_10[0x10]; 11977 11978 u8 reserved_at_20[0x10]; 11979 u8 op_mod[0x10]; 11980 11981 u8 reserved_at_40[0x40]; 11982 }; 11983 11984 enum { 11985 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11986 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11987 }; 11988 11989 struct mlx5_ifc_modify_memic_in_bits { 11990 u8 opcode[0x10]; 11991 u8 uid[0x10]; 11992 11993 u8 reserved_at_20[0x10]; 11994 u8 op_mod[0x10]; 11995 11996 u8 reserved_at_40[0x20]; 11997 11998 u8 reserved_at_60[0x18]; 11999 u8 memic_operation_type[0x8]; 12000 12001 u8 memic_start_addr[0x40]; 12002 12003 u8 reserved_at_c0[0x140]; 12004 }; 12005 12006 struct mlx5_ifc_modify_memic_out_bits { 12007 u8 status[0x8]; 12008 u8 reserved_at_8[0x18]; 12009 12010 u8 syndrome[0x20]; 12011 12012 u8 reserved_at_40[0x40]; 12013 12014 u8 memic_operation_addr[0x40]; 12015 12016 u8 reserved_at_c0[0x140]; 12017 }; 12018 12019 struct mlx5_ifc_alloc_memic_in_bits { 12020 u8 opcode[0x10]; 12021 u8 reserved_at_10[0x10]; 12022 12023 u8 reserved_at_20[0x10]; 12024 u8 op_mod[0x10]; 12025 12026 u8 reserved_at_30[0x20]; 12027 12028 u8 reserved_at_40[0x18]; 12029 u8 log_memic_addr_alignment[0x8]; 12030 12031 u8 range_start_addr[0x40]; 12032 12033 u8 range_size[0x20]; 12034 12035 u8 memic_size[0x20]; 12036 }; 12037 12038 struct mlx5_ifc_alloc_memic_out_bits { 12039 u8 status[0x8]; 12040 u8 reserved_at_8[0x18]; 12041 12042 u8 syndrome[0x20]; 12043 12044 u8 memic_start_addr[0x40]; 12045 }; 12046 12047 struct mlx5_ifc_dealloc_memic_in_bits { 12048 u8 opcode[0x10]; 12049 u8 reserved_at_10[0x10]; 12050 12051 u8 reserved_at_20[0x10]; 12052 u8 op_mod[0x10]; 12053 12054 u8 reserved_at_40[0x40]; 12055 12056 u8 memic_start_addr[0x40]; 12057 12058 u8 memic_size[0x20]; 12059 12060 u8 reserved_at_e0[0x20]; 12061 }; 12062 12063 struct mlx5_ifc_dealloc_memic_out_bits { 12064 u8 status[0x8]; 12065 u8 reserved_at_8[0x18]; 12066 12067 u8 syndrome[0x20]; 12068 12069 u8 reserved_at_40[0x40]; 12070 }; 12071 12072 struct mlx5_ifc_umem_bits { 12073 u8 reserved_at_0[0x80]; 12074 12075 u8 ats[0x1]; 12076 u8 reserved_at_81[0x1a]; 12077 u8 log_page_size[0x5]; 12078 12079 u8 page_offset[0x20]; 12080 12081 u8 num_of_mtt[0x40]; 12082 12083 struct mlx5_ifc_mtt_bits mtt[]; 12084 }; 12085 12086 struct mlx5_ifc_uctx_bits { 12087 u8 cap[0x20]; 12088 12089 u8 reserved_at_20[0x160]; 12090 }; 12091 12092 struct mlx5_ifc_sw_icm_bits { 12093 u8 modify_field_select[0x40]; 12094 12095 u8 reserved_at_40[0x18]; 12096 u8 log_sw_icm_size[0x8]; 12097 12098 u8 reserved_at_60[0x20]; 12099 12100 u8 sw_icm_start_addr[0x40]; 12101 12102 u8 reserved_at_c0[0x140]; 12103 }; 12104 12105 struct mlx5_ifc_geneve_tlv_option_bits { 12106 u8 modify_field_select[0x40]; 12107 12108 u8 reserved_at_40[0x18]; 12109 u8 geneve_option_fte_index[0x8]; 12110 12111 u8 option_class[0x10]; 12112 u8 option_type[0x8]; 12113 u8 reserved_at_78[0x3]; 12114 u8 option_data_length[0x5]; 12115 12116 u8 reserved_at_80[0x180]; 12117 }; 12118 12119 struct mlx5_ifc_create_umem_in_bits { 12120 u8 opcode[0x10]; 12121 u8 uid[0x10]; 12122 12123 u8 reserved_at_20[0x10]; 12124 u8 op_mod[0x10]; 12125 12126 u8 reserved_at_40[0x40]; 12127 12128 struct mlx5_ifc_umem_bits umem; 12129 }; 12130 12131 struct mlx5_ifc_create_umem_out_bits { 12132 u8 status[0x8]; 12133 u8 reserved_at_8[0x18]; 12134 12135 u8 syndrome[0x20]; 12136 12137 u8 reserved_at_40[0x8]; 12138 u8 umem_id[0x18]; 12139 12140 u8 reserved_at_60[0x20]; 12141 }; 12142 12143 struct mlx5_ifc_destroy_umem_in_bits { 12144 u8 opcode[0x10]; 12145 u8 uid[0x10]; 12146 12147 u8 reserved_at_20[0x10]; 12148 u8 op_mod[0x10]; 12149 12150 u8 reserved_at_40[0x8]; 12151 u8 umem_id[0x18]; 12152 12153 u8 reserved_at_60[0x20]; 12154 }; 12155 12156 struct mlx5_ifc_destroy_umem_out_bits { 12157 u8 status[0x8]; 12158 u8 reserved_at_8[0x18]; 12159 12160 u8 syndrome[0x20]; 12161 12162 u8 reserved_at_40[0x40]; 12163 }; 12164 12165 struct mlx5_ifc_create_uctx_in_bits { 12166 u8 opcode[0x10]; 12167 u8 reserved_at_10[0x10]; 12168 12169 u8 reserved_at_20[0x10]; 12170 u8 op_mod[0x10]; 12171 12172 u8 reserved_at_40[0x40]; 12173 12174 struct mlx5_ifc_uctx_bits uctx; 12175 }; 12176 12177 struct mlx5_ifc_create_uctx_out_bits { 12178 u8 status[0x8]; 12179 u8 reserved_at_8[0x18]; 12180 12181 u8 syndrome[0x20]; 12182 12183 u8 reserved_at_40[0x10]; 12184 u8 uid[0x10]; 12185 12186 u8 reserved_at_60[0x20]; 12187 }; 12188 12189 struct mlx5_ifc_destroy_uctx_in_bits { 12190 u8 opcode[0x10]; 12191 u8 reserved_at_10[0x10]; 12192 12193 u8 reserved_at_20[0x10]; 12194 u8 op_mod[0x10]; 12195 12196 u8 reserved_at_40[0x10]; 12197 u8 uid[0x10]; 12198 12199 u8 reserved_at_60[0x20]; 12200 }; 12201 12202 struct mlx5_ifc_destroy_uctx_out_bits { 12203 u8 status[0x8]; 12204 u8 reserved_at_8[0x18]; 12205 12206 u8 syndrome[0x20]; 12207 12208 u8 reserved_at_40[0x40]; 12209 }; 12210 12211 struct mlx5_ifc_create_sw_icm_in_bits { 12212 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12213 struct mlx5_ifc_sw_icm_bits sw_icm; 12214 }; 12215 12216 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 12217 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12218 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 12219 }; 12220 12221 struct mlx5_ifc_mtrc_string_db_param_bits { 12222 u8 string_db_base_address[0x20]; 12223 12224 u8 reserved_at_20[0x8]; 12225 u8 string_db_size[0x18]; 12226 }; 12227 12228 struct mlx5_ifc_mtrc_cap_bits { 12229 u8 trace_owner[0x1]; 12230 u8 trace_to_memory[0x1]; 12231 u8 reserved_at_2[0x4]; 12232 u8 trc_ver[0x2]; 12233 u8 reserved_at_8[0x14]; 12234 u8 num_string_db[0x4]; 12235 12236 u8 first_string_trace[0x8]; 12237 u8 num_string_trace[0x8]; 12238 u8 reserved_at_30[0x28]; 12239 12240 u8 log_max_trace_buffer_size[0x8]; 12241 12242 u8 reserved_at_60[0x20]; 12243 12244 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 12245 12246 u8 reserved_at_280[0x180]; 12247 }; 12248 12249 struct mlx5_ifc_mtrc_conf_bits { 12250 u8 reserved_at_0[0x1c]; 12251 u8 trace_mode[0x4]; 12252 u8 reserved_at_20[0x18]; 12253 u8 log_trace_buffer_size[0x8]; 12254 u8 trace_mkey[0x20]; 12255 u8 reserved_at_60[0x3a0]; 12256 }; 12257 12258 struct mlx5_ifc_mtrc_stdb_bits { 12259 u8 string_db_index[0x4]; 12260 u8 reserved_at_4[0x4]; 12261 u8 read_size[0x18]; 12262 u8 start_offset[0x20]; 12263 u8 string_db_data[]; 12264 }; 12265 12266 struct mlx5_ifc_mtrc_ctrl_bits { 12267 u8 trace_status[0x2]; 12268 u8 reserved_at_2[0x2]; 12269 u8 arm_event[0x1]; 12270 u8 reserved_at_5[0xb]; 12271 u8 modify_field_select[0x10]; 12272 u8 reserved_at_20[0x2b]; 12273 u8 current_timestamp52_32[0x15]; 12274 u8 current_timestamp31_0[0x20]; 12275 u8 reserved_at_80[0x180]; 12276 }; 12277 12278 struct mlx5_ifc_host_params_context_bits { 12279 u8 host_number[0x8]; 12280 u8 reserved_at_8[0x7]; 12281 u8 host_pf_disabled[0x1]; 12282 u8 host_num_of_vfs[0x10]; 12283 12284 u8 host_total_vfs[0x10]; 12285 u8 host_pci_bus[0x10]; 12286 12287 u8 reserved_at_40[0x10]; 12288 u8 host_pci_device[0x10]; 12289 12290 u8 reserved_at_60[0x10]; 12291 u8 host_pci_function[0x10]; 12292 12293 u8 reserved_at_80[0x180]; 12294 }; 12295 12296 struct mlx5_ifc_query_esw_functions_in_bits { 12297 u8 opcode[0x10]; 12298 u8 reserved_at_10[0x10]; 12299 12300 u8 reserved_at_20[0x10]; 12301 u8 op_mod[0x10]; 12302 12303 u8 reserved_at_40[0x40]; 12304 }; 12305 12306 struct mlx5_ifc_query_esw_functions_out_bits { 12307 u8 status[0x8]; 12308 u8 reserved_at_8[0x18]; 12309 12310 u8 syndrome[0x20]; 12311 12312 u8 reserved_at_40[0x40]; 12313 12314 struct mlx5_ifc_host_params_context_bits host_params_context; 12315 12316 u8 reserved_at_280[0x180]; 12317 u8 host_sf_enable[][0x40]; 12318 }; 12319 12320 struct mlx5_ifc_sf_partition_bits { 12321 u8 reserved_at_0[0x10]; 12322 u8 log_num_sf[0x8]; 12323 u8 log_sf_bar_size[0x8]; 12324 }; 12325 12326 struct mlx5_ifc_query_sf_partitions_out_bits { 12327 u8 status[0x8]; 12328 u8 reserved_at_8[0x18]; 12329 12330 u8 syndrome[0x20]; 12331 12332 u8 reserved_at_40[0x18]; 12333 u8 num_sf_partitions[0x8]; 12334 12335 u8 reserved_at_60[0x20]; 12336 12337 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12338 }; 12339 12340 struct mlx5_ifc_query_sf_partitions_in_bits { 12341 u8 opcode[0x10]; 12342 u8 reserved_at_10[0x10]; 12343 12344 u8 reserved_at_20[0x10]; 12345 u8 op_mod[0x10]; 12346 12347 u8 reserved_at_40[0x40]; 12348 }; 12349 12350 struct mlx5_ifc_dealloc_sf_out_bits { 12351 u8 status[0x8]; 12352 u8 reserved_at_8[0x18]; 12353 12354 u8 syndrome[0x20]; 12355 12356 u8 reserved_at_40[0x40]; 12357 }; 12358 12359 struct mlx5_ifc_dealloc_sf_in_bits { 12360 u8 opcode[0x10]; 12361 u8 reserved_at_10[0x10]; 12362 12363 u8 reserved_at_20[0x10]; 12364 u8 op_mod[0x10]; 12365 12366 u8 reserved_at_40[0x10]; 12367 u8 function_id[0x10]; 12368 12369 u8 reserved_at_60[0x20]; 12370 }; 12371 12372 struct mlx5_ifc_alloc_sf_out_bits { 12373 u8 status[0x8]; 12374 u8 reserved_at_8[0x18]; 12375 12376 u8 syndrome[0x20]; 12377 12378 u8 reserved_at_40[0x40]; 12379 }; 12380 12381 struct mlx5_ifc_alloc_sf_in_bits { 12382 u8 opcode[0x10]; 12383 u8 reserved_at_10[0x10]; 12384 12385 u8 reserved_at_20[0x10]; 12386 u8 op_mod[0x10]; 12387 12388 u8 reserved_at_40[0x10]; 12389 u8 function_id[0x10]; 12390 12391 u8 reserved_at_60[0x20]; 12392 }; 12393 12394 struct mlx5_ifc_affiliated_event_header_bits { 12395 u8 reserved_at_0[0x10]; 12396 u8 obj_type[0x10]; 12397 12398 u8 obj_id[0x20]; 12399 }; 12400 12401 enum { 12402 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 12403 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 12404 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 12405 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 12406 }; 12407 12408 enum { 12409 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12410 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12411 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12412 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12413 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12414 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12415 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12416 }; 12417 12418 enum { 12419 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12420 }; 12421 12422 enum { 12423 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12424 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12425 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12426 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12427 }; 12428 12429 enum { 12430 MLX5_IPSEC_ASO_MODE = 0x0, 12431 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12432 MLX5_IPSEC_ASO_INC_SN = 0x2, 12433 }; 12434 12435 enum { 12436 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12437 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12438 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12439 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12440 }; 12441 12442 struct mlx5_ifc_ipsec_aso_bits { 12443 u8 valid[0x1]; 12444 u8 reserved_at_201[0x1]; 12445 u8 mode[0x2]; 12446 u8 window_sz[0x2]; 12447 u8 soft_lft_arm[0x1]; 12448 u8 hard_lft_arm[0x1]; 12449 u8 remove_flow_enable[0x1]; 12450 u8 esn_event_arm[0x1]; 12451 u8 reserved_at_20a[0x16]; 12452 12453 u8 remove_flow_pkt_cnt[0x20]; 12454 12455 u8 remove_flow_soft_lft[0x20]; 12456 12457 u8 reserved_at_260[0x80]; 12458 12459 u8 mode_parameter[0x20]; 12460 12461 u8 replay_protection_window[0x100]; 12462 }; 12463 12464 struct mlx5_ifc_ipsec_obj_bits { 12465 u8 modify_field_select[0x40]; 12466 u8 full_offload[0x1]; 12467 u8 reserved_at_41[0x1]; 12468 u8 esn_en[0x1]; 12469 u8 esn_overlap[0x1]; 12470 u8 reserved_at_44[0x2]; 12471 u8 icv_length[0x2]; 12472 u8 reserved_at_48[0x4]; 12473 u8 aso_return_reg[0x4]; 12474 u8 reserved_at_50[0x10]; 12475 12476 u8 esn_msb[0x20]; 12477 12478 u8 reserved_at_80[0x8]; 12479 u8 dekn[0x18]; 12480 12481 u8 salt[0x20]; 12482 12483 u8 implicit_iv[0x40]; 12484 12485 u8 reserved_at_100[0x8]; 12486 u8 ipsec_aso_access_pd[0x18]; 12487 u8 reserved_at_120[0xe0]; 12488 12489 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12490 }; 12491 12492 struct mlx5_ifc_create_ipsec_obj_in_bits { 12493 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12494 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12495 }; 12496 12497 enum { 12498 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12499 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12500 }; 12501 12502 struct mlx5_ifc_query_ipsec_obj_out_bits { 12503 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12504 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12505 }; 12506 12507 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12508 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12509 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12510 }; 12511 12512 enum { 12513 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12514 }; 12515 12516 enum { 12517 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12518 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12519 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12520 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12521 }; 12522 12523 #define MLX5_MACSEC_ASO_INC_SN 0x2 12524 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12525 12526 struct mlx5_ifc_macsec_aso_bits { 12527 u8 valid[0x1]; 12528 u8 reserved_at_1[0x1]; 12529 u8 mode[0x2]; 12530 u8 window_size[0x2]; 12531 u8 soft_lifetime_arm[0x1]; 12532 u8 hard_lifetime_arm[0x1]; 12533 u8 remove_flow_enable[0x1]; 12534 u8 epn_event_arm[0x1]; 12535 u8 reserved_at_a[0x16]; 12536 12537 u8 remove_flow_packet_count[0x20]; 12538 12539 u8 remove_flow_soft_lifetime[0x20]; 12540 12541 u8 reserved_at_60[0x80]; 12542 12543 u8 mode_parameter[0x20]; 12544 12545 u8 replay_protection_window[8][0x20]; 12546 }; 12547 12548 struct mlx5_ifc_macsec_offload_obj_bits { 12549 u8 modify_field_select[0x40]; 12550 12551 u8 confidentiality_en[0x1]; 12552 u8 reserved_at_41[0x1]; 12553 u8 epn_en[0x1]; 12554 u8 epn_overlap[0x1]; 12555 u8 reserved_at_44[0x2]; 12556 u8 confidentiality_offset[0x2]; 12557 u8 reserved_at_48[0x4]; 12558 u8 aso_return_reg[0x4]; 12559 u8 reserved_at_50[0x10]; 12560 12561 u8 epn_msb[0x20]; 12562 12563 u8 reserved_at_80[0x8]; 12564 u8 dekn[0x18]; 12565 12566 u8 reserved_at_a0[0x20]; 12567 12568 u8 sci[0x40]; 12569 12570 u8 reserved_at_100[0x8]; 12571 u8 macsec_aso_access_pd[0x18]; 12572 12573 u8 reserved_at_120[0x60]; 12574 12575 u8 salt[3][0x20]; 12576 12577 u8 reserved_at_1e0[0x20]; 12578 12579 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12580 }; 12581 12582 struct mlx5_ifc_create_macsec_obj_in_bits { 12583 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12584 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12585 }; 12586 12587 struct mlx5_ifc_modify_macsec_obj_in_bits { 12588 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12589 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12590 }; 12591 12592 enum { 12593 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12594 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12595 }; 12596 12597 struct mlx5_ifc_query_macsec_obj_out_bits { 12598 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12599 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12600 }; 12601 12602 struct mlx5_ifc_wrapped_dek_bits { 12603 u8 gcm_iv[0x60]; 12604 12605 u8 reserved_at_60[0x20]; 12606 12607 u8 const0[0x1]; 12608 u8 key_size[0x1]; 12609 u8 reserved_at_82[0x2]; 12610 u8 key2_invalid[0x1]; 12611 u8 reserved_at_85[0x3]; 12612 u8 pd[0x18]; 12613 12614 u8 key_purpose[0x5]; 12615 u8 reserved_at_a5[0x13]; 12616 u8 kek_id[0x8]; 12617 12618 u8 reserved_at_c0[0x40]; 12619 12620 u8 key1[0x8][0x20]; 12621 12622 u8 key2[0x8][0x20]; 12623 12624 u8 reserved_at_300[0x40]; 12625 12626 u8 const1[0x1]; 12627 u8 reserved_at_341[0x1f]; 12628 12629 u8 reserved_at_360[0x20]; 12630 12631 u8 auth_tag[0x80]; 12632 }; 12633 12634 struct mlx5_ifc_encryption_key_obj_bits { 12635 u8 modify_field_select[0x40]; 12636 12637 u8 state[0x8]; 12638 u8 sw_wrapped[0x1]; 12639 u8 reserved_at_49[0xb]; 12640 u8 key_size[0x4]; 12641 u8 reserved_at_58[0x4]; 12642 u8 key_purpose[0x4]; 12643 12644 u8 reserved_at_60[0x8]; 12645 u8 pd[0x18]; 12646 12647 u8 reserved_at_80[0x100]; 12648 12649 u8 opaque[0x40]; 12650 12651 u8 reserved_at_1c0[0x40]; 12652 12653 u8 key[8][0x80]; 12654 12655 u8 sw_wrapped_dek[8][0x80]; 12656 12657 u8 reserved_at_a00[0x600]; 12658 }; 12659 12660 struct mlx5_ifc_create_encryption_key_in_bits { 12661 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12662 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12663 }; 12664 12665 struct mlx5_ifc_modify_encryption_key_in_bits { 12666 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12667 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12668 }; 12669 12670 enum { 12671 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12672 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12673 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12674 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12675 }; 12676 12677 struct mlx5_ifc_flow_meter_parameters_bits { 12678 u8 valid[0x1]; 12679 u8 bucket_overflow[0x1]; 12680 u8 start_color[0x2]; 12681 u8 both_buckets_on_green[0x1]; 12682 u8 reserved_at_5[0x1]; 12683 u8 meter_mode[0x2]; 12684 u8 reserved_at_8[0x18]; 12685 12686 u8 reserved_at_20[0x20]; 12687 12688 u8 reserved_at_40[0x3]; 12689 u8 cbs_exponent[0x5]; 12690 u8 cbs_mantissa[0x8]; 12691 u8 reserved_at_50[0x3]; 12692 u8 cir_exponent[0x5]; 12693 u8 cir_mantissa[0x8]; 12694 12695 u8 reserved_at_60[0x20]; 12696 12697 u8 reserved_at_80[0x3]; 12698 u8 ebs_exponent[0x5]; 12699 u8 ebs_mantissa[0x8]; 12700 u8 reserved_at_90[0x3]; 12701 u8 eir_exponent[0x5]; 12702 u8 eir_mantissa[0x8]; 12703 12704 u8 reserved_at_a0[0x60]; 12705 }; 12706 12707 struct mlx5_ifc_flow_meter_aso_obj_bits { 12708 u8 modify_field_select[0x40]; 12709 12710 u8 reserved_at_40[0x40]; 12711 12712 u8 reserved_at_80[0x8]; 12713 u8 meter_aso_access_pd[0x18]; 12714 12715 u8 reserved_at_a0[0x160]; 12716 12717 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12718 }; 12719 12720 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12721 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12722 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12723 }; 12724 12725 struct mlx5_ifc_int_kek_obj_bits { 12726 u8 modify_field_select[0x40]; 12727 12728 u8 state[0x8]; 12729 u8 auto_gen[0x1]; 12730 u8 reserved_at_49[0xb]; 12731 u8 key_size[0x4]; 12732 u8 reserved_at_58[0x8]; 12733 12734 u8 reserved_at_60[0x8]; 12735 u8 pd[0x18]; 12736 12737 u8 reserved_at_80[0x180]; 12738 u8 key[8][0x80]; 12739 12740 u8 reserved_at_600[0x200]; 12741 }; 12742 12743 struct mlx5_ifc_create_int_kek_obj_in_bits { 12744 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12745 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12746 }; 12747 12748 struct mlx5_ifc_create_int_kek_obj_out_bits { 12749 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12750 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12751 }; 12752 12753 struct mlx5_ifc_sampler_obj_bits { 12754 u8 modify_field_select[0x40]; 12755 12756 u8 table_type[0x8]; 12757 u8 level[0x8]; 12758 u8 reserved_at_50[0xf]; 12759 u8 ignore_flow_level[0x1]; 12760 12761 u8 sample_ratio[0x20]; 12762 12763 u8 reserved_at_80[0x8]; 12764 u8 sample_table_id[0x18]; 12765 12766 u8 reserved_at_a0[0x8]; 12767 u8 default_table_id[0x18]; 12768 12769 u8 sw_steering_icm_address_rx[0x40]; 12770 u8 sw_steering_icm_address_tx[0x40]; 12771 12772 u8 reserved_at_140[0xa0]; 12773 }; 12774 12775 struct mlx5_ifc_create_sampler_obj_in_bits { 12776 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12777 struct mlx5_ifc_sampler_obj_bits sampler_object; 12778 }; 12779 12780 struct mlx5_ifc_query_sampler_obj_out_bits { 12781 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12782 struct mlx5_ifc_sampler_obj_bits sampler_object; 12783 }; 12784 12785 enum { 12786 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12787 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12788 }; 12789 12790 enum { 12791 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12792 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12793 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12794 }; 12795 12796 struct mlx5_ifc_tls_static_params_bits { 12797 u8 const_2[0x2]; 12798 u8 tls_version[0x4]; 12799 u8 const_1[0x2]; 12800 u8 reserved_at_8[0x14]; 12801 u8 encryption_standard[0x4]; 12802 12803 u8 reserved_at_20[0x20]; 12804 12805 u8 initial_record_number[0x40]; 12806 12807 u8 resync_tcp_sn[0x20]; 12808 12809 u8 gcm_iv[0x20]; 12810 12811 u8 implicit_iv[0x40]; 12812 12813 u8 reserved_at_100[0x8]; 12814 u8 dek_index[0x18]; 12815 12816 u8 reserved_at_120[0xe0]; 12817 }; 12818 12819 struct mlx5_ifc_tls_progress_params_bits { 12820 u8 next_record_tcp_sn[0x20]; 12821 12822 u8 hw_resync_tcp_sn[0x20]; 12823 12824 u8 record_tracker_state[0x2]; 12825 u8 auth_state[0x2]; 12826 u8 reserved_at_44[0x4]; 12827 u8 hw_offset_record_number[0x18]; 12828 }; 12829 12830 enum { 12831 MLX5_MTT_PERM_READ = 1 << 0, 12832 MLX5_MTT_PERM_WRITE = 1 << 1, 12833 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12834 }; 12835 12836 enum { 12837 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12838 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12839 }; 12840 12841 struct mlx5_ifc_suspend_vhca_in_bits { 12842 u8 opcode[0x10]; 12843 u8 uid[0x10]; 12844 12845 u8 reserved_at_20[0x10]; 12846 u8 op_mod[0x10]; 12847 12848 u8 reserved_at_40[0x10]; 12849 u8 vhca_id[0x10]; 12850 12851 u8 reserved_at_60[0x20]; 12852 }; 12853 12854 struct mlx5_ifc_suspend_vhca_out_bits { 12855 u8 status[0x8]; 12856 u8 reserved_at_8[0x18]; 12857 12858 u8 syndrome[0x20]; 12859 12860 u8 reserved_at_40[0x40]; 12861 }; 12862 12863 enum { 12864 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12865 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12866 }; 12867 12868 struct mlx5_ifc_resume_vhca_in_bits { 12869 u8 opcode[0x10]; 12870 u8 uid[0x10]; 12871 12872 u8 reserved_at_20[0x10]; 12873 u8 op_mod[0x10]; 12874 12875 u8 reserved_at_40[0x10]; 12876 u8 vhca_id[0x10]; 12877 12878 u8 reserved_at_60[0x20]; 12879 }; 12880 12881 struct mlx5_ifc_resume_vhca_out_bits { 12882 u8 status[0x8]; 12883 u8 reserved_at_8[0x18]; 12884 12885 u8 syndrome[0x20]; 12886 12887 u8 reserved_at_40[0x40]; 12888 }; 12889 12890 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12891 u8 opcode[0x10]; 12892 u8 uid[0x10]; 12893 12894 u8 reserved_at_20[0x10]; 12895 u8 op_mod[0x10]; 12896 12897 u8 incremental[0x1]; 12898 u8 chunk[0x1]; 12899 u8 reserved_at_42[0xe]; 12900 u8 vhca_id[0x10]; 12901 12902 u8 reserved_at_60[0x20]; 12903 }; 12904 12905 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12906 u8 status[0x8]; 12907 u8 reserved_at_8[0x18]; 12908 12909 u8 syndrome[0x20]; 12910 12911 u8 reserved_at_40[0x40]; 12912 12913 u8 required_umem_size[0x20]; 12914 12915 u8 reserved_at_a0[0x20]; 12916 12917 u8 remaining_total_size[0x40]; 12918 12919 u8 reserved_at_100[0x100]; 12920 }; 12921 12922 struct mlx5_ifc_save_vhca_state_in_bits { 12923 u8 opcode[0x10]; 12924 u8 uid[0x10]; 12925 12926 u8 reserved_at_20[0x10]; 12927 u8 op_mod[0x10]; 12928 12929 u8 incremental[0x1]; 12930 u8 set_track[0x1]; 12931 u8 reserved_at_42[0xe]; 12932 u8 vhca_id[0x10]; 12933 12934 u8 reserved_at_60[0x20]; 12935 12936 u8 va[0x40]; 12937 12938 u8 mkey[0x20]; 12939 12940 u8 size[0x20]; 12941 }; 12942 12943 struct mlx5_ifc_save_vhca_state_out_bits { 12944 u8 status[0x8]; 12945 u8 reserved_at_8[0x18]; 12946 12947 u8 syndrome[0x20]; 12948 12949 u8 actual_image_size[0x20]; 12950 12951 u8 next_required_umem_size[0x20]; 12952 }; 12953 12954 struct mlx5_ifc_load_vhca_state_in_bits { 12955 u8 opcode[0x10]; 12956 u8 uid[0x10]; 12957 12958 u8 reserved_at_20[0x10]; 12959 u8 op_mod[0x10]; 12960 12961 u8 reserved_at_40[0x10]; 12962 u8 vhca_id[0x10]; 12963 12964 u8 reserved_at_60[0x20]; 12965 12966 u8 va[0x40]; 12967 12968 u8 mkey[0x20]; 12969 12970 u8 size[0x20]; 12971 }; 12972 12973 struct mlx5_ifc_load_vhca_state_out_bits { 12974 u8 status[0x8]; 12975 u8 reserved_at_8[0x18]; 12976 12977 u8 syndrome[0x20]; 12978 12979 u8 reserved_at_40[0x40]; 12980 }; 12981 12982 struct mlx5_ifc_adv_virtualization_cap_bits { 12983 u8 reserved_at_0[0x3]; 12984 u8 pg_track_log_max_num[0x5]; 12985 u8 pg_track_max_num_range[0x8]; 12986 u8 pg_track_log_min_addr_space[0x8]; 12987 u8 pg_track_log_max_addr_space[0x8]; 12988 12989 u8 reserved_at_20[0x3]; 12990 u8 pg_track_log_min_msg_size[0x5]; 12991 u8 reserved_at_28[0x3]; 12992 u8 pg_track_log_max_msg_size[0x5]; 12993 u8 reserved_at_30[0x3]; 12994 u8 pg_track_log_min_page_size[0x5]; 12995 u8 reserved_at_38[0x3]; 12996 u8 pg_track_log_max_page_size[0x5]; 12997 12998 u8 reserved_at_40[0x7c0]; 12999 }; 13000 13001 struct mlx5_ifc_page_track_report_entry_bits { 13002 u8 dirty_address_high[0x20]; 13003 13004 u8 dirty_address_low[0x20]; 13005 }; 13006 13007 enum { 13008 MLX5_PAGE_TRACK_STATE_TRACKING, 13009 MLX5_PAGE_TRACK_STATE_REPORTING, 13010 MLX5_PAGE_TRACK_STATE_ERROR, 13011 }; 13012 13013 struct mlx5_ifc_page_track_range_bits { 13014 u8 start_address[0x40]; 13015 13016 u8 length[0x40]; 13017 }; 13018 13019 struct mlx5_ifc_page_track_bits { 13020 u8 modify_field_select[0x40]; 13021 13022 u8 reserved_at_40[0x10]; 13023 u8 vhca_id[0x10]; 13024 13025 u8 reserved_at_60[0x20]; 13026 13027 u8 state[0x4]; 13028 u8 track_type[0x4]; 13029 u8 log_addr_space_size[0x8]; 13030 u8 reserved_at_90[0x3]; 13031 u8 log_page_size[0x5]; 13032 u8 reserved_at_98[0x3]; 13033 u8 log_msg_size[0x5]; 13034 13035 u8 reserved_at_a0[0x8]; 13036 u8 reporting_qpn[0x18]; 13037 13038 u8 reserved_at_c0[0x18]; 13039 u8 num_ranges[0x8]; 13040 13041 u8 reserved_at_e0[0x20]; 13042 13043 u8 range_start_address[0x40]; 13044 13045 u8 length[0x40]; 13046 13047 struct mlx5_ifc_page_track_range_bits track_range[0]; 13048 }; 13049 13050 struct mlx5_ifc_create_page_track_obj_in_bits { 13051 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13052 struct mlx5_ifc_page_track_bits obj_context; 13053 }; 13054 13055 struct mlx5_ifc_modify_page_track_obj_in_bits { 13056 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13057 struct mlx5_ifc_page_track_bits obj_context; 13058 }; 13059 13060 struct mlx5_ifc_query_page_track_obj_out_bits { 13061 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13062 struct mlx5_ifc_page_track_bits obj_context; 13063 }; 13064 13065 struct mlx5_ifc_msecq_reg_bits { 13066 u8 reserved_at_0[0x20]; 13067 13068 u8 reserved_at_20[0x12]; 13069 u8 network_option[0x2]; 13070 u8 local_ssm_code[0x4]; 13071 u8 local_enhanced_ssm_code[0x8]; 13072 13073 u8 local_clock_identity[0x40]; 13074 13075 u8 reserved_at_80[0x180]; 13076 }; 13077 13078 enum { 13079 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 13080 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 13081 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 13082 }; 13083 13084 enum mlx5_msees_admin_status { 13085 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 13086 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 13087 }; 13088 13089 enum mlx5_msees_oper_status { 13090 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 13091 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 13092 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 13093 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 13094 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 13095 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 13096 }; 13097 13098 enum mlx5_msees_failure_reason { 13099 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 13100 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 13101 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 13102 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 13103 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 13104 }; 13105 13106 struct mlx5_ifc_msees_reg_bits { 13107 u8 reserved_at_0[0x8]; 13108 u8 local_port[0x8]; 13109 u8 pnat[0x2]; 13110 u8 lp_msb[0x2]; 13111 u8 reserved_at_14[0xc]; 13112 13113 u8 field_select[0x20]; 13114 13115 u8 admin_status[0x4]; 13116 u8 oper_status[0x4]; 13117 u8 ho_acq[0x1]; 13118 u8 reserved_at_49[0xc]; 13119 u8 admin_freq_measure[0x1]; 13120 u8 oper_freq_measure[0x1]; 13121 u8 failure_reason[0x9]; 13122 13123 u8 frequency_diff[0x20]; 13124 13125 u8 reserved_at_80[0x180]; 13126 }; 13127 13128 #endif /* MLX5_IFC_H */ 13129