1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 84 }; 85 86 enum { 87 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 88 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 89 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 90 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 91 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 92 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 93 }; 94 95 enum { 96 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 97 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 98 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 99 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 100 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 101 MLX5_OBJ_TYPE_MKEY = 0xff01, 102 MLX5_OBJ_TYPE_QP = 0xff02, 103 MLX5_OBJ_TYPE_PSV = 0xff03, 104 MLX5_OBJ_TYPE_RMP = 0xff04, 105 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 106 MLX5_OBJ_TYPE_RQ = 0xff06, 107 MLX5_OBJ_TYPE_SQ = 0xff07, 108 MLX5_OBJ_TYPE_TIR = 0xff08, 109 MLX5_OBJ_TYPE_TIS = 0xff09, 110 MLX5_OBJ_TYPE_DCT = 0xff0a, 111 MLX5_OBJ_TYPE_XRQ = 0xff0b, 112 MLX5_OBJ_TYPE_RQT = 0xff0e, 113 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 114 MLX5_OBJ_TYPE_CQ = 0xff10, 115 }; 116 117 enum { 118 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 119 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 120 MLX5_CMD_OP_INIT_HCA = 0x102, 121 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 122 MLX5_CMD_OP_ENABLE_HCA = 0x104, 123 MLX5_CMD_OP_DISABLE_HCA = 0x105, 124 MLX5_CMD_OP_QUERY_PAGES = 0x107, 125 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 126 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 127 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 128 MLX5_CMD_OP_SET_ISSI = 0x10b, 129 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 130 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 131 MLX5_CMD_OP_ALLOC_SF = 0x113, 132 MLX5_CMD_OP_DEALLOC_SF = 0x114, 133 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 134 MLX5_CMD_OP_RESUME_VHCA = 0x116, 135 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 136 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 137 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 138 MLX5_CMD_OP_CREATE_MKEY = 0x200, 139 MLX5_CMD_OP_QUERY_MKEY = 0x201, 140 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 141 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 142 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 143 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 144 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 145 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 146 MLX5_CMD_OP_CREATE_EQ = 0x301, 147 MLX5_CMD_OP_DESTROY_EQ = 0x302, 148 MLX5_CMD_OP_QUERY_EQ = 0x303, 149 MLX5_CMD_OP_GEN_EQE = 0x304, 150 MLX5_CMD_OP_CREATE_CQ = 0x400, 151 MLX5_CMD_OP_DESTROY_CQ = 0x401, 152 MLX5_CMD_OP_QUERY_CQ = 0x402, 153 MLX5_CMD_OP_MODIFY_CQ = 0x403, 154 MLX5_CMD_OP_CREATE_QP = 0x500, 155 MLX5_CMD_OP_DESTROY_QP = 0x501, 156 MLX5_CMD_OP_RST2INIT_QP = 0x502, 157 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 158 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 159 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 160 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 161 MLX5_CMD_OP_2ERR_QP = 0x507, 162 MLX5_CMD_OP_2RST_QP = 0x50a, 163 MLX5_CMD_OP_QUERY_QP = 0x50b, 164 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 165 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 166 MLX5_CMD_OP_CREATE_PSV = 0x600, 167 MLX5_CMD_OP_DESTROY_PSV = 0x601, 168 MLX5_CMD_OP_CREATE_SRQ = 0x700, 169 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 170 MLX5_CMD_OP_QUERY_SRQ = 0x702, 171 MLX5_CMD_OP_ARM_RQ = 0x703, 172 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 173 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 174 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 175 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 176 MLX5_CMD_OP_CREATE_DCT = 0x710, 177 MLX5_CMD_OP_DESTROY_DCT = 0x711, 178 MLX5_CMD_OP_DRAIN_DCT = 0x712, 179 MLX5_CMD_OP_QUERY_DCT = 0x713, 180 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 181 MLX5_CMD_OP_CREATE_XRQ = 0x717, 182 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 183 MLX5_CMD_OP_QUERY_XRQ = 0x719, 184 MLX5_CMD_OP_ARM_XRQ = 0x71a, 185 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 186 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 187 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 188 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 189 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 190 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 191 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 192 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 193 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 194 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 195 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 196 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 197 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 198 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 200 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 202 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 203 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 204 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 205 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 206 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 207 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 208 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 209 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 210 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 211 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 212 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 213 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 214 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 215 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 216 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 217 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 218 MLX5_CMD_OP_ALLOC_PD = 0x800, 219 MLX5_CMD_OP_DEALLOC_PD = 0x801, 220 MLX5_CMD_OP_ALLOC_UAR = 0x802, 221 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 222 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 223 MLX5_CMD_OP_ACCESS_REG = 0x805, 224 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 225 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 226 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 227 MLX5_CMD_OP_MAD_IFC = 0x50d, 228 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 229 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 230 MLX5_CMD_OP_NOP = 0x80d, 231 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 232 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 233 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 234 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 235 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 236 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 237 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 238 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 239 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 240 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 241 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 242 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 243 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 244 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 245 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 246 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 247 MLX5_CMD_OP_CREATE_LAG = 0x840, 248 MLX5_CMD_OP_MODIFY_LAG = 0x841, 249 MLX5_CMD_OP_QUERY_LAG = 0x842, 250 MLX5_CMD_OP_DESTROY_LAG = 0x843, 251 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 252 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 253 MLX5_CMD_OP_CREATE_TIR = 0x900, 254 MLX5_CMD_OP_MODIFY_TIR = 0x901, 255 MLX5_CMD_OP_DESTROY_TIR = 0x902, 256 MLX5_CMD_OP_QUERY_TIR = 0x903, 257 MLX5_CMD_OP_CREATE_SQ = 0x904, 258 MLX5_CMD_OP_MODIFY_SQ = 0x905, 259 MLX5_CMD_OP_DESTROY_SQ = 0x906, 260 MLX5_CMD_OP_QUERY_SQ = 0x907, 261 MLX5_CMD_OP_CREATE_RQ = 0x908, 262 MLX5_CMD_OP_MODIFY_RQ = 0x909, 263 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 264 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 265 MLX5_CMD_OP_QUERY_RQ = 0x90b, 266 MLX5_CMD_OP_CREATE_RMP = 0x90c, 267 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 268 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 269 MLX5_CMD_OP_QUERY_RMP = 0x90f, 270 MLX5_CMD_OP_CREATE_TIS = 0x912, 271 MLX5_CMD_OP_MODIFY_TIS = 0x913, 272 MLX5_CMD_OP_DESTROY_TIS = 0x914, 273 MLX5_CMD_OP_QUERY_TIS = 0x915, 274 MLX5_CMD_OP_CREATE_RQT = 0x916, 275 MLX5_CMD_OP_MODIFY_RQT = 0x917, 276 MLX5_CMD_OP_DESTROY_RQT = 0x918, 277 MLX5_CMD_OP_QUERY_RQT = 0x919, 278 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 279 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 280 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 282 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 283 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 284 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 285 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 287 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 288 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 289 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 290 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 291 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 292 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 293 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 294 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 295 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 296 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 297 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 298 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 299 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 300 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 301 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 302 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 303 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 304 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 305 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 306 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 307 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 308 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 309 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 310 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 311 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 312 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 313 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 314 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 315 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 316 MLX5_CMD_OP_MAX 317 }; 318 319 /* Valid range for general commands that don't work over an object */ 320 enum { 321 MLX5_CMD_OP_GENERAL_START = 0xb00, 322 MLX5_CMD_OP_GENERAL_END = 0xd00, 323 }; 324 325 enum { 326 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 327 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 328 }; 329 330 enum { 331 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 332 }; 333 334 struct mlx5_ifc_flow_table_fields_supported_bits { 335 u8 outer_dmac[0x1]; 336 u8 outer_smac[0x1]; 337 u8 outer_ether_type[0x1]; 338 u8 outer_ip_version[0x1]; 339 u8 outer_first_prio[0x1]; 340 u8 outer_first_cfi[0x1]; 341 u8 outer_first_vid[0x1]; 342 u8 outer_ipv4_ttl[0x1]; 343 u8 outer_second_prio[0x1]; 344 u8 outer_second_cfi[0x1]; 345 u8 outer_second_vid[0x1]; 346 u8 reserved_at_b[0x1]; 347 u8 outer_sip[0x1]; 348 u8 outer_dip[0x1]; 349 u8 outer_frag[0x1]; 350 u8 outer_ip_protocol[0x1]; 351 u8 outer_ip_ecn[0x1]; 352 u8 outer_ip_dscp[0x1]; 353 u8 outer_udp_sport[0x1]; 354 u8 outer_udp_dport[0x1]; 355 u8 outer_tcp_sport[0x1]; 356 u8 outer_tcp_dport[0x1]; 357 u8 outer_tcp_flags[0x1]; 358 u8 outer_gre_protocol[0x1]; 359 u8 outer_gre_key[0x1]; 360 u8 outer_vxlan_vni[0x1]; 361 u8 outer_geneve_vni[0x1]; 362 u8 outer_geneve_oam[0x1]; 363 u8 outer_geneve_protocol_type[0x1]; 364 u8 outer_geneve_opt_len[0x1]; 365 u8 source_vhca_port[0x1]; 366 u8 source_eswitch_port[0x1]; 367 368 u8 inner_dmac[0x1]; 369 u8 inner_smac[0x1]; 370 u8 inner_ether_type[0x1]; 371 u8 inner_ip_version[0x1]; 372 u8 inner_first_prio[0x1]; 373 u8 inner_first_cfi[0x1]; 374 u8 inner_first_vid[0x1]; 375 u8 reserved_at_27[0x1]; 376 u8 inner_second_prio[0x1]; 377 u8 inner_second_cfi[0x1]; 378 u8 inner_second_vid[0x1]; 379 u8 reserved_at_2b[0x1]; 380 u8 inner_sip[0x1]; 381 u8 inner_dip[0x1]; 382 u8 inner_frag[0x1]; 383 u8 inner_ip_protocol[0x1]; 384 u8 inner_ip_ecn[0x1]; 385 u8 inner_ip_dscp[0x1]; 386 u8 inner_udp_sport[0x1]; 387 u8 inner_udp_dport[0x1]; 388 u8 inner_tcp_sport[0x1]; 389 u8 inner_tcp_dport[0x1]; 390 u8 inner_tcp_flags[0x1]; 391 u8 reserved_at_37[0x9]; 392 393 u8 geneve_tlv_option_0_data[0x1]; 394 u8 geneve_tlv_option_0_exist[0x1]; 395 u8 reserved_at_42[0x3]; 396 u8 outer_first_mpls_over_udp[0x4]; 397 u8 outer_first_mpls_over_gre[0x4]; 398 u8 inner_first_mpls[0x4]; 399 u8 outer_first_mpls[0x4]; 400 u8 reserved_at_55[0x2]; 401 u8 outer_esp_spi[0x1]; 402 u8 reserved_at_58[0x2]; 403 u8 bth_dst_qp[0x1]; 404 u8 reserved_at_5b[0x5]; 405 406 u8 reserved_at_60[0x18]; 407 u8 metadata_reg_c_7[0x1]; 408 u8 metadata_reg_c_6[0x1]; 409 u8 metadata_reg_c_5[0x1]; 410 u8 metadata_reg_c_4[0x1]; 411 u8 metadata_reg_c_3[0x1]; 412 u8 metadata_reg_c_2[0x1]; 413 u8 metadata_reg_c_1[0x1]; 414 u8 metadata_reg_c_0[0x1]; 415 }; 416 417 /* Table 2170 - Flow Table Fields Supported 2 Format */ 418 struct mlx5_ifc_flow_table_fields_supported_2_bits { 419 u8 reserved_at_0[0xe]; 420 u8 bth_opcode[0x1]; 421 u8 reserved_at_f[0x1]; 422 u8 tunnel_header_0_1[0x1]; 423 u8 reserved_at_11[0xf]; 424 425 u8 reserved_at_20[0x60]; 426 }; 427 428 struct mlx5_ifc_flow_table_prop_layout_bits { 429 u8 ft_support[0x1]; 430 u8 reserved_at_1[0x1]; 431 u8 flow_counter[0x1]; 432 u8 flow_modify_en[0x1]; 433 u8 modify_root[0x1]; 434 u8 identified_miss_table_mode[0x1]; 435 u8 flow_table_modify[0x1]; 436 u8 reformat[0x1]; 437 u8 decap[0x1]; 438 u8 reset_root_to_default[0x1]; 439 u8 pop_vlan[0x1]; 440 u8 push_vlan[0x1]; 441 u8 reserved_at_c[0x1]; 442 u8 pop_vlan_2[0x1]; 443 u8 push_vlan_2[0x1]; 444 u8 reformat_and_vlan_action[0x1]; 445 u8 reserved_at_10[0x1]; 446 u8 sw_owner[0x1]; 447 u8 reformat_l3_tunnel_to_l2[0x1]; 448 u8 reformat_l2_to_l3_tunnel[0x1]; 449 u8 reformat_and_modify_action[0x1]; 450 u8 ignore_flow_level[0x1]; 451 u8 reserved_at_16[0x1]; 452 u8 table_miss_action_domain[0x1]; 453 u8 termination_table[0x1]; 454 u8 reformat_and_fwd_to_table[0x1]; 455 u8 reserved_at_1a[0x2]; 456 u8 ipsec_encrypt[0x1]; 457 u8 ipsec_decrypt[0x1]; 458 u8 sw_owner_v2[0x1]; 459 u8 reserved_at_1f[0x1]; 460 461 u8 termination_table_raw_traffic[0x1]; 462 u8 reserved_at_21[0x1]; 463 u8 log_max_ft_size[0x6]; 464 u8 log_max_modify_header_context[0x8]; 465 u8 max_modify_header_actions[0x8]; 466 u8 max_ft_level[0x8]; 467 468 u8 reformat_add_esp_trasport[0x1]; 469 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 470 u8 reformat_add_esp_transport_over_udp[0x1]; 471 u8 reformat_del_esp_trasport[0x1]; 472 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 473 u8 reformat_del_esp_transport_over_udp[0x1]; 474 u8 execute_aso[0x1]; 475 u8 reserved_at_47[0x19]; 476 477 u8 reserved_at_60[0x2]; 478 u8 reformat_insert[0x1]; 479 u8 reformat_remove[0x1]; 480 u8 macsec_encrypt[0x1]; 481 u8 macsec_decrypt[0x1]; 482 u8 reserved_at_66[0x2]; 483 u8 reformat_add_macsec[0x1]; 484 u8 reformat_remove_macsec[0x1]; 485 u8 reserved_at_6a[0xe]; 486 u8 log_max_ft_num[0x8]; 487 488 u8 reserved_at_80[0x10]; 489 u8 log_max_flow_counter[0x8]; 490 u8 log_max_destination[0x8]; 491 492 u8 reserved_at_a0[0x18]; 493 u8 log_max_flow[0x8]; 494 495 u8 reserved_at_c0[0x40]; 496 497 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 498 499 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 500 }; 501 502 struct mlx5_ifc_odp_per_transport_service_cap_bits { 503 u8 send[0x1]; 504 u8 receive[0x1]; 505 u8 write[0x1]; 506 u8 read[0x1]; 507 u8 atomic[0x1]; 508 u8 srq_receive[0x1]; 509 u8 reserved_at_6[0x1a]; 510 }; 511 512 struct mlx5_ifc_ipv4_layout_bits { 513 u8 reserved_at_0[0x60]; 514 515 u8 ipv4[0x20]; 516 }; 517 518 struct mlx5_ifc_ipv6_layout_bits { 519 u8 ipv6[16][0x8]; 520 }; 521 522 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 523 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 524 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 525 u8 reserved_at_0[0x80]; 526 }; 527 528 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 529 u8 smac_47_16[0x20]; 530 531 u8 smac_15_0[0x10]; 532 u8 ethertype[0x10]; 533 534 u8 dmac_47_16[0x20]; 535 536 u8 dmac_15_0[0x10]; 537 u8 first_prio[0x3]; 538 u8 first_cfi[0x1]; 539 u8 first_vid[0xc]; 540 541 u8 ip_protocol[0x8]; 542 u8 ip_dscp[0x6]; 543 u8 ip_ecn[0x2]; 544 u8 cvlan_tag[0x1]; 545 u8 svlan_tag[0x1]; 546 u8 frag[0x1]; 547 u8 ip_version[0x4]; 548 u8 tcp_flags[0x9]; 549 550 u8 tcp_sport[0x10]; 551 u8 tcp_dport[0x10]; 552 553 u8 reserved_at_c0[0x10]; 554 u8 ipv4_ihl[0x4]; 555 u8 reserved_at_c4[0x4]; 556 557 u8 ttl_hoplimit[0x8]; 558 559 u8 udp_sport[0x10]; 560 u8 udp_dport[0x10]; 561 562 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 563 564 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 565 }; 566 567 struct mlx5_ifc_nvgre_key_bits { 568 u8 hi[0x18]; 569 u8 lo[0x8]; 570 }; 571 572 union mlx5_ifc_gre_key_bits { 573 struct mlx5_ifc_nvgre_key_bits nvgre; 574 u8 key[0x20]; 575 }; 576 577 struct mlx5_ifc_fte_match_set_misc_bits { 578 u8 gre_c_present[0x1]; 579 u8 reserved_at_1[0x1]; 580 u8 gre_k_present[0x1]; 581 u8 gre_s_present[0x1]; 582 u8 source_vhca_port[0x4]; 583 u8 source_sqn[0x18]; 584 585 u8 source_eswitch_owner_vhca_id[0x10]; 586 u8 source_port[0x10]; 587 588 u8 outer_second_prio[0x3]; 589 u8 outer_second_cfi[0x1]; 590 u8 outer_second_vid[0xc]; 591 u8 inner_second_prio[0x3]; 592 u8 inner_second_cfi[0x1]; 593 u8 inner_second_vid[0xc]; 594 595 u8 outer_second_cvlan_tag[0x1]; 596 u8 inner_second_cvlan_tag[0x1]; 597 u8 outer_second_svlan_tag[0x1]; 598 u8 inner_second_svlan_tag[0x1]; 599 u8 reserved_at_64[0xc]; 600 u8 gre_protocol[0x10]; 601 602 union mlx5_ifc_gre_key_bits gre_key; 603 604 u8 vxlan_vni[0x18]; 605 u8 bth_opcode[0x8]; 606 607 u8 geneve_vni[0x18]; 608 u8 reserved_at_d8[0x6]; 609 u8 geneve_tlv_option_0_exist[0x1]; 610 u8 geneve_oam[0x1]; 611 612 u8 reserved_at_e0[0xc]; 613 u8 outer_ipv6_flow_label[0x14]; 614 615 u8 reserved_at_100[0xc]; 616 u8 inner_ipv6_flow_label[0x14]; 617 618 u8 reserved_at_120[0xa]; 619 u8 geneve_opt_len[0x6]; 620 u8 geneve_protocol_type[0x10]; 621 622 u8 reserved_at_140[0x8]; 623 u8 bth_dst_qp[0x18]; 624 u8 inner_esp_spi[0x20]; 625 u8 outer_esp_spi[0x20]; 626 u8 reserved_at_1a0[0x60]; 627 }; 628 629 struct mlx5_ifc_fte_match_mpls_bits { 630 u8 mpls_label[0x14]; 631 u8 mpls_exp[0x3]; 632 u8 mpls_s_bos[0x1]; 633 u8 mpls_ttl[0x8]; 634 }; 635 636 struct mlx5_ifc_fte_match_set_misc2_bits { 637 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 638 639 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 640 641 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 642 643 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 644 645 u8 metadata_reg_c_7[0x20]; 646 647 u8 metadata_reg_c_6[0x20]; 648 649 u8 metadata_reg_c_5[0x20]; 650 651 u8 metadata_reg_c_4[0x20]; 652 653 u8 metadata_reg_c_3[0x20]; 654 655 u8 metadata_reg_c_2[0x20]; 656 657 u8 metadata_reg_c_1[0x20]; 658 659 u8 metadata_reg_c_0[0x20]; 660 661 u8 metadata_reg_a[0x20]; 662 663 u8 reserved_at_1a0[0x8]; 664 665 u8 macsec_syndrome[0x8]; 666 u8 ipsec_syndrome[0x8]; 667 u8 reserved_at_1b8[0x8]; 668 669 u8 reserved_at_1c0[0x40]; 670 }; 671 672 struct mlx5_ifc_fte_match_set_misc3_bits { 673 u8 inner_tcp_seq_num[0x20]; 674 675 u8 outer_tcp_seq_num[0x20]; 676 677 u8 inner_tcp_ack_num[0x20]; 678 679 u8 outer_tcp_ack_num[0x20]; 680 681 u8 reserved_at_80[0x8]; 682 u8 outer_vxlan_gpe_vni[0x18]; 683 684 u8 outer_vxlan_gpe_next_protocol[0x8]; 685 u8 outer_vxlan_gpe_flags[0x8]; 686 u8 reserved_at_b0[0x10]; 687 688 u8 icmp_header_data[0x20]; 689 690 u8 icmpv6_header_data[0x20]; 691 692 u8 icmp_type[0x8]; 693 u8 icmp_code[0x8]; 694 u8 icmpv6_type[0x8]; 695 u8 icmpv6_code[0x8]; 696 697 u8 geneve_tlv_option_0_data[0x20]; 698 699 u8 gtpu_teid[0x20]; 700 701 u8 gtpu_msg_type[0x8]; 702 u8 gtpu_msg_flags[0x8]; 703 u8 reserved_at_170[0x10]; 704 705 u8 gtpu_dw_2[0x20]; 706 707 u8 gtpu_first_ext_dw_0[0x20]; 708 709 u8 gtpu_dw_0[0x20]; 710 711 u8 reserved_at_1e0[0x20]; 712 }; 713 714 struct mlx5_ifc_fte_match_set_misc4_bits { 715 u8 prog_sample_field_value_0[0x20]; 716 717 u8 prog_sample_field_id_0[0x20]; 718 719 u8 prog_sample_field_value_1[0x20]; 720 721 u8 prog_sample_field_id_1[0x20]; 722 723 u8 prog_sample_field_value_2[0x20]; 724 725 u8 prog_sample_field_id_2[0x20]; 726 727 u8 prog_sample_field_value_3[0x20]; 728 729 u8 prog_sample_field_id_3[0x20]; 730 731 u8 reserved_at_100[0x100]; 732 }; 733 734 struct mlx5_ifc_fte_match_set_misc5_bits { 735 u8 macsec_tag_0[0x20]; 736 737 u8 macsec_tag_1[0x20]; 738 739 u8 macsec_tag_2[0x20]; 740 741 u8 macsec_tag_3[0x20]; 742 743 u8 tunnel_header_0[0x20]; 744 745 u8 tunnel_header_1[0x20]; 746 747 u8 tunnel_header_2[0x20]; 748 749 u8 tunnel_header_3[0x20]; 750 751 u8 reserved_at_100[0x100]; 752 }; 753 754 struct mlx5_ifc_cmd_pas_bits { 755 u8 pa_h[0x20]; 756 757 u8 pa_l[0x14]; 758 u8 reserved_at_34[0xc]; 759 }; 760 761 struct mlx5_ifc_uint64_bits { 762 u8 hi[0x20]; 763 764 u8 lo[0x20]; 765 }; 766 767 enum { 768 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 769 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 770 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 771 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 772 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 773 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 774 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 775 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 776 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 777 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 778 }; 779 780 struct mlx5_ifc_ads_bits { 781 u8 fl[0x1]; 782 u8 free_ar[0x1]; 783 u8 reserved_at_2[0xe]; 784 u8 pkey_index[0x10]; 785 786 u8 reserved_at_20[0x8]; 787 u8 grh[0x1]; 788 u8 mlid[0x7]; 789 u8 rlid[0x10]; 790 791 u8 ack_timeout[0x5]; 792 u8 reserved_at_45[0x3]; 793 u8 src_addr_index[0x8]; 794 u8 reserved_at_50[0x4]; 795 u8 stat_rate[0x4]; 796 u8 hop_limit[0x8]; 797 798 u8 reserved_at_60[0x4]; 799 u8 tclass[0x8]; 800 u8 flow_label[0x14]; 801 802 u8 rgid_rip[16][0x8]; 803 804 u8 reserved_at_100[0x4]; 805 u8 f_dscp[0x1]; 806 u8 f_ecn[0x1]; 807 u8 reserved_at_106[0x1]; 808 u8 f_eth_prio[0x1]; 809 u8 ecn[0x2]; 810 u8 dscp[0x6]; 811 u8 udp_sport[0x10]; 812 813 u8 dei_cfi[0x1]; 814 u8 eth_prio[0x3]; 815 u8 sl[0x4]; 816 u8 vhca_port_num[0x8]; 817 u8 rmac_47_32[0x10]; 818 819 u8 rmac_31_0[0x20]; 820 }; 821 822 struct mlx5_ifc_flow_table_nic_cap_bits { 823 u8 nic_rx_multi_path_tirs[0x1]; 824 u8 nic_rx_multi_path_tirs_fts[0x1]; 825 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 826 u8 reserved_at_3[0x4]; 827 u8 sw_owner_reformat_supported[0x1]; 828 u8 reserved_at_8[0x18]; 829 830 u8 encap_general_header[0x1]; 831 u8 reserved_at_21[0xa]; 832 u8 log_max_packet_reformat_context[0x5]; 833 u8 reserved_at_30[0x6]; 834 u8 max_encap_header_size[0xa]; 835 u8 reserved_at_40[0x1c0]; 836 837 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 838 839 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 840 841 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 842 843 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 844 845 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 846 847 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 848 849 u8 reserved_at_e00[0x700]; 850 851 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 852 853 u8 reserved_at_1580[0x280]; 854 855 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 856 857 u8 reserved_at_1880[0x780]; 858 859 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 860 861 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 862 863 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 864 865 u8 reserved_at_20c0[0x5f40]; 866 }; 867 868 struct mlx5_ifc_port_selection_cap_bits { 869 u8 reserved_at_0[0x10]; 870 u8 port_select_flow_table[0x1]; 871 u8 reserved_at_11[0x1]; 872 u8 port_select_flow_table_bypass[0x1]; 873 u8 reserved_at_13[0xd]; 874 875 u8 reserved_at_20[0x1e0]; 876 877 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 878 879 u8 reserved_at_400[0x7c00]; 880 }; 881 882 enum { 883 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 884 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 885 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 886 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 887 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 888 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 889 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 890 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 891 }; 892 893 struct mlx5_ifc_flow_table_eswitch_cap_bits { 894 u8 fdb_to_vport_reg_c_id[0x8]; 895 u8 reserved_at_8[0x5]; 896 u8 fdb_uplink_hairpin[0x1]; 897 u8 fdb_multi_path_any_table_limit_regc[0x1]; 898 u8 reserved_at_f[0x3]; 899 u8 fdb_multi_path_any_table[0x1]; 900 u8 reserved_at_13[0x2]; 901 u8 fdb_modify_header_fwd_to_table[0x1]; 902 u8 fdb_ipv4_ttl_modify[0x1]; 903 u8 flow_source[0x1]; 904 u8 reserved_at_18[0x2]; 905 u8 multi_fdb_encap[0x1]; 906 u8 egress_acl_forward_to_vport[0x1]; 907 u8 fdb_multi_path_to_table[0x1]; 908 u8 reserved_at_1d[0x3]; 909 910 u8 reserved_at_20[0x1e0]; 911 912 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 913 914 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 915 916 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 917 918 u8 reserved_at_800[0xC00]; 919 920 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 921 922 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 923 924 u8 reserved_at_1500[0x300]; 925 926 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 927 928 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 929 930 u8 sw_steering_uplink_icm_address_rx[0x40]; 931 932 u8 sw_steering_uplink_icm_address_tx[0x40]; 933 934 u8 reserved_at_1900[0x6700]; 935 }; 936 937 enum { 938 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 939 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 940 }; 941 942 struct mlx5_ifc_e_switch_cap_bits { 943 u8 vport_svlan_strip[0x1]; 944 u8 vport_cvlan_strip[0x1]; 945 u8 vport_svlan_insert[0x1]; 946 u8 vport_cvlan_insert_if_not_exist[0x1]; 947 u8 vport_cvlan_insert_overwrite[0x1]; 948 u8 reserved_at_5[0x1]; 949 u8 vport_cvlan_insert_always[0x1]; 950 u8 esw_shared_ingress_acl[0x1]; 951 u8 esw_uplink_ingress_acl[0x1]; 952 u8 root_ft_on_other_esw[0x1]; 953 u8 reserved_at_a[0xf]; 954 u8 esw_functions_changed[0x1]; 955 u8 reserved_at_1a[0x1]; 956 u8 ecpf_vport_exists[0x1]; 957 u8 counter_eswitch_affinity[0x1]; 958 u8 merged_eswitch[0x1]; 959 u8 nic_vport_node_guid_modify[0x1]; 960 u8 nic_vport_port_guid_modify[0x1]; 961 962 u8 vxlan_encap_decap[0x1]; 963 u8 nvgre_encap_decap[0x1]; 964 u8 reserved_at_22[0x1]; 965 u8 log_max_fdb_encap_uplink[0x5]; 966 u8 reserved_at_21[0x3]; 967 u8 log_max_packet_reformat_context[0x5]; 968 u8 reserved_2b[0x6]; 969 u8 max_encap_header_size[0xa]; 970 971 u8 reserved_at_40[0xb]; 972 u8 log_max_esw_sf[0x5]; 973 u8 esw_sf_base_id[0x10]; 974 975 u8 reserved_at_60[0x7a0]; 976 977 }; 978 979 struct mlx5_ifc_qos_cap_bits { 980 u8 packet_pacing[0x1]; 981 u8 esw_scheduling[0x1]; 982 u8 esw_bw_share[0x1]; 983 u8 esw_rate_limit[0x1]; 984 u8 reserved_at_4[0x1]; 985 u8 packet_pacing_burst_bound[0x1]; 986 u8 packet_pacing_typical_size[0x1]; 987 u8 reserved_at_7[0x1]; 988 u8 nic_sq_scheduling[0x1]; 989 u8 nic_bw_share[0x1]; 990 u8 nic_rate_limit[0x1]; 991 u8 packet_pacing_uid[0x1]; 992 u8 log_esw_max_sched_depth[0x4]; 993 u8 reserved_at_10[0x10]; 994 995 u8 reserved_at_20[0xb]; 996 u8 log_max_qos_nic_queue_group[0x5]; 997 u8 reserved_at_30[0x10]; 998 999 u8 packet_pacing_max_rate[0x20]; 1000 1001 u8 packet_pacing_min_rate[0x20]; 1002 1003 u8 reserved_at_80[0x10]; 1004 u8 packet_pacing_rate_table_size[0x10]; 1005 1006 u8 esw_element_type[0x10]; 1007 u8 esw_tsar_type[0x10]; 1008 1009 u8 reserved_at_c0[0x10]; 1010 u8 max_qos_para_vport[0x10]; 1011 1012 u8 max_tsar_bw_share[0x20]; 1013 1014 u8 reserved_at_100[0x20]; 1015 1016 u8 reserved_at_120[0x3]; 1017 u8 log_meter_aso_granularity[0x5]; 1018 u8 reserved_at_128[0x3]; 1019 u8 log_meter_aso_max_alloc[0x5]; 1020 u8 reserved_at_130[0x3]; 1021 u8 log_max_num_meter_aso[0x5]; 1022 u8 reserved_at_138[0x8]; 1023 1024 u8 reserved_at_140[0x6c0]; 1025 }; 1026 1027 struct mlx5_ifc_debug_cap_bits { 1028 u8 core_dump_general[0x1]; 1029 u8 core_dump_qp[0x1]; 1030 u8 reserved_at_2[0x7]; 1031 u8 resource_dump[0x1]; 1032 u8 reserved_at_a[0x16]; 1033 1034 u8 reserved_at_20[0x2]; 1035 u8 stall_detect[0x1]; 1036 u8 reserved_at_23[0x1d]; 1037 1038 u8 reserved_at_40[0x7c0]; 1039 }; 1040 1041 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1042 u8 csum_cap[0x1]; 1043 u8 vlan_cap[0x1]; 1044 u8 lro_cap[0x1]; 1045 u8 lro_psh_flag[0x1]; 1046 u8 lro_time_stamp[0x1]; 1047 u8 reserved_at_5[0x2]; 1048 u8 wqe_vlan_insert[0x1]; 1049 u8 self_lb_en_modifiable[0x1]; 1050 u8 reserved_at_9[0x2]; 1051 u8 max_lso_cap[0x5]; 1052 u8 multi_pkt_send_wqe[0x2]; 1053 u8 wqe_inline_mode[0x2]; 1054 u8 rss_ind_tbl_cap[0x4]; 1055 u8 reg_umr_sq[0x1]; 1056 u8 scatter_fcs[0x1]; 1057 u8 enhanced_multi_pkt_send_wqe[0x1]; 1058 u8 tunnel_lso_const_out_ip_id[0x1]; 1059 u8 tunnel_lro_gre[0x1]; 1060 u8 tunnel_lro_vxlan[0x1]; 1061 u8 tunnel_stateless_gre[0x1]; 1062 u8 tunnel_stateless_vxlan[0x1]; 1063 1064 u8 swp[0x1]; 1065 u8 swp_csum[0x1]; 1066 u8 swp_lso[0x1]; 1067 u8 cqe_checksum_full[0x1]; 1068 u8 tunnel_stateless_geneve_tx[0x1]; 1069 u8 tunnel_stateless_mpls_over_udp[0x1]; 1070 u8 tunnel_stateless_mpls_over_gre[0x1]; 1071 u8 tunnel_stateless_vxlan_gpe[0x1]; 1072 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1073 u8 tunnel_stateless_ip_over_ip[0x1]; 1074 u8 insert_trailer[0x1]; 1075 u8 reserved_at_2b[0x1]; 1076 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1077 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1078 u8 reserved_at_2e[0x2]; 1079 u8 max_vxlan_udp_ports[0x8]; 1080 u8 reserved_at_38[0x6]; 1081 u8 max_geneve_opt_len[0x1]; 1082 u8 tunnel_stateless_geneve_rx[0x1]; 1083 1084 u8 reserved_at_40[0x10]; 1085 u8 lro_min_mss_size[0x10]; 1086 1087 u8 reserved_at_60[0x120]; 1088 1089 u8 lro_timer_supported_periods[4][0x20]; 1090 1091 u8 reserved_at_200[0x600]; 1092 }; 1093 1094 enum { 1095 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1096 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1097 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1098 }; 1099 1100 struct mlx5_ifc_roce_cap_bits { 1101 u8 roce_apm[0x1]; 1102 u8 reserved_at_1[0x3]; 1103 u8 sw_r_roce_src_udp_port[0x1]; 1104 u8 fl_rc_qp_when_roce_disabled[0x1]; 1105 u8 fl_rc_qp_when_roce_enabled[0x1]; 1106 u8 reserved_at_7[0x1]; 1107 u8 qp_ooo_transmit_default[0x1]; 1108 u8 reserved_at_9[0x15]; 1109 u8 qp_ts_format[0x2]; 1110 1111 u8 reserved_at_20[0x60]; 1112 1113 u8 reserved_at_80[0xc]; 1114 u8 l3_type[0x4]; 1115 u8 reserved_at_90[0x8]; 1116 u8 roce_version[0x8]; 1117 1118 u8 reserved_at_a0[0x10]; 1119 u8 r_roce_dest_udp_port[0x10]; 1120 1121 u8 r_roce_max_src_udp_port[0x10]; 1122 u8 r_roce_min_src_udp_port[0x10]; 1123 1124 u8 reserved_at_e0[0x10]; 1125 u8 roce_address_table_size[0x10]; 1126 1127 u8 reserved_at_100[0x700]; 1128 }; 1129 1130 struct mlx5_ifc_sync_steering_in_bits { 1131 u8 opcode[0x10]; 1132 u8 uid[0x10]; 1133 1134 u8 reserved_at_20[0x10]; 1135 u8 op_mod[0x10]; 1136 1137 u8 reserved_at_40[0xc0]; 1138 }; 1139 1140 struct mlx5_ifc_sync_steering_out_bits { 1141 u8 status[0x8]; 1142 u8 reserved_at_8[0x18]; 1143 1144 u8 syndrome[0x20]; 1145 1146 u8 reserved_at_40[0x40]; 1147 }; 1148 1149 struct mlx5_ifc_sync_crypto_in_bits { 1150 u8 opcode[0x10]; 1151 u8 uid[0x10]; 1152 1153 u8 reserved_at_20[0x10]; 1154 u8 op_mod[0x10]; 1155 1156 u8 reserved_at_40[0x20]; 1157 1158 u8 reserved_at_60[0x10]; 1159 u8 crypto_type[0x10]; 1160 1161 u8 reserved_at_80[0x80]; 1162 }; 1163 1164 struct mlx5_ifc_sync_crypto_out_bits { 1165 u8 status[0x8]; 1166 u8 reserved_at_8[0x18]; 1167 1168 u8 syndrome[0x20]; 1169 1170 u8 reserved_at_40[0x40]; 1171 }; 1172 1173 struct mlx5_ifc_device_mem_cap_bits { 1174 u8 memic[0x1]; 1175 u8 reserved_at_1[0x1f]; 1176 1177 u8 reserved_at_20[0xb]; 1178 u8 log_min_memic_alloc_size[0x5]; 1179 u8 reserved_at_30[0x8]; 1180 u8 log_max_memic_addr_alignment[0x8]; 1181 1182 u8 memic_bar_start_addr[0x40]; 1183 1184 u8 memic_bar_size[0x20]; 1185 1186 u8 max_memic_size[0x20]; 1187 1188 u8 steering_sw_icm_start_address[0x40]; 1189 1190 u8 reserved_at_100[0x8]; 1191 u8 log_header_modify_sw_icm_size[0x8]; 1192 u8 reserved_at_110[0x2]; 1193 u8 log_sw_icm_alloc_granularity[0x6]; 1194 u8 log_steering_sw_icm_size[0x8]; 1195 1196 u8 reserved_at_120[0x18]; 1197 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1198 1199 u8 header_modify_sw_icm_start_address[0x40]; 1200 1201 u8 reserved_at_180[0x40]; 1202 1203 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1204 1205 u8 memic_operations[0x20]; 1206 1207 u8 reserved_at_220[0x5e0]; 1208 }; 1209 1210 struct mlx5_ifc_device_event_cap_bits { 1211 u8 user_affiliated_events[4][0x40]; 1212 1213 u8 user_unaffiliated_events[4][0x40]; 1214 }; 1215 1216 struct mlx5_ifc_virtio_emulation_cap_bits { 1217 u8 desc_tunnel_offload_type[0x1]; 1218 u8 eth_frame_offload_type[0x1]; 1219 u8 virtio_version_1_0[0x1]; 1220 u8 device_features_bits_mask[0xd]; 1221 u8 event_mode[0x8]; 1222 u8 virtio_queue_type[0x8]; 1223 1224 u8 max_tunnel_desc[0x10]; 1225 u8 reserved_at_30[0x3]; 1226 u8 log_doorbell_stride[0x5]; 1227 u8 reserved_at_38[0x3]; 1228 u8 log_doorbell_bar_size[0x5]; 1229 1230 u8 doorbell_bar_offset[0x40]; 1231 1232 u8 max_emulated_devices[0x8]; 1233 u8 max_num_virtio_queues[0x18]; 1234 1235 u8 reserved_at_a0[0x20]; 1236 1237 u8 reserved_at_c0[0x13]; 1238 u8 desc_group_mkey_supported[0x1]; 1239 u8 reserved_at_d4[0xc]; 1240 1241 u8 reserved_at_e0[0x20]; 1242 1243 u8 umem_1_buffer_param_a[0x20]; 1244 1245 u8 umem_1_buffer_param_b[0x20]; 1246 1247 u8 umem_2_buffer_param_a[0x20]; 1248 1249 u8 umem_2_buffer_param_b[0x20]; 1250 1251 u8 umem_3_buffer_param_a[0x20]; 1252 1253 u8 umem_3_buffer_param_b[0x20]; 1254 1255 u8 reserved_at_1c0[0x640]; 1256 }; 1257 1258 enum { 1259 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1260 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1261 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1262 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1263 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1264 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1265 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1266 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1267 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1268 }; 1269 1270 enum { 1271 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1272 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1273 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1274 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1275 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1276 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1277 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1278 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1279 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1280 }; 1281 1282 struct mlx5_ifc_atomic_caps_bits { 1283 u8 reserved_at_0[0x40]; 1284 1285 u8 atomic_req_8B_endianness_mode[0x2]; 1286 u8 reserved_at_42[0x4]; 1287 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1288 1289 u8 reserved_at_47[0x19]; 1290 1291 u8 reserved_at_60[0x20]; 1292 1293 u8 reserved_at_80[0x10]; 1294 u8 atomic_operations[0x10]; 1295 1296 u8 reserved_at_a0[0x10]; 1297 u8 atomic_size_qp[0x10]; 1298 1299 u8 reserved_at_c0[0x10]; 1300 u8 atomic_size_dc[0x10]; 1301 1302 u8 reserved_at_e0[0x720]; 1303 }; 1304 1305 struct mlx5_ifc_odp_cap_bits { 1306 u8 reserved_at_0[0x40]; 1307 1308 u8 sig[0x1]; 1309 u8 reserved_at_41[0x1f]; 1310 1311 u8 reserved_at_60[0x20]; 1312 1313 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1314 1315 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1316 1317 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1318 1319 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1320 1321 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1322 1323 u8 reserved_at_120[0x6E0]; 1324 }; 1325 1326 struct mlx5_ifc_tls_cap_bits { 1327 u8 tls_1_2_aes_gcm_128[0x1]; 1328 u8 tls_1_3_aes_gcm_128[0x1]; 1329 u8 tls_1_2_aes_gcm_256[0x1]; 1330 u8 tls_1_3_aes_gcm_256[0x1]; 1331 u8 reserved_at_4[0x1c]; 1332 1333 u8 reserved_at_20[0x7e0]; 1334 }; 1335 1336 struct mlx5_ifc_ipsec_cap_bits { 1337 u8 ipsec_full_offload[0x1]; 1338 u8 ipsec_crypto_offload[0x1]; 1339 u8 ipsec_esn[0x1]; 1340 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1341 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1342 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1343 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1344 u8 reserved_at_7[0x4]; 1345 u8 log_max_ipsec_offload[0x5]; 1346 u8 reserved_at_10[0x10]; 1347 1348 u8 min_log_ipsec_full_replay_window[0x8]; 1349 u8 max_log_ipsec_full_replay_window[0x8]; 1350 u8 reserved_at_30[0x7d0]; 1351 }; 1352 1353 struct mlx5_ifc_macsec_cap_bits { 1354 u8 macsec_epn[0x1]; 1355 u8 reserved_at_1[0x2]; 1356 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1357 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1358 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1359 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1360 u8 reserved_at_7[0x4]; 1361 u8 log_max_macsec_offload[0x5]; 1362 u8 reserved_at_10[0x10]; 1363 1364 u8 min_log_macsec_full_replay_window[0x8]; 1365 u8 max_log_macsec_full_replay_window[0x8]; 1366 u8 reserved_at_30[0x10]; 1367 1368 u8 reserved_at_40[0x7c0]; 1369 }; 1370 1371 enum { 1372 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1373 MLX5_WQ_TYPE_CYCLIC = 0x1, 1374 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1375 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1376 }; 1377 1378 enum { 1379 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1380 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1381 }; 1382 1383 enum { 1384 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1385 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1386 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1387 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1388 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1389 }; 1390 1391 enum { 1392 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1393 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1394 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1395 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1396 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1397 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1398 }; 1399 1400 enum { 1401 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1402 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1403 }; 1404 1405 enum { 1406 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1407 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1408 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1409 }; 1410 1411 enum { 1412 MLX5_CAP_PORT_TYPE_IB = 0x0, 1413 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1414 }; 1415 1416 enum { 1417 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1418 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1419 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1420 }; 1421 1422 enum { 1423 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1424 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1425 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1426 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1427 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1428 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1429 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1430 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1431 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1432 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1433 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1434 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1435 }; 1436 1437 enum { 1438 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1439 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1440 }; 1441 1442 #define MLX5_FC_BULK_SIZE_FACTOR 128 1443 1444 enum mlx5_fc_bulk_alloc_bitmask { 1445 MLX5_FC_BULK_128 = (1 << 0), 1446 MLX5_FC_BULK_256 = (1 << 1), 1447 MLX5_FC_BULK_512 = (1 << 2), 1448 MLX5_FC_BULK_1024 = (1 << 3), 1449 MLX5_FC_BULK_2048 = (1 << 4), 1450 MLX5_FC_BULK_4096 = (1 << 5), 1451 MLX5_FC_BULK_8192 = (1 << 6), 1452 MLX5_FC_BULK_16384 = (1 << 7), 1453 }; 1454 1455 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1456 1457 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1458 1459 enum { 1460 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1461 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1462 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1463 }; 1464 1465 struct mlx5_ifc_cmd_hca_cap_bits { 1466 u8 reserved_at_0[0x10]; 1467 u8 shared_object_to_user_object_allowed[0x1]; 1468 u8 reserved_at_13[0xe]; 1469 u8 vhca_resource_manager[0x1]; 1470 1471 u8 hca_cap_2[0x1]; 1472 u8 create_lag_when_not_master_up[0x1]; 1473 u8 dtor[0x1]; 1474 u8 event_on_vhca_state_teardown_request[0x1]; 1475 u8 event_on_vhca_state_in_use[0x1]; 1476 u8 event_on_vhca_state_active[0x1]; 1477 u8 event_on_vhca_state_allocated[0x1]; 1478 u8 event_on_vhca_state_invalid[0x1]; 1479 u8 reserved_at_28[0x8]; 1480 u8 vhca_id[0x10]; 1481 1482 u8 reserved_at_40[0x40]; 1483 1484 u8 log_max_srq_sz[0x8]; 1485 u8 log_max_qp_sz[0x8]; 1486 u8 event_cap[0x1]; 1487 u8 reserved_at_91[0x2]; 1488 u8 isolate_vl_tc_new[0x1]; 1489 u8 reserved_at_94[0x4]; 1490 u8 prio_tag_required[0x1]; 1491 u8 reserved_at_99[0x2]; 1492 u8 log_max_qp[0x5]; 1493 1494 u8 reserved_at_a0[0x3]; 1495 u8 ece_support[0x1]; 1496 u8 reserved_at_a4[0x5]; 1497 u8 reg_c_preserve[0x1]; 1498 u8 reserved_at_aa[0x1]; 1499 u8 log_max_srq[0x5]; 1500 u8 reserved_at_b0[0x1]; 1501 u8 uplink_follow[0x1]; 1502 u8 ts_cqe_to_dest_cqn[0x1]; 1503 u8 reserved_at_b3[0x6]; 1504 u8 go_back_n[0x1]; 1505 u8 shampo[0x1]; 1506 u8 reserved_at_bb[0x5]; 1507 1508 u8 max_sgl_for_optimized_performance[0x8]; 1509 u8 log_max_cq_sz[0x8]; 1510 u8 relaxed_ordering_write_umr[0x1]; 1511 u8 relaxed_ordering_read_umr[0x1]; 1512 u8 reserved_at_d2[0x7]; 1513 u8 virtio_net_device_emualtion_manager[0x1]; 1514 u8 virtio_blk_device_emualtion_manager[0x1]; 1515 u8 log_max_cq[0x5]; 1516 1517 u8 log_max_eq_sz[0x8]; 1518 u8 relaxed_ordering_write[0x1]; 1519 u8 relaxed_ordering_read_pci_enabled[0x1]; 1520 u8 log_max_mkey[0x6]; 1521 u8 reserved_at_f0[0x6]; 1522 u8 terminate_scatter_list_mkey[0x1]; 1523 u8 repeated_mkey[0x1]; 1524 u8 dump_fill_mkey[0x1]; 1525 u8 reserved_at_f9[0x2]; 1526 u8 fast_teardown[0x1]; 1527 u8 log_max_eq[0x4]; 1528 1529 u8 max_indirection[0x8]; 1530 u8 fixed_buffer_size[0x1]; 1531 u8 log_max_mrw_sz[0x7]; 1532 u8 force_teardown[0x1]; 1533 u8 reserved_at_111[0x1]; 1534 u8 log_max_bsf_list_size[0x6]; 1535 u8 umr_extended_translation_offset[0x1]; 1536 u8 null_mkey[0x1]; 1537 u8 log_max_klm_list_size[0x6]; 1538 1539 u8 reserved_at_120[0x2]; 1540 u8 qpc_extension[0x1]; 1541 u8 reserved_at_123[0x7]; 1542 u8 log_max_ra_req_dc[0x6]; 1543 u8 reserved_at_130[0x2]; 1544 u8 eth_wqe_too_small[0x1]; 1545 u8 reserved_at_133[0x6]; 1546 u8 vnic_env_cq_overrun[0x1]; 1547 u8 log_max_ra_res_dc[0x6]; 1548 1549 u8 reserved_at_140[0x5]; 1550 u8 release_all_pages[0x1]; 1551 u8 must_not_use[0x1]; 1552 u8 reserved_at_147[0x2]; 1553 u8 roce_accl[0x1]; 1554 u8 log_max_ra_req_qp[0x6]; 1555 u8 reserved_at_150[0xa]; 1556 u8 log_max_ra_res_qp[0x6]; 1557 1558 u8 end_pad[0x1]; 1559 u8 cc_query_allowed[0x1]; 1560 u8 cc_modify_allowed[0x1]; 1561 u8 start_pad[0x1]; 1562 u8 cache_line_128byte[0x1]; 1563 u8 reserved_at_165[0x4]; 1564 u8 rts2rts_qp_counters_set_id[0x1]; 1565 u8 reserved_at_16a[0x2]; 1566 u8 vnic_env_int_rq_oob[0x1]; 1567 u8 sbcam_reg[0x1]; 1568 u8 reserved_at_16e[0x1]; 1569 u8 qcam_reg[0x1]; 1570 u8 gid_table_size[0x10]; 1571 1572 u8 out_of_seq_cnt[0x1]; 1573 u8 vport_counters[0x1]; 1574 u8 retransmission_q_counters[0x1]; 1575 u8 debug[0x1]; 1576 u8 modify_rq_counter_set_id[0x1]; 1577 u8 rq_delay_drop[0x1]; 1578 u8 max_qp_cnt[0xa]; 1579 u8 pkey_table_size[0x10]; 1580 1581 u8 vport_group_manager[0x1]; 1582 u8 vhca_group_manager[0x1]; 1583 u8 ib_virt[0x1]; 1584 u8 eth_virt[0x1]; 1585 u8 vnic_env_queue_counters[0x1]; 1586 u8 ets[0x1]; 1587 u8 nic_flow_table[0x1]; 1588 u8 eswitch_manager[0x1]; 1589 u8 device_memory[0x1]; 1590 u8 mcam_reg[0x1]; 1591 u8 pcam_reg[0x1]; 1592 u8 local_ca_ack_delay[0x5]; 1593 u8 port_module_event[0x1]; 1594 u8 enhanced_error_q_counters[0x1]; 1595 u8 ports_check[0x1]; 1596 u8 reserved_at_1b3[0x1]; 1597 u8 disable_link_up[0x1]; 1598 u8 beacon_led[0x1]; 1599 u8 port_type[0x2]; 1600 u8 num_ports[0x8]; 1601 1602 u8 reserved_at_1c0[0x1]; 1603 u8 pps[0x1]; 1604 u8 pps_modify[0x1]; 1605 u8 log_max_msg[0x5]; 1606 u8 reserved_at_1c8[0x4]; 1607 u8 max_tc[0x4]; 1608 u8 temp_warn_event[0x1]; 1609 u8 dcbx[0x1]; 1610 u8 general_notification_event[0x1]; 1611 u8 reserved_at_1d3[0x2]; 1612 u8 fpga[0x1]; 1613 u8 rol_s[0x1]; 1614 u8 rol_g[0x1]; 1615 u8 reserved_at_1d8[0x1]; 1616 u8 wol_s[0x1]; 1617 u8 wol_g[0x1]; 1618 u8 wol_a[0x1]; 1619 u8 wol_b[0x1]; 1620 u8 wol_m[0x1]; 1621 u8 wol_u[0x1]; 1622 u8 wol_p[0x1]; 1623 1624 u8 stat_rate_support[0x10]; 1625 u8 reserved_at_1f0[0x1]; 1626 u8 pci_sync_for_fw_update_event[0x1]; 1627 u8 reserved_at_1f2[0x6]; 1628 u8 init2_lag_tx_port_affinity[0x1]; 1629 u8 reserved_at_1fa[0x3]; 1630 u8 cqe_version[0x4]; 1631 1632 u8 compact_address_vector[0x1]; 1633 u8 striding_rq[0x1]; 1634 u8 reserved_at_202[0x1]; 1635 u8 ipoib_enhanced_offloads[0x1]; 1636 u8 ipoib_basic_offloads[0x1]; 1637 u8 reserved_at_205[0x1]; 1638 u8 repeated_block_disabled[0x1]; 1639 u8 umr_modify_entity_size_disabled[0x1]; 1640 u8 umr_modify_atomic_disabled[0x1]; 1641 u8 umr_indirect_mkey_disabled[0x1]; 1642 u8 umr_fence[0x2]; 1643 u8 dc_req_scat_data_cqe[0x1]; 1644 u8 reserved_at_20d[0x2]; 1645 u8 drain_sigerr[0x1]; 1646 u8 cmdif_checksum[0x2]; 1647 u8 sigerr_cqe[0x1]; 1648 u8 reserved_at_213[0x1]; 1649 u8 wq_signature[0x1]; 1650 u8 sctr_data_cqe[0x1]; 1651 u8 reserved_at_216[0x1]; 1652 u8 sho[0x1]; 1653 u8 tph[0x1]; 1654 u8 rf[0x1]; 1655 u8 dct[0x1]; 1656 u8 qos[0x1]; 1657 u8 eth_net_offloads[0x1]; 1658 u8 roce[0x1]; 1659 u8 atomic[0x1]; 1660 u8 reserved_at_21f[0x1]; 1661 1662 u8 cq_oi[0x1]; 1663 u8 cq_resize[0x1]; 1664 u8 cq_moderation[0x1]; 1665 u8 reserved_at_223[0x3]; 1666 u8 cq_eq_remap[0x1]; 1667 u8 pg[0x1]; 1668 u8 block_lb_mc[0x1]; 1669 u8 reserved_at_229[0x1]; 1670 u8 scqe_break_moderation[0x1]; 1671 u8 cq_period_start_from_cqe[0x1]; 1672 u8 cd[0x1]; 1673 u8 reserved_at_22d[0x1]; 1674 u8 apm[0x1]; 1675 u8 vector_calc[0x1]; 1676 u8 umr_ptr_rlky[0x1]; 1677 u8 imaicl[0x1]; 1678 u8 qp_packet_based[0x1]; 1679 u8 reserved_at_233[0x3]; 1680 u8 qkv[0x1]; 1681 u8 pkv[0x1]; 1682 u8 set_deth_sqpn[0x1]; 1683 u8 reserved_at_239[0x3]; 1684 u8 xrc[0x1]; 1685 u8 ud[0x1]; 1686 u8 uc[0x1]; 1687 u8 rc[0x1]; 1688 1689 u8 uar_4k[0x1]; 1690 u8 reserved_at_241[0x7]; 1691 u8 fl_rc_qp_when_roce_disabled[0x1]; 1692 u8 regexp_params[0x1]; 1693 u8 uar_sz[0x6]; 1694 u8 port_selection_cap[0x1]; 1695 u8 reserved_at_251[0x1]; 1696 u8 umem_uid_0[0x1]; 1697 u8 reserved_at_253[0x5]; 1698 u8 log_pg_sz[0x8]; 1699 1700 u8 bf[0x1]; 1701 u8 driver_version[0x1]; 1702 u8 pad_tx_eth_packet[0x1]; 1703 u8 reserved_at_263[0x3]; 1704 u8 mkey_by_name[0x1]; 1705 u8 reserved_at_267[0x4]; 1706 1707 u8 log_bf_reg_size[0x5]; 1708 1709 u8 reserved_at_270[0x3]; 1710 u8 qp_error_syndrome[0x1]; 1711 u8 reserved_at_274[0x2]; 1712 u8 lag_dct[0x2]; 1713 u8 lag_tx_port_affinity[0x1]; 1714 u8 lag_native_fdb_selection[0x1]; 1715 u8 reserved_at_27a[0x1]; 1716 u8 lag_master[0x1]; 1717 u8 num_lag_ports[0x4]; 1718 1719 u8 reserved_at_280[0x10]; 1720 u8 max_wqe_sz_sq[0x10]; 1721 1722 u8 reserved_at_2a0[0x10]; 1723 u8 max_wqe_sz_rq[0x10]; 1724 1725 u8 max_flow_counter_31_16[0x10]; 1726 u8 max_wqe_sz_sq_dc[0x10]; 1727 1728 u8 reserved_at_2e0[0x7]; 1729 u8 max_qp_mcg[0x19]; 1730 1731 u8 reserved_at_300[0x10]; 1732 u8 flow_counter_bulk_alloc[0x8]; 1733 u8 log_max_mcg[0x8]; 1734 1735 u8 reserved_at_320[0x3]; 1736 u8 log_max_transport_domain[0x5]; 1737 u8 reserved_at_328[0x2]; 1738 u8 relaxed_ordering_read[0x1]; 1739 u8 log_max_pd[0x5]; 1740 u8 reserved_at_330[0x6]; 1741 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1742 u8 vnic_env_cnt_steering_fail[0x1]; 1743 u8 vport_counter_local_loopback[0x1]; 1744 u8 q_counter_aggregation[0x1]; 1745 u8 q_counter_other_vport[0x1]; 1746 u8 log_max_xrcd[0x5]; 1747 1748 u8 nic_receive_steering_discard[0x1]; 1749 u8 receive_discard_vport_down[0x1]; 1750 u8 transmit_discard_vport_down[0x1]; 1751 u8 eq_overrun_count[0x1]; 1752 u8 reserved_at_344[0x1]; 1753 u8 invalid_command_count[0x1]; 1754 u8 quota_exceeded_count[0x1]; 1755 u8 reserved_at_347[0x1]; 1756 u8 log_max_flow_counter_bulk[0x8]; 1757 u8 max_flow_counter_15_0[0x10]; 1758 1759 1760 u8 reserved_at_360[0x3]; 1761 u8 log_max_rq[0x5]; 1762 u8 reserved_at_368[0x3]; 1763 u8 log_max_sq[0x5]; 1764 u8 reserved_at_370[0x3]; 1765 u8 log_max_tir[0x5]; 1766 u8 reserved_at_378[0x3]; 1767 u8 log_max_tis[0x5]; 1768 1769 u8 basic_cyclic_rcv_wqe[0x1]; 1770 u8 reserved_at_381[0x2]; 1771 u8 log_max_rmp[0x5]; 1772 u8 reserved_at_388[0x3]; 1773 u8 log_max_rqt[0x5]; 1774 u8 reserved_at_390[0x3]; 1775 u8 log_max_rqt_size[0x5]; 1776 u8 reserved_at_398[0x3]; 1777 u8 log_max_tis_per_sq[0x5]; 1778 1779 u8 ext_stride_num_range[0x1]; 1780 u8 roce_rw_supported[0x1]; 1781 u8 log_max_current_uc_list_wr_supported[0x1]; 1782 u8 log_max_stride_sz_rq[0x5]; 1783 u8 reserved_at_3a8[0x3]; 1784 u8 log_min_stride_sz_rq[0x5]; 1785 u8 reserved_at_3b0[0x3]; 1786 u8 log_max_stride_sz_sq[0x5]; 1787 u8 reserved_at_3b8[0x3]; 1788 u8 log_min_stride_sz_sq[0x5]; 1789 1790 u8 hairpin[0x1]; 1791 u8 reserved_at_3c1[0x2]; 1792 u8 log_max_hairpin_queues[0x5]; 1793 u8 reserved_at_3c8[0x3]; 1794 u8 log_max_hairpin_wq_data_sz[0x5]; 1795 u8 reserved_at_3d0[0x3]; 1796 u8 log_max_hairpin_num_packets[0x5]; 1797 u8 reserved_at_3d8[0x3]; 1798 u8 log_max_wq_sz[0x5]; 1799 1800 u8 nic_vport_change_event[0x1]; 1801 u8 disable_local_lb_uc[0x1]; 1802 u8 disable_local_lb_mc[0x1]; 1803 u8 log_min_hairpin_wq_data_sz[0x5]; 1804 u8 reserved_at_3e8[0x1]; 1805 u8 silent_mode[0x1]; 1806 u8 vhca_state[0x1]; 1807 u8 log_max_vlan_list[0x5]; 1808 u8 reserved_at_3f0[0x3]; 1809 u8 log_max_current_mc_list[0x5]; 1810 u8 reserved_at_3f8[0x3]; 1811 u8 log_max_current_uc_list[0x5]; 1812 1813 u8 general_obj_types[0x40]; 1814 1815 u8 sq_ts_format[0x2]; 1816 u8 rq_ts_format[0x2]; 1817 u8 steering_format_version[0x4]; 1818 u8 create_qp_start_hint[0x18]; 1819 1820 u8 reserved_at_460[0x1]; 1821 u8 ats[0x1]; 1822 u8 cross_vhca_rqt[0x1]; 1823 u8 log_max_uctx[0x5]; 1824 u8 reserved_at_468[0x1]; 1825 u8 crypto[0x1]; 1826 u8 ipsec_offload[0x1]; 1827 u8 log_max_umem[0x5]; 1828 u8 max_num_eqs[0x10]; 1829 1830 u8 reserved_at_480[0x1]; 1831 u8 tls_tx[0x1]; 1832 u8 tls_rx[0x1]; 1833 u8 log_max_l2_table[0x5]; 1834 u8 reserved_at_488[0x8]; 1835 u8 log_uar_page_sz[0x10]; 1836 1837 u8 reserved_at_4a0[0x20]; 1838 u8 device_frequency_mhz[0x20]; 1839 u8 device_frequency_khz[0x20]; 1840 1841 u8 reserved_at_500[0x20]; 1842 u8 num_of_uars_per_page[0x20]; 1843 1844 u8 flex_parser_protocols[0x20]; 1845 1846 u8 max_geneve_tlv_options[0x8]; 1847 u8 reserved_at_568[0x3]; 1848 u8 max_geneve_tlv_option_data_len[0x5]; 1849 u8 reserved_at_570[0x9]; 1850 u8 adv_virtualization[0x1]; 1851 u8 reserved_at_57a[0x6]; 1852 1853 u8 reserved_at_580[0xb]; 1854 u8 log_max_dci_stream_channels[0x5]; 1855 u8 reserved_at_590[0x3]; 1856 u8 log_max_dci_errored_streams[0x5]; 1857 u8 reserved_at_598[0x8]; 1858 1859 u8 reserved_at_5a0[0x10]; 1860 u8 enhanced_cqe_compression[0x1]; 1861 u8 reserved_at_5b1[0x2]; 1862 u8 log_max_dek[0x5]; 1863 u8 reserved_at_5b8[0x4]; 1864 u8 mini_cqe_resp_stride_index[0x1]; 1865 u8 cqe_128_always[0x1]; 1866 u8 cqe_compression_128[0x1]; 1867 u8 cqe_compression[0x1]; 1868 1869 u8 cqe_compression_timeout[0x10]; 1870 u8 cqe_compression_max_num[0x10]; 1871 1872 u8 reserved_at_5e0[0x8]; 1873 u8 flex_parser_id_gtpu_dw_0[0x4]; 1874 u8 reserved_at_5ec[0x4]; 1875 u8 tag_matching[0x1]; 1876 u8 rndv_offload_rc[0x1]; 1877 u8 rndv_offload_dc[0x1]; 1878 u8 log_tag_matching_list_sz[0x5]; 1879 u8 reserved_at_5f8[0x3]; 1880 u8 log_max_xrq[0x5]; 1881 1882 u8 affiliate_nic_vport_criteria[0x8]; 1883 u8 native_port_num[0x8]; 1884 u8 num_vhca_ports[0x8]; 1885 u8 flex_parser_id_gtpu_teid[0x4]; 1886 u8 reserved_at_61c[0x2]; 1887 u8 sw_owner_id[0x1]; 1888 u8 reserved_at_61f[0x1]; 1889 1890 u8 max_num_of_monitor_counters[0x10]; 1891 u8 num_ppcnt_monitor_counters[0x10]; 1892 1893 u8 max_num_sf[0x10]; 1894 u8 num_q_monitor_counters[0x10]; 1895 1896 u8 reserved_at_660[0x20]; 1897 1898 u8 sf[0x1]; 1899 u8 sf_set_partition[0x1]; 1900 u8 reserved_at_682[0x1]; 1901 u8 log_max_sf[0x5]; 1902 u8 apu[0x1]; 1903 u8 reserved_at_689[0x4]; 1904 u8 migration[0x1]; 1905 u8 reserved_at_68e[0x2]; 1906 u8 log_min_sf_size[0x8]; 1907 u8 max_num_sf_partitions[0x8]; 1908 1909 u8 uctx_cap[0x20]; 1910 1911 u8 reserved_at_6c0[0x4]; 1912 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1913 u8 flex_parser_id_icmp_dw1[0x4]; 1914 u8 flex_parser_id_icmp_dw0[0x4]; 1915 u8 flex_parser_id_icmpv6_dw1[0x4]; 1916 u8 flex_parser_id_icmpv6_dw0[0x4]; 1917 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1918 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1919 1920 u8 max_num_match_definer[0x10]; 1921 u8 sf_base_id[0x10]; 1922 1923 u8 flex_parser_id_gtpu_dw_2[0x4]; 1924 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1925 u8 num_total_dynamic_vf_msix[0x18]; 1926 u8 reserved_at_720[0x14]; 1927 u8 dynamic_msix_table_size[0xc]; 1928 u8 reserved_at_740[0xc]; 1929 u8 min_dynamic_vf_msix_table_size[0x4]; 1930 u8 reserved_at_750[0x4]; 1931 u8 max_dynamic_vf_msix_table_size[0xc]; 1932 1933 u8 reserved_at_760[0x3]; 1934 u8 log_max_num_header_modify_argument[0x5]; 1935 u8 reserved_at_768[0x4]; 1936 u8 log_header_modify_argument_granularity[0x4]; 1937 u8 reserved_at_770[0x3]; 1938 u8 log_header_modify_argument_max_alloc[0x5]; 1939 u8 reserved_at_778[0x8]; 1940 1941 u8 vhca_tunnel_commands[0x40]; 1942 u8 match_definer_format_supported[0x40]; 1943 }; 1944 1945 enum { 1946 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 1947 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 1948 }; 1949 1950 enum { 1951 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 1952 }; 1953 1954 struct mlx5_ifc_cmd_hca_cap_2_bits { 1955 u8 reserved_at_0[0x80]; 1956 1957 u8 migratable[0x1]; 1958 u8 reserved_at_81[0x1f]; 1959 1960 u8 max_reformat_insert_size[0x8]; 1961 u8 max_reformat_insert_offset[0x8]; 1962 u8 max_reformat_remove_size[0x8]; 1963 u8 max_reformat_remove_offset[0x8]; 1964 1965 u8 reserved_at_c0[0x8]; 1966 u8 migration_multi_load[0x1]; 1967 u8 migration_tracking_state[0x1]; 1968 u8 reserved_at_ca[0x6]; 1969 u8 migration_in_chunks[0x1]; 1970 u8 reserved_at_d1[0xf]; 1971 1972 u8 cross_vhca_object_to_object_supported[0x20]; 1973 1974 u8 allowed_object_for_other_vhca_access[0x40]; 1975 1976 u8 reserved_at_140[0x60]; 1977 1978 u8 flow_table_type_2_type[0x8]; 1979 u8 reserved_at_1a8[0x3]; 1980 u8 log_min_mkey_entity_size[0x5]; 1981 u8 reserved_at_1b0[0x10]; 1982 1983 u8 reserved_at_1c0[0x60]; 1984 1985 u8 reserved_at_220[0x1]; 1986 u8 sw_vhca_id_valid[0x1]; 1987 u8 sw_vhca_id[0xe]; 1988 u8 reserved_at_230[0x10]; 1989 1990 u8 reserved_at_240[0xb]; 1991 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1992 u8 reserved_at_250[0x10]; 1993 1994 u8 reserved_at_260[0x120]; 1995 u8 reserved_at_380[0x10]; 1996 u8 ec_vf_vport_base[0x10]; 1997 1998 u8 reserved_at_3a0[0x10]; 1999 u8 max_rqt_vhca_id[0x10]; 2000 2001 u8 reserved_at_3c0[0x440]; 2002 }; 2003 2004 enum mlx5_ifc_flow_destination_type { 2005 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2006 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2007 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2008 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2009 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2010 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2011 }; 2012 2013 enum mlx5_flow_table_miss_action { 2014 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2015 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2016 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2017 }; 2018 2019 struct mlx5_ifc_dest_format_struct_bits { 2020 u8 destination_type[0x8]; 2021 u8 destination_id[0x18]; 2022 2023 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2024 u8 packet_reformat[0x1]; 2025 u8 reserved_at_22[0x6]; 2026 u8 destination_table_type[0x8]; 2027 u8 destination_eswitch_owner_vhca_id[0x10]; 2028 }; 2029 2030 struct mlx5_ifc_flow_counter_list_bits { 2031 u8 flow_counter_id[0x20]; 2032 2033 u8 reserved_at_20[0x20]; 2034 }; 2035 2036 struct mlx5_ifc_extended_dest_format_bits { 2037 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2038 2039 u8 packet_reformat_id[0x20]; 2040 2041 u8 reserved_at_60[0x20]; 2042 }; 2043 2044 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2045 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2046 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2047 }; 2048 2049 struct mlx5_ifc_fte_match_param_bits { 2050 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2051 2052 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2053 2054 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2055 2056 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2057 2058 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2059 2060 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2061 2062 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2063 2064 u8 reserved_at_e00[0x200]; 2065 }; 2066 2067 enum { 2068 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2069 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2070 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2071 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2072 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2073 }; 2074 2075 struct mlx5_ifc_rx_hash_field_select_bits { 2076 u8 l3_prot_type[0x1]; 2077 u8 l4_prot_type[0x1]; 2078 u8 selected_fields[0x1e]; 2079 }; 2080 2081 enum { 2082 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2083 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2084 }; 2085 2086 enum { 2087 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2088 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2089 }; 2090 2091 struct mlx5_ifc_wq_bits { 2092 u8 wq_type[0x4]; 2093 u8 wq_signature[0x1]; 2094 u8 end_padding_mode[0x2]; 2095 u8 cd_slave[0x1]; 2096 u8 reserved_at_8[0x18]; 2097 2098 u8 hds_skip_first_sge[0x1]; 2099 u8 log2_hds_buf_size[0x3]; 2100 u8 reserved_at_24[0x7]; 2101 u8 page_offset[0x5]; 2102 u8 lwm[0x10]; 2103 2104 u8 reserved_at_40[0x8]; 2105 u8 pd[0x18]; 2106 2107 u8 reserved_at_60[0x8]; 2108 u8 uar_page[0x18]; 2109 2110 u8 dbr_addr[0x40]; 2111 2112 u8 hw_counter[0x20]; 2113 2114 u8 sw_counter[0x20]; 2115 2116 u8 reserved_at_100[0xc]; 2117 u8 log_wq_stride[0x4]; 2118 u8 reserved_at_110[0x3]; 2119 u8 log_wq_pg_sz[0x5]; 2120 u8 reserved_at_118[0x3]; 2121 u8 log_wq_sz[0x5]; 2122 2123 u8 dbr_umem_valid[0x1]; 2124 u8 wq_umem_valid[0x1]; 2125 u8 reserved_at_122[0x1]; 2126 u8 log_hairpin_num_packets[0x5]; 2127 u8 reserved_at_128[0x3]; 2128 u8 log_hairpin_data_sz[0x5]; 2129 2130 u8 reserved_at_130[0x4]; 2131 u8 log_wqe_num_of_strides[0x4]; 2132 u8 two_byte_shift_en[0x1]; 2133 u8 reserved_at_139[0x4]; 2134 u8 log_wqe_stride_size[0x3]; 2135 2136 u8 reserved_at_140[0x80]; 2137 2138 u8 headers_mkey[0x20]; 2139 2140 u8 shampo_enable[0x1]; 2141 u8 reserved_at_1e1[0x4]; 2142 u8 log_reservation_size[0x3]; 2143 u8 reserved_at_1e8[0x5]; 2144 u8 log_max_num_of_packets_per_reservation[0x3]; 2145 u8 reserved_at_1f0[0x6]; 2146 u8 log_headers_entry_size[0x2]; 2147 u8 reserved_at_1f8[0x4]; 2148 u8 log_headers_buffer_entry_num[0x4]; 2149 2150 u8 reserved_at_200[0x400]; 2151 2152 struct mlx5_ifc_cmd_pas_bits pas[]; 2153 }; 2154 2155 struct mlx5_ifc_rq_num_bits { 2156 u8 reserved_at_0[0x8]; 2157 u8 rq_num[0x18]; 2158 }; 2159 2160 struct mlx5_ifc_rq_vhca_bits { 2161 u8 reserved_at_0[0x8]; 2162 u8 rq_num[0x18]; 2163 u8 reserved_at_20[0x10]; 2164 u8 rq_vhca_id[0x10]; 2165 }; 2166 2167 struct mlx5_ifc_mac_address_layout_bits { 2168 u8 reserved_at_0[0x10]; 2169 u8 mac_addr_47_32[0x10]; 2170 2171 u8 mac_addr_31_0[0x20]; 2172 }; 2173 2174 struct mlx5_ifc_vlan_layout_bits { 2175 u8 reserved_at_0[0x14]; 2176 u8 vlan[0x0c]; 2177 2178 u8 reserved_at_20[0x20]; 2179 }; 2180 2181 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2182 u8 reserved_at_0[0xa0]; 2183 2184 u8 min_time_between_cnps[0x20]; 2185 2186 u8 reserved_at_c0[0x12]; 2187 u8 cnp_dscp[0x6]; 2188 u8 reserved_at_d8[0x4]; 2189 u8 cnp_prio_mode[0x1]; 2190 u8 cnp_802p_prio[0x3]; 2191 2192 u8 reserved_at_e0[0x720]; 2193 }; 2194 2195 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2196 u8 reserved_at_0[0x60]; 2197 2198 u8 reserved_at_60[0x4]; 2199 u8 clamp_tgt_rate[0x1]; 2200 u8 reserved_at_65[0x3]; 2201 u8 clamp_tgt_rate_after_time_inc[0x1]; 2202 u8 reserved_at_69[0x17]; 2203 2204 u8 reserved_at_80[0x20]; 2205 2206 u8 rpg_time_reset[0x20]; 2207 2208 u8 rpg_byte_reset[0x20]; 2209 2210 u8 rpg_threshold[0x20]; 2211 2212 u8 rpg_max_rate[0x20]; 2213 2214 u8 rpg_ai_rate[0x20]; 2215 2216 u8 rpg_hai_rate[0x20]; 2217 2218 u8 rpg_gd[0x20]; 2219 2220 u8 rpg_min_dec_fac[0x20]; 2221 2222 u8 rpg_min_rate[0x20]; 2223 2224 u8 reserved_at_1c0[0xe0]; 2225 2226 u8 rate_to_set_on_first_cnp[0x20]; 2227 2228 u8 dce_tcp_g[0x20]; 2229 2230 u8 dce_tcp_rtt[0x20]; 2231 2232 u8 rate_reduce_monitor_period[0x20]; 2233 2234 u8 reserved_at_320[0x20]; 2235 2236 u8 initial_alpha_value[0x20]; 2237 2238 u8 reserved_at_360[0x4a0]; 2239 }; 2240 2241 struct mlx5_ifc_cong_control_r_roce_general_bits { 2242 u8 reserved_at_0[0x80]; 2243 2244 u8 reserved_at_80[0x10]; 2245 u8 rtt_resp_dscp_valid[0x1]; 2246 u8 reserved_at_91[0x9]; 2247 u8 rtt_resp_dscp[0x6]; 2248 2249 u8 reserved_at_a0[0x760]; 2250 }; 2251 2252 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2253 u8 reserved_at_0[0x80]; 2254 2255 u8 rppp_max_rps[0x20]; 2256 2257 u8 rpg_time_reset[0x20]; 2258 2259 u8 rpg_byte_reset[0x20]; 2260 2261 u8 rpg_threshold[0x20]; 2262 2263 u8 rpg_max_rate[0x20]; 2264 2265 u8 rpg_ai_rate[0x20]; 2266 2267 u8 rpg_hai_rate[0x20]; 2268 2269 u8 rpg_gd[0x20]; 2270 2271 u8 rpg_min_dec_fac[0x20]; 2272 2273 u8 rpg_min_rate[0x20]; 2274 2275 u8 reserved_at_1c0[0x640]; 2276 }; 2277 2278 enum { 2279 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2280 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2281 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2282 }; 2283 2284 struct mlx5_ifc_resize_field_select_bits { 2285 u8 resize_field_select[0x20]; 2286 }; 2287 2288 struct mlx5_ifc_resource_dump_bits { 2289 u8 more_dump[0x1]; 2290 u8 inline_dump[0x1]; 2291 u8 reserved_at_2[0xa]; 2292 u8 seq_num[0x4]; 2293 u8 segment_type[0x10]; 2294 2295 u8 reserved_at_20[0x10]; 2296 u8 vhca_id[0x10]; 2297 2298 u8 index1[0x20]; 2299 2300 u8 index2[0x20]; 2301 2302 u8 num_of_obj1[0x10]; 2303 u8 num_of_obj2[0x10]; 2304 2305 u8 reserved_at_a0[0x20]; 2306 2307 u8 device_opaque[0x40]; 2308 2309 u8 mkey[0x20]; 2310 2311 u8 size[0x20]; 2312 2313 u8 address[0x40]; 2314 2315 u8 inline_data[52][0x20]; 2316 }; 2317 2318 struct mlx5_ifc_resource_dump_menu_record_bits { 2319 u8 reserved_at_0[0x4]; 2320 u8 num_of_obj2_supports_active[0x1]; 2321 u8 num_of_obj2_supports_all[0x1]; 2322 u8 must_have_num_of_obj2[0x1]; 2323 u8 support_num_of_obj2[0x1]; 2324 u8 num_of_obj1_supports_active[0x1]; 2325 u8 num_of_obj1_supports_all[0x1]; 2326 u8 must_have_num_of_obj1[0x1]; 2327 u8 support_num_of_obj1[0x1]; 2328 u8 must_have_index2[0x1]; 2329 u8 support_index2[0x1]; 2330 u8 must_have_index1[0x1]; 2331 u8 support_index1[0x1]; 2332 u8 segment_type[0x10]; 2333 2334 u8 segment_name[4][0x20]; 2335 2336 u8 index1_name[4][0x20]; 2337 2338 u8 index2_name[4][0x20]; 2339 }; 2340 2341 struct mlx5_ifc_resource_dump_segment_header_bits { 2342 u8 length_dw[0x10]; 2343 u8 segment_type[0x10]; 2344 }; 2345 2346 struct mlx5_ifc_resource_dump_command_segment_bits { 2347 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2348 2349 u8 segment_called[0x10]; 2350 u8 vhca_id[0x10]; 2351 2352 u8 index1[0x20]; 2353 2354 u8 index2[0x20]; 2355 2356 u8 num_of_obj1[0x10]; 2357 u8 num_of_obj2[0x10]; 2358 }; 2359 2360 struct mlx5_ifc_resource_dump_error_segment_bits { 2361 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2362 2363 u8 reserved_at_20[0x10]; 2364 u8 syndrome_id[0x10]; 2365 2366 u8 reserved_at_40[0x40]; 2367 2368 u8 error[8][0x20]; 2369 }; 2370 2371 struct mlx5_ifc_resource_dump_info_segment_bits { 2372 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2373 2374 u8 reserved_at_20[0x18]; 2375 u8 dump_version[0x8]; 2376 2377 u8 hw_version[0x20]; 2378 2379 u8 fw_version[0x20]; 2380 }; 2381 2382 struct mlx5_ifc_resource_dump_menu_segment_bits { 2383 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2384 2385 u8 reserved_at_20[0x10]; 2386 u8 num_of_records[0x10]; 2387 2388 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2389 }; 2390 2391 struct mlx5_ifc_resource_dump_resource_segment_bits { 2392 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2393 2394 u8 reserved_at_20[0x20]; 2395 2396 u8 index1[0x20]; 2397 2398 u8 index2[0x20]; 2399 2400 u8 payload[][0x20]; 2401 }; 2402 2403 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2404 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2405 }; 2406 2407 struct mlx5_ifc_menu_resource_dump_response_bits { 2408 struct mlx5_ifc_resource_dump_info_segment_bits info; 2409 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2410 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2411 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2412 }; 2413 2414 enum { 2415 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2416 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2417 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2418 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2419 }; 2420 2421 struct mlx5_ifc_modify_field_select_bits { 2422 u8 modify_field_select[0x20]; 2423 }; 2424 2425 struct mlx5_ifc_field_select_r_roce_np_bits { 2426 u8 field_select_r_roce_np[0x20]; 2427 }; 2428 2429 struct mlx5_ifc_field_select_r_roce_rp_bits { 2430 u8 field_select_r_roce_rp[0x20]; 2431 }; 2432 2433 enum { 2434 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2435 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2436 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2437 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2438 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2439 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2440 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2441 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2442 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2443 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2444 }; 2445 2446 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2447 u8 field_select_8021qaurp[0x20]; 2448 }; 2449 2450 struct mlx5_ifc_phys_layer_cntrs_bits { 2451 u8 time_since_last_clear_high[0x20]; 2452 2453 u8 time_since_last_clear_low[0x20]; 2454 2455 u8 symbol_errors_high[0x20]; 2456 2457 u8 symbol_errors_low[0x20]; 2458 2459 u8 sync_headers_errors_high[0x20]; 2460 2461 u8 sync_headers_errors_low[0x20]; 2462 2463 u8 edpl_bip_errors_lane0_high[0x20]; 2464 2465 u8 edpl_bip_errors_lane0_low[0x20]; 2466 2467 u8 edpl_bip_errors_lane1_high[0x20]; 2468 2469 u8 edpl_bip_errors_lane1_low[0x20]; 2470 2471 u8 edpl_bip_errors_lane2_high[0x20]; 2472 2473 u8 edpl_bip_errors_lane2_low[0x20]; 2474 2475 u8 edpl_bip_errors_lane3_high[0x20]; 2476 2477 u8 edpl_bip_errors_lane3_low[0x20]; 2478 2479 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2480 2481 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2482 2483 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2484 2485 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2486 2487 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2488 2489 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2490 2491 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2492 2493 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2494 2495 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2496 2497 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2498 2499 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2500 2501 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2502 2503 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2504 2505 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2506 2507 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2508 2509 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2510 2511 u8 rs_fec_corrected_blocks_high[0x20]; 2512 2513 u8 rs_fec_corrected_blocks_low[0x20]; 2514 2515 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2516 2517 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2518 2519 u8 rs_fec_no_errors_blocks_high[0x20]; 2520 2521 u8 rs_fec_no_errors_blocks_low[0x20]; 2522 2523 u8 rs_fec_single_error_blocks_high[0x20]; 2524 2525 u8 rs_fec_single_error_blocks_low[0x20]; 2526 2527 u8 rs_fec_corrected_symbols_total_high[0x20]; 2528 2529 u8 rs_fec_corrected_symbols_total_low[0x20]; 2530 2531 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2532 2533 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2534 2535 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2536 2537 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2538 2539 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2540 2541 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2542 2543 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2544 2545 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2546 2547 u8 link_down_events[0x20]; 2548 2549 u8 successful_recovery_events[0x20]; 2550 2551 u8 reserved_at_640[0x180]; 2552 }; 2553 2554 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2555 u8 time_since_last_clear_high[0x20]; 2556 2557 u8 time_since_last_clear_low[0x20]; 2558 2559 u8 phy_received_bits_high[0x20]; 2560 2561 u8 phy_received_bits_low[0x20]; 2562 2563 u8 phy_symbol_errors_high[0x20]; 2564 2565 u8 phy_symbol_errors_low[0x20]; 2566 2567 u8 phy_corrected_bits_high[0x20]; 2568 2569 u8 phy_corrected_bits_low[0x20]; 2570 2571 u8 phy_corrected_bits_lane0_high[0x20]; 2572 2573 u8 phy_corrected_bits_lane0_low[0x20]; 2574 2575 u8 phy_corrected_bits_lane1_high[0x20]; 2576 2577 u8 phy_corrected_bits_lane1_low[0x20]; 2578 2579 u8 phy_corrected_bits_lane2_high[0x20]; 2580 2581 u8 phy_corrected_bits_lane2_low[0x20]; 2582 2583 u8 phy_corrected_bits_lane3_high[0x20]; 2584 2585 u8 phy_corrected_bits_lane3_low[0x20]; 2586 2587 u8 reserved_at_200[0x5c0]; 2588 }; 2589 2590 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2591 u8 symbol_error_counter[0x10]; 2592 2593 u8 link_error_recovery_counter[0x8]; 2594 2595 u8 link_downed_counter[0x8]; 2596 2597 u8 port_rcv_errors[0x10]; 2598 2599 u8 port_rcv_remote_physical_errors[0x10]; 2600 2601 u8 port_rcv_switch_relay_errors[0x10]; 2602 2603 u8 port_xmit_discards[0x10]; 2604 2605 u8 port_xmit_constraint_errors[0x8]; 2606 2607 u8 port_rcv_constraint_errors[0x8]; 2608 2609 u8 reserved_at_70[0x8]; 2610 2611 u8 link_overrun_errors[0x8]; 2612 2613 u8 reserved_at_80[0x10]; 2614 2615 u8 vl_15_dropped[0x10]; 2616 2617 u8 reserved_at_a0[0x80]; 2618 2619 u8 port_xmit_wait[0x20]; 2620 }; 2621 2622 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2623 u8 transmit_queue_high[0x20]; 2624 2625 u8 transmit_queue_low[0x20]; 2626 2627 u8 no_buffer_discard_uc_high[0x20]; 2628 2629 u8 no_buffer_discard_uc_low[0x20]; 2630 2631 u8 reserved_at_80[0x740]; 2632 }; 2633 2634 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2635 u8 wred_discard_high[0x20]; 2636 2637 u8 wred_discard_low[0x20]; 2638 2639 u8 ecn_marked_tc_high[0x20]; 2640 2641 u8 ecn_marked_tc_low[0x20]; 2642 2643 u8 reserved_at_80[0x740]; 2644 }; 2645 2646 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2647 u8 rx_octets_high[0x20]; 2648 2649 u8 rx_octets_low[0x20]; 2650 2651 u8 reserved_at_40[0xc0]; 2652 2653 u8 rx_frames_high[0x20]; 2654 2655 u8 rx_frames_low[0x20]; 2656 2657 u8 tx_octets_high[0x20]; 2658 2659 u8 tx_octets_low[0x20]; 2660 2661 u8 reserved_at_180[0xc0]; 2662 2663 u8 tx_frames_high[0x20]; 2664 2665 u8 tx_frames_low[0x20]; 2666 2667 u8 rx_pause_high[0x20]; 2668 2669 u8 rx_pause_low[0x20]; 2670 2671 u8 rx_pause_duration_high[0x20]; 2672 2673 u8 rx_pause_duration_low[0x20]; 2674 2675 u8 tx_pause_high[0x20]; 2676 2677 u8 tx_pause_low[0x20]; 2678 2679 u8 tx_pause_duration_high[0x20]; 2680 2681 u8 tx_pause_duration_low[0x20]; 2682 2683 u8 rx_pause_transition_high[0x20]; 2684 2685 u8 rx_pause_transition_low[0x20]; 2686 2687 u8 rx_discards_high[0x20]; 2688 2689 u8 rx_discards_low[0x20]; 2690 2691 u8 device_stall_minor_watermark_cnt_high[0x20]; 2692 2693 u8 device_stall_minor_watermark_cnt_low[0x20]; 2694 2695 u8 device_stall_critical_watermark_cnt_high[0x20]; 2696 2697 u8 device_stall_critical_watermark_cnt_low[0x20]; 2698 2699 u8 reserved_at_480[0x340]; 2700 }; 2701 2702 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2703 u8 port_transmit_wait_high[0x20]; 2704 2705 u8 port_transmit_wait_low[0x20]; 2706 2707 u8 reserved_at_40[0x100]; 2708 2709 u8 rx_buffer_almost_full_high[0x20]; 2710 2711 u8 rx_buffer_almost_full_low[0x20]; 2712 2713 u8 rx_buffer_full_high[0x20]; 2714 2715 u8 rx_buffer_full_low[0x20]; 2716 2717 u8 rx_icrc_encapsulated_high[0x20]; 2718 2719 u8 rx_icrc_encapsulated_low[0x20]; 2720 2721 u8 reserved_at_200[0x5c0]; 2722 }; 2723 2724 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2725 u8 dot3stats_alignment_errors_high[0x20]; 2726 2727 u8 dot3stats_alignment_errors_low[0x20]; 2728 2729 u8 dot3stats_fcs_errors_high[0x20]; 2730 2731 u8 dot3stats_fcs_errors_low[0x20]; 2732 2733 u8 dot3stats_single_collision_frames_high[0x20]; 2734 2735 u8 dot3stats_single_collision_frames_low[0x20]; 2736 2737 u8 dot3stats_multiple_collision_frames_high[0x20]; 2738 2739 u8 dot3stats_multiple_collision_frames_low[0x20]; 2740 2741 u8 dot3stats_sqe_test_errors_high[0x20]; 2742 2743 u8 dot3stats_sqe_test_errors_low[0x20]; 2744 2745 u8 dot3stats_deferred_transmissions_high[0x20]; 2746 2747 u8 dot3stats_deferred_transmissions_low[0x20]; 2748 2749 u8 dot3stats_late_collisions_high[0x20]; 2750 2751 u8 dot3stats_late_collisions_low[0x20]; 2752 2753 u8 dot3stats_excessive_collisions_high[0x20]; 2754 2755 u8 dot3stats_excessive_collisions_low[0x20]; 2756 2757 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2758 2759 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2760 2761 u8 dot3stats_carrier_sense_errors_high[0x20]; 2762 2763 u8 dot3stats_carrier_sense_errors_low[0x20]; 2764 2765 u8 dot3stats_frame_too_longs_high[0x20]; 2766 2767 u8 dot3stats_frame_too_longs_low[0x20]; 2768 2769 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2770 2771 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2772 2773 u8 dot3stats_symbol_errors_high[0x20]; 2774 2775 u8 dot3stats_symbol_errors_low[0x20]; 2776 2777 u8 dot3control_in_unknown_opcodes_high[0x20]; 2778 2779 u8 dot3control_in_unknown_opcodes_low[0x20]; 2780 2781 u8 dot3in_pause_frames_high[0x20]; 2782 2783 u8 dot3in_pause_frames_low[0x20]; 2784 2785 u8 dot3out_pause_frames_high[0x20]; 2786 2787 u8 dot3out_pause_frames_low[0x20]; 2788 2789 u8 reserved_at_400[0x3c0]; 2790 }; 2791 2792 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2793 u8 ether_stats_drop_events_high[0x20]; 2794 2795 u8 ether_stats_drop_events_low[0x20]; 2796 2797 u8 ether_stats_octets_high[0x20]; 2798 2799 u8 ether_stats_octets_low[0x20]; 2800 2801 u8 ether_stats_pkts_high[0x20]; 2802 2803 u8 ether_stats_pkts_low[0x20]; 2804 2805 u8 ether_stats_broadcast_pkts_high[0x20]; 2806 2807 u8 ether_stats_broadcast_pkts_low[0x20]; 2808 2809 u8 ether_stats_multicast_pkts_high[0x20]; 2810 2811 u8 ether_stats_multicast_pkts_low[0x20]; 2812 2813 u8 ether_stats_crc_align_errors_high[0x20]; 2814 2815 u8 ether_stats_crc_align_errors_low[0x20]; 2816 2817 u8 ether_stats_undersize_pkts_high[0x20]; 2818 2819 u8 ether_stats_undersize_pkts_low[0x20]; 2820 2821 u8 ether_stats_oversize_pkts_high[0x20]; 2822 2823 u8 ether_stats_oversize_pkts_low[0x20]; 2824 2825 u8 ether_stats_fragments_high[0x20]; 2826 2827 u8 ether_stats_fragments_low[0x20]; 2828 2829 u8 ether_stats_jabbers_high[0x20]; 2830 2831 u8 ether_stats_jabbers_low[0x20]; 2832 2833 u8 ether_stats_collisions_high[0x20]; 2834 2835 u8 ether_stats_collisions_low[0x20]; 2836 2837 u8 ether_stats_pkts64octets_high[0x20]; 2838 2839 u8 ether_stats_pkts64octets_low[0x20]; 2840 2841 u8 ether_stats_pkts65to127octets_high[0x20]; 2842 2843 u8 ether_stats_pkts65to127octets_low[0x20]; 2844 2845 u8 ether_stats_pkts128to255octets_high[0x20]; 2846 2847 u8 ether_stats_pkts128to255octets_low[0x20]; 2848 2849 u8 ether_stats_pkts256to511octets_high[0x20]; 2850 2851 u8 ether_stats_pkts256to511octets_low[0x20]; 2852 2853 u8 ether_stats_pkts512to1023octets_high[0x20]; 2854 2855 u8 ether_stats_pkts512to1023octets_low[0x20]; 2856 2857 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2858 2859 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2860 2861 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2862 2863 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2864 2865 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2866 2867 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2868 2869 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2870 2871 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2872 2873 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2874 2875 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2876 2877 u8 reserved_at_540[0x280]; 2878 }; 2879 2880 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2881 u8 if_in_octets_high[0x20]; 2882 2883 u8 if_in_octets_low[0x20]; 2884 2885 u8 if_in_ucast_pkts_high[0x20]; 2886 2887 u8 if_in_ucast_pkts_low[0x20]; 2888 2889 u8 if_in_discards_high[0x20]; 2890 2891 u8 if_in_discards_low[0x20]; 2892 2893 u8 if_in_errors_high[0x20]; 2894 2895 u8 if_in_errors_low[0x20]; 2896 2897 u8 if_in_unknown_protos_high[0x20]; 2898 2899 u8 if_in_unknown_protos_low[0x20]; 2900 2901 u8 if_out_octets_high[0x20]; 2902 2903 u8 if_out_octets_low[0x20]; 2904 2905 u8 if_out_ucast_pkts_high[0x20]; 2906 2907 u8 if_out_ucast_pkts_low[0x20]; 2908 2909 u8 if_out_discards_high[0x20]; 2910 2911 u8 if_out_discards_low[0x20]; 2912 2913 u8 if_out_errors_high[0x20]; 2914 2915 u8 if_out_errors_low[0x20]; 2916 2917 u8 if_in_multicast_pkts_high[0x20]; 2918 2919 u8 if_in_multicast_pkts_low[0x20]; 2920 2921 u8 if_in_broadcast_pkts_high[0x20]; 2922 2923 u8 if_in_broadcast_pkts_low[0x20]; 2924 2925 u8 if_out_multicast_pkts_high[0x20]; 2926 2927 u8 if_out_multicast_pkts_low[0x20]; 2928 2929 u8 if_out_broadcast_pkts_high[0x20]; 2930 2931 u8 if_out_broadcast_pkts_low[0x20]; 2932 2933 u8 reserved_at_340[0x480]; 2934 }; 2935 2936 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2937 u8 a_frames_transmitted_ok_high[0x20]; 2938 2939 u8 a_frames_transmitted_ok_low[0x20]; 2940 2941 u8 a_frames_received_ok_high[0x20]; 2942 2943 u8 a_frames_received_ok_low[0x20]; 2944 2945 u8 a_frame_check_sequence_errors_high[0x20]; 2946 2947 u8 a_frame_check_sequence_errors_low[0x20]; 2948 2949 u8 a_alignment_errors_high[0x20]; 2950 2951 u8 a_alignment_errors_low[0x20]; 2952 2953 u8 a_octets_transmitted_ok_high[0x20]; 2954 2955 u8 a_octets_transmitted_ok_low[0x20]; 2956 2957 u8 a_octets_received_ok_high[0x20]; 2958 2959 u8 a_octets_received_ok_low[0x20]; 2960 2961 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2962 2963 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2964 2965 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2966 2967 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2968 2969 u8 a_multicast_frames_received_ok_high[0x20]; 2970 2971 u8 a_multicast_frames_received_ok_low[0x20]; 2972 2973 u8 a_broadcast_frames_received_ok_high[0x20]; 2974 2975 u8 a_broadcast_frames_received_ok_low[0x20]; 2976 2977 u8 a_in_range_length_errors_high[0x20]; 2978 2979 u8 a_in_range_length_errors_low[0x20]; 2980 2981 u8 a_out_of_range_length_field_high[0x20]; 2982 2983 u8 a_out_of_range_length_field_low[0x20]; 2984 2985 u8 a_frame_too_long_errors_high[0x20]; 2986 2987 u8 a_frame_too_long_errors_low[0x20]; 2988 2989 u8 a_symbol_error_during_carrier_high[0x20]; 2990 2991 u8 a_symbol_error_during_carrier_low[0x20]; 2992 2993 u8 a_mac_control_frames_transmitted_high[0x20]; 2994 2995 u8 a_mac_control_frames_transmitted_low[0x20]; 2996 2997 u8 a_mac_control_frames_received_high[0x20]; 2998 2999 u8 a_mac_control_frames_received_low[0x20]; 3000 3001 u8 a_unsupported_opcodes_received_high[0x20]; 3002 3003 u8 a_unsupported_opcodes_received_low[0x20]; 3004 3005 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3006 3007 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3008 3009 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3010 3011 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3012 3013 u8 reserved_at_4c0[0x300]; 3014 }; 3015 3016 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3017 u8 life_time_counter_high[0x20]; 3018 3019 u8 life_time_counter_low[0x20]; 3020 3021 u8 rx_errors[0x20]; 3022 3023 u8 tx_errors[0x20]; 3024 3025 u8 l0_to_recovery_eieos[0x20]; 3026 3027 u8 l0_to_recovery_ts[0x20]; 3028 3029 u8 l0_to_recovery_framing[0x20]; 3030 3031 u8 l0_to_recovery_retrain[0x20]; 3032 3033 u8 crc_error_dllp[0x20]; 3034 3035 u8 crc_error_tlp[0x20]; 3036 3037 u8 tx_overflow_buffer_pkt_high[0x20]; 3038 3039 u8 tx_overflow_buffer_pkt_low[0x20]; 3040 3041 u8 outbound_stalled_reads[0x20]; 3042 3043 u8 outbound_stalled_writes[0x20]; 3044 3045 u8 outbound_stalled_reads_events[0x20]; 3046 3047 u8 outbound_stalled_writes_events[0x20]; 3048 3049 u8 reserved_at_200[0x5c0]; 3050 }; 3051 3052 struct mlx5_ifc_cmd_inter_comp_event_bits { 3053 u8 command_completion_vector[0x20]; 3054 3055 u8 reserved_at_20[0xc0]; 3056 }; 3057 3058 struct mlx5_ifc_stall_vl_event_bits { 3059 u8 reserved_at_0[0x18]; 3060 u8 port_num[0x1]; 3061 u8 reserved_at_19[0x3]; 3062 u8 vl[0x4]; 3063 3064 u8 reserved_at_20[0xa0]; 3065 }; 3066 3067 struct mlx5_ifc_db_bf_congestion_event_bits { 3068 u8 event_subtype[0x8]; 3069 u8 reserved_at_8[0x8]; 3070 u8 congestion_level[0x8]; 3071 u8 reserved_at_18[0x8]; 3072 3073 u8 reserved_at_20[0xa0]; 3074 }; 3075 3076 struct mlx5_ifc_gpio_event_bits { 3077 u8 reserved_at_0[0x60]; 3078 3079 u8 gpio_event_hi[0x20]; 3080 3081 u8 gpio_event_lo[0x20]; 3082 3083 u8 reserved_at_a0[0x40]; 3084 }; 3085 3086 struct mlx5_ifc_port_state_change_event_bits { 3087 u8 reserved_at_0[0x40]; 3088 3089 u8 port_num[0x4]; 3090 u8 reserved_at_44[0x1c]; 3091 3092 u8 reserved_at_60[0x80]; 3093 }; 3094 3095 struct mlx5_ifc_dropped_packet_logged_bits { 3096 u8 reserved_at_0[0xe0]; 3097 }; 3098 3099 struct mlx5_ifc_default_timeout_bits { 3100 u8 to_multiplier[0x3]; 3101 u8 reserved_at_3[0x9]; 3102 u8 to_value[0x14]; 3103 }; 3104 3105 struct mlx5_ifc_dtor_reg_bits { 3106 u8 reserved_at_0[0x20]; 3107 3108 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3109 3110 u8 reserved_at_40[0x60]; 3111 3112 struct mlx5_ifc_default_timeout_bits health_poll_to; 3113 3114 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3115 3116 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3117 3118 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3119 3120 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3121 3122 struct mlx5_ifc_default_timeout_bits tear_down_to; 3123 3124 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3125 3126 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3127 3128 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3129 3130 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3131 3132 u8 reserved_at_1c0[0x20]; 3133 }; 3134 3135 enum { 3136 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3137 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3138 }; 3139 3140 struct mlx5_ifc_cq_error_bits { 3141 u8 reserved_at_0[0x8]; 3142 u8 cqn[0x18]; 3143 3144 u8 reserved_at_20[0x20]; 3145 3146 u8 reserved_at_40[0x18]; 3147 u8 syndrome[0x8]; 3148 3149 u8 reserved_at_60[0x80]; 3150 }; 3151 3152 struct mlx5_ifc_rdma_page_fault_event_bits { 3153 u8 bytes_committed[0x20]; 3154 3155 u8 r_key[0x20]; 3156 3157 u8 reserved_at_40[0x10]; 3158 u8 packet_len[0x10]; 3159 3160 u8 rdma_op_len[0x20]; 3161 3162 u8 rdma_va[0x40]; 3163 3164 u8 reserved_at_c0[0x5]; 3165 u8 rdma[0x1]; 3166 u8 write[0x1]; 3167 u8 requestor[0x1]; 3168 u8 qp_number[0x18]; 3169 }; 3170 3171 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3172 u8 bytes_committed[0x20]; 3173 3174 u8 reserved_at_20[0x10]; 3175 u8 wqe_index[0x10]; 3176 3177 u8 reserved_at_40[0x10]; 3178 u8 len[0x10]; 3179 3180 u8 reserved_at_60[0x60]; 3181 3182 u8 reserved_at_c0[0x5]; 3183 u8 rdma[0x1]; 3184 u8 write_read[0x1]; 3185 u8 requestor[0x1]; 3186 u8 qpn[0x18]; 3187 }; 3188 3189 struct mlx5_ifc_qp_events_bits { 3190 u8 reserved_at_0[0xa0]; 3191 3192 u8 type[0x8]; 3193 u8 reserved_at_a8[0x18]; 3194 3195 u8 reserved_at_c0[0x8]; 3196 u8 qpn_rqn_sqn[0x18]; 3197 }; 3198 3199 struct mlx5_ifc_dct_events_bits { 3200 u8 reserved_at_0[0xc0]; 3201 3202 u8 reserved_at_c0[0x8]; 3203 u8 dct_number[0x18]; 3204 }; 3205 3206 struct mlx5_ifc_comp_event_bits { 3207 u8 reserved_at_0[0xc0]; 3208 3209 u8 reserved_at_c0[0x8]; 3210 u8 cq_number[0x18]; 3211 }; 3212 3213 enum { 3214 MLX5_QPC_STATE_RST = 0x0, 3215 MLX5_QPC_STATE_INIT = 0x1, 3216 MLX5_QPC_STATE_RTR = 0x2, 3217 MLX5_QPC_STATE_RTS = 0x3, 3218 MLX5_QPC_STATE_SQER = 0x4, 3219 MLX5_QPC_STATE_ERR = 0x6, 3220 MLX5_QPC_STATE_SQD = 0x7, 3221 MLX5_QPC_STATE_SUSPENDED = 0x9, 3222 }; 3223 3224 enum { 3225 MLX5_QPC_ST_RC = 0x0, 3226 MLX5_QPC_ST_UC = 0x1, 3227 MLX5_QPC_ST_UD = 0x2, 3228 MLX5_QPC_ST_XRC = 0x3, 3229 MLX5_QPC_ST_DCI = 0x5, 3230 MLX5_QPC_ST_QP0 = 0x7, 3231 MLX5_QPC_ST_QP1 = 0x8, 3232 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3233 MLX5_QPC_ST_REG_UMR = 0xc, 3234 }; 3235 3236 enum { 3237 MLX5_QPC_PM_STATE_ARMED = 0x0, 3238 MLX5_QPC_PM_STATE_REARM = 0x1, 3239 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3240 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3241 }; 3242 3243 enum { 3244 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3245 }; 3246 3247 enum { 3248 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3249 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3250 }; 3251 3252 enum { 3253 MLX5_QPC_MTU_256_BYTES = 0x1, 3254 MLX5_QPC_MTU_512_BYTES = 0x2, 3255 MLX5_QPC_MTU_1K_BYTES = 0x3, 3256 MLX5_QPC_MTU_2K_BYTES = 0x4, 3257 MLX5_QPC_MTU_4K_BYTES = 0x5, 3258 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3259 }; 3260 3261 enum { 3262 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3263 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3264 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3265 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3266 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3267 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3268 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3269 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3270 }; 3271 3272 enum { 3273 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3274 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3275 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3276 }; 3277 3278 enum { 3279 MLX5_QPC_CS_RES_DISABLE = 0x0, 3280 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3281 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3282 }; 3283 3284 enum { 3285 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3286 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3287 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3288 }; 3289 3290 struct mlx5_ifc_qpc_bits { 3291 u8 state[0x4]; 3292 u8 lag_tx_port_affinity[0x4]; 3293 u8 st[0x8]; 3294 u8 reserved_at_10[0x2]; 3295 u8 isolate_vl_tc[0x1]; 3296 u8 pm_state[0x2]; 3297 u8 reserved_at_15[0x1]; 3298 u8 req_e2e_credit_mode[0x2]; 3299 u8 offload_type[0x4]; 3300 u8 end_padding_mode[0x2]; 3301 u8 reserved_at_1e[0x2]; 3302 3303 u8 wq_signature[0x1]; 3304 u8 block_lb_mc[0x1]; 3305 u8 atomic_like_write_en[0x1]; 3306 u8 latency_sensitive[0x1]; 3307 u8 reserved_at_24[0x1]; 3308 u8 drain_sigerr[0x1]; 3309 u8 reserved_at_26[0x2]; 3310 u8 pd[0x18]; 3311 3312 u8 mtu[0x3]; 3313 u8 log_msg_max[0x5]; 3314 u8 reserved_at_48[0x1]; 3315 u8 log_rq_size[0x4]; 3316 u8 log_rq_stride[0x3]; 3317 u8 no_sq[0x1]; 3318 u8 log_sq_size[0x4]; 3319 u8 reserved_at_55[0x1]; 3320 u8 retry_mode[0x2]; 3321 u8 ts_format[0x2]; 3322 u8 reserved_at_5a[0x1]; 3323 u8 rlky[0x1]; 3324 u8 ulp_stateless_offload_mode[0x4]; 3325 3326 u8 counter_set_id[0x8]; 3327 u8 uar_page[0x18]; 3328 3329 u8 reserved_at_80[0x8]; 3330 u8 user_index[0x18]; 3331 3332 u8 reserved_at_a0[0x3]; 3333 u8 log_page_size[0x5]; 3334 u8 remote_qpn[0x18]; 3335 3336 struct mlx5_ifc_ads_bits primary_address_path; 3337 3338 struct mlx5_ifc_ads_bits secondary_address_path; 3339 3340 u8 log_ack_req_freq[0x4]; 3341 u8 reserved_at_384[0x4]; 3342 u8 log_sra_max[0x3]; 3343 u8 reserved_at_38b[0x2]; 3344 u8 retry_count[0x3]; 3345 u8 rnr_retry[0x3]; 3346 u8 reserved_at_393[0x1]; 3347 u8 fre[0x1]; 3348 u8 cur_rnr_retry[0x3]; 3349 u8 cur_retry_count[0x3]; 3350 u8 reserved_at_39b[0x5]; 3351 3352 u8 reserved_at_3a0[0x20]; 3353 3354 u8 reserved_at_3c0[0x8]; 3355 u8 next_send_psn[0x18]; 3356 3357 u8 reserved_at_3e0[0x3]; 3358 u8 log_num_dci_stream_channels[0x5]; 3359 u8 cqn_snd[0x18]; 3360 3361 u8 reserved_at_400[0x3]; 3362 u8 log_num_dci_errored_streams[0x5]; 3363 u8 deth_sqpn[0x18]; 3364 3365 u8 reserved_at_420[0x20]; 3366 3367 u8 reserved_at_440[0x8]; 3368 u8 last_acked_psn[0x18]; 3369 3370 u8 reserved_at_460[0x8]; 3371 u8 ssn[0x18]; 3372 3373 u8 reserved_at_480[0x8]; 3374 u8 log_rra_max[0x3]; 3375 u8 reserved_at_48b[0x1]; 3376 u8 atomic_mode[0x4]; 3377 u8 rre[0x1]; 3378 u8 rwe[0x1]; 3379 u8 rae[0x1]; 3380 u8 reserved_at_493[0x1]; 3381 u8 page_offset[0x6]; 3382 u8 reserved_at_49a[0x3]; 3383 u8 cd_slave_receive[0x1]; 3384 u8 cd_slave_send[0x1]; 3385 u8 cd_master[0x1]; 3386 3387 u8 reserved_at_4a0[0x3]; 3388 u8 min_rnr_nak[0x5]; 3389 u8 next_rcv_psn[0x18]; 3390 3391 u8 reserved_at_4c0[0x8]; 3392 u8 xrcd[0x18]; 3393 3394 u8 reserved_at_4e0[0x8]; 3395 u8 cqn_rcv[0x18]; 3396 3397 u8 dbr_addr[0x40]; 3398 3399 u8 q_key[0x20]; 3400 3401 u8 reserved_at_560[0x5]; 3402 u8 rq_type[0x3]; 3403 u8 srqn_rmpn_xrqn[0x18]; 3404 3405 u8 reserved_at_580[0x8]; 3406 u8 rmsn[0x18]; 3407 3408 u8 hw_sq_wqebb_counter[0x10]; 3409 u8 sw_sq_wqebb_counter[0x10]; 3410 3411 u8 hw_rq_counter[0x20]; 3412 3413 u8 sw_rq_counter[0x20]; 3414 3415 u8 reserved_at_600[0x20]; 3416 3417 u8 reserved_at_620[0xf]; 3418 u8 cgs[0x1]; 3419 u8 cs_req[0x8]; 3420 u8 cs_res[0x8]; 3421 3422 u8 dc_access_key[0x40]; 3423 3424 u8 reserved_at_680[0x3]; 3425 u8 dbr_umem_valid[0x1]; 3426 3427 u8 reserved_at_684[0xbc]; 3428 }; 3429 3430 struct mlx5_ifc_roce_addr_layout_bits { 3431 u8 source_l3_address[16][0x8]; 3432 3433 u8 reserved_at_80[0x3]; 3434 u8 vlan_valid[0x1]; 3435 u8 vlan_id[0xc]; 3436 u8 source_mac_47_32[0x10]; 3437 3438 u8 source_mac_31_0[0x20]; 3439 3440 u8 reserved_at_c0[0x14]; 3441 u8 roce_l3_type[0x4]; 3442 u8 roce_version[0x8]; 3443 3444 u8 reserved_at_e0[0x20]; 3445 }; 3446 3447 struct mlx5_ifc_crypto_cap_bits { 3448 u8 reserved_at_0[0x3]; 3449 u8 synchronize_dek[0x1]; 3450 u8 int_kek_manual[0x1]; 3451 u8 int_kek_auto[0x1]; 3452 u8 reserved_at_6[0x1a]; 3453 3454 u8 reserved_at_20[0x3]; 3455 u8 log_dek_max_alloc[0x5]; 3456 u8 reserved_at_28[0x3]; 3457 u8 log_max_num_deks[0x5]; 3458 u8 reserved_at_30[0x10]; 3459 3460 u8 reserved_at_40[0x20]; 3461 3462 u8 reserved_at_60[0x3]; 3463 u8 log_dek_granularity[0x5]; 3464 u8 reserved_at_68[0x3]; 3465 u8 log_max_num_int_kek[0x5]; 3466 u8 sw_wrapped_dek[0x10]; 3467 3468 u8 reserved_at_80[0x780]; 3469 }; 3470 3471 union mlx5_ifc_hca_cap_union_bits { 3472 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3473 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3474 struct mlx5_ifc_odp_cap_bits odp_cap; 3475 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3476 struct mlx5_ifc_roce_cap_bits roce_cap; 3477 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3478 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3479 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3480 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3481 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3482 struct mlx5_ifc_qos_cap_bits qos_cap; 3483 struct mlx5_ifc_debug_cap_bits debug_cap; 3484 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3485 struct mlx5_ifc_tls_cap_bits tls_cap; 3486 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3487 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3488 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3489 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3490 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3491 u8 reserved_at_0[0x8000]; 3492 }; 3493 3494 enum { 3495 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3496 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3497 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3498 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3499 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3500 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3501 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3502 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3503 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3504 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3505 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3506 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3507 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3508 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3509 }; 3510 3511 enum { 3512 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3513 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3514 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3515 }; 3516 3517 enum { 3518 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3519 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3520 }; 3521 3522 struct mlx5_ifc_vlan_bits { 3523 u8 ethtype[0x10]; 3524 u8 prio[0x3]; 3525 u8 cfi[0x1]; 3526 u8 vid[0xc]; 3527 }; 3528 3529 enum { 3530 MLX5_FLOW_METER_COLOR_RED = 0x0, 3531 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3532 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3533 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3534 }; 3535 3536 enum { 3537 MLX5_EXE_ASO_FLOW_METER = 0x2, 3538 }; 3539 3540 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3541 u8 return_reg_id[0x4]; 3542 u8 aso_type[0x4]; 3543 u8 reserved_at_8[0x14]; 3544 u8 action[0x1]; 3545 u8 init_color[0x2]; 3546 u8 meter_id[0x1]; 3547 }; 3548 3549 union mlx5_ifc_exe_aso_ctrl { 3550 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3551 }; 3552 3553 struct mlx5_ifc_execute_aso_bits { 3554 u8 valid[0x1]; 3555 u8 reserved_at_1[0x7]; 3556 u8 aso_object_id[0x18]; 3557 3558 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3559 }; 3560 3561 struct mlx5_ifc_flow_context_bits { 3562 struct mlx5_ifc_vlan_bits push_vlan; 3563 3564 u8 group_id[0x20]; 3565 3566 u8 reserved_at_40[0x8]; 3567 u8 flow_tag[0x18]; 3568 3569 u8 reserved_at_60[0x10]; 3570 u8 action[0x10]; 3571 3572 u8 extended_destination[0x1]; 3573 u8 reserved_at_81[0x1]; 3574 u8 flow_source[0x2]; 3575 u8 encrypt_decrypt_type[0x4]; 3576 u8 destination_list_size[0x18]; 3577 3578 u8 reserved_at_a0[0x8]; 3579 u8 flow_counter_list_size[0x18]; 3580 3581 u8 packet_reformat_id[0x20]; 3582 3583 u8 modify_header_id[0x20]; 3584 3585 struct mlx5_ifc_vlan_bits push_vlan_2; 3586 3587 u8 encrypt_decrypt_obj_id[0x20]; 3588 u8 reserved_at_140[0xc0]; 3589 3590 struct mlx5_ifc_fte_match_param_bits match_value; 3591 3592 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3593 3594 u8 reserved_at_1300[0x500]; 3595 3596 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3597 }; 3598 3599 enum { 3600 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3601 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3602 }; 3603 3604 struct mlx5_ifc_xrc_srqc_bits { 3605 u8 state[0x4]; 3606 u8 log_xrc_srq_size[0x4]; 3607 u8 reserved_at_8[0x18]; 3608 3609 u8 wq_signature[0x1]; 3610 u8 cont_srq[0x1]; 3611 u8 reserved_at_22[0x1]; 3612 u8 rlky[0x1]; 3613 u8 basic_cyclic_rcv_wqe[0x1]; 3614 u8 log_rq_stride[0x3]; 3615 u8 xrcd[0x18]; 3616 3617 u8 page_offset[0x6]; 3618 u8 reserved_at_46[0x1]; 3619 u8 dbr_umem_valid[0x1]; 3620 u8 cqn[0x18]; 3621 3622 u8 reserved_at_60[0x20]; 3623 3624 u8 user_index_equal_xrc_srqn[0x1]; 3625 u8 reserved_at_81[0x1]; 3626 u8 log_page_size[0x6]; 3627 u8 user_index[0x18]; 3628 3629 u8 reserved_at_a0[0x20]; 3630 3631 u8 reserved_at_c0[0x8]; 3632 u8 pd[0x18]; 3633 3634 u8 lwm[0x10]; 3635 u8 wqe_cnt[0x10]; 3636 3637 u8 reserved_at_100[0x40]; 3638 3639 u8 db_record_addr_h[0x20]; 3640 3641 u8 db_record_addr_l[0x1e]; 3642 u8 reserved_at_17e[0x2]; 3643 3644 u8 reserved_at_180[0x80]; 3645 }; 3646 3647 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3648 u8 counter_error_queues[0x20]; 3649 3650 u8 total_error_queues[0x20]; 3651 3652 u8 send_queue_priority_update_flow[0x20]; 3653 3654 u8 reserved_at_60[0x20]; 3655 3656 u8 nic_receive_steering_discard[0x40]; 3657 3658 u8 receive_discard_vport_down[0x40]; 3659 3660 u8 transmit_discard_vport_down[0x40]; 3661 3662 u8 async_eq_overrun[0x20]; 3663 3664 u8 comp_eq_overrun[0x20]; 3665 3666 u8 reserved_at_180[0x20]; 3667 3668 u8 invalid_command[0x20]; 3669 3670 u8 quota_exceeded_command[0x20]; 3671 3672 u8 internal_rq_out_of_buffer[0x20]; 3673 3674 u8 cq_overrun[0x20]; 3675 3676 u8 eth_wqe_too_small[0x20]; 3677 3678 u8 reserved_at_220[0xc0]; 3679 3680 u8 generated_pkt_steering_fail[0x40]; 3681 3682 u8 handled_pkt_steering_fail[0x40]; 3683 3684 u8 reserved_at_360[0xc80]; 3685 }; 3686 3687 struct mlx5_ifc_traffic_counter_bits { 3688 u8 packets[0x40]; 3689 3690 u8 octets[0x40]; 3691 }; 3692 3693 struct mlx5_ifc_tisc_bits { 3694 u8 strict_lag_tx_port_affinity[0x1]; 3695 u8 tls_en[0x1]; 3696 u8 reserved_at_2[0x2]; 3697 u8 lag_tx_port_affinity[0x04]; 3698 3699 u8 reserved_at_8[0x4]; 3700 u8 prio[0x4]; 3701 u8 reserved_at_10[0x10]; 3702 3703 u8 reserved_at_20[0x100]; 3704 3705 u8 reserved_at_120[0x8]; 3706 u8 transport_domain[0x18]; 3707 3708 u8 reserved_at_140[0x8]; 3709 u8 underlay_qpn[0x18]; 3710 3711 u8 reserved_at_160[0x8]; 3712 u8 pd[0x18]; 3713 3714 u8 reserved_at_180[0x380]; 3715 }; 3716 3717 enum { 3718 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3719 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3720 }; 3721 3722 enum { 3723 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3724 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3725 }; 3726 3727 enum { 3728 MLX5_RX_HASH_FN_NONE = 0x0, 3729 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3730 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3731 }; 3732 3733 enum { 3734 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3735 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3736 }; 3737 3738 struct mlx5_ifc_tirc_bits { 3739 u8 reserved_at_0[0x20]; 3740 3741 u8 disp_type[0x4]; 3742 u8 tls_en[0x1]; 3743 u8 reserved_at_25[0x1b]; 3744 3745 u8 reserved_at_40[0x40]; 3746 3747 u8 reserved_at_80[0x4]; 3748 u8 lro_timeout_period_usecs[0x10]; 3749 u8 packet_merge_mask[0x4]; 3750 u8 lro_max_ip_payload_size[0x8]; 3751 3752 u8 reserved_at_a0[0x40]; 3753 3754 u8 reserved_at_e0[0x8]; 3755 u8 inline_rqn[0x18]; 3756 3757 u8 rx_hash_symmetric[0x1]; 3758 u8 reserved_at_101[0x1]; 3759 u8 tunneled_offload_en[0x1]; 3760 u8 reserved_at_103[0x5]; 3761 u8 indirect_table[0x18]; 3762 3763 u8 rx_hash_fn[0x4]; 3764 u8 reserved_at_124[0x2]; 3765 u8 self_lb_block[0x2]; 3766 u8 transport_domain[0x18]; 3767 3768 u8 rx_hash_toeplitz_key[10][0x20]; 3769 3770 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3771 3772 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3773 3774 u8 reserved_at_2c0[0x4c0]; 3775 }; 3776 3777 enum { 3778 MLX5_SRQC_STATE_GOOD = 0x0, 3779 MLX5_SRQC_STATE_ERROR = 0x1, 3780 }; 3781 3782 struct mlx5_ifc_srqc_bits { 3783 u8 state[0x4]; 3784 u8 log_srq_size[0x4]; 3785 u8 reserved_at_8[0x18]; 3786 3787 u8 wq_signature[0x1]; 3788 u8 cont_srq[0x1]; 3789 u8 reserved_at_22[0x1]; 3790 u8 rlky[0x1]; 3791 u8 reserved_at_24[0x1]; 3792 u8 log_rq_stride[0x3]; 3793 u8 xrcd[0x18]; 3794 3795 u8 page_offset[0x6]; 3796 u8 reserved_at_46[0x2]; 3797 u8 cqn[0x18]; 3798 3799 u8 reserved_at_60[0x20]; 3800 3801 u8 reserved_at_80[0x2]; 3802 u8 log_page_size[0x6]; 3803 u8 reserved_at_88[0x18]; 3804 3805 u8 reserved_at_a0[0x20]; 3806 3807 u8 reserved_at_c0[0x8]; 3808 u8 pd[0x18]; 3809 3810 u8 lwm[0x10]; 3811 u8 wqe_cnt[0x10]; 3812 3813 u8 reserved_at_100[0x40]; 3814 3815 u8 dbr_addr[0x40]; 3816 3817 u8 reserved_at_180[0x80]; 3818 }; 3819 3820 enum { 3821 MLX5_SQC_STATE_RST = 0x0, 3822 MLX5_SQC_STATE_RDY = 0x1, 3823 MLX5_SQC_STATE_ERR = 0x3, 3824 }; 3825 3826 struct mlx5_ifc_sqc_bits { 3827 u8 rlky[0x1]; 3828 u8 cd_master[0x1]; 3829 u8 fre[0x1]; 3830 u8 flush_in_error_en[0x1]; 3831 u8 allow_multi_pkt_send_wqe[0x1]; 3832 u8 min_wqe_inline_mode[0x3]; 3833 u8 state[0x4]; 3834 u8 reg_umr[0x1]; 3835 u8 allow_swp[0x1]; 3836 u8 hairpin[0x1]; 3837 u8 reserved_at_f[0xb]; 3838 u8 ts_format[0x2]; 3839 u8 reserved_at_1c[0x4]; 3840 3841 u8 reserved_at_20[0x8]; 3842 u8 user_index[0x18]; 3843 3844 u8 reserved_at_40[0x8]; 3845 u8 cqn[0x18]; 3846 3847 u8 reserved_at_60[0x8]; 3848 u8 hairpin_peer_rq[0x18]; 3849 3850 u8 reserved_at_80[0x10]; 3851 u8 hairpin_peer_vhca[0x10]; 3852 3853 u8 reserved_at_a0[0x20]; 3854 3855 u8 reserved_at_c0[0x8]; 3856 u8 ts_cqe_to_dest_cqn[0x18]; 3857 3858 u8 reserved_at_e0[0x10]; 3859 u8 packet_pacing_rate_limit_index[0x10]; 3860 u8 tis_lst_sz[0x10]; 3861 u8 qos_queue_group_id[0x10]; 3862 3863 u8 reserved_at_120[0x40]; 3864 3865 u8 reserved_at_160[0x8]; 3866 u8 tis_num_0[0x18]; 3867 3868 struct mlx5_ifc_wq_bits wq; 3869 }; 3870 3871 enum { 3872 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3873 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3874 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3875 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3876 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3877 }; 3878 3879 enum { 3880 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3881 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3882 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3883 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3884 }; 3885 3886 struct mlx5_ifc_scheduling_context_bits { 3887 u8 element_type[0x8]; 3888 u8 reserved_at_8[0x18]; 3889 3890 u8 element_attributes[0x20]; 3891 3892 u8 parent_element_id[0x20]; 3893 3894 u8 reserved_at_60[0x40]; 3895 3896 u8 bw_share[0x20]; 3897 3898 u8 max_average_bw[0x20]; 3899 3900 u8 reserved_at_e0[0x120]; 3901 }; 3902 3903 struct mlx5_ifc_rqtc_bits { 3904 u8 reserved_at_0[0xa0]; 3905 3906 u8 reserved_at_a0[0x5]; 3907 u8 list_q_type[0x3]; 3908 u8 reserved_at_a8[0x8]; 3909 u8 rqt_max_size[0x10]; 3910 3911 u8 rq_vhca_id_format[0x1]; 3912 u8 reserved_at_c1[0xf]; 3913 u8 rqt_actual_size[0x10]; 3914 3915 u8 reserved_at_e0[0x6a0]; 3916 3917 union { 3918 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 3919 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 3920 }; 3921 }; 3922 3923 enum { 3924 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3925 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3926 }; 3927 3928 enum { 3929 MLX5_RQC_STATE_RST = 0x0, 3930 MLX5_RQC_STATE_RDY = 0x1, 3931 MLX5_RQC_STATE_ERR = 0x3, 3932 }; 3933 3934 enum { 3935 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3936 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3937 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3938 }; 3939 3940 enum { 3941 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3942 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3943 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3944 }; 3945 3946 struct mlx5_ifc_rqc_bits { 3947 u8 rlky[0x1]; 3948 u8 delay_drop_en[0x1]; 3949 u8 scatter_fcs[0x1]; 3950 u8 vsd[0x1]; 3951 u8 mem_rq_type[0x4]; 3952 u8 state[0x4]; 3953 u8 reserved_at_c[0x1]; 3954 u8 flush_in_error_en[0x1]; 3955 u8 hairpin[0x1]; 3956 u8 reserved_at_f[0xb]; 3957 u8 ts_format[0x2]; 3958 u8 reserved_at_1c[0x4]; 3959 3960 u8 reserved_at_20[0x8]; 3961 u8 user_index[0x18]; 3962 3963 u8 reserved_at_40[0x8]; 3964 u8 cqn[0x18]; 3965 3966 u8 counter_set_id[0x8]; 3967 u8 reserved_at_68[0x18]; 3968 3969 u8 reserved_at_80[0x8]; 3970 u8 rmpn[0x18]; 3971 3972 u8 reserved_at_a0[0x8]; 3973 u8 hairpin_peer_sq[0x18]; 3974 3975 u8 reserved_at_c0[0x10]; 3976 u8 hairpin_peer_vhca[0x10]; 3977 3978 u8 reserved_at_e0[0x46]; 3979 u8 shampo_no_match_alignment_granularity[0x2]; 3980 u8 reserved_at_128[0x6]; 3981 u8 shampo_match_criteria_type[0x2]; 3982 u8 reservation_timeout[0x10]; 3983 3984 u8 reserved_at_140[0x40]; 3985 3986 struct mlx5_ifc_wq_bits wq; 3987 }; 3988 3989 enum { 3990 MLX5_RMPC_STATE_RDY = 0x1, 3991 MLX5_RMPC_STATE_ERR = 0x3, 3992 }; 3993 3994 struct mlx5_ifc_rmpc_bits { 3995 u8 reserved_at_0[0x8]; 3996 u8 state[0x4]; 3997 u8 reserved_at_c[0x14]; 3998 3999 u8 basic_cyclic_rcv_wqe[0x1]; 4000 u8 reserved_at_21[0x1f]; 4001 4002 u8 reserved_at_40[0x140]; 4003 4004 struct mlx5_ifc_wq_bits wq; 4005 }; 4006 4007 enum { 4008 VHCA_ID_TYPE_HW = 0, 4009 VHCA_ID_TYPE_SW = 1, 4010 }; 4011 4012 struct mlx5_ifc_nic_vport_context_bits { 4013 u8 reserved_at_0[0x5]; 4014 u8 min_wqe_inline_mode[0x3]; 4015 u8 reserved_at_8[0x15]; 4016 u8 disable_mc_local_lb[0x1]; 4017 u8 disable_uc_local_lb[0x1]; 4018 u8 roce_en[0x1]; 4019 4020 u8 arm_change_event[0x1]; 4021 u8 reserved_at_21[0x1a]; 4022 u8 event_on_mtu[0x1]; 4023 u8 event_on_promisc_change[0x1]; 4024 u8 event_on_vlan_change[0x1]; 4025 u8 event_on_mc_address_change[0x1]; 4026 u8 event_on_uc_address_change[0x1]; 4027 4028 u8 vhca_id_type[0x1]; 4029 u8 reserved_at_41[0xb]; 4030 u8 affiliation_criteria[0x4]; 4031 u8 affiliated_vhca_id[0x10]; 4032 4033 u8 reserved_at_60[0xd0]; 4034 4035 u8 mtu[0x10]; 4036 4037 u8 system_image_guid[0x40]; 4038 u8 port_guid[0x40]; 4039 u8 node_guid[0x40]; 4040 4041 u8 reserved_at_200[0x140]; 4042 u8 qkey_violation_counter[0x10]; 4043 u8 reserved_at_350[0x430]; 4044 4045 u8 promisc_uc[0x1]; 4046 u8 promisc_mc[0x1]; 4047 u8 promisc_all[0x1]; 4048 u8 reserved_at_783[0x2]; 4049 u8 allowed_list_type[0x3]; 4050 u8 reserved_at_788[0xc]; 4051 u8 allowed_list_size[0xc]; 4052 4053 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4054 4055 u8 reserved_at_7e0[0x20]; 4056 4057 u8 current_uc_mac_address[][0x40]; 4058 }; 4059 4060 enum { 4061 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4062 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4063 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4064 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4065 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4066 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4067 }; 4068 4069 struct mlx5_ifc_mkc_bits { 4070 u8 reserved_at_0[0x1]; 4071 u8 free[0x1]; 4072 u8 reserved_at_2[0x1]; 4073 u8 access_mode_4_2[0x3]; 4074 u8 reserved_at_6[0x7]; 4075 u8 relaxed_ordering_write[0x1]; 4076 u8 reserved_at_e[0x1]; 4077 u8 small_fence_on_rdma_read_response[0x1]; 4078 u8 umr_en[0x1]; 4079 u8 a[0x1]; 4080 u8 rw[0x1]; 4081 u8 rr[0x1]; 4082 u8 lw[0x1]; 4083 u8 lr[0x1]; 4084 u8 access_mode_1_0[0x2]; 4085 u8 reserved_at_18[0x2]; 4086 u8 ma_translation_mode[0x2]; 4087 u8 reserved_at_1c[0x4]; 4088 4089 u8 qpn[0x18]; 4090 u8 mkey_7_0[0x8]; 4091 4092 u8 reserved_at_40[0x20]; 4093 4094 u8 length64[0x1]; 4095 u8 bsf_en[0x1]; 4096 u8 sync_umr[0x1]; 4097 u8 reserved_at_63[0x2]; 4098 u8 expected_sigerr_count[0x1]; 4099 u8 reserved_at_66[0x1]; 4100 u8 en_rinval[0x1]; 4101 u8 pd[0x18]; 4102 4103 u8 start_addr[0x40]; 4104 4105 u8 len[0x40]; 4106 4107 u8 bsf_octword_size[0x20]; 4108 4109 u8 reserved_at_120[0x80]; 4110 4111 u8 translations_octword_size[0x20]; 4112 4113 u8 reserved_at_1c0[0x19]; 4114 u8 relaxed_ordering_read[0x1]; 4115 u8 reserved_at_1d9[0x1]; 4116 u8 log_page_size[0x5]; 4117 4118 u8 reserved_at_1e0[0x20]; 4119 }; 4120 4121 struct mlx5_ifc_pkey_bits { 4122 u8 reserved_at_0[0x10]; 4123 u8 pkey[0x10]; 4124 }; 4125 4126 struct mlx5_ifc_array128_auto_bits { 4127 u8 array128_auto[16][0x8]; 4128 }; 4129 4130 struct mlx5_ifc_hca_vport_context_bits { 4131 u8 field_select[0x20]; 4132 4133 u8 reserved_at_20[0xe0]; 4134 4135 u8 sm_virt_aware[0x1]; 4136 u8 has_smi[0x1]; 4137 u8 has_raw[0x1]; 4138 u8 grh_required[0x1]; 4139 u8 reserved_at_104[0xc]; 4140 u8 port_physical_state[0x4]; 4141 u8 vport_state_policy[0x4]; 4142 u8 port_state[0x4]; 4143 u8 vport_state[0x4]; 4144 4145 u8 reserved_at_120[0x20]; 4146 4147 u8 system_image_guid[0x40]; 4148 4149 u8 port_guid[0x40]; 4150 4151 u8 node_guid[0x40]; 4152 4153 u8 cap_mask1[0x20]; 4154 4155 u8 cap_mask1_field_select[0x20]; 4156 4157 u8 cap_mask2[0x20]; 4158 4159 u8 cap_mask2_field_select[0x20]; 4160 4161 u8 reserved_at_280[0x80]; 4162 4163 u8 lid[0x10]; 4164 u8 reserved_at_310[0x4]; 4165 u8 init_type_reply[0x4]; 4166 u8 lmc[0x3]; 4167 u8 subnet_timeout[0x5]; 4168 4169 u8 sm_lid[0x10]; 4170 u8 sm_sl[0x4]; 4171 u8 reserved_at_334[0xc]; 4172 4173 u8 qkey_violation_counter[0x10]; 4174 u8 pkey_violation_counter[0x10]; 4175 4176 u8 reserved_at_360[0xca0]; 4177 }; 4178 4179 struct mlx5_ifc_esw_vport_context_bits { 4180 u8 fdb_to_vport_reg_c[0x1]; 4181 u8 reserved_at_1[0x2]; 4182 u8 vport_svlan_strip[0x1]; 4183 u8 vport_cvlan_strip[0x1]; 4184 u8 vport_svlan_insert[0x1]; 4185 u8 vport_cvlan_insert[0x2]; 4186 u8 fdb_to_vport_reg_c_id[0x8]; 4187 u8 reserved_at_10[0x10]; 4188 4189 u8 reserved_at_20[0x20]; 4190 4191 u8 svlan_cfi[0x1]; 4192 u8 svlan_pcp[0x3]; 4193 u8 svlan_id[0xc]; 4194 u8 cvlan_cfi[0x1]; 4195 u8 cvlan_pcp[0x3]; 4196 u8 cvlan_id[0xc]; 4197 4198 u8 reserved_at_60[0x720]; 4199 4200 u8 sw_steering_vport_icm_address_rx[0x40]; 4201 4202 u8 sw_steering_vport_icm_address_tx[0x40]; 4203 }; 4204 4205 enum { 4206 MLX5_EQC_STATUS_OK = 0x0, 4207 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4208 }; 4209 4210 enum { 4211 MLX5_EQC_ST_ARMED = 0x9, 4212 MLX5_EQC_ST_FIRED = 0xa, 4213 }; 4214 4215 struct mlx5_ifc_eqc_bits { 4216 u8 status[0x4]; 4217 u8 reserved_at_4[0x9]; 4218 u8 ec[0x1]; 4219 u8 oi[0x1]; 4220 u8 reserved_at_f[0x5]; 4221 u8 st[0x4]; 4222 u8 reserved_at_18[0x8]; 4223 4224 u8 reserved_at_20[0x20]; 4225 4226 u8 reserved_at_40[0x14]; 4227 u8 page_offset[0x6]; 4228 u8 reserved_at_5a[0x6]; 4229 4230 u8 reserved_at_60[0x3]; 4231 u8 log_eq_size[0x5]; 4232 u8 uar_page[0x18]; 4233 4234 u8 reserved_at_80[0x20]; 4235 4236 u8 reserved_at_a0[0x14]; 4237 u8 intr[0xc]; 4238 4239 u8 reserved_at_c0[0x3]; 4240 u8 log_page_size[0x5]; 4241 u8 reserved_at_c8[0x18]; 4242 4243 u8 reserved_at_e0[0x60]; 4244 4245 u8 reserved_at_140[0x8]; 4246 u8 consumer_counter[0x18]; 4247 4248 u8 reserved_at_160[0x8]; 4249 u8 producer_counter[0x18]; 4250 4251 u8 reserved_at_180[0x80]; 4252 }; 4253 4254 enum { 4255 MLX5_DCTC_STATE_ACTIVE = 0x0, 4256 MLX5_DCTC_STATE_DRAINING = 0x1, 4257 MLX5_DCTC_STATE_DRAINED = 0x2, 4258 }; 4259 4260 enum { 4261 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4262 MLX5_DCTC_CS_RES_NA = 0x1, 4263 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4264 }; 4265 4266 enum { 4267 MLX5_DCTC_MTU_256_BYTES = 0x1, 4268 MLX5_DCTC_MTU_512_BYTES = 0x2, 4269 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4270 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4271 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4272 }; 4273 4274 struct mlx5_ifc_dctc_bits { 4275 u8 reserved_at_0[0x4]; 4276 u8 state[0x4]; 4277 u8 reserved_at_8[0x18]; 4278 4279 u8 reserved_at_20[0x8]; 4280 u8 user_index[0x18]; 4281 4282 u8 reserved_at_40[0x8]; 4283 u8 cqn[0x18]; 4284 4285 u8 counter_set_id[0x8]; 4286 u8 atomic_mode[0x4]; 4287 u8 rre[0x1]; 4288 u8 rwe[0x1]; 4289 u8 rae[0x1]; 4290 u8 atomic_like_write_en[0x1]; 4291 u8 latency_sensitive[0x1]; 4292 u8 rlky[0x1]; 4293 u8 free_ar[0x1]; 4294 u8 reserved_at_73[0xd]; 4295 4296 u8 reserved_at_80[0x8]; 4297 u8 cs_res[0x8]; 4298 u8 reserved_at_90[0x3]; 4299 u8 min_rnr_nak[0x5]; 4300 u8 reserved_at_98[0x8]; 4301 4302 u8 reserved_at_a0[0x8]; 4303 u8 srqn_xrqn[0x18]; 4304 4305 u8 reserved_at_c0[0x8]; 4306 u8 pd[0x18]; 4307 4308 u8 tclass[0x8]; 4309 u8 reserved_at_e8[0x4]; 4310 u8 flow_label[0x14]; 4311 4312 u8 dc_access_key[0x40]; 4313 4314 u8 reserved_at_140[0x5]; 4315 u8 mtu[0x3]; 4316 u8 port[0x8]; 4317 u8 pkey_index[0x10]; 4318 4319 u8 reserved_at_160[0x8]; 4320 u8 my_addr_index[0x8]; 4321 u8 reserved_at_170[0x8]; 4322 u8 hop_limit[0x8]; 4323 4324 u8 dc_access_key_violation_count[0x20]; 4325 4326 u8 reserved_at_1a0[0x14]; 4327 u8 dei_cfi[0x1]; 4328 u8 eth_prio[0x3]; 4329 u8 ecn[0x2]; 4330 u8 dscp[0x6]; 4331 4332 u8 reserved_at_1c0[0x20]; 4333 u8 ece[0x20]; 4334 }; 4335 4336 enum { 4337 MLX5_CQC_STATUS_OK = 0x0, 4338 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4339 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4340 }; 4341 4342 enum { 4343 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4344 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4345 }; 4346 4347 enum { 4348 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4349 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4350 MLX5_CQC_ST_FIRED = 0xa, 4351 }; 4352 4353 enum { 4354 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4355 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4356 MLX5_CQ_PERIOD_NUM_MODES 4357 }; 4358 4359 struct mlx5_ifc_cqc_bits { 4360 u8 status[0x4]; 4361 u8 reserved_at_4[0x2]; 4362 u8 dbr_umem_valid[0x1]; 4363 u8 apu_cq[0x1]; 4364 u8 cqe_sz[0x3]; 4365 u8 cc[0x1]; 4366 u8 reserved_at_c[0x1]; 4367 u8 scqe_break_moderation_en[0x1]; 4368 u8 oi[0x1]; 4369 u8 cq_period_mode[0x2]; 4370 u8 cqe_comp_en[0x1]; 4371 u8 mini_cqe_res_format[0x2]; 4372 u8 st[0x4]; 4373 u8 reserved_at_18[0x6]; 4374 u8 cqe_compression_layout[0x2]; 4375 4376 u8 reserved_at_20[0x20]; 4377 4378 u8 reserved_at_40[0x14]; 4379 u8 page_offset[0x6]; 4380 u8 reserved_at_5a[0x6]; 4381 4382 u8 reserved_at_60[0x3]; 4383 u8 log_cq_size[0x5]; 4384 u8 uar_page[0x18]; 4385 4386 u8 reserved_at_80[0x4]; 4387 u8 cq_period[0xc]; 4388 u8 cq_max_count[0x10]; 4389 4390 u8 c_eqn_or_apu_element[0x20]; 4391 4392 u8 reserved_at_c0[0x3]; 4393 u8 log_page_size[0x5]; 4394 u8 reserved_at_c8[0x18]; 4395 4396 u8 reserved_at_e0[0x20]; 4397 4398 u8 reserved_at_100[0x8]; 4399 u8 last_notified_index[0x18]; 4400 4401 u8 reserved_at_120[0x8]; 4402 u8 last_solicit_index[0x18]; 4403 4404 u8 reserved_at_140[0x8]; 4405 u8 consumer_counter[0x18]; 4406 4407 u8 reserved_at_160[0x8]; 4408 u8 producer_counter[0x18]; 4409 4410 u8 reserved_at_180[0x40]; 4411 4412 u8 dbr_addr[0x40]; 4413 }; 4414 4415 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4416 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4417 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4418 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4419 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4420 u8 reserved_at_0[0x800]; 4421 }; 4422 4423 struct mlx5_ifc_query_adapter_param_block_bits { 4424 u8 reserved_at_0[0xc0]; 4425 4426 u8 reserved_at_c0[0x8]; 4427 u8 ieee_vendor_id[0x18]; 4428 4429 u8 reserved_at_e0[0x10]; 4430 u8 vsd_vendor_id[0x10]; 4431 4432 u8 vsd[208][0x8]; 4433 4434 u8 vsd_contd_psid[16][0x8]; 4435 }; 4436 4437 enum { 4438 MLX5_XRQC_STATE_GOOD = 0x0, 4439 MLX5_XRQC_STATE_ERROR = 0x1, 4440 }; 4441 4442 enum { 4443 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4444 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4445 }; 4446 4447 enum { 4448 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4449 }; 4450 4451 struct mlx5_ifc_tag_matching_topology_context_bits { 4452 u8 log_matching_list_sz[0x4]; 4453 u8 reserved_at_4[0xc]; 4454 u8 append_next_index[0x10]; 4455 4456 u8 sw_phase_cnt[0x10]; 4457 u8 hw_phase_cnt[0x10]; 4458 4459 u8 reserved_at_40[0x40]; 4460 }; 4461 4462 struct mlx5_ifc_xrqc_bits { 4463 u8 state[0x4]; 4464 u8 rlkey[0x1]; 4465 u8 reserved_at_5[0xf]; 4466 u8 topology[0x4]; 4467 u8 reserved_at_18[0x4]; 4468 u8 offload[0x4]; 4469 4470 u8 reserved_at_20[0x8]; 4471 u8 user_index[0x18]; 4472 4473 u8 reserved_at_40[0x8]; 4474 u8 cqn[0x18]; 4475 4476 u8 reserved_at_60[0xa0]; 4477 4478 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4479 4480 u8 reserved_at_180[0x280]; 4481 4482 struct mlx5_ifc_wq_bits wq; 4483 }; 4484 4485 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4486 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4487 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4488 u8 reserved_at_0[0x20]; 4489 }; 4490 4491 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4492 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4493 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4494 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4495 u8 reserved_at_0[0x20]; 4496 }; 4497 4498 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4499 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4500 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4501 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4502 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4503 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4504 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4505 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4506 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4507 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4508 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4509 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4510 u8 reserved_at_0[0x7c0]; 4511 }; 4512 4513 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4514 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4515 u8 reserved_at_0[0x7c0]; 4516 }; 4517 4518 union mlx5_ifc_event_auto_bits { 4519 struct mlx5_ifc_comp_event_bits comp_event; 4520 struct mlx5_ifc_dct_events_bits dct_events; 4521 struct mlx5_ifc_qp_events_bits qp_events; 4522 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4523 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4524 struct mlx5_ifc_cq_error_bits cq_error; 4525 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4526 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4527 struct mlx5_ifc_gpio_event_bits gpio_event; 4528 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4529 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4530 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4531 u8 reserved_at_0[0xe0]; 4532 }; 4533 4534 struct mlx5_ifc_health_buffer_bits { 4535 u8 reserved_at_0[0x100]; 4536 4537 u8 assert_existptr[0x20]; 4538 4539 u8 assert_callra[0x20]; 4540 4541 u8 reserved_at_140[0x20]; 4542 4543 u8 time[0x20]; 4544 4545 u8 fw_version[0x20]; 4546 4547 u8 hw_id[0x20]; 4548 4549 u8 rfr[0x1]; 4550 u8 reserved_at_1c1[0x3]; 4551 u8 valid[0x1]; 4552 u8 severity[0x3]; 4553 u8 reserved_at_1c8[0x18]; 4554 4555 u8 irisc_index[0x8]; 4556 u8 synd[0x8]; 4557 u8 ext_synd[0x10]; 4558 }; 4559 4560 struct mlx5_ifc_register_loopback_control_bits { 4561 u8 no_lb[0x1]; 4562 u8 reserved_at_1[0x7]; 4563 u8 port[0x8]; 4564 u8 reserved_at_10[0x10]; 4565 4566 u8 reserved_at_20[0x60]; 4567 }; 4568 4569 struct mlx5_ifc_vport_tc_element_bits { 4570 u8 traffic_class[0x4]; 4571 u8 reserved_at_4[0xc]; 4572 u8 vport_number[0x10]; 4573 }; 4574 4575 struct mlx5_ifc_vport_element_bits { 4576 u8 reserved_at_0[0x10]; 4577 u8 vport_number[0x10]; 4578 }; 4579 4580 enum { 4581 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4582 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4583 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4584 }; 4585 4586 struct mlx5_ifc_tsar_element_bits { 4587 u8 reserved_at_0[0x8]; 4588 u8 tsar_type[0x8]; 4589 u8 reserved_at_10[0x10]; 4590 }; 4591 4592 enum { 4593 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4594 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4595 }; 4596 4597 struct mlx5_ifc_teardown_hca_out_bits { 4598 u8 status[0x8]; 4599 u8 reserved_at_8[0x18]; 4600 4601 u8 syndrome[0x20]; 4602 4603 u8 reserved_at_40[0x3f]; 4604 4605 u8 state[0x1]; 4606 }; 4607 4608 enum { 4609 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4610 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4611 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4612 }; 4613 4614 struct mlx5_ifc_teardown_hca_in_bits { 4615 u8 opcode[0x10]; 4616 u8 reserved_at_10[0x10]; 4617 4618 u8 reserved_at_20[0x10]; 4619 u8 op_mod[0x10]; 4620 4621 u8 reserved_at_40[0x10]; 4622 u8 profile[0x10]; 4623 4624 u8 reserved_at_60[0x20]; 4625 }; 4626 4627 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4628 u8 status[0x8]; 4629 u8 reserved_at_8[0x18]; 4630 4631 u8 syndrome[0x20]; 4632 4633 u8 reserved_at_40[0x40]; 4634 }; 4635 4636 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4637 u8 opcode[0x10]; 4638 u8 uid[0x10]; 4639 4640 u8 reserved_at_20[0x10]; 4641 u8 op_mod[0x10]; 4642 4643 u8 reserved_at_40[0x8]; 4644 u8 qpn[0x18]; 4645 4646 u8 reserved_at_60[0x20]; 4647 4648 u8 opt_param_mask[0x20]; 4649 4650 u8 reserved_at_a0[0x20]; 4651 4652 struct mlx5_ifc_qpc_bits qpc; 4653 4654 u8 reserved_at_800[0x80]; 4655 }; 4656 4657 struct mlx5_ifc_sqd2rts_qp_out_bits { 4658 u8 status[0x8]; 4659 u8 reserved_at_8[0x18]; 4660 4661 u8 syndrome[0x20]; 4662 4663 u8 reserved_at_40[0x40]; 4664 }; 4665 4666 struct mlx5_ifc_sqd2rts_qp_in_bits { 4667 u8 opcode[0x10]; 4668 u8 uid[0x10]; 4669 4670 u8 reserved_at_20[0x10]; 4671 u8 op_mod[0x10]; 4672 4673 u8 reserved_at_40[0x8]; 4674 u8 qpn[0x18]; 4675 4676 u8 reserved_at_60[0x20]; 4677 4678 u8 opt_param_mask[0x20]; 4679 4680 u8 reserved_at_a0[0x20]; 4681 4682 struct mlx5_ifc_qpc_bits qpc; 4683 4684 u8 reserved_at_800[0x80]; 4685 }; 4686 4687 struct mlx5_ifc_set_roce_address_out_bits { 4688 u8 status[0x8]; 4689 u8 reserved_at_8[0x18]; 4690 4691 u8 syndrome[0x20]; 4692 4693 u8 reserved_at_40[0x40]; 4694 }; 4695 4696 struct mlx5_ifc_set_roce_address_in_bits { 4697 u8 opcode[0x10]; 4698 u8 reserved_at_10[0x10]; 4699 4700 u8 reserved_at_20[0x10]; 4701 u8 op_mod[0x10]; 4702 4703 u8 roce_address_index[0x10]; 4704 u8 reserved_at_50[0xc]; 4705 u8 vhca_port_num[0x4]; 4706 4707 u8 reserved_at_60[0x20]; 4708 4709 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4710 }; 4711 4712 struct mlx5_ifc_set_mad_demux_out_bits { 4713 u8 status[0x8]; 4714 u8 reserved_at_8[0x18]; 4715 4716 u8 syndrome[0x20]; 4717 4718 u8 reserved_at_40[0x40]; 4719 }; 4720 4721 enum { 4722 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4723 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4724 }; 4725 4726 struct mlx5_ifc_set_mad_demux_in_bits { 4727 u8 opcode[0x10]; 4728 u8 reserved_at_10[0x10]; 4729 4730 u8 reserved_at_20[0x10]; 4731 u8 op_mod[0x10]; 4732 4733 u8 reserved_at_40[0x20]; 4734 4735 u8 reserved_at_60[0x6]; 4736 u8 demux_mode[0x2]; 4737 u8 reserved_at_68[0x18]; 4738 }; 4739 4740 struct mlx5_ifc_set_l2_table_entry_out_bits { 4741 u8 status[0x8]; 4742 u8 reserved_at_8[0x18]; 4743 4744 u8 syndrome[0x20]; 4745 4746 u8 reserved_at_40[0x40]; 4747 }; 4748 4749 struct mlx5_ifc_set_l2_table_entry_in_bits { 4750 u8 opcode[0x10]; 4751 u8 reserved_at_10[0x10]; 4752 4753 u8 reserved_at_20[0x10]; 4754 u8 op_mod[0x10]; 4755 4756 u8 reserved_at_40[0x60]; 4757 4758 u8 reserved_at_a0[0x8]; 4759 u8 table_index[0x18]; 4760 4761 u8 reserved_at_c0[0x20]; 4762 4763 u8 reserved_at_e0[0x10]; 4764 u8 silent_mode_valid[0x1]; 4765 u8 silent_mode[0x1]; 4766 u8 reserved_at_f2[0x1]; 4767 u8 vlan_valid[0x1]; 4768 u8 vlan[0xc]; 4769 4770 struct mlx5_ifc_mac_address_layout_bits mac_address; 4771 4772 u8 reserved_at_140[0xc0]; 4773 }; 4774 4775 struct mlx5_ifc_set_issi_out_bits { 4776 u8 status[0x8]; 4777 u8 reserved_at_8[0x18]; 4778 4779 u8 syndrome[0x20]; 4780 4781 u8 reserved_at_40[0x40]; 4782 }; 4783 4784 struct mlx5_ifc_set_issi_in_bits { 4785 u8 opcode[0x10]; 4786 u8 reserved_at_10[0x10]; 4787 4788 u8 reserved_at_20[0x10]; 4789 u8 op_mod[0x10]; 4790 4791 u8 reserved_at_40[0x10]; 4792 u8 current_issi[0x10]; 4793 4794 u8 reserved_at_60[0x20]; 4795 }; 4796 4797 struct mlx5_ifc_set_hca_cap_out_bits { 4798 u8 status[0x8]; 4799 u8 reserved_at_8[0x18]; 4800 4801 u8 syndrome[0x20]; 4802 4803 u8 reserved_at_40[0x40]; 4804 }; 4805 4806 struct mlx5_ifc_set_hca_cap_in_bits { 4807 u8 opcode[0x10]; 4808 u8 reserved_at_10[0x10]; 4809 4810 u8 reserved_at_20[0x10]; 4811 u8 op_mod[0x10]; 4812 4813 u8 other_function[0x1]; 4814 u8 ec_vf_function[0x1]; 4815 u8 reserved_at_42[0xe]; 4816 u8 function_id[0x10]; 4817 4818 u8 reserved_at_60[0x20]; 4819 4820 union mlx5_ifc_hca_cap_union_bits capability; 4821 }; 4822 4823 enum { 4824 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4825 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4826 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4827 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4828 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4829 }; 4830 4831 struct mlx5_ifc_set_fte_out_bits { 4832 u8 status[0x8]; 4833 u8 reserved_at_8[0x18]; 4834 4835 u8 syndrome[0x20]; 4836 4837 u8 reserved_at_40[0x40]; 4838 }; 4839 4840 struct mlx5_ifc_set_fte_in_bits { 4841 u8 opcode[0x10]; 4842 u8 reserved_at_10[0x10]; 4843 4844 u8 reserved_at_20[0x10]; 4845 u8 op_mod[0x10]; 4846 4847 u8 other_vport[0x1]; 4848 u8 reserved_at_41[0xf]; 4849 u8 vport_number[0x10]; 4850 4851 u8 reserved_at_60[0x20]; 4852 4853 u8 table_type[0x8]; 4854 u8 reserved_at_88[0x18]; 4855 4856 u8 reserved_at_a0[0x8]; 4857 u8 table_id[0x18]; 4858 4859 u8 ignore_flow_level[0x1]; 4860 u8 reserved_at_c1[0x17]; 4861 u8 modify_enable_mask[0x8]; 4862 4863 u8 reserved_at_e0[0x20]; 4864 4865 u8 flow_index[0x20]; 4866 4867 u8 reserved_at_120[0xe0]; 4868 4869 struct mlx5_ifc_flow_context_bits flow_context; 4870 }; 4871 4872 struct mlx5_ifc_rts2rts_qp_out_bits { 4873 u8 status[0x8]; 4874 u8 reserved_at_8[0x18]; 4875 4876 u8 syndrome[0x20]; 4877 4878 u8 reserved_at_40[0x20]; 4879 u8 ece[0x20]; 4880 }; 4881 4882 struct mlx5_ifc_rts2rts_qp_in_bits { 4883 u8 opcode[0x10]; 4884 u8 uid[0x10]; 4885 4886 u8 reserved_at_20[0x10]; 4887 u8 op_mod[0x10]; 4888 4889 u8 reserved_at_40[0x8]; 4890 u8 qpn[0x18]; 4891 4892 u8 reserved_at_60[0x20]; 4893 4894 u8 opt_param_mask[0x20]; 4895 4896 u8 ece[0x20]; 4897 4898 struct mlx5_ifc_qpc_bits qpc; 4899 4900 u8 reserved_at_800[0x80]; 4901 }; 4902 4903 struct mlx5_ifc_rtr2rts_qp_out_bits { 4904 u8 status[0x8]; 4905 u8 reserved_at_8[0x18]; 4906 4907 u8 syndrome[0x20]; 4908 4909 u8 reserved_at_40[0x20]; 4910 u8 ece[0x20]; 4911 }; 4912 4913 struct mlx5_ifc_rtr2rts_qp_in_bits { 4914 u8 opcode[0x10]; 4915 u8 uid[0x10]; 4916 4917 u8 reserved_at_20[0x10]; 4918 u8 op_mod[0x10]; 4919 4920 u8 reserved_at_40[0x8]; 4921 u8 qpn[0x18]; 4922 4923 u8 reserved_at_60[0x20]; 4924 4925 u8 opt_param_mask[0x20]; 4926 4927 u8 ece[0x20]; 4928 4929 struct mlx5_ifc_qpc_bits qpc; 4930 4931 u8 reserved_at_800[0x80]; 4932 }; 4933 4934 struct mlx5_ifc_rst2init_qp_out_bits { 4935 u8 status[0x8]; 4936 u8 reserved_at_8[0x18]; 4937 4938 u8 syndrome[0x20]; 4939 4940 u8 reserved_at_40[0x20]; 4941 u8 ece[0x20]; 4942 }; 4943 4944 struct mlx5_ifc_rst2init_qp_in_bits { 4945 u8 opcode[0x10]; 4946 u8 uid[0x10]; 4947 4948 u8 reserved_at_20[0x10]; 4949 u8 op_mod[0x10]; 4950 4951 u8 reserved_at_40[0x8]; 4952 u8 qpn[0x18]; 4953 4954 u8 reserved_at_60[0x20]; 4955 4956 u8 opt_param_mask[0x20]; 4957 4958 u8 ece[0x20]; 4959 4960 struct mlx5_ifc_qpc_bits qpc; 4961 4962 u8 reserved_at_800[0x80]; 4963 }; 4964 4965 struct mlx5_ifc_query_xrq_out_bits { 4966 u8 status[0x8]; 4967 u8 reserved_at_8[0x18]; 4968 4969 u8 syndrome[0x20]; 4970 4971 u8 reserved_at_40[0x40]; 4972 4973 struct mlx5_ifc_xrqc_bits xrq_context; 4974 }; 4975 4976 struct mlx5_ifc_query_xrq_in_bits { 4977 u8 opcode[0x10]; 4978 u8 reserved_at_10[0x10]; 4979 4980 u8 reserved_at_20[0x10]; 4981 u8 op_mod[0x10]; 4982 4983 u8 reserved_at_40[0x8]; 4984 u8 xrqn[0x18]; 4985 4986 u8 reserved_at_60[0x20]; 4987 }; 4988 4989 struct mlx5_ifc_query_xrc_srq_out_bits { 4990 u8 status[0x8]; 4991 u8 reserved_at_8[0x18]; 4992 4993 u8 syndrome[0x20]; 4994 4995 u8 reserved_at_40[0x40]; 4996 4997 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4998 4999 u8 reserved_at_280[0x600]; 5000 5001 u8 pas[][0x40]; 5002 }; 5003 5004 struct mlx5_ifc_query_xrc_srq_in_bits { 5005 u8 opcode[0x10]; 5006 u8 reserved_at_10[0x10]; 5007 5008 u8 reserved_at_20[0x10]; 5009 u8 op_mod[0x10]; 5010 5011 u8 reserved_at_40[0x8]; 5012 u8 xrc_srqn[0x18]; 5013 5014 u8 reserved_at_60[0x20]; 5015 }; 5016 5017 enum { 5018 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5019 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5020 }; 5021 5022 struct mlx5_ifc_query_vport_state_out_bits { 5023 u8 status[0x8]; 5024 u8 reserved_at_8[0x18]; 5025 5026 u8 syndrome[0x20]; 5027 5028 u8 reserved_at_40[0x20]; 5029 5030 u8 reserved_at_60[0x18]; 5031 u8 admin_state[0x4]; 5032 u8 state[0x4]; 5033 }; 5034 5035 enum { 5036 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5037 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5038 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5039 }; 5040 5041 struct mlx5_ifc_arm_monitor_counter_in_bits { 5042 u8 opcode[0x10]; 5043 u8 uid[0x10]; 5044 5045 u8 reserved_at_20[0x10]; 5046 u8 op_mod[0x10]; 5047 5048 u8 reserved_at_40[0x20]; 5049 5050 u8 reserved_at_60[0x20]; 5051 }; 5052 5053 struct mlx5_ifc_arm_monitor_counter_out_bits { 5054 u8 status[0x8]; 5055 u8 reserved_at_8[0x18]; 5056 5057 u8 syndrome[0x20]; 5058 5059 u8 reserved_at_40[0x40]; 5060 }; 5061 5062 enum { 5063 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5064 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5065 }; 5066 5067 enum mlx5_monitor_counter_ppcnt { 5068 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5069 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5070 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5071 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5072 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5073 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5074 }; 5075 5076 enum { 5077 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5078 }; 5079 5080 struct mlx5_ifc_monitor_counter_output_bits { 5081 u8 reserved_at_0[0x4]; 5082 u8 type[0x4]; 5083 u8 reserved_at_8[0x8]; 5084 u8 counter[0x10]; 5085 5086 u8 counter_group_id[0x20]; 5087 }; 5088 5089 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5090 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5091 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5092 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5093 5094 struct mlx5_ifc_set_monitor_counter_in_bits { 5095 u8 opcode[0x10]; 5096 u8 uid[0x10]; 5097 5098 u8 reserved_at_20[0x10]; 5099 u8 op_mod[0x10]; 5100 5101 u8 reserved_at_40[0x10]; 5102 u8 num_of_counters[0x10]; 5103 5104 u8 reserved_at_60[0x20]; 5105 5106 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5107 }; 5108 5109 struct mlx5_ifc_set_monitor_counter_out_bits { 5110 u8 status[0x8]; 5111 u8 reserved_at_8[0x18]; 5112 5113 u8 syndrome[0x20]; 5114 5115 u8 reserved_at_40[0x40]; 5116 }; 5117 5118 struct mlx5_ifc_query_vport_state_in_bits { 5119 u8 opcode[0x10]; 5120 u8 reserved_at_10[0x10]; 5121 5122 u8 reserved_at_20[0x10]; 5123 u8 op_mod[0x10]; 5124 5125 u8 other_vport[0x1]; 5126 u8 reserved_at_41[0xf]; 5127 u8 vport_number[0x10]; 5128 5129 u8 reserved_at_60[0x20]; 5130 }; 5131 5132 struct mlx5_ifc_query_vnic_env_out_bits { 5133 u8 status[0x8]; 5134 u8 reserved_at_8[0x18]; 5135 5136 u8 syndrome[0x20]; 5137 5138 u8 reserved_at_40[0x40]; 5139 5140 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5141 }; 5142 5143 enum { 5144 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5145 }; 5146 5147 struct mlx5_ifc_query_vnic_env_in_bits { 5148 u8 opcode[0x10]; 5149 u8 reserved_at_10[0x10]; 5150 5151 u8 reserved_at_20[0x10]; 5152 u8 op_mod[0x10]; 5153 5154 u8 other_vport[0x1]; 5155 u8 reserved_at_41[0xf]; 5156 u8 vport_number[0x10]; 5157 5158 u8 reserved_at_60[0x20]; 5159 }; 5160 5161 struct mlx5_ifc_query_vport_counter_out_bits { 5162 u8 status[0x8]; 5163 u8 reserved_at_8[0x18]; 5164 5165 u8 syndrome[0x20]; 5166 5167 u8 reserved_at_40[0x40]; 5168 5169 struct mlx5_ifc_traffic_counter_bits received_errors; 5170 5171 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5172 5173 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5174 5175 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5176 5177 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5178 5179 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5180 5181 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5182 5183 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5184 5185 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5186 5187 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5188 5189 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5190 5191 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5192 5193 struct mlx5_ifc_traffic_counter_bits local_loopback; 5194 5195 u8 reserved_at_700[0x980]; 5196 }; 5197 5198 enum { 5199 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5200 }; 5201 5202 struct mlx5_ifc_query_vport_counter_in_bits { 5203 u8 opcode[0x10]; 5204 u8 reserved_at_10[0x10]; 5205 5206 u8 reserved_at_20[0x10]; 5207 u8 op_mod[0x10]; 5208 5209 u8 other_vport[0x1]; 5210 u8 reserved_at_41[0xb]; 5211 u8 port_num[0x4]; 5212 u8 vport_number[0x10]; 5213 5214 u8 reserved_at_60[0x60]; 5215 5216 u8 clear[0x1]; 5217 u8 reserved_at_c1[0x1f]; 5218 5219 u8 reserved_at_e0[0x20]; 5220 }; 5221 5222 struct mlx5_ifc_query_tis_out_bits { 5223 u8 status[0x8]; 5224 u8 reserved_at_8[0x18]; 5225 5226 u8 syndrome[0x20]; 5227 5228 u8 reserved_at_40[0x40]; 5229 5230 struct mlx5_ifc_tisc_bits tis_context; 5231 }; 5232 5233 struct mlx5_ifc_query_tis_in_bits { 5234 u8 opcode[0x10]; 5235 u8 reserved_at_10[0x10]; 5236 5237 u8 reserved_at_20[0x10]; 5238 u8 op_mod[0x10]; 5239 5240 u8 reserved_at_40[0x8]; 5241 u8 tisn[0x18]; 5242 5243 u8 reserved_at_60[0x20]; 5244 }; 5245 5246 struct mlx5_ifc_query_tir_out_bits { 5247 u8 status[0x8]; 5248 u8 reserved_at_8[0x18]; 5249 5250 u8 syndrome[0x20]; 5251 5252 u8 reserved_at_40[0xc0]; 5253 5254 struct mlx5_ifc_tirc_bits tir_context; 5255 }; 5256 5257 struct mlx5_ifc_query_tir_in_bits { 5258 u8 opcode[0x10]; 5259 u8 reserved_at_10[0x10]; 5260 5261 u8 reserved_at_20[0x10]; 5262 u8 op_mod[0x10]; 5263 5264 u8 reserved_at_40[0x8]; 5265 u8 tirn[0x18]; 5266 5267 u8 reserved_at_60[0x20]; 5268 }; 5269 5270 struct mlx5_ifc_query_srq_out_bits { 5271 u8 status[0x8]; 5272 u8 reserved_at_8[0x18]; 5273 5274 u8 syndrome[0x20]; 5275 5276 u8 reserved_at_40[0x40]; 5277 5278 struct mlx5_ifc_srqc_bits srq_context_entry; 5279 5280 u8 reserved_at_280[0x600]; 5281 5282 u8 pas[][0x40]; 5283 }; 5284 5285 struct mlx5_ifc_query_srq_in_bits { 5286 u8 opcode[0x10]; 5287 u8 reserved_at_10[0x10]; 5288 5289 u8 reserved_at_20[0x10]; 5290 u8 op_mod[0x10]; 5291 5292 u8 reserved_at_40[0x8]; 5293 u8 srqn[0x18]; 5294 5295 u8 reserved_at_60[0x20]; 5296 }; 5297 5298 struct mlx5_ifc_query_sq_out_bits { 5299 u8 status[0x8]; 5300 u8 reserved_at_8[0x18]; 5301 5302 u8 syndrome[0x20]; 5303 5304 u8 reserved_at_40[0xc0]; 5305 5306 struct mlx5_ifc_sqc_bits sq_context; 5307 }; 5308 5309 struct mlx5_ifc_query_sq_in_bits { 5310 u8 opcode[0x10]; 5311 u8 reserved_at_10[0x10]; 5312 5313 u8 reserved_at_20[0x10]; 5314 u8 op_mod[0x10]; 5315 5316 u8 reserved_at_40[0x8]; 5317 u8 sqn[0x18]; 5318 5319 u8 reserved_at_60[0x20]; 5320 }; 5321 5322 struct mlx5_ifc_query_special_contexts_out_bits { 5323 u8 status[0x8]; 5324 u8 reserved_at_8[0x18]; 5325 5326 u8 syndrome[0x20]; 5327 5328 u8 dump_fill_mkey[0x20]; 5329 5330 u8 resd_lkey[0x20]; 5331 5332 u8 null_mkey[0x20]; 5333 5334 u8 terminate_scatter_list_mkey[0x20]; 5335 5336 u8 repeated_mkey[0x20]; 5337 5338 u8 reserved_at_a0[0x20]; 5339 }; 5340 5341 struct mlx5_ifc_query_special_contexts_in_bits { 5342 u8 opcode[0x10]; 5343 u8 reserved_at_10[0x10]; 5344 5345 u8 reserved_at_20[0x10]; 5346 u8 op_mod[0x10]; 5347 5348 u8 reserved_at_40[0x40]; 5349 }; 5350 5351 struct mlx5_ifc_query_scheduling_element_out_bits { 5352 u8 opcode[0x10]; 5353 u8 reserved_at_10[0x10]; 5354 5355 u8 reserved_at_20[0x10]; 5356 u8 op_mod[0x10]; 5357 5358 u8 reserved_at_40[0xc0]; 5359 5360 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5361 5362 u8 reserved_at_300[0x100]; 5363 }; 5364 5365 enum { 5366 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5367 SCHEDULING_HIERARCHY_NIC = 0x3, 5368 }; 5369 5370 struct mlx5_ifc_query_scheduling_element_in_bits { 5371 u8 opcode[0x10]; 5372 u8 reserved_at_10[0x10]; 5373 5374 u8 reserved_at_20[0x10]; 5375 u8 op_mod[0x10]; 5376 5377 u8 scheduling_hierarchy[0x8]; 5378 u8 reserved_at_48[0x18]; 5379 5380 u8 scheduling_element_id[0x20]; 5381 5382 u8 reserved_at_80[0x180]; 5383 }; 5384 5385 struct mlx5_ifc_query_rqt_out_bits { 5386 u8 status[0x8]; 5387 u8 reserved_at_8[0x18]; 5388 5389 u8 syndrome[0x20]; 5390 5391 u8 reserved_at_40[0xc0]; 5392 5393 struct mlx5_ifc_rqtc_bits rqt_context; 5394 }; 5395 5396 struct mlx5_ifc_query_rqt_in_bits { 5397 u8 opcode[0x10]; 5398 u8 reserved_at_10[0x10]; 5399 5400 u8 reserved_at_20[0x10]; 5401 u8 op_mod[0x10]; 5402 5403 u8 reserved_at_40[0x8]; 5404 u8 rqtn[0x18]; 5405 5406 u8 reserved_at_60[0x20]; 5407 }; 5408 5409 struct mlx5_ifc_query_rq_out_bits { 5410 u8 status[0x8]; 5411 u8 reserved_at_8[0x18]; 5412 5413 u8 syndrome[0x20]; 5414 5415 u8 reserved_at_40[0xc0]; 5416 5417 struct mlx5_ifc_rqc_bits rq_context; 5418 }; 5419 5420 struct mlx5_ifc_query_rq_in_bits { 5421 u8 opcode[0x10]; 5422 u8 reserved_at_10[0x10]; 5423 5424 u8 reserved_at_20[0x10]; 5425 u8 op_mod[0x10]; 5426 5427 u8 reserved_at_40[0x8]; 5428 u8 rqn[0x18]; 5429 5430 u8 reserved_at_60[0x20]; 5431 }; 5432 5433 struct mlx5_ifc_query_roce_address_out_bits { 5434 u8 status[0x8]; 5435 u8 reserved_at_8[0x18]; 5436 5437 u8 syndrome[0x20]; 5438 5439 u8 reserved_at_40[0x40]; 5440 5441 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5442 }; 5443 5444 struct mlx5_ifc_query_roce_address_in_bits { 5445 u8 opcode[0x10]; 5446 u8 reserved_at_10[0x10]; 5447 5448 u8 reserved_at_20[0x10]; 5449 u8 op_mod[0x10]; 5450 5451 u8 roce_address_index[0x10]; 5452 u8 reserved_at_50[0xc]; 5453 u8 vhca_port_num[0x4]; 5454 5455 u8 reserved_at_60[0x20]; 5456 }; 5457 5458 struct mlx5_ifc_query_rmp_out_bits { 5459 u8 status[0x8]; 5460 u8 reserved_at_8[0x18]; 5461 5462 u8 syndrome[0x20]; 5463 5464 u8 reserved_at_40[0xc0]; 5465 5466 struct mlx5_ifc_rmpc_bits rmp_context; 5467 }; 5468 5469 struct mlx5_ifc_query_rmp_in_bits { 5470 u8 opcode[0x10]; 5471 u8 reserved_at_10[0x10]; 5472 5473 u8 reserved_at_20[0x10]; 5474 u8 op_mod[0x10]; 5475 5476 u8 reserved_at_40[0x8]; 5477 u8 rmpn[0x18]; 5478 5479 u8 reserved_at_60[0x20]; 5480 }; 5481 5482 struct mlx5_ifc_cqe_error_syndrome_bits { 5483 u8 hw_error_syndrome[0x8]; 5484 u8 hw_syndrome_type[0x4]; 5485 u8 reserved_at_c[0x4]; 5486 u8 vendor_error_syndrome[0x8]; 5487 u8 syndrome[0x8]; 5488 }; 5489 5490 struct mlx5_ifc_qp_context_extension_bits { 5491 u8 reserved_at_0[0x60]; 5492 5493 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5494 5495 u8 reserved_at_80[0x580]; 5496 }; 5497 5498 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5499 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5500 5501 u8 pas[0][0x40]; 5502 }; 5503 5504 struct mlx5_ifc_qp_pas_list_in_bits { 5505 struct mlx5_ifc_cmd_pas_bits pas[0]; 5506 }; 5507 5508 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5509 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5510 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5511 }; 5512 5513 struct mlx5_ifc_query_qp_out_bits { 5514 u8 status[0x8]; 5515 u8 reserved_at_8[0x18]; 5516 5517 u8 syndrome[0x20]; 5518 5519 u8 reserved_at_40[0x40]; 5520 5521 u8 opt_param_mask[0x20]; 5522 5523 u8 ece[0x20]; 5524 5525 struct mlx5_ifc_qpc_bits qpc; 5526 5527 u8 reserved_at_800[0x80]; 5528 5529 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5530 }; 5531 5532 struct mlx5_ifc_query_qp_in_bits { 5533 u8 opcode[0x10]; 5534 u8 reserved_at_10[0x10]; 5535 5536 u8 reserved_at_20[0x10]; 5537 u8 op_mod[0x10]; 5538 5539 u8 qpc_ext[0x1]; 5540 u8 reserved_at_41[0x7]; 5541 u8 qpn[0x18]; 5542 5543 u8 reserved_at_60[0x20]; 5544 }; 5545 5546 struct mlx5_ifc_query_q_counter_out_bits { 5547 u8 status[0x8]; 5548 u8 reserved_at_8[0x18]; 5549 5550 u8 syndrome[0x20]; 5551 5552 u8 reserved_at_40[0x40]; 5553 5554 u8 rx_write_requests[0x20]; 5555 5556 u8 reserved_at_a0[0x20]; 5557 5558 u8 rx_read_requests[0x20]; 5559 5560 u8 reserved_at_e0[0x20]; 5561 5562 u8 rx_atomic_requests[0x20]; 5563 5564 u8 reserved_at_120[0x20]; 5565 5566 u8 rx_dct_connect[0x20]; 5567 5568 u8 reserved_at_160[0x20]; 5569 5570 u8 out_of_buffer[0x20]; 5571 5572 u8 reserved_at_1a0[0x20]; 5573 5574 u8 out_of_sequence[0x20]; 5575 5576 u8 reserved_at_1e0[0x20]; 5577 5578 u8 duplicate_request[0x20]; 5579 5580 u8 reserved_at_220[0x20]; 5581 5582 u8 rnr_nak_retry_err[0x20]; 5583 5584 u8 reserved_at_260[0x20]; 5585 5586 u8 packet_seq_err[0x20]; 5587 5588 u8 reserved_at_2a0[0x20]; 5589 5590 u8 implied_nak_seq_err[0x20]; 5591 5592 u8 reserved_at_2e0[0x20]; 5593 5594 u8 local_ack_timeout_err[0x20]; 5595 5596 u8 reserved_at_320[0xa0]; 5597 5598 u8 resp_local_length_error[0x20]; 5599 5600 u8 req_local_length_error[0x20]; 5601 5602 u8 resp_local_qp_error[0x20]; 5603 5604 u8 local_operation_error[0x20]; 5605 5606 u8 resp_local_protection[0x20]; 5607 5608 u8 req_local_protection[0x20]; 5609 5610 u8 resp_cqe_error[0x20]; 5611 5612 u8 req_cqe_error[0x20]; 5613 5614 u8 req_mw_binding[0x20]; 5615 5616 u8 req_bad_response[0x20]; 5617 5618 u8 req_remote_invalid_request[0x20]; 5619 5620 u8 resp_remote_invalid_request[0x20]; 5621 5622 u8 req_remote_access_errors[0x20]; 5623 5624 u8 resp_remote_access_errors[0x20]; 5625 5626 u8 req_remote_operation_errors[0x20]; 5627 5628 u8 req_transport_retries_exceeded[0x20]; 5629 5630 u8 cq_overflow[0x20]; 5631 5632 u8 resp_cqe_flush_error[0x20]; 5633 5634 u8 req_cqe_flush_error[0x20]; 5635 5636 u8 reserved_at_620[0x20]; 5637 5638 u8 roce_adp_retrans[0x20]; 5639 5640 u8 roce_adp_retrans_to[0x20]; 5641 5642 u8 roce_slow_restart[0x20]; 5643 5644 u8 roce_slow_restart_cnps[0x20]; 5645 5646 u8 roce_slow_restart_trans[0x20]; 5647 5648 u8 reserved_at_6e0[0x120]; 5649 }; 5650 5651 struct mlx5_ifc_query_q_counter_in_bits { 5652 u8 opcode[0x10]; 5653 u8 reserved_at_10[0x10]; 5654 5655 u8 reserved_at_20[0x10]; 5656 u8 op_mod[0x10]; 5657 5658 u8 other_vport[0x1]; 5659 u8 reserved_at_41[0xf]; 5660 u8 vport_number[0x10]; 5661 5662 u8 reserved_at_60[0x60]; 5663 5664 u8 clear[0x1]; 5665 u8 aggregate[0x1]; 5666 u8 reserved_at_c2[0x1e]; 5667 5668 u8 reserved_at_e0[0x18]; 5669 u8 counter_set_id[0x8]; 5670 }; 5671 5672 struct mlx5_ifc_query_pages_out_bits { 5673 u8 status[0x8]; 5674 u8 reserved_at_8[0x18]; 5675 5676 u8 syndrome[0x20]; 5677 5678 u8 embedded_cpu_function[0x1]; 5679 u8 reserved_at_41[0xf]; 5680 u8 function_id[0x10]; 5681 5682 u8 num_pages[0x20]; 5683 }; 5684 5685 enum { 5686 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5687 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5688 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5689 }; 5690 5691 struct mlx5_ifc_query_pages_in_bits { 5692 u8 opcode[0x10]; 5693 u8 reserved_at_10[0x10]; 5694 5695 u8 reserved_at_20[0x10]; 5696 u8 op_mod[0x10]; 5697 5698 u8 embedded_cpu_function[0x1]; 5699 u8 reserved_at_41[0xf]; 5700 u8 function_id[0x10]; 5701 5702 u8 reserved_at_60[0x20]; 5703 }; 5704 5705 struct mlx5_ifc_query_nic_vport_context_out_bits { 5706 u8 status[0x8]; 5707 u8 reserved_at_8[0x18]; 5708 5709 u8 syndrome[0x20]; 5710 5711 u8 reserved_at_40[0x40]; 5712 5713 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5714 }; 5715 5716 struct mlx5_ifc_query_nic_vport_context_in_bits { 5717 u8 opcode[0x10]; 5718 u8 reserved_at_10[0x10]; 5719 5720 u8 reserved_at_20[0x10]; 5721 u8 op_mod[0x10]; 5722 5723 u8 other_vport[0x1]; 5724 u8 reserved_at_41[0xf]; 5725 u8 vport_number[0x10]; 5726 5727 u8 reserved_at_60[0x5]; 5728 u8 allowed_list_type[0x3]; 5729 u8 reserved_at_68[0x18]; 5730 }; 5731 5732 struct mlx5_ifc_query_mkey_out_bits { 5733 u8 status[0x8]; 5734 u8 reserved_at_8[0x18]; 5735 5736 u8 syndrome[0x20]; 5737 5738 u8 reserved_at_40[0x40]; 5739 5740 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5741 5742 u8 reserved_at_280[0x600]; 5743 5744 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5745 5746 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5747 }; 5748 5749 struct mlx5_ifc_query_mkey_in_bits { 5750 u8 opcode[0x10]; 5751 u8 reserved_at_10[0x10]; 5752 5753 u8 reserved_at_20[0x10]; 5754 u8 op_mod[0x10]; 5755 5756 u8 reserved_at_40[0x8]; 5757 u8 mkey_index[0x18]; 5758 5759 u8 pg_access[0x1]; 5760 u8 reserved_at_61[0x1f]; 5761 }; 5762 5763 struct mlx5_ifc_query_mad_demux_out_bits { 5764 u8 status[0x8]; 5765 u8 reserved_at_8[0x18]; 5766 5767 u8 syndrome[0x20]; 5768 5769 u8 reserved_at_40[0x40]; 5770 5771 u8 mad_dumux_parameters_block[0x20]; 5772 }; 5773 5774 struct mlx5_ifc_query_mad_demux_in_bits { 5775 u8 opcode[0x10]; 5776 u8 reserved_at_10[0x10]; 5777 5778 u8 reserved_at_20[0x10]; 5779 u8 op_mod[0x10]; 5780 5781 u8 reserved_at_40[0x40]; 5782 }; 5783 5784 struct mlx5_ifc_query_l2_table_entry_out_bits { 5785 u8 status[0x8]; 5786 u8 reserved_at_8[0x18]; 5787 5788 u8 syndrome[0x20]; 5789 5790 u8 reserved_at_40[0xa0]; 5791 5792 u8 reserved_at_e0[0x13]; 5793 u8 vlan_valid[0x1]; 5794 u8 vlan[0xc]; 5795 5796 struct mlx5_ifc_mac_address_layout_bits mac_address; 5797 5798 u8 reserved_at_140[0xc0]; 5799 }; 5800 5801 struct mlx5_ifc_query_l2_table_entry_in_bits { 5802 u8 opcode[0x10]; 5803 u8 reserved_at_10[0x10]; 5804 5805 u8 reserved_at_20[0x10]; 5806 u8 op_mod[0x10]; 5807 5808 u8 reserved_at_40[0x60]; 5809 5810 u8 reserved_at_a0[0x8]; 5811 u8 table_index[0x18]; 5812 5813 u8 reserved_at_c0[0x140]; 5814 }; 5815 5816 struct mlx5_ifc_query_issi_out_bits { 5817 u8 status[0x8]; 5818 u8 reserved_at_8[0x18]; 5819 5820 u8 syndrome[0x20]; 5821 5822 u8 reserved_at_40[0x10]; 5823 u8 current_issi[0x10]; 5824 5825 u8 reserved_at_60[0xa0]; 5826 5827 u8 reserved_at_100[76][0x8]; 5828 u8 supported_issi_dw0[0x20]; 5829 }; 5830 5831 struct mlx5_ifc_query_issi_in_bits { 5832 u8 opcode[0x10]; 5833 u8 reserved_at_10[0x10]; 5834 5835 u8 reserved_at_20[0x10]; 5836 u8 op_mod[0x10]; 5837 5838 u8 reserved_at_40[0x40]; 5839 }; 5840 5841 struct mlx5_ifc_set_driver_version_out_bits { 5842 u8 status[0x8]; 5843 u8 reserved_0[0x18]; 5844 5845 u8 syndrome[0x20]; 5846 u8 reserved_1[0x40]; 5847 }; 5848 5849 struct mlx5_ifc_set_driver_version_in_bits { 5850 u8 opcode[0x10]; 5851 u8 reserved_0[0x10]; 5852 5853 u8 reserved_1[0x10]; 5854 u8 op_mod[0x10]; 5855 5856 u8 reserved_2[0x40]; 5857 u8 driver_version[64][0x8]; 5858 }; 5859 5860 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5861 u8 status[0x8]; 5862 u8 reserved_at_8[0x18]; 5863 5864 u8 syndrome[0x20]; 5865 5866 u8 reserved_at_40[0x40]; 5867 5868 struct mlx5_ifc_pkey_bits pkey[]; 5869 }; 5870 5871 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5872 u8 opcode[0x10]; 5873 u8 reserved_at_10[0x10]; 5874 5875 u8 reserved_at_20[0x10]; 5876 u8 op_mod[0x10]; 5877 5878 u8 other_vport[0x1]; 5879 u8 reserved_at_41[0xb]; 5880 u8 port_num[0x4]; 5881 u8 vport_number[0x10]; 5882 5883 u8 reserved_at_60[0x10]; 5884 u8 pkey_index[0x10]; 5885 }; 5886 5887 enum { 5888 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5889 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5890 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5891 }; 5892 5893 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5894 u8 status[0x8]; 5895 u8 reserved_at_8[0x18]; 5896 5897 u8 syndrome[0x20]; 5898 5899 u8 reserved_at_40[0x20]; 5900 5901 u8 gids_num[0x10]; 5902 u8 reserved_at_70[0x10]; 5903 5904 struct mlx5_ifc_array128_auto_bits gid[]; 5905 }; 5906 5907 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5908 u8 opcode[0x10]; 5909 u8 reserved_at_10[0x10]; 5910 5911 u8 reserved_at_20[0x10]; 5912 u8 op_mod[0x10]; 5913 5914 u8 other_vport[0x1]; 5915 u8 reserved_at_41[0xb]; 5916 u8 port_num[0x4]; 5917 u8 vport_number[0x10]; 5918 5919 u8 reserved_at_60[0x10]; 5920 u8 gid_index[0x10]; 5921 }; 5922 5923 struct mlx5_ifc_query_hca_vport_context_out_bits { 5924 u8 status[0x8]; 5925 u8 reserved_at_8[0x18]; 5926 5927 u8 syndrome[0x20]; 5928 5929 u8 reserved_at_40[0x40]; 5930 5931 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5932 }; 5933 5934 struct mlx5_ifc_query_hca_vport_context_in_bits { 5935 u8 opcode[0x10]; 5936 u8 reserved_at_10[0x10]; 5937 5938 u8 reserved_at_20[0x10]; 5939 u8 op_mod[0x10]; 5940 5941 u8 other_vport[0x1]; 5942 u8 reserved_at_41[0xb]; 5943 u8 port_num[0x4]; 5944 u8 vport_number[0x10]; 5945 5946 u8 reserved_at_60[0x20]; 5947 }; 5948 5949 struct mlx5_ifc_query_hca_cap_out_bits { 5950 u8 status[0x8]; 5951 u8 reserved_at_8[0x18]; 5952 5953 u8 syndrome[0x20]; 5954 5955 u8 reserved_at_40[0x40]; 5956 5957 union mlx5_ifc_hca_cap_union_bits capability; 5958 }; 5959 5960 struct mlx5_ifc_query_hca_cap_in_bits { 5961 u8 opcode[0x10]; 5962 u8 reserved_at_10[0x10]; 5963 5964 u8 reserved_at_20[0x10]; 5965 u8 op_mod[0x10]; 5966 5967 u8 other_function[0x1]; 5968 u8 ec_vf_function[0x1]; 5969 u8 reserved_at_42[0xe]; 5970 u8 function_id[0x10]; 5971 5972 u8 reserved_at_60[0x20]; 5973 }; 5974 5975 struct mlx5_ifc_other_hca_cap_bits { 5976 u8 roce[0x1]; 5977 u8 reserved_at_1[0x27f]; 5978 }; 5979 5980 struct mlx5_ifc_query_other_hca_cap_out_bits { 5981 u8 status[0x8]; 5982 u8 reserved_at_8[0x18]; 5983 5984 u8 syndrome[0x20]; 5985 5986 u8 reserved_at_40[0x40]; 5987 5988 struct mlx5_ifc_other_hca_cap_bits other_capability; 5989 }; 5990 5991 struct mlx5_ifc_query_other_hca_cap_in_bits { 5992 u8 opcode[0x10]; 5993 u8 reserved_at_10[0x10]; 5994 5995 u8 reserved_at_20[0x10]; 5996 u8 op_mod[0x10]; 5997 5998 u8 reserved_at_40[0x10]; 5999 u8 function_id[0x10]; 6000 6001 u8 reserved_at_60[0x20]; 6002 }; 6003 6004 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6005 u8 status[0x8]; 6006 u8 reserved_at_8[0x18]; 6007 6008 u8 syndrome[0x20]; 6009 6010 u8 reserved_at_40[0x40]; 6011 }; 6012 6013 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6014 u8 opcode[0x10]; 6015 u8 reserved_at_10[0x10]; 6016 6017 u8 reserved_at_20[0x10]; 6018 u8 op_mod[0x10]; 6019 6020 u8 reserved_at_40[0x10]; 6021 u8 function_id[0x10]; 6022 u8 field_select[0x20]; 6023 6024 struct mlx5_ifc_other_hca_cap_bits other_capability; 6025 }; 6026 6027 struct mlx5_ifc_flow_table_context_bits { 6028 u8 reformat_en[0x1]; 6029 u8 decap_en[0x1]; 6030 u8 sw_owner[0x1]; 6031 u8 termination_table[0x1]; 6032 u8 table_miss_action[0x4]; 6033 u8 level[0x8]; 6034 u8 reserved_at_10[0x8]; 6035 u8 log_size[0x8]; 6036 6037 u8 reserved_at_20[0x8]; 6038 u8 table_miss_id[0x18]; 6039 6040 u8 reserved_at_40[0x8]; 6041 u8 lag_master_next_table_id[0x18]; 6042 6043 u8 reserved_at_60[0x60]; 6044 6045 u8 sw_owner_icm_root_1[0x40]; 6046 6047 u8 sw_owner_icm_root_0[0x40]; 6048 6049 }; 6050 6051 struct mlx5_ifc_query_flow_table_out_bits { 6052 u8 status[0x8]; 6053 u8 reserved_at_8[0x18]; 6054 6055 u8 syndrome[0x20]; 6056 6057 u8 reserved_at_40[0x80]; 6058 6059 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6060 }; 6061 6062 struct mlx5_ifc_query_flow_table_in_bits { 6063 u8 opcode[0x10]; 6064 u8 reserved_at_10[0x10]; 6065 6066 u8 reserved_at_20[0x10]; 6067 u8 op_mod[0x10]; 6068 6069 u8 reserved_at_40[0x40]; 6070 6071 u8 table_type[0x8]; 6072 u8 reserved_at_88[0x18]; 6073 6074 u8 reserved_at_a0[0x8]; 6075 u8 table_id[0x18]; 6076 6077 u8 reserved_at_c0[0x140]; 6078 }; 6079 6080 struct mlx5_ifc_query_fte_out_bits { 6081 u8 status[0x8]; 6082 u8 reserved_at_8[0x18]; 6083 6084 u8 syndrome[0x20]; 6085 6086 u8 reserved_at_40[0x1c0]; 6087 6088 struct mlx5_ifc_flow_context_bits flow_context; 6089 }; 6090 6091 struct mlx5_ifc_query_fte_in_bits { 6092 u8 opcode[0x10]; 6093 u8 reserved_at_10[0x10]; 6094 6095 u8 reserved_at_20[0x10]; 6096 u8 op_mod[0x10]; 6097 6098 u8 reserved_at_40[0x40]; 6099 6100 u8 table_type[0x8]; 6101 u8 reserved_at_88[0x18]; 6102 6103 u8 reserved_at_a0[0x8]; 6104 u8 table_id[0x18]; 6105 6106 u8 reserved_at_c0[0x40]; 6107 6108 u8 flow_index[0x20]; 6109 6110 u8 reserved_at_120[0xe0]; 6111 }; 6112 6113 struct mlx5_ifc_match_definer_format_0_bits { 6114 u8 reserved_at_0[0x100]; 6115 6116 u8 metadata_reg_c_0[0x20]; 6117 6118 u8 metadata_reg_c_1[0x20]; 6119 6120 u8 outer_dmac_47_16[0x20]; 6121 6122 u8 outer_dmac_15_0[0x10]; 6123 u8 outer_ethertype[0x10]; 6124 6125 u8 reserved_at_180[0x1]; 6126 u8 sx_sniffer[0x1]; 6127 u8 functional_lb[0x1]; 6128 u8 outer_ip_frag[0x1]; 6129 u8 outer_qp_type[0x2]; 6130 u8 outer_encap_type[0x2]; 6131 u8 port_number[0x2]; 6132 u8 outer_l3_type[0x2]; 6133 u8 outer_l4_type[0x2]; 6134 u8 outer_first_vlan_type[0x2]; 6135 u8 outer_first_vlan_prio[0x3]; 6136 u8 outer_first_vlan_cfi[0x1]; 6137 u8 outer_first_vlan_vid[0xc]; 6138 6139 u8 outer_l4_type_ext[0x4]; 6140 u8 reserved_at_1a4[0x2]; 6141 u8 outer_ipsec_layer[0x2]; 6142 u8 outer_l2_type[0x2]; 6143 u8 force_lb[0x1]; 6144 u8 outer_l2_ok[0x1]; 6145 u8 outer_l3_ok[0x1]; 6146 u8 outer_l4_ok[0x1]; 6147 u8 outer_second_vlan_type[0x2]; 6148 u8 outer_second_vlan_prio[0x3]; 6149 u8 outer_second_vlan_cfi[0x1]; 6150 u8 outer_second_vlan_vid[0xc]; 6151 6152 u8 outer_smac_47_16[0x20]; 6153 6154 u8 outer_smac_15_0[0x10]; 6155 u8 inner_ipv4_checksum_ok[0x1]; 6156 u8 inner_l4_checksum_ok[0x1]; 6157 u8 outer_ipv4_checksum_ok[0x1]; 6158 u8 outer_l4_checksum_ok[0x1]; 6159 u8 inner_l3_ok[0x1]; 6160 u8 inner_l4_ok[0x1]; 6161 u8 outer_l3_ok_duplicate[0x1]; 6162 u8 outer_l4_ok_duplicate[0x1]; 6163 u8 outer_tcp_cwr[0x1]; 6164 u8 outer_tcp_ece[0x1]; 6165 u8 outer_tcp_urg[0x1]; 6166 u8 outer_tcp_ack[0x1]; 6167 u8 outer_tcp_psh[0x1]; 6168 u8 outer_tcp_rst[0x1]; 6169 u8 outer_tcp_syn[0x1]; 6170 u8 outer_tcp_fin[0x1]; 6171 }; 6172 6173 struct mlx5_ifc_match_definer_format_22_bits { 6174 u8 reserved_at_0[0x100]; 6175 6176 u8 outer_ip_src_addr[0x20]; 6177 6178 u8 outer_ip_dest_addr[0x20]; 6179 6180 u8 outer_l4_sport[0x10]; 6181 u8 outer_l4_dport[0x10]; 6182 6183 u8 reserved_at_160[0x1]; 6184 u8 sx_sniffer[0x1]; 6185 u8 functional_lb[0x1]; 6186 u8 outer_ip_frag[0x1]; 6187 u8 outer_qp_type[0x2]; 6188 u8 outer_encap_type[0x2]; 6189 u8 port_number[0x2]; 6190 u8 outer_l3_type[0x2]; 6191 u8 outer_l4_type[0x2]; 6192 u8 outer_first_vlan_type[0x2]; 6193 u8 outer_first_vlan_prio[0x3]; 6194 u8 outer_first_vlan_cfi[0x1]; 6195 u8 outer_first_vlan_vid[0xc]; 6196 6197 u8 metadata_reg_c_0[0x20]; 6198 6199 u8 outer_dmac_47_16[0x20]; 6200 6201 u8 outer_smac_47_16[0x20]; 6202 6203 u8 outer_smac_15_0[0x10]; 6204 u8 outer_dmac_15_0[0x10]; 6205 }; 6206 6207 struct mlx5_ifc_match_definer_format_23_bits { 6208 u8 reserved_at_0[0x100]; 6209 6210 u8 inner_ip_src_addr[0x20]; 6211 6212 u8 inner_ip_dest_addr[0x20]; 6213 6214 u8 inner_l4_sport[0x10]; 6215 u8 inner_l4_dport[0x10]; 6216 6217 u8 reserved_at_160[0x1]; 6218 u8 sx_sniffer[0x1]; 6219 u8 functional_lb[0x1]; 6220 u8 inner_ip_frag[0x1]; 6221 u8 inner_qp_type[0x2]; 6222 u8 inner_encap_type[0x2]; 6223 u8 port_number[0x2]; 6224 u8 inner_l3_type[0x2]; 6225 u8 inner_l4_type[0x2]; 6226 u8 inner_first_vlan_type[0x2]; 6227 u8 inner_first_vlan_prio[0x3]; 6228 u8 inner_first_vlan_cfi[0x1]; 6229 u8 inner_first_vlan_vid[0xc]; 6230 6231 u8 tunnel_header_0[0x20]; 6232 6233 u8 inner_dmac_47_16[0x20]; 6234 6235 u8 inner_smac_47_16[0x20]; 6236 6237 u8 inner_smac_15_0[0x10]; 6238 u8 inner_dmac_15_0[0x10]; 6239 }; 6240 6241 struct mlx5_ifc_match_definer_format_29_bits { 6242 u8 reserved_at_0[0xc0]; 6243 6244 u8 outer_ip_dest_addr[0x80]; 6245 6246 u8 outer_ip_src_addr[0x80]; 6247 6248 u8 outer_l4_sport[0x10]; 6249 u8 outer_l4_dport[0x10]; 6250 6251 u8 reserved_at_1e0[0x20]; 6252 }; 6253 6254 struct mlx5_ifc_match_definer_format_30_bits { 6255 u8 reserved_at_0[0xa0]; 6256 6257 u8 outer_ip_dest_addr[0x80]; 6258 6259 u8 outer_ip_src_addr[0x80]; 6260 6261 u8 outer_dmac_47_16[0x20]; 6262 6263 u8 outer_smac_47_16[0x20]; 6264 6265 u8 outer_smac_15_0[0x10]; 6266 u8 outer_dmac_15_0[0x10]; 6267 }; 6268 6269 struct mlx5_ifc_match_definer_format_31_bits { 6270 u8 reserved_at_0[0xc0]; 6271 6272 u8 inner_ip_dest_addr[0x80]; 6273 6274 u8 inner_ip_src_addr[0x80]; 6275 6276 u8 inner_l4_sport[0x10]; 6277 u8 inner_l4_dport[0x10]; 6278 6279 u8 reserved_at_1e0[0x20]; 6280 }; 6281 6282 struct mlx5_ifc_match_definer_format_32_bits { 6283 u8 reserved_at_0[0xa0]; 6284 6285 u8 inner_ip_dest_addr[0x80]; 6286 6287 u8 inner_ip_src_addr[0x80]; 6288 6289 u8 inner_dmac_47_16[0x20]; 6290 6291 u8 inner_smac_47_16[0x20]; 6292 6293 u8 inner_smac_15_0[0x10]; 6294 u8 inner_dmac_15_0[0x10]; 6295 }; 6296 6297 enum { 6298 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6299 }; 6300 6301 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6302 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6303 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6304 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6305 6306 struct mlx5_ifc_match_definer_match_mask_bits { 6307 u8 reserved_at_1c0[5][0x20]; 6308 u8 match_dw_8[0x20]; 6309 u8 match_dw_7[0x20]; 6310 u8 match_dw_6[0x20]; 6311 u8 match_dw_5[0x20]; 6312 u8 match_dw_4[0x20]; 6313 u8 match_dw_3[0x20]; 6314 u8 match_dw_2[0x20]; 6315 u8 match_dw_1[0x20]; 6316 u8 match_dw_0[0x20]; 6317 6318 u8 match_byte_7[0x8]; 6319 u8 match_byte_6[0x8]; 6320 u8 match_byte_5[0x8]; 6321 u8 match_byte_4[0x8]; 6322 6323 u8 match_byte_3[0x8]; 6324 u8 match_byte_2[0x8]; 6325 u8 match_byte_1[0x8]; 6326 u8 match_byte_0[0x8]; 6327 }; 6328 6329 struct mlx5_ifc_match_definer_bits { 6330 u8 modify_field_select[0x40]; 6331 6332 u8 reserved_at_40[0x40]; 6333 6334 u8 reserved_at_80[0x10]; 6335 u8 format_id[0x10]; 6336 6337 u8 reserved_at_a0[0x60]; 6338 6339 u8 format_select_dw3[0x8]; 6340 u8 format_select_dw2[0x8]; 6341 u8 format_select_dw1[0x8]; 6342 u8 format_select_dw0[0x8]; 6343 6344 u8 format_select_dw7[0x8]; 6345 u8 format_select_dw6[0x8]; 6346 u8 format_select_dw5[0x8]; 6347 u8 format_select_dw4[0x8]; 6348 6349 u8 reserved_at_100[0x18]; 6350 u8 format_select_dw8[0x8]; 6351 6352 u8 reserved_at_120[0x20]; 6353 6354 u8 format_select_byte3[0x8]; 6355 u8 format_select_byte2[0x8]; 6356 u8 format_select_byte1[0x8]; 6357 u8 format_select_byte0[0x8]; 6358 6359 u8 format_select_byte7[0x8]; 6360 u8 format_select_byte6[0x8]; 6361 u8 format_select_byte5[0x8]; 6362 u8 format_select_byte4[0x8]; 6363 6364 u8 reserved_at_180[0x40]; 6365 6366 union { 6367 struct { 6368 u8 match_mask[16][0x20]; 6369 }; 6370 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6371 }; 6372 }; 6373 6374 struct mlx5_ifc_general_obj_create_param_bits { 6375 u8 alias_object[0x1]; 6376 u8 reserved_at_1[0x2]; 6377 u8 log_obj_range[0x5]; 6378 u8 reserved_at_8[0x18]; 6379 }; 6380 6381 struct mlx5_ifc_general_obj_query_param_bits { 6382 u8 alias_object[0x1]; 6383 u8 obj_offset[0x1f]; 6384 }; 6385 6386 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6387 u8 opcode[0x10]; 6388 u8 uid[0x10]; 6389 6390 u8 vhca_tunnel_id[0x10]; 6391 u8 obj_type[0x10]; 6392 6393 u8 obj_id[0x20]; 6394 6395 union { 6396 struct mlx5_ifc_general_obj_create_param_bits create; 6397 struct mlx5_ifc_general_obj_query_param_bits query; 6398 } op_param; 6399 }; 6400 6401 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6402 u8 status[0x8]; 6403 u8 reserved_at_8[0x18]; 6404 6405 u8 syndrome[0x20]; 6406 6407 u8 obj_id[0x20]; 6408 6409 u8 reserved_at_60[0x20]; 6410 }; 6411 6412 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6413 u8 opcode[0x10]; 6414 u8 uid[0x10]; 6415 u8 reserved_at_20[0x10]; 6416 u8 op_mod[0x10]; 6417 u8 reserved_at_40[0x50]; 6418 u8 object_type_to_be_accessed[0x10]; 6419 u8 object_id_to_be_accessed[0x20]; 6420 u8 reserved_at_c0[0x40]; 6421 union { 6422 u8 access_key_raw[0x100]; 6423 u8 access_key[8][0x20]; 6424 }; 6425 }; 6426 6427 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6428 u8 status[0x8]; 6429 u8 reserved_at_8[0x18]; 6430 u8 syndrome[0x20]; 6431 u8 reserved_at_40[0x40]; 6432 }; 6433 6434 struct mlx5_ifc_modify_header_arg_bits { 6435 u8 reserved_at_0[0x80]; 6436 6437 u8 reserved_at_80[0x8]; 6438 u8 access_pd[0x18]; 6439 }; 6440 6441 struct mlx5_ifc_create_modify_header_arg_in_bits { 6442 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6443 struct mlx5_ifc_modify_header_arg_bits arg; 6444 }; 6445 6446 struct mlx5_ifc_create_match_definer_in_bits { 6447 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6448 6449 struct mlx5_ifc_match_definer_bits obj_context; 6450 }; 6451 6452 struct mlx5_ifc_create_match_definer_out_bits { 6453 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6454 }; 6455 6456 struct mlx5_ifc_alias_context_bits { 6457 u8 vhca_id_to_be_accessed[0x10]; 6458 u8 reserved_at_10[0xd]; 6459 u8 status[0x3]; 6460 u8 object_id_to_be_accessed[0x20]; 6461 u8 reserved_at_40[0x40]; 6462 union { 6463 u8 access_key_raw[0x100]; 6464 u8 access_key[8][0x20]; 6465 }; 6466 u8 metadata[0x80]; 6467 }; 6468 6469 struct mlx5_ifc_create_alias_obj_in_bits { 6470 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6471 struct mlx5_ifc_alias_context_bits alias_ctx; 6472 }; 6473 6474 enum { 6475 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6476 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6477 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6478 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6479 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6480 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6481 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6482 }; 6483 6484 struct mlx5_ifc_query_flow_group_out_bits { 6485 u8 status[0x8]; 6486 u8 reserved_at_8[0x18]; 6487 6488 u8 syndrome[0x20]; 6489 6490 u8 reserved_at_40[0xa0]; 6491 6492 u8 start_flow_index[0x20]; 6493 6494 u8 reserved_at_100[0x20]; 6495 6496 u8 end_flow_index[0x20]; 6497 6498 u8 reserved_at_140[0xa0]; 6499 6500 u8 reserved_at_1e0[0x18]; 6501 u8 match_criteria_enable[0x8]; 6502 6503 struct mlx5_ifc_fte_match_param_bits match_criteria; 6504 6505 u8 reserved_at_1200[0xe00]; 6506 }; 6507 6508 struct mlx5_ifc_query_flow_group_in_bits { 6509 u8 opcode[0x10]; 6510 u8 reserved_at_10[0x10]; 6511 6512 u8 reserved_at_20[0x10]; 6513 u8 op_mod[0x10]; 6514 6515 u8 reserved_at_40[0x40]; 6516 6517 u8 table_type[0x8]; 6518 u8 reserved_at_88[0x18]; 6519 6520 u8 reserved_at_a0[0x8]; 6521 u8 table_id[0x18]; 6522 6523 u8 group_id[0x20]; 6524 6525 u8 reserved_at_e0[0x120]; 6526 }; 6527 6528 struct mlx5_ifc_query_flow_counter_out_bits { 6529 u8 status[0x8]; 6530 u8 reserved_at_8[0x18]; 6531 6532 u8 syndrome[0x20]; 6533 6534 u8 reserved_at_40[0x40]; 6535 6536 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6537 }; 6538 6539 struct mlx5_ifc_query_flow_counter_in_bits { 6540 u8 opcode[0x10]; 6541 u8 reserved_at_10[0x10]; 6542 6543 u8 reserved_at_20[0x10]; 6544 u8 op_mod[0x10]; 6545 6546 u8 reserved_at_40[0x80]; 6547 6548 u8 clear[0x1]; 6549 u8 reserved_at_c1[0xf]; 6550 u8 num_of_counters[0x10]; 6551 6552 u8 flow_counter_id[0x20]; 6553 }; 6554 6555 struct mlx5_ifc_query_esw_vport_context_out_bits { 6556 u8 status[0x8]; 6557 u8 reserved_at_8[0x18]; 6558 6559 u8 syndrome[0x20]; 6560 6561 u8 reserved_at_40[0x40]; 6562 6563 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6564 }; 6565 6566 struct mlx5_ifc_query_esw_vport_context_in_bits { 6567 u8 opcode[0x10]; 6568 u8 reserved_at_10[0x10]; 6569 6570 u8 reserved_at_20[0x10]; 6571 u8 op_mod[0x10]; 6572 6573 u8 other_vport[0x1]; 6574 u8 reserved_at_41[0xf]; 6575 u8 vport_number[0x10]; 6576 6577 u8 reserved_at_60[0x20]; 6578 }; 6579 6580 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6581 u8 status[0x8]; 6582 u8 reserved_at_8[0x18]; 6583 6584 u8 syndrome[0x20]; 6585 6586 u8 reserved_at_40[0x40]; 6587 }; 6588 6589 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6590 u8 reserved_at_0[0x1b]; 6591 u8 fdb_to_vport_reg_c_id[0x1]; 6592 u8 vport_cvlan_insert[0x1]; 6593 u8 vport_svlan_insert[0x1]; 6594 u8 vport_cvlan_strip[0x1]; 6595 u8 vport_svlan_strip[0x1]; 6596 }; 6597 6598 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6599 u8 opcode[0x10]; 6600 u8 reserved_at_10[0x10]; 6601 6602 u8 reserved_at_20[0x10]; 6603 u8 op_mod[0x10]; 6604 6605 u8 other_vport[0x1]; 6606 u8 reserved_at_41[0xf]; 6607 u8 vport_number[0x10]; 6608 6609 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6610 6611 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6612 }; 6613 6614 struct mlx5_ifc_query_eq_out_bits { 6615 u8 status[0x8]; 6616 u8 reserved_at_8[0x18]; 6617 6618 u8 syndrome[0x20]; 6619 6620 u8 reserved_at_40[0x40]; 6621 6622 struct mlx5_ifc_eqc_bits eq_context_entry; 6623 6624 u8 reserved_at_280[0x40]; 6625 6626 u8 event_bitmask[0x40]; 6627 6628 u8 reserved_at_300[0x580]; 6629 6630 u8 pas[][0x40]; 6631 }; 6632 6633 struct mlx5_ifc_query_eq_in_bits { 6634 u8 opcode[0x10]; 6635 u8 reserved_at_10[0x10]; 6636 6637 u8 reserved_at_20[0x10]; 6638 u8 op_mod[0x10]; 6639 6640 u8 reserved_at_40[0x18]; 6641 u8 eq_number[0x8]; 6642 6643 u8 reserved_at_60[0x20]; 6644 }; 6645 6646 struct mlx5_ifc_packet_reformat_context_in_bits { 6647 u8 reformat_type[0x8]; 6648 u8 reserved_at_8[0x4]; 6649 u8 reformat_param_0[0x4]; 6650 u8 reserved_at_10[0x6]; 6651 u8 reformat_data_size[0xa]; 6652 6653 u8 reformat_param_1[0x8]; 6654 u8 reserved_at_28[0x8]; 6655 u8 reformat_data[2][0x8]; 6656 6657 u8 more_reformat_data[][0x8]; 6658 }; 6659 6660 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6661 u8 status[0x8]; 6662 u8 reserved_at_8[0x18]; 6663 6664 u8 syndrome[0x20]; 6665 6666 u8 reserved_at_40[0xa0]; 6667 6668 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6669 }; 6670 6671 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6672 u8 opcode[0x10]; 6673 u8 reserved_at_10[0x10]; 6674 6675 u8 reserved_at_20[0x10]; 6676 u8 op_mod[0x10]; 6677 6678 u8 packet_reformat_id[0x20]; 6679 6680 u8 reserved_at_60[0xa0]; 6681 }; 6682 6683 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6684 u8 status[0x8]; 6685 u8 reserved_at_8[0x18]; 6686 6687 u8 syndrome[0x20]; 6688 6689 u8 packet_reformat_id[0x20]; 6690 6691 u8 reserved_at_60[0x20]; 6692 }; 6693 6694 enum { 6695 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6696 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6697 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6698 }; 6699 6700 enum mlx5_reformat_ctx_type { 6701 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6702 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6703 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6704 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6705 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6706 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6707 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6708 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 6709 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6710 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6711 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 6712 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6713 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 6714 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6715 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6716 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6717 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6718 }; 6719 6720 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6721 u8 opcode[0x10]; 6722 u8 reserved_at_10[0x10]; 6723 6724 u8 reserved_at_20[0x10]; 6725 u8 op_mod[0x10]; 6726 6727 u8 reserved_at_40[0xa0]; 6728 6729 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6730 }; 6731 6732 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6733 u8 status[0x8]; 6734 u8 reserved_at_8[0x18]; 6735 6736 u8 syndrome[0x20]; 6737 6738 u8 reserved_at_40[0x40]; 6739 }; 6740 6741 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6742 u8 opcode[0x10]; 6743 u8 reserved_at_10[0x10]; 6744 6745 u8 reserved_20[0x10]; 6746 u8 op_mod[0x10]; 6747 6748 u8 packet_reformat_id[0x20]; 6749 6750 u8 reserved_60[0x20]; 6751 }; 6752 6753 struct mlx5_ifc_set_action_in_bits { 6754 u8 action_type[0x4]; 6755 u8 field[0xc]; 6756 u8 reserved_at_10[0x3]; 6757 u8 offset[0x5]; 6758 u8 reserved_at_18[0x3]; 6759 u8 length[0x5]; 6760 6761 u8 data[0x20]; 6762 }; 6763 6764 struct mlx5_ifc_add_action_in_bits { 6765 u8 action_type[0x4]; 6766 u8 field[0xc]; 6767 u8 reserved_at_10[0x10]; 6768 6769 u8 data[0x20]; 6770 }; 6771 6772 struct mlx5_ifc_copy_action_in_bits { 6773 u8 action_type[0x4]; 6774 u8 src_field[0xc]; 6775 u8 reserved_at_10[0x3]; 6776 u8 src_offset[0x5]; 6777 u8 reserved_at_18[0x3]; 6778 u8 length[0x5]; 6779 6780 u8 reserved_at_20[0x4]; 6781 u8 dst_field[0xc]; 6782 u8 reserved_at_30[0x3]; 6783 u8 dst_offset[0x5]; 6784 u8 reserved_at_38[0x8]; 6785 }; 6786 6787 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6788 struct mlx5_ifc_set_action_in_bits set_action_in; 6789 struct mlx5_ifc_add_action_in_bits add_action_in; 6790 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6791 u8 reserved_at_0[0x40]; 6792 }; 6793 6794 enum { 6795 MLX5_ACTION_TYPE_SET = 0x1, 6796 MLX5_ACTION_TYPE_ADD = 0x2, 6797 MLX5_ACTION_TYPE_COPY = 0x3, 6798 }; 6799 6800 enum { 6801 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6802 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6803 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6804 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6805 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6806 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6807 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6808 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6809 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6810 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6811 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6812 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6813 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6814 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6815 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6816 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6817 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6818 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6819 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6820 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6821 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6822 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6823 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6824 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6825 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6826 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6827 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6828 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6829 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6830 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6831 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6832 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6833 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6834 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6835 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6836 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6837 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6838 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6839 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6840 }; 6841 6842 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6843 u8 status[0x8]; 6844 u8 reserved_at_8[0x18]; 6845 6846 u8 syndrome[0x20]; 6847 6848 u8 modify_header_id[0x20]; 6849 6850 u8 reserved_at_60[0x20]; 6851 }; 6852 6853 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6854 u8 opcode[0x10]; 6855 u8 reserved_at_10[0x10]; 6856 6857 u8 reserved_at_20[0x10]; 6858 u8 op_mod[0x10]; 6859 6860 u8 reserved_at_40[0x20]; 6861 6862 u8 table_type[0x8]; 6863 u8 reserved_at_68[0x10]; 6864 u8 num_of_actions[0x8]; 6865 6866 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6867 }; 6868 6869 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6870 u8 status[0x8]; 6871 u8 reserved_at_8[0x18]; 6872 6873 u8 syndrome[0x20]; 6874 6875 u8 reserved_at_40[0x40]; 6876 }; 6877 6878 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6879 u8 opcode[0x10]; 6880 u8 reserved_at_10[0x10]; 6881 6882 u8 reserved_at_20[0x10]; 6883 u8 op_mod[0x10]; 6884 6885 u8 modify_header_id[0x20]; 6886 6887 u8 reserved_at_60[0x20]; 6888 }; 6889 6890 struct mlx5_ifc_query_modify_header_context_in_bits { 6891 u8 opcode[0x10]; 6892 u8 uid[0x10]; 6893 6894 u8 reserved_at_20[0x10]; 6895 u8 op_mod[0x10]; 6896 6897 u8 modify_header_id[0x20]; 6898 6899 u8 reserved_at_60[0xa0]; 6900 }; 6901 6902 struct mlx5_ifc_query_dct_out_bits { 6903 u8 status[0x8]; 6904 u8 reserved_at_8[0x18]; 6905 6906 u8 syndrome[0x20]; 6907 6908 u8 reserved_at_40[0x40]; 6909 6910 struct mlx5_ifc_dctc_bits dct_context_entry; 6911 6912 u8 reserved_at_280[0x180]; 6913 }; 6914 6915 struct mlx5_ifc_query_dct_in_bits { 6916 u8 opcode[0x10]; 6917 u8 reserved_at_10[0x10]; 6918 6919 u8 reserved_at_20[0x10]; 6920 u8 op_mod[0x10]; 6921 6922 u8 reserved_at_40[0x8]; 6923 u8 dctn[0x18]; 6924 6925 u8 reserved_at_60[0x20]; 6926 }; 6927 6928 struct mlx5_ifc_query_cq_out_bits { 6929 u8 status[0x8]; 6930 u8 reserved_at_8[0x18]; 6931 6932 u8 syndrome[0x20]; 6933 6934 u8 reserved_at_40[0x40]; 6935 6936 struct mlx5_ifc_cqc_bits cq_context; 6937 6938 u8 reserved_at_280[0x600]; 6939 6940 u8 pas[][0x40]; 6941 }; 6942 6943 struct mlx5_ifc_query_cq_in_bits { 6944 u8 opcode[0x10]; 6945 u8 reserved_at_10[0x10]; 6946 6947 u8 reserved_at_20[0x10]; 6948 u8 op_mod[0x10]; 6949 6950 u8 reserved_at_40[0x8]; 6951 u8 cqn[0x18]; 6952 6953 u8 reserved_at_60[0x20]; 6954 }; 6955 6956 struct mlx5_ifc_query_cong_status_out_bits { 6957 u8 status[0x8]; 6958 u8 reserved_at_8[0x18]; 6959 6960 u8 syndrome[0x20]; 6961 6962 u8 reserved_at_40[0x20]; 6963 6964 u8 enable[0x1]; 6965 u8 tag_enable[0x1]; 6966 u8 reserved_at_62[0x1e]; 6967 }; 6968 6969 struct mlx5_ifc_query_cong_status_in_bits { 6970 u8 opcode[0x10]; 6971 u8 reserved_at_10[0x10]; 6972 6973 u8 reserved_at_20[0x10]; 6974 u8 op_mod[0x10]; 6975 6976 u8 reserved_at_40[0x18]; 6977 u8 priority[0x4]; 6978 u8 cong_protocol[0x4]; 6979 6980 u8 reserved_at_60[0x20]; 6981 }; 6982 6983 struct mlx5_ifc_query_cong_statistics_out_bits { 6984 u8 status[0x8]; 6985 u8 reserved_at_8[0x18]; 6986 6987 u8 syndrome[0x20]; 6988 6989 u8 reserved_at_40[0x40]; 6990 6991 u8 rp_cur_flows[0x20]; 6992 6993 u8 sum_flows[0x20]; 6994 6995 u8 rp_cnp_ignored_high[0x20]; 6996 6997 u8 rp_cnp_ignored_low[0x20]; 6998 6999 u8 rp_cnp_handled_high[0x20]; 7000 7001 u8 rp_cnp_handled_low[0x20]; 7002 7003 u8 reserved_at_140[0x100]; 7004 7005 u8 time_stamp_high[0x20]; 7006 7007 u8 time_stamp_low[0x20]; 7008 7009 u8 accumulators_period[0x20]; 7010 7011 u8 np_ecn_marked_roce_packets_high[0x20]; 7012 7013 u8 np_ecn_marked_roce_packets_low[0x20]; 7014 7015 u8 np_cnp_sent_high[0x20]; 7016 7017 u8 np_cnp_sent_low[0x20]; 7018 7019 u8 reserved_at_320[0x560]; 7020 }; 7021 7022 struct mlx5_ifc_query_cong_statistics_in_bits { 7023 u8 opcode[0x10]; 7024 u8 reserved_at_10[0x10]; 7025 7026 u8 reserved_at_20[0x10]; 7027 u8 op_mod[0x10]; 7028 7029 u8 clear[0x1]; 7030 u8 reserved_at_41[0x1f]; 7031 7032 u8 reserved_at_60[0x20]; 7033 }; 7034 7035 struct mlx5_ifc_query_cong_params_out_bits { 7036 u8 status[0x8]; 7037 u8 reserved_at_8[0x18]; 7038 7039 u8 syndrome[0x20]; 7040 7041 u8 reserved_at_40[0x40]; 7042 7043 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7044 }; 7045 7046 struct mlx5_ifc_query_cong_params_in_bits { 7047 u8 opcode[0x10]; 7048 u8 reserved_at_10[0x10]; 7049 7050 u8 reserved_at_20[0x10]; 7051 u8 op_mod[0x10]; 7052 7053 u8 reserved_at_40[0x1c]; 7054 u8 cong_protocol[0x4]; 7055 7056 u8 reserved_at_60[0x20]; 7057 }; 7058 7059 struct mlx5_ifc_query_adapter_out_bits { 7060 u8 status[0x8]; 7061 u8 reserved_at_8[0x18]; 7062 7063 u8 syndrome[0x20]; 7064 7065 u8 reserved_at_40[0x40]; 7066 7067 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7068 }; 7069 7070 struct mlx5_ifc_query_adapter_in_bits { 7071 u8 opcode[0x10]; 7072 u8 reserved_at_10[0x10]; 7073 7074 u8 reserved_at_20[0x10]; 7075 u8 op_mod[0x10]; 7076 7077 u8 reserved_at_40[0x40]; 7078 }; 7079 7080 struct mlx5_ifc_qp_2rst_out_bits { 7081 u8 status[0x8]; 7082 u8 reserved_at_8[0x18]; 7083 7084 u8 syndrome[0x20]; 7085 7086 u8 reserved_at_40[0x40]; 7087 }; 7088 7089 struct mlx5_ifc_qp_2rst_in_bits { 7090 u8 opcode[0x10]; 7091 u8 uid[0x10]; 7092 7093 u8 reserved_at_20[0x10]; 7094 u8 op_mod[0x10]; 7095 7096 u8 reserved_at_40[0x8]; 7097 u8 qpn[0x18]; 7098 7099 u8 reserved_at_60[0x20]; 7100 }; 7101 7102 struct mlx5_ifc_qp_2err_out_bits { 7103 u8 status[0x8]; 7104 u8 reserved_at_8[0x18]; 7105 7106 u8 syndrome[0x20]; 7107 7108 u8 reserved_at_40[0x40]; 7109 }; 7110 7111 struct mlx5_ifc_qp_2err_in_bits { 7112 u8 opcode[0x10]; 7113 u8 uid[0x10]; 7114 7115 u8 reserved_at_20[0x10]; 7116 u8 op_mod[0x10]; 7117 7118 u8 reserved_at_40[0x8]; 7119 u8 qpn[0x18]; 7120 7121 u8 reserved_at_60[0x20]; 7122 }; 7123 7124 struct mlx5_ifc_page_fault_resume_out_bits { 7125 u8 status[0x8]; 7126 u8 reserved_at_8[0x18]; 7127 7128 u8 syndrome[0x20]; 7129 7130 u8 reserved_at_40[0x40]; 7131 }; 7132 7133 struct mlx5_ifc_page_fault_resume_in_bits { 7134 u8 opcode[0x10]; 7135 u8 reserved_at_10[0x10]; 7136 7137 u8 reserved_at_20[0x10]; 7138 u8 op_mod[0x10]; 7139 7140 u8 error[0x1]; 7141 u8 reserved_at_41[0x4]; 7142 u8 page_fault_type[0x3]; 7143 u8 wq_number[0x18]; 7144 7145 u8 reserved_at_60[0x8]; 7146 u8 token[0x18]; 7147 }; 7148 7149 struct mlx5_ifc_nop_out_bits { 7150 u8 status[0x8]; 7151 u8 reserved_at_8[0x18]; 7152 7153 u8 syndrome[0x20]; 7154 7155 u8 reserved_at_40[0x40]; 7156 }; 7157 7158 struct mlx5_ifc_nop_in_bits { 7159 u8 opcode[0x10]; 7160 u8 reserved_at_10[0x10]; 7161 7162 u8 reserved_at_20[0x10]; 7163 u8 op_mod[0x10]; 7164 7165 u8 reserved_at_40[0x40]; 7166 }; 7167 7168 struct mlx5_ifc_modify_vport_state_out_bits { 7169 u8 status[0x8]; 7170 u8 reserved_at_8[0x18]; 7171 7172 u8 syndrome[0x20]; 7173 7174 u8 reserved_at_40[0x40]; 7175 }; 7176 7177 struct mlx5_ifc_modify_vport_state_in_bits { 7178 u8 opcode[0x10]; 7179 u8 reserved_at_10[0x10]; 7180 7181 u8 reserved_at_20[0x10]; 7182 u8 op_mod[0x10]; 7183 7184 u8 other_vport[0x1]; 7185 u8 reserved_at_41[0xf]; 7186 u8 vport_number[0x10]; 7187 7188 u8 reserved_at_60[0x18]; 7189 u8 admin_state[0x4]; 7190 u8 reserved_at_7c[0x4]; 7191 }; 7192 7193 struct mlx5_ifc_modify_tis_out_bits { 7194 u8 status[0x8]; 7195 u8 reserved_at_8[0x18]; 7196 7197 u8 syndrome[0x20]; 7198 7199 u8 reserved_at_40[0x40]; 7200 }; 7201 7202 struct mlx5_ifc_modify_tis_bitmask_bits { 7203 u8 reserved_at_0[0x20]; 7204 7205 u8 reserved_at_20[0x1d]; 7206 u8 lag_tx_port_affinity[0x1]; 7207 u8 strict_lag_tx_port_affinity[0x1]; 7208 u8 prio[0x1]; 7209 }; 7210 7211 struct mlx5_ifc_modify_tis_in_bits { 7212 u8 opcode[0x10]; 7213 u8 uid[0x10]; 7214 7215 u8 reserved_at_20[0x10]; 7216 u8 op_mod[0x10]; 7217 7218 u8 reserved_at_40[0x8]; 7219 u8 tisn[0x18]; 7220 7221 u8 reserved_at_60[0x20]; 7222 7223 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7224 7225 u8 reserved_at_c0[0x40]; 7226 7227 struct mlx5_ifc_tisc_bits ctx; 7228 }; 7229 7230 struct mlx5_ifc_modify_tir_bitmask_bits { 7231 u8 reserved_at_0[0x20]; 7232 7233 u8 reserved_at_20[0x1b]; 7234 u8 self_lb_en[0x1]; 7235 u8 reserved_at_3c[0x1]; 7236 u8 hash[0x1]; 7237 u8 reserved_at_3e[0x1]; 7238 u8 packet_merge[0x1]; 7239 }; 7240 7241 struct mlx5_ifc_modify_tir_out_bits { 7242 u8 status[0x8]; 7243 u8 reserved_at_8[0x18]; 7244 7245 u8 syndrome[0x20]; 7246 7247 u8 reserved_at_40[0x40]; 7248 }; 7249 7250 struct mlx5_ifc_modify_tir_in_bits { 7251 u8 opcode[0x10]; 7252 u8 uid[0x10]; 7253 7254 u8 reserved_at_20[0x10]; 7255 u8 op_mod[0x10]; 7256 7257 u8 reserved_at_40[0x8]; 7258 u8 tirn[0x18]; 7259 7260 u8 reserved_at_60[0x20]; 7261 7262 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7263 7264 u8 reserved_at_c0[0x40]; 7265 7266 struct mlx5_ifc_tirc_bits ctx; 7267 }; 7268 7269 struct mlx5_ifc_modify_sq_out_bits { 7270 u8 status[0x8]; 7271 u8 reserved_at_8[0x18]; 7272 7273 u8 syndrome[0x20]; 7274 7275 u8 reserved_at_40[0x40]; 7276 }; 7277 7278 struct mlx5_ifc_modify_sq_in_bits { 7279 u8 opcode[0x10]; 7280 u8 uid[0x10]; 7281 7282 u8 reserved_at_20[0x10]; 7283 u8 op_mod[0x10]; 7284 7285 u8 sq_state[0x4]; 7286 u8 reserved_at_44[0x4]; 7287 u8 sqn[0x18]; 7288 7289 u8 reserved_at_60[0x20]; 7290 7291 u8 modify_bitmask[0x40]; 7292 7293 u8 reserved_at_c0[0x40]; 7294 7295 struct mlx5_ifc_sqc_bits ctx; 7296 }; 7297 7298 struct mlx5_ifc_modify_scheduling_element_out_bits { 7299 u8 status[0x8]; 7300 u8 reserved_at_8[0x18]; 7301 7302 u8 syndrome[0x20]; 7303 7304 u8 reserved_at_40[0x1c0]; 7305 }; 7306 7307 enum { 7308 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7309 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7310 }; 7311 7312 struct mlx5_ifc_modify_scheduling_element_in_bits { 7313 u8 opcode[0x10]; 7314 u8 reserved_at_10[0x10]; 7315 7316 u8 reserved_at_20[0x10]; 7317 u8 op_mod[0x10]; 7318 7319 u8 scheduling_hierarchy[0x8]; 7320 u8 reserved_at_48[0x18]; 7321 7322 u8 scheduling_element_id[0x20]; 7323 7324 u8 reserved_at_80[0x20]; 7325 7326 u8 modify_bitmask[0x20]; 7327 7328 u8 reserved_at_c0[0x40]; 7329 7330 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7331 7332 u8 reserved_at_300[0x100]; 7333 }; 7334 7335 struct mlx5_ifc_modify_rqt_out_bits { 7336 u8 status[0x8]; 7337 u8 reserved_at_8[0x18]; 7338 7339 u8 syndrome[0x20]; 7340 7341 u8 reserved_at_40[0x40]; 7342 }; 7343 7344 struct mlx5_ifc_rqt_bitmask_bits { 7345 u8 reserved_at_0[0x20]; 7346 7347 u8 reserved_at_20[0x1f]; 7348 u8 rqn_list[0x1]; 7349 }; 7350 7351 struct mlx5_ifc_modify_rqt_in_bits { 7352 u8 opcode[0x10]; 7353 u8 uid[0x10]; 7354 7355 u8 reserved_at_20[0x10]; 7356 u8 op_mod[0x10]; 7357 7358 u8 reserved_at_40[0x8]; 7359 u8 rqtn[0x18]; 7360 7361 u8 reserved_at_60[0x20]; 7362 7363 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7364 7365 u8 reserved_at_c0[0x40]; 7366 7367 struct mlx5_ifc_rqtc_bits ctx; 7368 }; 7369 7370 struct mlx5_ifc_modify_rq_out_bits { 7371 u8 status[0x8]; 7372 u8 reserved_at_8[0x18]; 7373 7374 u8 syndrome[0x20]; 7375 7376 u8 reserved_at_40[0x40]; 7377 }; 7378 7379 enum { 7380 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7381 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7382 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7383 }; 7384 7385 struct mlx5_ifc_modify_rq_in_bits { 7386 u8 opcode[0x10]; 7387 u8 uid[0x10]; 7388 7389 u8 reserved_at_20[0x10]; 7390 u8 op_mod[0x10]; 7391 7392 u8 rq_state[0x4]; 7393 u8 reserved_at_44[0x4]; 7394 u8 rqn[0x18]; 7395 7396 u8 reserved_at_60[0x20]; 7397 7398 u8 modify_bitmask[0x40]; 7399 7400 u8 reserved_at_c0[0x40]; 7401 7402 struct mlx5_ifc_rqc_bits ctx; 7403 }; 7404 7405 struct mlx5_ifc_modify_rmp_out_bits { 7406 u8 status[0x8]; 7407 u8 reserved_at_8[0x18]; 7408 7409 u8 syndrome[0x20]; 7410 7411 u8 reserved_at_40[0x40]; 7412 }; 7413 7414 struct mlx5_ifc_rmp_bitmask_bits { 7415 u8 reserved_at_0[0x20]; 7416 7417 u8 reserved_at_20[0x1f]; 7418 u8 lwm[0x1]; 7419 }; 7420 7421 struct mlx5_ifc_modify_rmp_in_bits { 7422 u8 opcode[0x10]; 7423 u8 uid[0x10]; 7424 7425 u8 reserved_at_20[0x10]; 7426 u8 op_mod[0x10]; 7427 7428 u8 rmp_state[0x4]; 7429 u8 reserved_at_44[0x4]; 7430 u8 rmpn[0x18]; 7431 7432 u8 reserved_at_60[0x20]; 7433 7434 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7435 7436 u8 reserved_at_c0[0x40]; 7437 7438 struct mlx5_ifc_rmpc_bits ctx; 7439 }; 7440 7441 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7442 u8 status[0x8]; 7443 u8 reserved_at_8[0x18]; 7444 7445 u8 syndrome[0x20]; 7446 7447 u8 reserved_at_40[0x40]; 7448 }; 7449 7450 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7451 u8 reserved_at_0[0x12]; 7452 u8 affiliation[0x1]; 7453 u8 reserved_at_13[0x1]; 7454 u8 disable_uc_local_lb[0x1]; 7455 u8 disable_mc_local_lb[0x1]; 7456 u8 node_guid[0x1]; 7457 u8 port_guid[0x1]; 7458 u8 min_inline[0x1]; 7459 u8 mtu[0x1]; 7460 u8 change_event[0x1]; 7461 u8 promisc[0x1]; 7462 u8 permanent_address[0x1]; 7463 u8 addresses_list[0x1]; 7464 u8 roce_en[0x1]; 7465 u8 reserved_at_1f[0x1]; 7466 }; 7467 7468 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7469 u8 opcode[0x10]; 7470 u8 reserved_at_10[0x10]; 7471 7472 u8 reserved_at_20[0x10]; 7473 u8 op_mod[0x10]; 7474 7475 u8 other_vport[0x1]; 7476 u8 reserved_at_41[0xf]; 7477 u8 vport_number[0x10]; 7478 7479 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7480 7481 u8 reserved_at_80[0x780]; 7482 7483 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7484 }; 7485 7486 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7487 u8 status[0x8]; 7488 u8 reserved_at_8[0x18]; 7489 7490 u8 syndrome[0x20]; 7491 7492 u8 reserved_at_40[0x40]; 7493 }; 7494 7495 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7496 u8 opcode[0x10]; 7497 u8 reserved_at_10[0x10]; 7498 7499 u8 reserved_at_20[0x10]; 7500 u8 op_mod[0x10]; 7501 7502 u8 other_vport[0x1]; 7503 u8 reserved_at_41[0xb]; 7504 u8 port_num[0x4]; 7505 u8 vport_number[0x10]; 7506 7507 u8 reserved_at_60[0x20]; 7508 7509 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7510 }; 7511 7512 struct mlx5_ifc_modify_cq_out_bits { 7513 u8 status[0x8]; 7514 u8 reserved_at_8[0x18]; 7515 7516 u8 syndrome[0x20]; 7517 7518 u8 reserved_at_40[0x40]; 7519 }; 7520 7521 enum { 7522 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7523 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7524 }; 7525 7526 struct mlx5_ifc_modify_cq_in_bits { 7527 u8 opcode[0x10]; 7528 u8 uid[0x10]; 7529 7530 u8 reserved_at_20[0x10]; 7531 u8 op_mod[0x10]; 7532 7533 u8 reserved_at_40[0x8]; 7534 u8 cqn[0x18]; 7535 7536 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7537 7538 struct mlx5_ifc_cqc_bits cq_context; 7539 7540 u8 reserved_at_280[0x60]; 7541 7542 u8 cq_umem_valid[0x1]; 7543 u8 reserved_at_2e1[0x1f]; 7544 7545 u8 reserved_at_300[0x580]; 7546 7547 u8 pas[][0x40]; 7548 }; 7549 7550 struct mlx5_ifc_modify_cong_status_out_bits { 7551 u8 status[0x8]; 7552 u8 reserved_at_8[0x18]; 7553 7554 u8 syndrome[0x20]; 7555 7556 u8 reserved_at_40[0x40]; 7557 }; 7558 7559 struct mlx5_ifc_modify_cong_status_in_bits { 7560 u8 opcode[0x10]; 7561 u8 reserved_at_10[0x10]; 7562 7563 u8 reserved_at_20[0x10]; 7564 u8 op_mod[0x10]; 7565 7566 u8 reserved_at_40[0x18]; 7567 u8 priority[0x4]; 7568 u8 cong_protocol[0x4]; 7569 7570 u8 enable[0x1]; 7571 u8 tag_enable[0x1]; 7572 u8 reserved_at_62[0x1e]; 7573 }; 7574 7575 struct mlx5_ifc_modify_cong_params_out_bits { 7576 u8 status[0x8]; 7577 u8 reserved_at_8[0x18]; 7578 7579 u8 syndrome[0x20]; 7580 7581 u8 reserved_at_40[0x40]; 7582 }; 7583 7584 struct mlx5_ifc_modify_cong_params_in_bits { 7585 u8 opcode[0x10]; 7586 u8 reserved_at_10[0x10]; 7587 7588 u8 reserved_at_20[0x10]; 7589 u8 op_mod[0x10]; 7590 7591 u8 reserved_at_40[0x1c]; 7592 u8 cong_protocol[0x4]; 7593 7594 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7595 7596 u8 reserved_at_80[0x80]; 7597 7598 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7599 }; 7600 7601 struct mlx5_ifc_manage_pages_out_bits { 7602 u8 status[0x8]; 7603 u8 reserved_at_8[0x18]; 7604 7605 u8 syndrome[0x20]; 7606 7607 u8 output_num_entries[0x20]; 7608 7609 u8 reserved_at_60[0x20]; 7610 7611 u8 pas[][0x40]; 7612 }; 7613 7614 enum { 7615 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7616 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7617 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7618 }; 7619 7620 struct mlx5_ifc_manage_pages_in_bits { 7621 u8 opcode[0x10]; 7622 u8 reserved_at_10[0x10]; 7623 7624 u8 reserved_at_20[0x10]; 7625 u8 op_mod[0x10]; 7626 7627 u8 embedded_cpu_function[0x1]; 7628 u8 reserved_at_41[0xf]; 7629 u8 function_id[0x10]; 7630 7631 u8 input_num_entries[0x20]; 7632 7633 u8 pas[][0x40]; 7634 }; 7635 7636 struct mlx5_ifc_mad_ifc_out_bits { 7637 u8 status[0x8]; 7638 u8 reserved_at_8[0x18]; 7639 7640 u8 syndrome[0x20]; 7641 7642 u8 reserved_at_40[0x40]; 7643 7644 u8 response_mad_packet[256][0x8]; 7645 }; 7646 7647 struct mlx5_ifc_mad_ifc_in_bits { 7648 u8 opcode[0x10]; 7649 u8 reserved_at_10[0x10]; 7650 7651 u8 reserved_at_20[0x10]; 7652 u8 op_mod[0x10]; 7653 7654 u8 remote_lid[0x10]; 7655 u8 reserved_at_50[0x8]; 7656 u8 port[0x8]; 7657 7658 u8 reserved_at_60[0x20]; 7659 7660 u8 mad[256][0x8]; 7661 }; 7662 7663 struct mlx5_ifc_init_hca_out_bits { 7664 u8 status[0x8]; 7665 u8 reserved_at_8[0x18]; 7666 7667 u8 syndrome[0x20]; 7668 7669 u8 reserved_at_40[0x40]; 7670 }; 7671 7672 struct mlx5_ifc_init_hca_in_bits { 7673 u8 opcode[0x10]; 7674 u8 reserved_at_10[0x10]; 7675 7676 u8 reserved_at_20[0x10]; 7677 u8 op_mod[0x10]; 7678 7679 u8 reserved_at_40[0x20]; 7680 7681 u8 reserved_at_60[0x2]; 7682 u8 sw_vhca_id[0xe]; 7683 u8 reserved_at_70[0x10]; 7684 7685 u8 sw_owner_id[4][0x20]; 7686 }; 7687 7688 struct mlx5_ifc_init2rtr_qp_out_bits { 7689 u8 status[0x8]; 7690 u8 reserved_at_8[0x18]; 7691 7692 u8 syndrome[0x20]; 7693 7694 u8 reserved_at_40[0x20]; 7695 u8 ece[0x20]; 7696 }; 7697 7698 struct mlx5_ifc_init2rtr_qp_in_bits { 7699 u8 opcode[0x10]; 7700 u8 uid[0x10]; 7701 7702 u8 reserved_at_20[0x10]; 7703 u8 op_mod[0x10]; 7704 7705 u8 reserved_at_40[0x8]; 7706 u8 qpn[0x18]; 7707 7708 u8 reserved_at_60[0x20]; 7709 7710 u8 opt_param_mask[0x20]; 7711 7712 u8 ece[0x20]; 7713 7714 struct mlx5_ifc_qpc_bits qpc; 7715 7716 u8 reserved_at_800[0x80]; 7717 }; 7718 7719 struct mlx5_ifc_init2init_qp_out_bits { 7720 u8 status[0x8]; 7721 u8 reserved_at_8[0x18]; 7722 7723 u8 syndrome[0x20]; 7724 7725 u8 reserved_at_40[0x20]; 7726 u8 ece[0x20]; 7727 }; 7728 7729 struct mlx5_ifc_init2init_qp_in_bits { 7730 u8 opcode[0x10]; 7731 u8 uid[0x10]; 7732 7733 u8 reserved_at_20[0x10]; 7734 u8 op_mod[0x10]; 7735 7736 u8 reserved_at_40[0x8]; 7737 u8 qpn[0x18]; 7738 7739 u8 reserved_at_60[0x20]; 7740 7741 u8 opt_param_mask[0x20]; 7742 7743 u8 ece[0x20]; 7744 7745 struct mlx5_ifc_qpc_bits qpc; 7746 7747 u8 reserved_at_800[0x80]; 7748 }; 7749 7750 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7751 u8 status[0x8]; 7752 u8 reserved_at_8[0x18]; 7753 7754 u8 syndrome[0x20]; 7755 7756 u8 reserved_at_40[0x40]; 7757 7758 u8 packet_headers_log[128][0x8]; 7759 7760 u8 packet_syndrome[64][0x8]; 7761 }; 7762 7763 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7764 u8 opcode[0x10]; 7765 u8 reserved_at_10[0x10]; 7766 7767 u8 reserved_at_20[0x10]; 7768 u8 op_mod[0x10]; 7769 7770 u8 reserved_at_40[0x40]; 7771 }; 7772 7773 struct mlx5_ifc_gen_eqe_in_bits { 7774 u8 opcode[0x10]; 7775 u8 reserved_at_10[0x10]; 7776 7777 u8 reserved_at_20[0x10]; 7778 u8 op_mod[0x10]; 7779 7780 u8 reserved_at_40[0x18]; 7781 u8 eq_number[0x8]; 7782 7783 u8 reserved_at_60[0x20]; 7784 7785 u8 eqe[64][0x8]; 7786 }; 7787 7788 struct mlx5_ifc_gen_eq_out_bits { 7789 u8 status[0x8]; 7790 u8 reserved_at_8[0x18]; 7791 7792 u8 syndrome[0x20]; 7793 7794 u8 reserved_at_40[0x40]; 7795 }; 7796 7797 struct mlx5_ifc_enable_hca_out_bits { 7798 u8 status[0x8]; 7799 u8 reserved_at_8[0x18]; 7800 7801 u8 syndrome[0x20]; 7802 7803 u8 reserved_at_40[0x20]; 7804 }; 7805 7806 struct mlx5_ifc_enable_hca_in_bits { 7807 u8 opcode[0x10]; 7808 u8 reserved_at_10[0x10]; 7809 7810 u8 reserved_at_20[0x10]; 7811 u8 op_mod[0x10]; 7812 7813 u8 embedded_cpu_function[0x1]; 7814 u8 reserved_at_41[0xf]; 7815 u8 function_id[0x10]; 7816 7817 u8 reserved_at_60[0x20]; 7818 }; 7819 7820 struct mlx5_ifc_drain_dct_out_bits { 7821 u8 status[0x8]; 7822 u8 reserved_at_8[0x18]; 7823 7824 u8 syndrome[0x20]; 7825 7826 u8 reserved_at_40[0x40]; 7827 }; 7828 7829 struct mlx5_ifc_drain_dct_in_bits { 7830 u8 opcode[0x10]; 7831 u8 uid[0x10]; 7832 7833 u8 reserved_at_20[0x10]; 7834 u8 op_mod[0x10]; 7835 7836 u8 reserved_at_40[0x8]; 7837 u8 dctn[0x18]; 7838 7839 u8 reserved_at_60[0x20]; 7840 }; 7841 7842 struct mlx5_ifc_disable_hca_out_bits { 7843 u8 status[0x8]; 7844 u8 reserved_at_8[0x18]; 7845 7846 u8 syndrome[0x20]; 7847 7848 u8 reserved_at_40[0x20]; 7849 }; 7850 7851 struct mlx5_ifc_disable_hca_in_bits { 7852 u8 opcode[0x10]; 7853 u8 reserved_at_10[0x10]; 7854 7855 u8 reserved_at_20[0x10]; 7856 u8 op_mod[0x10]; 7857 7858 u8 embedded_cpu_function[0x1]; 7859 u8 reserved_at_41[0xf]; 7860 u8 function_id[0x10]; 7861 7862 u8 reserved_at_60[0x20]; 7863 }; 7864 7865 struct mlx5_ifc_detach_from_mcg_out_bits { 7866 u8 status[0x8]; 7867 u8 reserved_at_8[0x18]; 7868 7869 u8 syndrome[0x20]; 7870 7871 u8 reserved_at_40[0x40]; 7872 }; 7873 7874 struct mlx5_ifc_detach_from_mcg_in_bits { 7875 u8 opcode[0x10]; 7876 u8 uid[0x10]; 7877 7878 u8 reserved_at_20[0x10]; 7879 u8 op_mod[0x10]; 7880 7881 u8 reserved_at_40[0x8]; 7882 u8 qpn[0x18]; 7883 7884 u8 reserved_at_60[0x20]; 7885 7886 u8 multicast_gid[16][0x8]; 7887 }; 7888 7889 struct mlx5_ifc_destroy_xrq_out_bits { 7890 u8 status[0x8]; 7891 u8 reserved_at_8[0x18]; 7892 7893 u8 syndrome[0x20]; 7894 7895 u8 reserved_at_40[0x40]; 7896 }; 7897 7898 struct mlx5_ifc_destroy_xrq_in_bits { 7899 u8 opcode[0x10]; 7900 u8 uid[0x10]; 7901 7902 u8 reserved_at_20[0x10]; 7903 u8 op_mod[0x10]; 7904 7905 u8 reserved_at_40[0x8]; 7906 u8 xrqn[0x18]; 7907 7908 u8 reserved_at_60[0x20]; 7909 }; 7910 7911 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7912 u8 status[0x8]; 7913 u8 reserved_at_8[0x18]; 7914 7915 u8 syndrome[0x20]; 7916 7917 u8 reserved_at_40[0x40]; 7918 }; 7919 7920 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7921 u8 opcode[0x10]; 7922 u8 uid[0x10]; 7923 7924 u8 reserved_at_20[0x10]; 7925 u8 op_mod[0x10]; 7926 7927 u8 reserved_at_40[0x8]; 7928 u8 xrc_srqn[0x18]; 7929 7930 u8 reserved_at_60[0x20]; 7931 }; 7932 7933 struct mlx5_ifc_destroy_tis_out_bits { 7934 u8 status[0x8]; 7935 u8 reserved_at_8[0x18]; 7936 7937 u8 syndrome[0x20]; 7938 7939 u8 reserved_at_40[0x40]; 7940 }; 7941 7942 struct mlx5_ifc_destroy_tis_in_bits { 7943 u8 opcode[0x10]; 7944 u8 uid[0x10]; 7945 7946 u8 reserved_at_20[0x10]; 7947 u8 op_mod[0x10]; 7948 7949 u8 reserved_at_40[0x8]; 7950 u8 tisn[0x18]; 7951 7952 u8 reserved_at_60[0x20]; 7953 }; 7954 7955 struct mlx5_ifc_destroy_tir_out_bits { 7956 u8 status[0x8]; 7957 u8 reserved_at_8[0x18]; 7958 7959 u8 syndrome[0x20]; 7960 7961 u8 reserved_at_40[0x40]; 7962 }; 7963 7964 struct mlx5_ifc_destroy_tir_in_bits { 7965 u8 opcode[0x10]; 7966 u8 uid[0x10]; 7967 7968 u8 reserved_at_20[0x10]; 7969 u8 op_mod[0x10]; 7970 7971 u8 reserved_at_40[0x8]; 7972 u8 tirn[0x18]; 7973 7974 u8 reserved_at_60[0x20]; 7975 }; 7976 7977 struct mlx5_ifc_destroy_srq_out_bits { 7978 u8 status[0x8]; 7979 u8 reserved_at_8[0x18]; 7980 7981 u8 syndrome[0x20]; 7982 7983 u8 reserved_at_40[0x40]; 7984 }; 7985 7986 struct mlx5_ifc_destroy_srq_in_bits { 7987 u8 opcode[0x10]; 7988 u8 uid[0x10]; 7989 7990 u8 reserved_at_20[0x10]; 7991 u8 op_mod[0x10]; 7992 7993 u8 reserved_at_40[0x8]; 7994 u8 srqn[0x18]; 7995 7996 u8 reserved_at_60[0x20]; 7997 }; 7998 7999 struct mlx5_ifc_destroy_sq_out_bits { 8000 u8 status[0x8]; 8001 u8 reserved_at_8[0x18]; 8002 8003 u8 syndrome[0x20]; 8004 8005 u8 reserved_at_40[0x40]; 8006 }; 8007 8008 struct mlx5_ifc_destroy_sq_in_bits { 8009 u8 opcode[0x10]; 8010 u8 uid[0x10]; 8011 8012 u8 reserved_at_20[0x10]; 8013 u8 op_mod[0x10]; 8014 8015 u8 reserved_at_40[0x8]; 8016 u8 sqn[0x18]; 8017 8018 u8 reserved_at_60[0x20]; 8019 }; 8020 8021 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8022 u8 status[0x8]; 8023 u8 reserved_at_8[0x18]; 8024 8025 u8 syndrome[0x20]; 8026 8027 u8 reserved_at_40[0x1c0]; 8028 }; 8029 8030 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8031 u8 opcode[0x10]; 8032 u8 reserved_at_10[0x10]; 8033 8034 u8 reserved_at_20[0x10]; 8035 u8 op_mod[0x10]; 8036 8037 u8 scheduling_hierarchy[0x8]; 8038 u8 reserved_at_48[0x18]; 8039 8040 u8 scheduling_element_id[0x20]; 8041 8042 u8 reserved_at_80[0x180]; 8043 }; 8044 8045 struct mlx5_ifc_destroy_rqt_out_bits { 8046 u8 status[0x8]; 8047 u8 reserved_at_8[0x18]; 8048 8049 u8 syndrome[0x20]; 8050 8051 u8 reserved_at_40[0x40]; 8052 }; 8053 8054 struct mlx5_ifc_destroy_rqt_in_bits { 8055 u8 opcode[0x10]; 8056 u8 uid[0x10]; 8057 8058 u8 reserved_at_20[0x10]; 8059 u8 op_mod[0x10]; 8060 8061 u8 reserved_at_40[0x8]; 8062 u8 rqtn[0x18]; 8063 8064 u8 reserved_at_60[0x20]; 8065 }; 8066 8067 struct mlx5_ifc_destroy_rq_out_bits { 8068 u8 status[0x8]; 8069 u8 reserved_at_8[0x18]; 8070 8071 u8 syndrome[0x20]; 8072 8073 u8 reserved_at_40[0x40]; 8074 }; 8075 8076 struct mlx5_ifc_destroy_rq_in_bits { 8077 u8 opcode[0x10]; 8078 u8 uid[0x10]; 8079 8080 u8 reserved_at_20[0x10]; 8081 u8 op_mod[0x10]; 8082 8083 u8 reserved_at_40[0x8]; 8084 u8 rqn[0x18]; 8085 8086 u8 reserved_at_60[0x20]; 8087 }; 8088 8089 struct mlx5_ifc_set_delay_drop_params_in_bits { 8090 u8 opcode[0x10]; 8091 u8 reserved_at_10[0x10]; 8092 8093 u8 reserved_at_20[0x10]; 8094 u8 op_mod[0x10]; 8095 8096 u8 reserved_at_40[0x20]; 8097 8098 u8 reserved_at_60[0x10]; 8099 u8 delay_drop_timeout[0x10]; 8100 }; 8101 8102 struct mlx5_ifc_set_delay_drop_params_out_bits { 8103 u8 status[0x8]; 8104 u8 reserved_at_8[0x18]; 8105 8106 u8 syndrome[0x20]; 8107 8108 u8 reserved_at_40[0x40]; 8109 }; 8110 8111 struct mlx5_ifc_destroy_rmp_out_bits { 8112 u8 status[0x8]; 8113 u8 reserved_at_8[0x18]; 8114 8115 u8 syndrome[0x20]; 8116 8117 u8 reserved_at_40[0x40]; 8118 }; 8119 8120 struct mlx5_ifc_destroy_rmp_in_bits { 8121 u8 opcode[0x10]; 8122 u8 uid[0x10]; 8123 8124 u8 reserved_at_20[0x10]; 8125 u8 op_mod[0x10]; 8126 8127 u8 reserved_at_40[0x8]; 8128 u8 rmpn[0x18]; 8129 8130 u8 reserved_at_60[0x20]; 8131 }; 8132 8133 struct mlx5_ifc_destroy_qp_out_bits { 8134 u8 status[0x8]; 8135 u8 reserved_at_8[0x18]; 8136 8137 u8 syndrome[0x20]; 8138 8139 u8 reserved_at_40[0x40]; 8140 }; 8141 8142 struct mlx5_ifc_destroy_qp_in_bits { 8143 u8 opcode[0x10]; 8144 u8 uid[0x10]; 8145 8146 u8 reserved_at_20[0x10]; 8147 u8 op_mod[0x10]; 8148 8149 u8 reserved_at_40[0x8]; 8150 u8 qpn[0x18]; 8151 8152 u8 reserved_at_60[0x20]; 8153 }; 8154 8155 struct mlx5_ifc_destroy_psv_out_bits { 8156 u8 status[0x8]; 8157 u8 reserved_at_8[0x18]; 8158 8159 u8 syndrome[0x20]; 8160 8161 u8 reserved_at_40[0x40]; 8162 }; 8163 8164 struct mlx5_ifc_destroy_psv_in_bits { 8165 u8 opcode[0x10]; 8166 u8 reserved_at_10[0x10]; 8167 8168 u8 reserved_at_20[0x10]; 8169 u8 op_mod[0x10]; 8170 8171 u8 reserved_at_40[0x8]; 8172 u8 psvn[0x18]; 8173 8174 u8 reserved_at_60[0x20]; 8175 }; 8176 8177 struct mlx5_ifc_destroy_mkey_out_bits { 8178 u8 status[0x8]; 8179 u8 reserved_at_8[0x18]; 8180 8181 u8 syndrome[0x20]; 8182 8183 u8 reserved_at_40[0x40]; 8184 }; 8185 8186 struct mlx5_ifc_destroy_mkey_in_bits { 8187 u8 opcode[0x10]; 8188 u8 uid[0x10]; 8189 8190 u8 reserved_at_20[0x10]; 8191 u8 op_mod[0x10]; 8192 8193 u8 reserved_at_40[0x8]; 8194 u8 mkey_index[0x18]; 8195 8196 u8 reserved_at_60[0x20]; 8197 }; 8198 8199 struct mlx5_ifc_destroy_flow_table_out_bits { 8200 u8 status[0x8]; 8201 u8 reserved_at_8[0x18]; 8202 8203 u8 syndrome[0x20]; 8204 8205 u8 reserved_at_40[0x40]; 8206 }; 8207 8208 struct mlx5_ifc_destroy_flow_table_in_bits { 8209 u8 opcode[0x10]; 8210 u8 reserved_at_10[0x10]; 8211 8212 u8 reserved_at_20[0x10]; 8213 u8 op_mod[0x10]; 8214 8215 u8 other_vport[0x1]; 8216 u8 reserved_at_41[0xf]; 8217 u8 vport_number[0x10]; 8218 8219 u8 reserved_at_60[0x20]; 8220 8221 u8 table_type[0x8]; 8222 u8 reserved_at_88[0x18]; 8223 8224 u8 reserved_at_a0[0x8]; 8225 u8 table_id[0x18]; 8226 8227 u8 reserved_at_c0[0x140]; 8228 }; 8229 8230 struct mlx5_ifc_destroy_flow_group_out_bits { 8231 u8 status[0x8]; 8232 u8 reserved_at_8[0x18]; 8233 8234 u8 syndrome[0x20]; 8235 8236 u8 reserved_at_40[0x40]; 8237 }; 8238 8239 struct mlx5_ifc_destroy_flow_group_in_bits { 8240 u8 opcode[0x10]; 8241 u8 reserved_at_10[0x10]; 8242 8243 u8 reserved_at_20[0x10]; 8244 u8 op_mod[0x10]; 8245 8246 u8 other_vport[0x1]; 8247 u8 reserved_at_41[0xf]; 8248 u8 vport_number[0x10]; 8249 8250 u8 reserved_at_60[0x20]; 8251 8252 u8 table_type[0x8]; 8253 u8 reserved_at_88[0x18]; 8254 8255 u8 reserved_at_a0[0x8]; 8256 u8 table_id[0x18]; 8257 8258 u8 group_id[0x20]; 8259 8260 u8 reserved_at_e0[0x120]; 8261 }; 8262 8263 struct mlx5_ifc_destroy_eq_out_bits { 8264 u8 status[0x8]; 8265 u8 reserved_at_8[0x18]; 8266 8267 u8 syndrome[0x20]; 8268 8269 u8 reserved_at_40[0x40]; 8270 }; 8271 8272 struct mlx5_ifc_destroy_eq_in_bits { 8273 u8 opcode[0x10]; 8274 u8 reserved_at_10[0x10]; 8275 8276 u8 reserved_at_20[0x10]; 8277 u8 op_mod[0x10]; 8278 8279 u8 reserved_at_40[0x18]; 8280 u8 eq_number[0x8]; 8281 8282 u8 reserved_at_60[0x20]; 8283 }; 8284 8285 struct mlx5_ifc_destroy_dct_out_bits { 8286 u8 status[0x8]; 8287 u8 reserved_at_8[0x18]; 8288 8289 u8 syndrome[0x20]; 8290 8291 u8 reserved_at_40[0x40]; 8292 }; 8293 8294 struct mlx5_ifc_destroy_dct_in_bits { 8295 u8 opcode[0x10]; 8296 u8 uid[0x10]; 8297 8298 u8 reserved_at_20[0x10]; 8299 u8 op_mod[0x10]; 8300 8301 u8 reserved_at_40[0x8]; 8302 u8 dctn[0x18]; 8303 8304 u8 reserved_at_60[0x20]; 8305 }; 8306 8307 struct mlx5_ifc_destroy_cq_out_bits { 8308 u8 status[0x8]; 8309 u8 reserved_at_8[0x18]; 8310 8311 u8 syndrome[0x20]; 8312 8313 u8 reserved_at_40[0x40]; 8314 }; 8315 8316 struct mlx5_ifc_destroy_cq_in_bits { 8317 u8 opcode[0x10]; 8318 u8 uid[0x10]; 8319 8320 u8 reserved_at_20[0x10]; 8321 u8 op_mod[0x10]; 8322 8323 u8 reserved_at_40[0x8]; 8324 u8 cqn[0x18]; 8325 8326 u8 reserved_at_60[0x20]; 8327 }; 8328 8329 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8330 u8 status[0x8]; 8331 u8 reserved_at_8[0x18]; 8332 8333 u8 syndrome[0x20]; 8334 8335 u8 reserved_at_40[0x40]; 8336 }; 8337 8338 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8339 u8 opcode[0x10]; 8340 u8 reserved_at_10[0x10]; 8341 8342 u8 reserved_at_20[0x10]; 8343 u8 op_mod[0x10]; 8344 8345 u8 reserved_at_40[0x20]; 8346 8347 u8 reserved_at_60[0x10]; 8348 u8 vxlan_udp_port[0x10]; 8349 }; 8350 8351 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8352 u8 status[0x8]; 8353 u8 reserved_at_8[0x18]; 8354 8355 u8 syndrome[0x20]; 8356 8357 u8 reserved_at_40[0x40]; 8358 }; 8359 8360 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8361 u8 opcode[0x10]; 8362 u8 reserved_at_10[0x10]; 8363 8364 u8 reserved_at_20[0x10]; 8365 u8 op_mod[0x10]; 8366 8367 u8 reserved_at_40[0x60]; 8368 8369 u8 reserved_at_a0[0x8]; 8370 u8 table_index[0x18]; 8371 8372 u8 reserved_at_c0[0x140]; 8373 }; 8374 8375 struct mlx5_ifc_delete_fte_out_bits { 8376 u8 status[0x8]; 8377 u8 reserved_at_8[0x18]; 8378 8379 u8 syndrome[0x20]; 8380 8381 u8 reserved_at_40[0x40]; 8382 }; 8383 8384 struct mlx5_ifc_delete_fte_in_bits { 8385 u8 opcode[0x10]; 8386 u8 reserved_at_10[0x10]; 8387 8388 u8 reserved_at_20[0x10]; 8389 u8 op_mod[0x10]; 8390 8391 u8 other_vport[0x1]; 8392 u8 reserved_at_41[0xf]; 8393 u8 vport_number[0x10]; 8394 8395 u8 reserved_at_60[0x20]; 8396 8397 u8 table_type[0x8]; 8398 u8 reserved_at_88[0x18]; 8399 8400 u8 reserved_at_a0[0x8]; 8401 u8 table_id[0x18]; 8402 8403 u8 reserved_at_c0[0x40]; 8404 8405 u8 flow_index[0x20]; 8406 8407 u8 reserved_at_120[0xe0]; 8408 }; 8409 8410 struct mlx5_ifc_dealloc_xrcd_out_bits { 8411 u8 status[0x8]; 8412 u8 reserved_at_8[0x18]; 8413 8414 u8 syndrome[0x20]; 8415 8416 u8 reserved_at_40[0x40]; 8417 }; 8418 8419 struct mlx5_ifc_dealloc_xrcd_in_bits { 8420 u8 opcode[0x10]; 8421 u8 uid[0x10]; 8422 8423 u8 reserved_at_20[0x10]; 8424 u8 op_mod[0x10]; 8425 8426 u8 reserved_at_40[0x8]; 8427 u8 xrcd[0x18]; 8428 8429 u8 reserved_at_60[0x20]; 8430 }; 8431 8432 struct mlx5_ifc_dealloc_uar_out_bits { 8433 u8 status[0x8]; 8434 u8 reserved_at_8[0x18]; 8435 8436 u8 syndrome[0x20]; 8437 8438 u8 reserved_at_40[0x40]; 8439 }; 8440 8441 struct mlx5_ifc_dealloc_uar_in_bits { 8442 u8 opcode[0x10]; 8443 u8 uid[0x10]; 8444 8445 u8 reserved_at_20[0x10]; 8446 u8 op_mod[0x10]; 8447 8448 u8 reserved_at_40[0x8]; 8449 u8 uar[0x18]; 8450 8451 u8 reserved_at_60[0x20]; 8452 }; 8453 8454 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8455 u8 status[0x8]; 8456 u8 reserved_at_8[0x18]; 8457 8458 u8 syndrome[0x20]; 8459 8460 u8 reserved_at_40[0x40]; 8461 }; 8462 8463 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8464 u8 opcode[0x10]; 8465 u8 uid[0x10]; 8466 8467 u8 reserved_at_20[0x10]; 8468 u8 op_mod[0x10]; 8469 8470 u8 reserved_at_40[0x8]; 8471 u8 transport_domain[0x18]; 8472 8473 u8 reserved_at_60[0x20]; 8474 }; 8475 8476 struct mlx5_ifc_dealloc_q_counter_out_bits { 8477 u8 status[0x8]; 8478 u8 reserved_at_8[0x18]; 8479 8480 u8 syndrome[0x20]; 8481 8482 u8 reserved_at_40[0x40]; 8483 }; 8484 8485 struct mlx5_ifc_dealloc_q_counter_in_bits { 8486 u8 opcode[0x10]; 8487 u8 reserved_at_10[0x10]; 8488 8489 u8 reserved_at_20[0x10]; 8490 u8 op_mod[0x10]; 8491 8492 u8 reserved_at_40[0x18]; 8493 u8 counter_set_id[0x8]; 8494 8495 u8 reserved_at_60[0x20]; 8496 }; 8497 8498 struct mlx5_ifc_dealloc_pd_out_bits { 8499 u8 status[0x8]; 8500 u8 reserved_at_8[0x18]; 8501 8502 u8 syndrome[0x20]; 8503 8504 u8 reserved_at_40[0x40]; 8505 }; 8506 8507 struct mlx5_ifc_dealloc_pd_in_bits { 8508 u8 opcode[0x10]; 8509 u8 uid[0x10]; 8510 8511 u8 reserved_at_20[0x10]; 8512 u8 op_mod[0x10]; 8513 8514 u8 reserved_at_40[0x8]; 8515 u8 pd[0x18]; 8516 8517 u8 reserved_at_60[0x20]; 8518 }; 8519 8520 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8521 u8 status[0x8]; 8522 u8 reserved_at_8[0x18]; 8523 8524 u8 syndrome[0x20]; 8525 8526 u8 reserved_at_40[0x40]; 8527 }; 8528 8529 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8530 u8 opcode[0x10]; 8531 u8 reserved_at_10[0x10]; 8532 8533 u8 reserved_at_20[0x10]; 8534 u8 op_mod[0x10]; 8535 8536 u8 flow_counter_id[0x20]; 8537 8538 u8 reserved_at_60[0x20]; 8539 }; 8540 8541 struct mlx5_ifc_create_xrq_out_bits { 8542 u8 status[0x8]; 8543 u8 reserved_at_8[0x18]; 8544 8545 u8 syndrome[0x20]; 8546 8547 u8 reserved_at_40[0x8]; 8548 u8 xrqn[0x18]; 8549 8550 u8 reserved_at_60[0x20]; 8551 }; 8552 8553 struct mlx5_ifc_create_xrq_in_bits { 8554 u8 opcode[0x10]; 8555 u8 uid[0x10]; 8556 8557 u8 reserved_at_20[0x10]; 8558 u8 op_mod[0x10]; 8559 8560 u8 reserved_at_40[0x40]; 8561 8562 struct mlx5_ifc_xrqc_bits xrq_context; 8563 }; 8564 8565 struct mlx5_ifc_create_xrc_srq_out_bits { 8566 u8 status[0x8]; 8567 u8 reserved_at_8[0x18]; 8568 8569 u8 syndrome[0x20]; 8570 8571 u8 reserved_at_40[0x8]; 8572 u8 xrc_srqn[0x18]; 8573 8574 u8 reserved_at_60[0x20]; 8575 }; 8576 8577 struct mlx5_ifc_create_xrc_srq_in_bits { 8578 u8 opcode[0x10]; 8579 u8 uid[0x10]; 8580 8581 u8 reserved_at_20[0x10]; 8582 u8 op_mod[0x10]; 8583 8584 u8 reserved_at_40[0x40]; 8585 8586 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8587 8588 u8 reserved_at_280[0x60]; 8589 8590 u8 xrc_srq_umem_valid[0x1]; 8591 u8 reserved_at_2e1[0x1f]; 8592 8593 u8 reserved_at_300[0x580]; 8594 8595 u8 pas[][0x40]; 8596 }; 8597 8598 struct mlx5_ifc_create_tis_out_bits { 8599 u8 status[0x8]; 8600 u8 reserved_at_8[0x18]; 8601 8602 u8 syndrome[0x20]; 8603 8604 u8 reserved_at_40[0x8]; 8605 u8 tisn[0x18]; 8606 8607 u8 reserved_at_60[0x20]; 8608 }; 8609 8610 struct mlx5_ifc_create_tis_in_bits { 8611 u8 opcode[0x10]; 8612 u8 uid[0x10]; 8613 8614 u8 reserved_at_20[0x10]; 8615 u8 op_mod[0x10]; 8616 8617 u8 reserved_at_40[0xc0]; 8618 8619 struct mlx5_ifc_tisc_bits ctx; 8620 }; 8621 8622 struct mlx5_ifc_create_tir_out_bits { 8623 u8 status[0x8]; 8624 u8 icm_address_63_40[0x18]; 8625 8626 u8 syndrome[0x20]; 8627 8628 u8 icm_address_39_32[0x8]; 8629 u8 tirn[0x18]; 8630 8631 u8 icm_address_31_0[0x20]; 8632 }; 8633 8634 struct mlx5_ifc_create_tir_in_bits { 8635 u8 opcode[0x10]; 8636 u8 uid[0x10]; 8637 8638 u8 reserved_at_20[0x10]; 8639 u8 op_mod[0x10]; 8640 8641 u8 reserved_at_40[0xc0]; 8642 8643 struct mlx5_ifc_tirc_bits ctx; 8644 }; 8645 8646 struct mlx5_ifc_create_srq_out_bits { 8647 u8 status[0x8]; 8648 u8 reserved_at_8[0x18]; 8649 8650 u8 syndrome[0x20]; 8651 8652 u8 reserved_at_40[0x8]; 8653 u8 srqn[0x18]; 8654 8655 u8 reserved_at_60[0x20]; 8656 }; 8657 8658 struct mlx5_ifc_create_srq_in_bits { 8659 u8 opcode[0x10]; 8660 u8 uid[0x10]; 8661 8662 u8 reserved_at_20[0x10]; 8663 u8 op_mod[0x10]; 8664 8665 u8 reserved_at_40[0x40]; 8666 8667 struct mlx5_ifc_srqc_bits srq_context_entry; 8668 8669 u8 reserved_at_280[0x600]; 8670 8671 u8 pas[][0x40]; 8672 }; 8673 8674 struct mlx5_ifc_create_sq_out_bits { 8675 u8 status[0x8]; 8676 u8 reserved_at_8[0x18]; 8677 8678 u8 syndrome[0x20]; 8679 8680 u8 reserved_at_40[0x8]; 8681 u8 sqn[0x18]; 8682 8683 u8 reserved_at_60[0x20]; 8684 }; 8685 8686 struct mlx5_ifc_create_sq_in_bits { 8687 u8 opcode[0x10]; 8688 u8 uid[0x10]; 8689 8690 u8 reserved_at_20[0x10]; 8691 u8 op_mod[0x10]; 8692 8693 u8 reserved_at_40[0xc0]; 8694 8695 struct mlx5_ifc_sqc_bits ctx; 8696 }; 8697 8698 struct mlx5_ifc_create_scheduling_element_out_bits { 8699 u8 status[0x8]; 8700 u8 reserved_at_8[0x18]; 8701 8702 u8 syndrome[0x20]; 8703 8704 u8 reserved_at_40[0x40]; 8705 8706 u8 scheduling_element_id[0x20]; 8707 8708 u8 reserved_at_a0[0x160]; 8709 }; 8710 8711 struct mlx5_ifc_create_scheduling_element_in_bits { 8712 u8 opcode[0x10]; 8713 u8 reserved_at_10[0x10]; 8714 8715 u8 reserved_at_20[0x10]; 8716 u8 op_mod[0x10]; 8717 8718 u8 scheduling_hierarchy[0x8]; 8719 u8 reserved_at_48[0x18]; 8720 8721 u8 reserved_at_60[0xa0]; 8722 8723 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8724 8725 u8 reserved_at_300[0x100]; 8726 }; 8727 8728 struct mlx5_ifc_create_rqt_out_bits { 8729 u8 status[0x8]; 8730 u8 reserved_at_8[0x18]; 8731 8732 u8 syndrome[0x20]; 8733 8734 u8 reserved_at_40[0x8]; 8735 u8 rqtn[0x18]; 8736 8737 u8 reserved_at_60[0x20]; 8738 }; 8739 8740 struct mlx5_ifc_create_rqt_in_bits { 8741 u8 opcode[0x10]; 8742 u8 uid[0x10]; 8743 8744 u8 reserved_at_20[0x10]; 8745 u8 op_mod[0x10]; 8746 8747 u8 reserved_at_40[0xc0]; 8748 8749 struct mlx5_ifc_rqtc_bits rqt_context; 8750 }; 8751 8752 struct mlx5_ifc_create_rq_out_bits { 8753 u8 status[0x8]; 8754 u8 reserved_at_8[0x18]; 8755 8756 u8 syndrome[0x20]; 8757 8758 u8 reserved_at_40[0x8]; 8759 u8 rqn[0x18]; 8760 8761 u8 reserved_at_60[0x20]; 8762 }; 8763 8764 struct mlx5_ifc_create_rq_in_bits { 8765 u8 opcode[0x10]; 8766 u8 uid[0x10]; 8767 8768 u8 reserved_at_20[0x10]; 8769 u8 op_mod[0x10]; 8770 8771 u8 reserved_at_40[0xc0]; 8772 8773 struct mlx5_ifc_rqc_bits ctx; 8774 }; 8775 8776 struct mlx5_ifc_create_rmp_out_bits { 8777 u8 status[0x8]; 8778 u8 reserved_at_8[0x18]; 8779 8780 u8 syndrome[0x20]; 8781 8782 u8 reserved_at_40[0x8]; 8783 u8 rmpn[0x18]; 8784 8785 u8 reserved_at_60[0x20]; 8786 }; 8787 8788 struct mlx5_ifc_create_rmp_in_bits { 8789 u8 opcode[0x10]; 8790 u8 uid[0x10]; 8791 8792 u8 reserved_at_20[0x10]; 8793 u8 op_mod[0x10]; 8794 8795 u8 reserved_at_40[0xc0]; 8796 8797 struct mlx5_ifc_rmpc_bits ctx; 8798 }; 8799 8800 struct mlx5_ifc_create_qp_out_bits { 8801 u8 status[0x8]; 8802 u8 reserved_at_8[0x18]; 8803 8804 u8 syndrome[0x20]; 8805 8806 u8 reserved_at_40[0x8]; 8807 u8 qpn[0x18]; 8808 8809 u8 ece[0x20]; 8810 }; 8811 8812 struct mlx5_ifc_create_qp_in_bits { 8813 u8 opcode[0x10]; 8814 u8 uid[0x10]; 8815 8816 u8 reserved_at_20[0x10]; 8817 u8 op_mod[0x10]; 8818 8819 u8 qpc_ext[0x1]; 8820 u8 reserved_at_41[0x7]; 8821 u8 input_qpn[0x18]; 8822 8823 u8 reserved_at_60[0x20]; 8824 u8 opt_param_mask[0x20]; 8825 8826 u8 ece[0x20]; 8827 8828 struct mlx5_ifc_qpc_bits qpc; 8829 8830 u8 reserved_at_800[0x60]; 8831 8832 u8 wq_umem_valid[0x1]; 8833 u8 reserved_at_861[0x1f]; 8834 8835 u8 pas[][0x40]; 8836 }; 8837 8838 struct mlx5_ifc_create_psv_out_bits { 8839 u8 status[0x8]; 8840 u8 reserved_at_8[0x18]; 8841 8842 u8 syndrome[0x20]; 8843 8844 u8 reserved_at_40[0x40]; 8845 8846 u8 reserved_at_80[0x8]; 8847 u8 psv0_index[0x18]; 8848 8849 u8 reserved_at_a0[0x8]; 8850 u8 psv1_index[0x18]; 8851 8852 u8 reserved_at_c0[0x8]; 8853 u8 psv2_index[0x18]; 8854 8855 u8 reserved_at_e0[0x8]; 8856 u8 psv3_index[0x18]; 8857 }; 8858 8859 struct mlx5_ifc_create_psv_in_bits { 8860 u8 opcode[0x10]; 8861 u8 reserved_at_10[0x10]; 8862 8863 u8 reserved_at_20[0x10]; 8864 u8 op_mod[0x10]; 8865 8866 u8 num_psv[0x4]; 8867 u8 reserved_at_44[0x4]; 8868 u8 pd[0x18]; 8869 8870 u8 reserved_at_60[0x20]; 8871 }; 8872 8873 struct mlx5_ifc_create_mkey_out_bits { 8874 u8 status[0x8]; 8875 u8 reserved_at_8[0x18]; 8876 8877 u8 syndrome[0x20]; 8878 8879 u8 reserved_at_40[0x8]; 8880 u8 mkey_index[0x18]; 8881 8882 u8 reserved_at_60[0x20]; 8883 }; 8884 8885 struct mlx5_ifc_create_mkey_in_bits { 8886 u8 opcode[0x10]; 8887 u8 uid[0x10]; 8888 8889 u8 reserved_at_20[0x10]; 8890 u8 op_mod[0x10]; 8891 8892 u8 reserved_at_40[0x20]; 8893 8894 u8 pg_access[0x1]; 8895 u8 mkey_umem_valid[0x1]; 8896 u8 reserved_at_62[0x1e]; 8897 8898 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8899 8900 u8 reserved_at_280[0x80]; 8901 8902 u8 translations_octword_actual_size[0x20]; 8903 8904 u8 reserved_at_320[0x560]; 8905 8906 u8 klm_pas_mtt[][0x20]; 8907 }; 8908 8909 enum { 8910 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8911 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8912 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8913 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8914 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8915 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8916 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8917 }; 8918 8919 struct mlx5_ifc_create_flow_table_out_bits { 8920 u8 status[0x8]; 8921 u8 icm_address_63_40[0x18]; 8922 8923 u8 syndrome[0x20]; 8924 8925 u8 icm_address_39_32[0x8]; 8926 u8 table_id[0x18]; 8927 8928 u8 icm_address_31_0[0x20]; 8929 }; 8930 8931 struct mlx5_ifc_create_flow_table_in_bits { 8932 u8 opcode[0x10]; 8933 u8 uid[0x10]; 8934 8935 u8 reserved_at_20[0x10]; 8936 u8 op_mod[0x10]; 8937 8938 u8 other_vport[0x1]; 8939 u8 reserved_at_41[0xf]; 8940 u8 vport_number[0x10]; 8941 8942 u8 reserved_at_60[0x20]; 8943 8944 u8 table_type[0x8]; 8945 u8 reserved_at_88[0x18]; 8946 8947 u8 reserved_at_a0[0x20]; 8948 8949 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8950 }; 8951 8952 struct mlx5_ifc_create_flow_group_out_bits { 8953 u8 status[0x8]; 8954 u8 reserved_at_8[0x18]; 8955 8956 u8 syndrome[0x20]; 8957 8958 u8 reserved_at_40[0x8]; 8959 u8 group_id[0x18]; 8960 8961 u8 reserved_at_60[0x20]; 8962 }; 8963 8964 enum { 8965 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8966 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8967 }; 8968 8969 enum { 8970 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8971 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8972 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8973 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8974 }; 8975 8976 struct mlx5_ifc_create_flow_group_in_bits { 8977 u8 opcode[0x10]; 8978 u8 reserved_at_10[0x10]; 8979 8980 u8 reserved_at_20[0x10]; 8981 u8 op_mod[0x10]; 8982 8983 u8 other_vport[0x1]; 8984 u8 reserved_at_41[0xf]; 8985 u8 vport_number[0x10]; 8986 8987 u8 reserved_at_60[0x20]; 8988 8989 u8 table_type[0x8]; 8990 u8 reserved_at_88[0x4]; 8991 u8 group_type[0x4]; 8992 u8 reserved_at_90[0x10]; 8993 8994 u8 reserved_at_a0[0x8]; 8995 u8 table_id[0x18]; 8996 8997 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8998 8999 u8 reserved_at_c1[0x1f]; 9000 9001 u8 start_flow_index[0x20]; 9002 9003 u8 reserved_at_100[0x20]; 9004 9005 u8 end_flow_index[0x20]; 9006 9007 u8 reserved_at_140[0x10]; 9008 u8 match_definer_id[0x10]; 9009 9010 u8 reserved_at_160[0x80]; 9011 9012 u8 reserved_at_1e0[0x18]; 9013 u8 match_criteria_enable[0x8]; 9014 9015 struct mlx5_ifc_fte_match_param_bits match_criteria; 9016 9017 u8 reserved_at_1200[0xe00]; 9018 }; 9019 9020 struct mlx5_ifc_create_eq_out_bits { 9021 u8 status[0x8]; 9022 u8 reserved_at_8[0x18]; 9023 9024 u8 syndrome[0x20]; 9025 9026 u8 reserved_at_40[0x18]; 9027 u8 eq_number[0x8]; 9028 9029 u8 reserved_at_60[0x20]; 9030 }; 9031 9032 struct mlx5_ifc_create_eq_in_bits { 9033 u8 opcode[0x10]; 9034 u8 uid[0x10]; 9035 9036 u8 reserved_at_20[0x10]; 9037 u8 op_mod[0x10]; 9038 9039 u8 reserved_at_40[0x40]; 9040 9041 struct mlx5_ifc_eqc_bits eq_context_entry; 9042 9043 u8 reserved_at_280[0x40]; 9044 9045 u8 event_bitmask[4][0x40]; 9046 9047 u8 reserved_at_3c0[0x4c0]; 9048 9049 u8 pas[][0x40]; 9050 }; 9051 9052 struct mlx5_ifc_create_dct_out_bits { 9053 u8 status[0x8]; 9054 u8 reserved_at_8[0x18]; 9055 9056 u8 syndrome[0x20]; 9057 9058 u8 reserved_at_40[0x8]; 9059 u8 dctn[0x18]; 9060 9061 u8 ece[0x20]; 9062 }; 9063 9064 struct mlx5_ifc_create_dct_in_bits { 9065 u8 opcode[0x10]; 9066 u8 uid[0x10]; 9067 9068 u8 reserved_at_20[0x10]; 9069 u8 op_mod[0x10]; 9070 9071 u8 reserved_at_40[0x40]; 9072 9073 struct mlx5_ifc_dctc_bits dct_context_entry; 9074 9075 u8 reserved_at_280[0x180]; 9076 }; 9077 9078 struct mlx5_ifc_create_cq_out_bits { 9079 u8 status[0x8]; 9080 u8 reserved_at_8[0x18]; 9081 9082 u8 syndrome[0x20]; 9083 9084 u8 reserved_at_40[0x8]; 9085 u8 cqn[0x18]; 9086 9087 u8 reserved_at_60[0x20]; 9088 }; 9089 9090 struct mlx5_ifc_create_cq_in_bits { 9091 u8 opcode[0x10]; 9092 u8 uid[0x10]; 9093 9094 u8 reserved_at_20[0x10]; 9095 u8 op_mod[0x10]; 9096 9097 u8 reserved_at_40[0x40]; 9098 9099 struct mlx5_ifc_cqc_bits cq_context; 9100 9101 u8 reserved_at_280[0x60]; 9102 9103 u8 cq_umem_valid[0x1]; 9104 u8 reserved_at_2e1[0x59f]; 9105 9106 u8 pas[][0x40]; 9107 }; 9108 9109 struct mlx5_ifc_config_int_moderation_out_bits { 9110 u8 status[0x8]; 9111 u8 reserved_at_8[0x18]; 9112 9113 u8 syndrome[0x20]; 9114 9115 u8 reserved_at_40[0x4]; 9116 u8 min_delay[0xc]; 9117 u8 int_vector[0x10]; 9118 9119 u8 reserved_at_60[0x20]; 9120 }; 9121 9122 enum { 9123 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9124 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9125 }; 9126 9127 struct mlx5_ifc_config_int_moderation_in_bits { 9128 u8 opcode[0x10]; 9129 u8 reserved_at_10[0x10]; 9130 9131 u8 reserved_at_20[0x10]; 9132 u8 op_mod[0x10]; 9133 9134 u8 reserved_at_40[0x4]; 9135 u8 min_delay[0xc]; 9136 u8 int_vector[0x10]; 9137 9138 u8 reserved_at_60[0x20]; 9139 }; 9140 9141 struct mlx5_ifc_attach_to_mcg_out_bits { 9142 u8 status[0x8]; 9143 u8 reserved_at_8[0x18]; 9144 9145 u8 syndrome[0x20]; 9146 9147 u8 reserved_at_40[0x40]; 9148 }; 9149 9150 struct mlx5_ifc_attach_to_mcg_in_bits { 9151 u8 opcode[0x10]; 9152 u8 uid[0x10]; 9153 9154 u8 reserved_at_20[0x10]; 9155 u8 op_mod[0x10]; 9156 9157 u8 reserved_at_40[0x8]; 9158 u8 qpn[0x18]; 9159 9160 u8 reserved_at_60[0x20]; 9161 9162 u8 multicast_gid[16][0x8]; 9163 }; 9164 9165 struct mlx5_ifc_arm_xrq_out_bits { 9166 u8 status[0x8]; 9167 u8 reserved_at_8[0x18]; 9168 9169 u8 syndrome[0x20]; 9170 9171 u8 reserved_at_40[0x40]; 9172 }; 9173 9174 struct mlx5_ifc_arm_xrq_in_bits { 9175 u8 opcode[0x10]; 9176 u8 reserved_at_10[0x10]; 9177 9178 u8 reserved_at_20[0x10]; 9179 u8 op_mod[0x10]; 9180 9181 u8 reserved_at_40[0x8]; 9182 u8 xrqn[0x18]; 9183 9184 u8 reserved_at_60[0x10]; 9185 u8 lwm[0x10]; 9186 }; 9187 9188 struct mlx5_ifc_arm_xrc_srq_out_bits { 9189 u8 status[0x8]; 9190 u8 reserved_at_8[0x18]; 9191 9192 u8 syndrome[0x20]; 9193 9194 u8 reserved_at_40[0x40]; 9195 }; 9196 9197 enum { 9198 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9199 }; 9200 9201 struct mlx5_ifc_arm_xrc_srq_in_bits { 9202 u8 opcode[0x10]; 9203 u8 uid[0x10]; 9204 9205 u8 reserved_at_20[0x10]; 9206 u8 op_mod[0x10]; 9207 9208 u8 reserved_at_40[0x8]; 9209 u8 xrc_srqn[0x18]; 9210 9211 u8 reserved_at_60[0x10]; 9212 u8 lwm[0x10]; 9213 }; 9214 9215 struct mlx5_ifc_arm_rq_out_bits { 9216 u8 status[0x8]; 9217 u8 reserved_at_8[0x18]; 9218 9219 u8 syndrome[0x20]; 9220 9221 u8 reserved_at_40[0x40]; 9222 }; 9223 9224 enum { 9225 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9226 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9227 }; 9228 9229 struct mlx5_ifc_arm_rq_in_bits { 9230 u8 opcode[0x10]; 9231 u8 uid[0x10]; 9232 9233 u8 reserved_at_20[0x10]; 9234 u8 op_mod[0x10]; 9235 9236 u8 reserved_at_40[0x8]; 9237 u8 srq_number[0x18]; 9238 9239 u8 reserved_at_60[0x10]; 9240 u8 lwm[0x10]; 9241 }; 9242 9243 struct mlx5_ifc_arm_dct_out_bits { 9244 u8 status[0x8]; 9245 u8 reserved_at_8[0x18]; 9246 9247 u8 syndrome[0x20]; 9248 9249 u8 reserved_at_40[0x40]; 9250 }; 9251 9252 struct mlx5_ifc_arm_dct_in_bits { 9253 u8 opcode[0x10]; 9254 u8 reserved_at_10[0x10]; 9255 9256 u8 reserved_at_20[0x10]; 9257 u8 op_mod[0x10]; 9258 9259 u8 reserved_at_40[0x8]; 9260 u8 dct_number[0x18]; 9261 9262 u8 reserved_at_60[0x20]; 9263 }; 9264 9265 struct mlx5_ifc_alloc_xrcd_out_bits { 9266 u8 status[0x8]; 9267 u8 reserved_at_8[0x18]; 9268 9269 u8 syndrome[0x20]; 9270 9271 u8 reserved_at_40[0x8]; 9272 u8 xrcd[0x18]; 9273 9274 u8 reserved_at_60[0x20]; 9275 }; 9276 9277 struct mlx5_ifc_alloc_xrcd_in_bits { 9278 u8 opcode[0x10]; 9279 u8 uid[0x10]; 9280 9281 u8 reserved_at_20[0x10]; 9282 u8 op_mod[0x10]; 9283 9284 u8 reserved_at_40[0x40]; 9285 }; 9286 9287 struct mlx5_ifc_alloc_uar_out_bits { 9288 u8 status[0x8]; 9289 u8 reserved_at_8[0x18]; 9290 9291 u8 syndrome[0x20]; 9292 9293 u8 reserved_at_40[0x8]; 9294 u8 uar[0x18]; 9295 9296 u8 reserved_at_60[0x20]; 9297 }; 9298 9299 struct mlx5_ifc_alloc_uar_in_bits { 9300 u8 opcode[0x10]; 9301 u8 uid[0x10]; 9302 9303 u8 reserved_at_20[0x10]; 9304 u8 op_mod[0x10]; 9305 9306 u8 reserved_at_40[0x40]; 9307 }; 9308 9309 struct mlx5_ifc_alloc_transport_domain_out_bits { 9310 u8 status[0x8]; 9311 u8 reserved_at_8[0x18]; 9312 9313 u8 syndrome[0x20]; 9314 9315 u8 reserved_at_40[0x8]; 9316 u8 transport_domain[0x18]; 9317 9318 u8 reserved_at_60[0x20]; 9319 }; 9320 9321 struct mlx5_ifc_alloc_transport_domain_in_bits { 9322 u8 opcode[0x10]; 9323 u8 uid[0x10]; 9324 9325 u8 reserved_at_20[0x10]; 9326 u8 op_mod[0x10]; 9327 9328 u8 reserved_at_40[0x40]; 9329 }; 9330 9331 struct mlx5_ifc_alloc_q_counter_out_bits { 9332 u8 status[0x8]; 9333 u8 reserved_at_8[0x18]; 9334 9335 u8 syndrome[0x20]; 9336 9337 u8 reserved_at_40[0x18]; 9338 u8 counter_set_id[0x8]; 9339 9340 u8 reserved_at_60[0x20]; 9341 }; 9342 9343 struct mlx5_ifc_alloc_q_counter_in_bits { 9344 u8 opcode[0x10]; 9345 u8 uid[0x10]; 9346 9347 u8 reserved_at_20[0x10]; 9348 u8 op_mod[0x10]; 9349 9350 u8 reserved_at_40[0x40]; 9351 }; 9352 9353 struct mlx5_ifc_alloc_pd_out_bits { 9354 u8 status[0x8]; 9355 u8 reserved_at_8[0x18]; 9356 9357 u8 syndrome[0x20]; 9358 9359 u8 reserved_at_40[0x8]; 9360 u8 pd[0x18]; 9361 9362 u8 reserved_at_60[0x20]; 9363 }; 9364 9365 struct mlx5_ifc_alloc_pd_in_bits { 9366 u8 opcode[0x10]; 9367 u8 uid[0x10]; 9368 9369 u8 reserved_at_20[0x10]; 9370 u8 op_mod[0x10]; 9371 9372 u8 reserved_at_40[0x40]; 9373 }; 9374 9375 struct mlx5_ifc_alloc_flow_counter_out_bits { 9376 u8 status[0x8]; 9377 u8 reserved_at_8[0x18]; 9378 9379 u8 syndrome[0x20]; 9380 9381 u8 flow_counter_id[0x20]; 9382 9383 u8 reserved_at_60[0x20]; 9384 }; 9385 9386 struct mlx5_ifc_alloc_flow_counter_in_bits { 9387 u8 opcode[0x10]; 9388 u8 reserved_at_10[0x10]; 9389 9390 u8 reserved_at_20[0x10]; 9391 u8 op_mod[0x10]; 9392 9393 u8 reserved_at_40[0x33]; 9394 u8 flow_counter_bulk_log_size[0x5]; 9395 u8 flow_counter_bulk[0x8]; 9396 }; 9397 9398 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9399 u8 status[0x8]; 9400 u8 reserved_at_8[0x18]; 9401 9402 u8 syndrome[0x20]; 9403 9404 u8 reserved_at_40[0x40]; 9405 }; 9406 9407 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9408 u8 opcode[0x10]; 9409 u8 reserved_at_10[0x10]; 9410 9411 u8 reserved_at_20[0x10]; 9412 u8 op_mod[0x10]; 9413 9414 u8 reserved_at_40[0x20]; 9415 9416 u8 reserved_at_60[0x10]; 9417 u8 vxlan_udp_port[0x10]; 9418 }; 9419 9420 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9421 u8 status[0x8]; 9422 u8 reserved_at_8[0x18]; 9423 9424 u8 syndrome[0x20]; 9425 9426 u8 reserved_at_40[0x40]; 9427 }; 9428 9429 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9430 u8 rate_limit[0x20]; 9431 9432 u8 burst_upper_bound[0x20]; 9433 9434 u8 reserved_at_40[0x10]; 9435 u8 typical_packet_size[0x10]; 9436 9437 u8 reserved_at_60[0x120]; 9438 }; 9439 9440 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9441 u8 opcode[0x10]; 9442 u8 uid[0x10]; 9443 9444 u8 reserved_at_20[0x10]; 9445 u8 op_mod[0x10]; 9446 9447 u8 reserved_at_40[0x10]; 9448 u8 rate_limit_index[0x10]; 9449 9450 u8 reserved_at_60[0x20]; 9451 9452 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9453 }; 9454 9455 struct mlx5_ifc_access_register_out_bits { 9456 u8 status[0x8]; 9457 u8 reserved_at_8[0x18]; 9458 9459 u8 syndrome[0x20]; 9460 9461 u8 reserved_at_40[0x40]; 9462 9463 u8 register_data[][0x20]; 9464 }; 9465 9466 enum { 9467 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9468 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9469 }; 9470 9471 struct mlx5_ifc_access_register_in_bits { 9472 u8 opcode[0x10]; 9473 u8 reserved_at_10[0x10]; 9474 9475 u8 reserved_at_20[0x10]; 9476 u8 op_mod[0x10]; 9477 9478 u8 reserved_at_40[0x10]; 9479 u8 register_id[0x10]; 9480 9481 u8 argument[0x20]; 9482 9483 u8 register_data[][0x20]; 9484 }; 9485 9486 struct mlx5_ifc_sltp_reg_bits { 9487 u8 status[0x4]; 9488 u8 version[0x4]; 9489 u8 local_port[0x8]; 9490 u8 pnat[0x2]; 9491 u8 reserved_at_12[0x2]; 9492 u8 lane[0x4]; 9493 u8 reserved_at_18[0x8]; 9494 9495 u8 reserved_at_20[0x20]; 9496 9497 u8 reserved_at_40[0x7]; 9498 u8 polarity[0x1]; 9499 u8 ob_tap0[0x8]; 9500 u8 ob_tap1[0x8]; 9501 u8 ob_tap2[0x8]; 9502 9503 u8 reserved_at_60[0xc]; 9504 u8 ob_preemp_mode[0x4]; 9505 u8 ob_reg[0x8]; 9506 u8 ob_bias[0x8]; 9507 9508 u8 reserved_at_80[0x20]; 9509 }; 9510 9511 struct mlx5_ifc_slrg_reg_bits { 9512 u8 status[0x4]; 9513 u8 version[0x4]; 9514 u8 local_port[0x8]; 9515 u8 pnat[0x2]; 9516 u8 reserved_at_12[0x2]; 9517 u8 lane[0x4]; 9518 u8 reserved_at_18[0x8]; 9519 9520 u8 time_to_link_up[0x10]; 9521 u8 reserved_at_30[0xc]; 9522 u8 grade_lane_speed[0x4]; 9523 9524 u8 grade_version[0x8]; 9525 u8 grade[0x18]; 9526 9527 u8 reserved_at_60[0x4]; 9528 u8 height_grade_type[0x4]; 9529 u8 height_grade[0x18]; 9530 9531 u8 height_dz[0x10]; 9532 u8 height_dv[0x10]; 9533 9534 u8 reserved_at_a0[0x10]; 9535 u8 height_sigma[0x10]; 9536 9537 u8 reserved_at_c0[0x20]; 9538 9539 u8 reserved_at_e0[0x4]; 9540 u8 phase_grade_type[0x4]; 9541 u8 phase_grade[0x18]; 9542 9543 u8 reserved_at_100[0x8]; 9544 u8 phase_eo_pos[0x8]; 9545 u8 reserved_at_110[0x8]; 9546 u8 phase_eo_neg[0x8]; 9547 9548 u8 ffe_set_tested[0x10]; 9549 u8 test_errors_per_lane[0x10]; 9550 }; 9551 9552 struct mlx5_ifc_pvlc_reg_bits { 9553 u8 reserved_at_0[0x8]; 9554 u8 local_port[0x8]; 9555 u8 reserved_at_10[0x10]; 9556 9557 u8 reserved_at_20[0x1c]; 9558 u8 vl_hw_cap[0x4]; 9559 9560 u8 reserved_at_40[0x1c]; 9561 u8 vl_admin[0x4]; 9562 9563 u8 reserved_at_60[0x1c]; 9564 u8 vl_operational[0x4]; 9565 }; 9566 9567 struct mlx5_ifc_pude_reg_bits { 9568 u8 swid[0x8]; 9569 u8 local_port[0x8]; 9570 u8 reserved_at_10[0x4]; 9571 u8 admin_status[0x4]; 9572 u8 reserved_at_18[0x4]; 9573 u8 oper_status[0x4]; 9574 9575 u8 reserved_at_20[0x60]; 9576 }; 9577 9578 struct mlx5_ifc_ptys_reg_bits { 9579 u8 reserved_at_0[0x1]; 9580 u8 an_disable_admin[0x1]; 9581 u8 an_disable_cap[0x1]; 9582 u8 reserved_at_3[0x5]; 9583 u8 local_port[0x8]; 9584 u8 reserved_at_10[0xd]; 9585 u8 proto_mask[0x3]; 9586 9587 u8 an_status[0x4]; 9588 u8 reserved_at_24[0xc]; 9589 u8 data_rate_oper[0x10]; 9590 9591 u8 ext_eth_proto_capability[0x20]; 9592 9593 u8 eth_proto_capability[0x20]; 9594 9595 u8 ib_link_width_capability[0x10]; 9596 u8 ib_proto_capability[0x10]; 9597 9598 u8 ext_eth_proto_admin[0x20]; 9599 9600 u8 eth_proto_admin[0x20]; 9601 9602 u8 ib_link_width_admin[0x10]; 9603 u8 ib_proto_admin[0x10]; 9604 9605 u8 ext_eth_proto_oper[0x20]; 9606 9607 u8 eth_proto_oper[0x20]; 9608 9609 u8 ib_link_width_oper[0x10]; 9610 u8 ib_proto_oper[0x10]; 9611 9612 u8 reserved_at_160[0x1c]; 9613 u8 connector_type[0x4]; 9614 9615 u8 eth_proto_lp_advertise[0x20]; 9616 9617 u8 reserved_at_1a0[0x60]; 9618 }; 9619 9620 struct mlx5_ifc_mlcr_reg_bits { 9621 u8 reserved_at_0[0x8]; 9622 u8 local_port[0x8]; 9623 u8 reserved_at_10[0x20]; 9624 9625 u8 beacon_duration[0x10]; 9626 u8 reserved_at_40[0x10]; 9627 9628 u8 beacon_remain[0x10]; 9629 }; 9630 9631 struct mlx5_ifc_ptas_reg_bits { 9632 u8 reserved_at_0[0x20]; 9633 9634 u8 algorithm_options[0x10]; 9635 u8 reserved_at_30[0x4]; 9636 u8 repetitions_mode[0x4]; 9637 u8 num_of_repetitions[0x8]; 9638 9639 u8 grade_version[0x8]; 9640 u8 height_grade_type[0x4]; 9641 u8 phase_grade_type[0x4]; 9642 u8 height_grade_weight[0x8]; 9643 u8 phase_grade_weight[0x8]; 9644 9645 u8 gisim_measure_bits[0x10]; 9646 u8 adaptive_tap_measure_bits[0x10]; 9647 9648 u8 ber_bath_high_error_threshold[0x10]; 9649 u8 ber_bath_mid_error_threshold[0x10]; 9650 9651 u8 ber_bath_low_error_threshold[0x10]; 9652 u8 one_ratio_high_threshold[0x10]; 9653 9654 u8 one_ratio_high_mid_threshold[0x10]; 9655 u8 one_ratio_low_mid_threshold[0x10]; 9656 9657 u8 one_ratio_low_threshold[0x10]; 9658 u8 ndeo_error_threshold[0x10]; 9659 9660 u8 mixer_offset_step_size[0x10]; 9661 u8 reserved_at_110[0x8]; 9662 u8 mix90_phase_for_voltage_bath[0x8]; 9663 9664 u8 mixer_offset_start[0x10]; 9665 u8 mixer_offset_end[0x10]; 9666 9667 u8 reserved_at_140[0x15]; 9668 u8 ber_test_time[0xb]; 9669 }; 9670 9671 struct mlx5_ifc_pspa_reg_bits { 9672 u8 swid[0x8]; 9673 u8 local_port[0x8]; 9674 u8 sub_port[0x8]; 9675 u8 reserved_at_18[0x8]; 9676 9677 u8 reserved_at_20[0x20]; 9678 }; 9679 9680 struct mlx5_ifc_pqdr_reg_bits { 9681 u8 reserved_at_0[0x8]; 9682 u8 local_port[0x8]; 9683 u8 reserved_at_10[0x5]; 9684 u8 prio[0x3]; 9685 u8 reserved_at_18[0x6]; 9686 u8 mode[0x2]; 9687 9688 u8 reserved_at_20[0x20]; 9689 9690 u8 reserved_at_40[0x10]; 9691 u8 min_threshold[0x10]; 9692 9693 u8 reserved_at_60[0x10]; 9694 u8 max_threshold[0x10]; 9695 9696 u8 reserved_at_80[0x10]; 9697 u8 mark_probability_denominator[0x10]; 9698 9699 u8 reserved_at_a0[0x60]; 9700 }; 9701 9702 struct mlx5_ifc_ppsc_reg_bits { 9703 u8 reserved_at_0[0x8]; 9704 u8 local_port[0x8]; 9705 u8 reserved_at_10[0x10]; 9706 9707 u8 reserved_at_20[0x60]; 9708 9709 u8 reserved_at_80[0x1c]; 9710 u8 wrps_admin[0x4]; 9711 9712 u8 reserved_at_a0[0x1c]; 9713 u8 wrps_status[0x4]; 9714 9715 u8 reserved_at_c0[0x8]; 9716 u8 up_threshold[0x8]; 9717 u8 reserved_at_d0[0x8]; 9718 u8 down_threshold[0x8]; 9719 9720 u8 reserved_at_e0[0x20]; 9721 9722 u8 reserved_at_100[0x1c]; 9723 u8 srps_admin[0x4]; 9724 9725 u8 reserved_at_120[0x1c]; 9726 u8 srps_status[0x4]; 9727 9728 u8 reserved_at_140[0x40]; 9729 }; 9730 9731 struct mlx5_ifc_pplr_reg_bits { 9732 u8 reserved_at_0[0x8]; 9733 u8 local_port[0x8]; 9734 u8 reserved_at_10[0x10]; 9735 9736 u8 reserved_at_20[0x8]; 9737 u8 lb_cap[0x8]; 9738 u8 reserved_at_30[0x8]; 9739 u8 lb_en[0x8]; 9740 }; 9741 9742 struct mlx5_ifc_pplm_reg_bits { 9743 u8 reserved_at_0[0x8]; 9744 u8 local_port[0x8]; 9745 u8 reserved_at_10[0x10]; 9746 9747 u8 reserved_at_20[0x20]; 9748 9749 u8 port_profile_mode[0x8]; 9750 u8 static_port_profile[0x8]; 9751 u8 active_port_profile[0x8]; 9752 u8 reserved_at_58[0x8]; 9753 9754 u8 retransmission_active[0x8]; 9755 u8 fec_mode_active[0x18]; 9756 9757 u8 rs_fec_correction_bypass_cap[0x4]; 9758 u8 reserved_at_84[0x8]; 9759 u8 fec_override_cap_56g[0x4]; 9760 u8 fec_override_cap_100g[0x4]; 9761 u8 fec_override_cap_50g[0x4]; 9762 u8 fec_override_cap_25g[0x4]; 9763 u8 fec_override_cap_10g_40g[0x4]; 9764 9765 u8 rs_fec_correction_bypass_admin[0x4]; 9766 u8 reserved_at_a4[0x8]; 9767 u8 fec_override_admin_56g[0x4]; 9768 u8 fec_override_admin_100g[0x4]; 9769 u8 fec_override_admin_50g[0x4]; 9770 u8 fec_override_admin_25g[0x4]; 9771 u8 fec_override_admin_10g_40g[0x4]; 9772 9773 u8 fec_override_cap_400g_8x[0x10]; 9774 u8 fec_override_cap_200g_4x[0x10]; 9775 9776 u8 fec_override_cap_100g_2x[0x10]; 9777 u8 fec_override_cap_50g_1x[0x10]; 9778 9779 u8 fec_override_admin_400g_8x[0x10]; 9780 u8 fec_override_admin_200g_4x[0x10]; 9781 9782 u8 fec_override_admin_100g_2x[0x10]; 9783 u8 fec_override_admin_50g_1x[0x10]; 9784 9785 u8 reserved_at_140[0x140]; 9786 }; 9787 9788 struct mlx5_ifc_ppcnt_reg_bits { 9789 u8 swid[0x8]; 9790 u8 local_port[0x8]; 9791 u8 pnat[0x2]; 9792 u8 reserved_at_12[0x8]; 9793 u8 grp[0x6]; 9794 9795 u8 clr[0x1]; 9796 u8 reserved_at_21[0x1c]; 9797 u8 prio_tc[0x3]; 9798 9799 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9800 }; 9801 9802 struct mlx5_ifc_mpein_reg_bits { 9803 u8 reserved_at_0[0x2]; 9804 u8 depth[0x6]; 9805 u8 pcie_index[0x8]; 9806 u8 node[0x8]; 9807 u8 reserved_at_18[0x8]; 9808 9809 u8 capability_mask[0x20]; 9810 9811 u8 reserved_at_40[0x8]; 9812 u8 link_width_enabled[0x8]; 9813 u8 link_speed_enabled[0x10]; 9814 9815 u8 lane0_physical_position[0x8]; 9816 u8 link_width_active[0x8]; 9817 u8 link_speed_active[0x10]; 9818 9819 u8 num_of_pfs[0x10]; 9820 u8 num_of_vfs[0x10]; 9821 9822 u8 bdf0[0x10]; 9823 u8 reserved_at_b0[0x10]; 9824 9825 u8 max_read_request_size[0x4]; 9826 u8 max_payload_size[0x4]; 9827 u8 reserved_at_c8[0x5]; 9828 u8 pwr_status[0x3]; 9829 u8 port_type[0x4]; 9830 u8 reserved_at_d4[0xb]; 9831 u8 lane_reversal[0x1]; 9832 9833 u8 reserved_at_e0[0x14]; 9834 u8 pci_power[0xc]; 9835 9836 u8 reserved_at_100[0x20]; 9837 9838 u8 device_status[0x10]; 9839 u8 port_state[0x8]; 9840 u8 reserved_at_138[0x8]; 9841 9842 u8 reserved_at_140[0x10]; 9843 u8 receiver_detect_result[0x10]; 9844 9845 u8 reserved_at_160[0x20]; 9846 }; 9847 9848 struct mlx5_ifc_mpcnt_reg_bits { 9849 u8 reserved_at_0[0x8]; 9850 u8 pcie_index[0x8]; 9851 u8 reserved_at_10[0xa]; 9852 u8 grp[0x6]; 9853 9854 u8 clr[0x1]; 9855 u8 reserved_at_21[0x1f]; 9856 9857 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9858 }; 9859 9860 struct mlx5_ifc_ppad_reg_bits { 9861 u8 reserved_at_0[0x3]; 9862 u8 single_mac[0x1]; 9863 u8 reserved_at_4[0x4]; 9864 u8 local_port[0x8]; 9865 u8 mac_47_32[0x10]; 9866 9867 u8 mac_31_0[0x20]; 9868 9869 u8 reserved_at_40[0x40]; 9870 }; 9871 9872 struct mlx5_ifc_pmtu_reg_bits { 9873 u8 reserved_at_0[0x8]; 9874 u8 local_port[0x8]; 9875 u8 reserved_at_10[0x10]; 9876 9877 u8 max_mtu[0x10]; 9878 u8 reserved_at_30[0x10]; 9879 9880 u8 admin_mtu[0x10]; 9881 u8 reserved_at_50[0x10]; 9882 9883 u8 oper_mtu[0x10]; 9884 u8 reserved_at_70[0x10]; 9885 }; 9886 9887 struct mlx5_ifc_pmpr_reg_bits { 9888 u8 reserved_at_0[0x8]; 9889 u8 module[0x8]; 9890 u8 reserved_at_10[0x10]; 9891 9892 u8 reserved_at_20[0x18]; 9893 u8 attenuation_5g[0x8]; 9894 9895 u8 reserved_at_40[0x18]; 9896 u8 attenuation_7g[0x8]; 9897 9898 u8 reserved_at_60[0x18]; 9899 u8 attenuation_12g[0x8]; 9900 }; 9901 9902 struct mlx5_ifc_pmpe_reg_bits { 9903 u8 reserved_at_0[0x8]; 9904 u8 module[0x8]; 9905 u8 reserved_at_10[0xc]; 9906 u8 module_status[0x4]; 9907 9908 u8 reserved_at_20[0x60]; 9909 }; 9910 9911 struct mlx5_ifc_pmpc_reg_bits { 9912 u8 module_state_updated[32][0x8]; 9913 }; 9914 9915 struct mlx5_ifc_pmlpn_reg_bits { 9916 u8 reserved_at_0[0x4]; 9917 u8 mlpn_status[0x4]; 9918 u8 local_port[0x8]; 9919 u8 reserved_at_10[0x10]; 9920 9921 u8 e[0x1]; 9922 u8 reserved_at_21[0x1f]; 9923 }; 9924 9925 struct mlx5_ifc_pmlp_reg_bits { 9926 u8 rxtx[0x1]; 9927 u8 reserved_at_1[0x7]; 9928 u8 local_port[0x8]; 9929 u8 reserved_at_10[0x8]; 9930 u8 width[0x8]; 9931 9932 u8 lane0_module_mapping[0x20]; 9933 9934 u8 lane1_module_mapping[0x20]; 9935 9936 u8 lane2_module_mapping[0x20]; 9937 9938 u8 lane3_module_mapping[0x20]; 9939 9940 u8 reserved_at_a0[0x160]; 9941 }; 9942 9943 struct mlx5_ifc_pmaos_reg_bits { 9944 u8 reserved_at_0[0x8]; 9945 u8 module[0x8]; 9946 u8 reserved_at_10[0x4]; 9947 u8 admin_status[0x4]; 9948 u8 reserved_at_18[0x4]; 9949 u8 oper_status[0x4]; 9950 9951 u8 ase[0x1]; 9952 u8 ee[0x1]; 9953 u8 reserved_at_22[0x1c]; 9954 u8 e[0x2]; 9955 9956 u8 reserved_at_40[0x40]; 9957 }; 9958 9959 struct mlx5_ifc_plpc_reg_bits { 9960 u8 reserved_at_0[0x4]; 9961 u8 profile_id[0xc]; 9962 u8 reserved_at_10[0x4]; 9963 u8 proto_mask[0x4]; 9964 u8 reserved_at_18[0x8]; 9965 9966 u8 reserved_at_20[0x10]; 9967 u8 lane_speed[0x10]; 9968 9969 u8 reserved_at_40[0x17]; 9970 u8 lpbf[0x1]; 9971 u8 fec_mode_policy[0x8]; 9972 9973 u8 retransmission_capability[0x8]; 9974 u8 fec_mode_capability[0x18]; 9975 9976 u8 retransmission_support_admin[0x8]; 9977 u8 fec_mode_support_admin[0x18]; 9978 9979 u8 retransmission_request_admin[0x8]; 9980 u8 fec_mode_request_admin[0x18]; 9981 9982 u8 reserved_at_c0[0x80]; 9983 }; 9984 9985 struct mlx5_ifc_plib_reg_bits { 9986 u8 reserved_at_0[0x8]; 9987 u8 local_port[0x8]; 9988 u8 reserved_at_10[0x8]; 9989 u8 ib_port[0x8]; 9990 9991 u8 reserved_at_20[0x60]; 9992 }; 9993 9994 struct mlx5_ifc_plbf_reg_bits { 9995 u8 reserved_at_0[0x8]; 9996 u8 local_port[0x8]; 9997 u8 reserved_at_10[0xd]; 9998 u8 lbf_mode[0x3]; 9999 10000 u8 reserved_at_20[0x20]; 10001 }; 10002 10003 struct mlx5_ifc_pipg_reg_bits { 10004 u8 reserved_at_0[0x8]; 10005 u8 local_port[0x8]; 10006 u8 reserved_at_10[0x10]; 10007 10008 u8 dic[0x1]; 10009 u8 reserved_at_21[0x19]; 10010 u8 ipg[0x4]; 10011 u8 reserved_at_3e[0x2]; 10012 }; 10013 10014 struct mlx5_ifc_pifr_reg_bits { 10015 u8 reserved_at_0[0x8]; 10016 u8 local_port[0x8]; 10017 u8 reserved_at_10[0x10]; 10018 10019 u8 reserved_at_20[0xe0]; 10020 10021 u8 port_filter[8][0x20]; 10022 10023 u8 port_filter_update_en[8][0x20]; 10024 }; 10025 10026 struct mlx5_ifc_pfcc_reg_bits { 10027 u8 reserved_at_0[0x8]; 10028 u8 local_port[0x8]; 10029 u8 reserved_at_10[0xb]; 10030 u8 ppan_mask_n[0x1]; 10031 u8 minor_stall_mask[0x1]; 10032 u8 critical_stall_mask[0x1]; 10033 u8 reserved_at_1e[0x2]; 10034 10035 u8 ppan[0x4]; 10036 u8 reserved_at_24[0x4]; 10037 u8 prio_mask_tx[0x8]; 10038 u8 reserved_at_30[0x8]; 10039 u8 prio_mask_rx[0x8]; 10040 10041 u8 pptx[0x1]; 10042 u8 aptx[0x1]; 10043 u8 pptx_mask_n[0x1]; 10044 u8 reserved_at_43[0x5]; 10045 u8 pfctx[0x8]; 10046 u8 reserved_at_50[0x10]; 10047 10048 u8 pprx[0x1]; 10049 u8 aprx[0x1]; 10050 u8 pprx_mask_n[0x1]; 10051 u8 reserved_at_63[0x5]; 10052 u8 pfcrx[0x8]; 10053 u8 reserved_at_70[0x10]; 10054 10055 u8 device_stall_minor_watermark[0x10]; 10056 u8 device_stall_critical_watermark[0x10]; 10057 10058 u8 reserved_at_a0[0x60]; 10059 }; 10060 10061 struct mlx5_ifc_pelc_reg_bits { 10062 u8 op[0x4]; 10063 u8 reserved_at_4[0x4]; 10064 u8 local_port[0x8]; 10065 u8 reserved_at_10[0x10]; 10066 10067 u8 op_admin[0x8]; 10068 u8 op_capability[0x8]; 10069 u8 op_request[0x8]; 10070 u8 op_active[0x8]; 10071 10072 u8 admin[0x40]; 10073 10074 u8 capability[0x40]; 10075 10076 u8 request[0x40]; 10077 10078 u8 active[0x40]; 10079 10080 u8 reserved_at_140[0x80]; 10081 }; 10082 10083 struct mlx5_ifc_peir_reg_bits { 10084 u8 reserved_at_0[0x8]; 10085 u8 local_port[0x8]; 10086 u8 reserved_at_10[0x10]; 10087 10088 u8 reserved_at_20[0xc]; 10089 u8 error_count[0x4]; 10090 u8 reserved_at_30[0x10]; 10091 10092 u8 reserved_at_40[0xc]; 10093 u8 lane[0x4]; 10094 u8 reserved_at_50[0x8]; 10095 u8 error_type[0x8]; 10096 }; 10097 10098 struct mlx5_ifc_mpegc_reg_bits { 10099 u8 reserved_at_0[0x30]; 10100 u8 field_select[0x10]; 10101 10102 u8 tx_overflow_sense[0x1]; 10103 u8 mark_cqe[0x1]; 10104 u8 mark_cnp[0x1]; 10105 u8 reserved_at_43[0x1b]; 10106 u8 tx_lossy_overflow_oper[0x2]; 10107 10108 u8 reserved_at_60[0x100]; 10109 }; 10110 10111 struct mlx5_ifc_mpir_reg_bits { 10112 u8 sdm[0x1]; 10113 u8 reserved_at_1[0x1b]; 10114 u8 host_buses[0x4]; 10115 10116 u8 reserved_at_20[0x20]; 10117 10118 u8 local_port[0x8]; 10119 u8 reserved_at_28[0x15]; 10120 u8 sd_group[0x3]; 10121 10122 u8 reserved_at_60[0x20]; 10123 }; 10124 10125 enum { 10126 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10127 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10128 }; 10129 10130 enum { 10131 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10132 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10133 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10134 }; 10135 10136 struct mlx5_ifc_mtutc_reg_bits { 10137 u8 reserved_at_0[0x5]; 10138 u8 freq_adj_units[0x3]; 10139 u8 reserved_at_8[0x3]; 10140 u8 log_max_freq_adjustment[0x5]; 10141 10142 u8 reserved_at_10[0xc]; 10143 u8 operation[0x4]; 10144 10145 u8 freq_adjustment[0x20]; 10146 10147 u8 reserved_at_40[0x40]; 10148 10149 u8 utc_sec[0x20]; 10150 10151 u8 reserved_at_a0[0x2]; 10152 u8 utc_nsec[0x1e]; 10153 10154 u8 time_adjustment[0x20]; 10155 }; 10156 10157 struct mlx5_ifc_pcam_enhanced_features_bits { 10158 u8 reserved_at_0[0x68]; 10159 u8 fec_50G_per_lane_in_pplm[0x1]; 10160 u8 reserved_at_69[0x4]; 10161 u8 rx_icrc_encapsulated_counter[0x1]; 10162 u8 reserved_at_6e[0x4]; 10163 u8 ptys_extended_ethernet[0x1]; 10164 u8 reserved_at_73[0x3]; 10165 u8 pfcc_mask[0x1]; 10166 u8 reserved_at_77[0x3]; 10167 u8 per_lane_error_counters[0x1]; 10168 u8 rx_buffer_fullness_counters[0x1]; 10169 u8 ptys_connector_type[0x1]; 10170 u8 reserved_at_7d[0x1]; 10171 u8 ppcnt_discard_group[0x1]; 10172 u8 ppcnt_statistical_group[0x1]; 10173 }; 10174 10175 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10176 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10177 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10178 10179 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10180 u8 pplm[0x1]; 10181 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10182 10183 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10184 u8 pbmc[0x1]; 10185 u8 pptb[0x1]; 10186 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10187 u8 ppcnt[0x1]; 10188 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10189 }; 10190 10191 struct mlx5_ifc_pcam_reg_bits { 10192 u8 reserved_at_0[0x8]; 10193 u8 feature_group[0x8]; 10194 u8 reserved_at_10[0x8]; 10195 u8 access_reg_group[0x8]; 10196 10197 u8 reserved_at_20[0x20]; 10198 10199 union { 10200 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10201 u8 reserved_at_0[0x80]; 10202 } port_access_reg_cap_mask; 10203 10204 u8 reserved_at_c0[0x80]; 10205 10206 union { 10207 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10208 u8 reserved_at_0[0x80]; 10209 } feature_cap_mask; 10210 10211 u8 reserved_at_1c0[0xc0]; 10212 }; 10213 10214 struct mlx5_ifc_mcam_enhanced_features_bits { 10215 u8 reserved_at_0[0x50]; 10216 u8 mtutc_freq_adj_units[0x1]; 10217 u8 mtutc_time_adjustment_extended_range[0x1]; 10218 u8 reserved_at_52[0xb]; 10219 u8 mcia_32dwords[0x1]; 10220 u8 out_pulse_duration_ns[0x1]; 10221 u8 npps_period[0x1]; 10222 u8 reserved_at_60[0xa]; 10223 u8 reset_state[0x1]; 10224 u8 ptpcyc2realtime_modify[0x1]; 10225 u8 reserved_at_6c[0x2]; 10226 u8 pci_status_and_power[0x1]; 10227 u8 reserved_at_6f[0x5]; 10228 u8 mark_tx_action_cnp[0x1]; 10229 u8 mark_tx_action_cqe[0x1]; 10230 u8 dynamic_tx_overflow[0x1]; 10231 u8 reserved_at_77[0x4]; 10232 u8 pcie_outbound_stalled[0x1]; 10233 u8 tx_overflow_buffer_pkt[0x1]; 10234 u8 mtpps_enh_out_per_adj[0x1]; 10235 u8 mtpps_fs[0x1]; 10236 u8 pcie_performance_group[0x1]; 10237 }; 10238 10239 struct mlx5_ifc_mcam_access_reg_bits { 10240 u8 reserved_at_0[0x1c]; 10241 u8 mcda[0x1]; 10242 u8 mcc[0x1]; 10243 u8 mcqi[0x1]; 10244 u8 mcqs[0x1]; 10245 10246 u8 regs_95_to_87[0x9]; 10247 u8 mpegc[0x1]; 10248 u8 mtutc[0x1]; 10249 u8 regs_84_to_68[0x11]; 10250 u8 tracer_registers[0x4]; 10251 10252 u8 regs_63_to_46[0x12]; 10253 u8 mrtc[0x1]; 10254 u8 regs_44_to_32[0xd]; 10255 10256 u8 regs_31_to_10[0x16]; 10257 u8 mtmp[0x1]; 10258 u8 regs_8_to_0[0x9]; 10259 }; 10260 10261 struct mlx5_ifc_mcam_access_reg_bits1 { 10262 u8 regs_127_to_96[0x20]; 10263 10264 u8 regs_95_to_64[0x20]; 10265 10266 u8 regs_63_to_32[0x20]; 10267 10268 u8 regs_31_to_0[0x20]; 10269 }; 10270 10271 struct mlx5_ifc_mcam_access_reg_bits2 { 10272 u8 regs_127_to_99[0x1d]; 10273 u8 mirc[0x1]; 10274 u8 regs_97_to_96[0x2]; 10275 10276 u8 regs_95_to_87[0x09]; 10277 u8 synce_registers[0x2]; 10278 u8 regs_84_to_64[0x15]; 10279 10280 u8 regs_63_to_32[0x20]; 10281 10282 u8 regs_31_to_0[0x20]; 10283 }; 10284 10285 struct mlx5_ifc_mcam_reg_bits { 10286 u8 reserved_at_0[0x8]; 10287 u8 feature_group[0x8]; 10288 u8 reserved_at_10[0x8]; 10289 u8 access_reg_group[0x8]; 10290 10291 u8 reserved_at_20[0x20]; 10292 10293 union { 10294 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10295 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10296 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10297 u8 reserved_at_0[0x80]; 10298 } mng_access_reg_cap_mask; 10299 10300 u8 reserved_at_c0[0x80]; 10301 10302 union { 10303 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10304 u8 reserved_at_0[0x80]; 10305 } mng_feature_cap_mask; 10306 10307 u8 reserved_at_1c0[0x80]; 10308 }; 10309 10310 struct mlx5_ifc_qcam_access_reg_cap_mask { 10311 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10312 u8 qpdpm[0x1]; 10313 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10314 u8 qdpm[0x1]; 10315 u8 qpts[0x1]; 10316 u8 qcap[0x1]; 10317 u8 qcam_access_reg_cap_mask_0[0x1]; 10318 }; 10319 10320 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10321 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10322 u8 qpts_trust_both[0x1]; 10323 }; 10324 10325 struct mlx5_ifc_qcam_reg_bits { 10326 u8 reserved_at_0[0x8]; 10327 u8 feature_group[0x8]; 10328 u8 reserved_at_10[0x8]; 10329 u8 access_reg_group[0x8]; 10330 u8 reserved_at_20[0x20]; 10331 10332 union { 10333 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10334 u8 reserved_at_0[0x80]; 10335 } qos_access_reg_cap_mask; 10336 10337 u8 reserved_at_c0[0x80]; 10338 10339 union { 10340 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10341 u8 reserved_at_0[0x80]; 10342 } qos_feature_cap_mask; 10343 10344 u8 reserved_at_1c0[0x80]; 10345 }; 10346 10347 struct mlx5_ifc_core_dump_reg_bits { 10348 u8 reserved_at_0[0x18]; 10349 u8 core_dump_type[0x8]; 10350 10351 u8 reserved_at_20[0x30]; 10352 u8 vhca_id[0x10]; 10353 10354 u8 reserved_at_60[0x8]; 10355 u8 qpn[0x18]; 10356 u8 reserved_at_80[0x180]; 10357 }; 10358 10359 struct mlx5_ifc_pcap_reg_bits { 10360 u8 reserved_at_0[0x8]; 10361 u8 local_port[0x8]; 10362 u8 reserved_at_10[0x10]; 10363 10364 u8 port_capability_mask[4][0x20]; 10365 }; 10366 10367 struct mlx5_ifc_paos_reg_bits { 10368 u8 swid[0x8]; 10369 u8 local_port[0x8]; 10370 u8 reserved_at_10[0x4]; 10371 u8 admin_status[0x4]; 10372 u8 reserved_at_18[0x4]; 10373 u8 oper_status[0x4]; 10374 10375 u8 ase[0x1]; 10376 u8 ee[0x1]; 10377 u8 reserved_at_22[0x1c]; 10378 u8 e[0x2]; 10379 10380 u8 reserved_at_40[0x40]; 10381 }; 10382 10383 struct mlx5_ifc_pamp_reg_bits { 10384 u8 reserved_at_0[0x8]; 10385 u8 opamp_group[0x8]; 10386 u8 reserved_at_10[0xc]; 10387 u8 opamp_group_type[0x4]; 10388 10389 u8 start_index[0x10]; 10390 u8 reserved_at_30[0x4]; 10391 u8 num_of_indices[0xc]; 10392 10393 u8 index_data[18][0x10]; 10394 }; 10395 10396 struct mlx5_ifc_pcmr_reg_bits { 10397 u8 reserved_at_0[0x8]; 10398 u8 local_port[0x8]; 10399 u8 reserved_at_10[0x10]; 10400 10401 u8 entropy_force_cap[0x1]; 10402 u8 entropy_calc_cap[0x1]; 10403 u8 entropy_gre_calc_cap[0x1]; 10404 u8 reserved_at_23[0xf]; 10405 u8 rx_ts_over_crc_cap[0x1]; 10406 u8 reserved_at_33[0xb]; 10407 u8 fcs_cap[0x1]; 10408 u8 reserved_at_3f[0x1]; 10409 10410 u8 entropy_force[0x1]; 10411 u8 entropy_calc[0x1]; 10412 u8 entropy_gre_calc[0x1]; 10413 u8 reserved_at_43[0xf]; 10414 u8 rx_ts_over_crc[0x1]; 10415 u8 reserved_at_53[0xb]; 10416 u8 fcs_chk[0x1]; 10417 u8 reserved_at_5f[0x1]; 10418 }; 10419 10420 struct mlx5_ifc_lane_2_module_mapping_bits { 10421 u8 reserved_at_0[0x4]; 10422 u8 rx_lane[0x4]; 10423 u8 reserved_at_8[0x4]; 10424 u8 tx_lane[0x4]; 10425 u8 reserved_at_10[0x8]; 10426 u8 module[0x8]; 10427 }; 10428 10429 struct mlx5_ifc_bufferx_reg_bits { 10430 u8 reserved_at_0[0x6]; 10431 u8 lossy[0x1]; 10432 u8 epsb[0x1]; 10433 u8 reserved_at_8[0x8]; 10434 u8 size[0x10]; 10435 10436 u8 xoff_threshold[0x10]; 10437 u8 xon_threshold[0x10]; 10438 }; 10439 10440 struct mlx5_ifc_set_node_in_bits { 10441 u8 node_description[64][0x8]; 10442 }; 10443 10444 struct mlx5_ifc_register_power_settings_bits { 10445 u8 reserved_at_0[0x18]; 10446 u8 power_settings_level[0x8]; 10447 10448 u8 reserved_at_20[0x60]; 10449 }; 10450 10451 struct mlx5_ifc_register_host_endianness_bits { 10452 u8 he[0x1]; 10453 u8 reserved_at_1[0x1f]; 10454 10455 u8 reserved_at_20[0x60]; 10456 }; 10457 10458 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10459 u8 reserved_at_0[0x20]; 10460 10461 u8 mkey[0x20]; 10462 10463 u8 addressh_63_32[0x20]; 10464 10465 u8 addressl_31_0[0x20]; 10466 }; 10467 10468 struct mlx5_ifc_ud_adrs_vector_bits { 10469 u8 dc_key[0x40]; 10470 10471 u8 ext[0x1]; 10472 u8 reserved_at_41[0x7]; 10473 u8 destination_qp_dct[0x18]; 10474 10475 u8 static_rate[0x4]; 10476 u8 sl_eth_prio[0x4]; 10477 u8 fl[0x1]; 10478 u8 mlid[0x7]; 10479 u8 rlid_udp_sport[0x10]; 10480 10481 u8 reserved_at_80[0x20]; 10482 10483 u8 rmac_47_16[0x20]; 10484 10485 u8 rmac_15_0[0x10]; 10486 u8 tclass[0x8]; 10487 u8 hop_limit[0x8]; 10488 10489 u8 reserved_at_e0[0x1]; 10490 u8 grh[0x1]; 10491 u8 reserved_at_e2[0x2]; 10492 u8 src_addr_index[0x8]; 10493 u8 flow_label[0x14]; 10494 10495 u8 rgid_rip[16][0x8]; 10496 }; 10497 10498 struct mlx5_ifc_pages_req_event_bits { 10499 u8 reserved_at_0[0x10]; 10500 u8 function_id[0x10]; 10501 10502 u8 num_pages[0x20]; 10503 10504 u8 reserved_at_40[0xa0]; 10505 }; 10506 10507 struct mlx5_ifc_eqe_bits { 10508 u8 reserved_at_0[0x8]; 10509 u8 event_type[0x8]; 10510 u8 reserved_at_10[0x8]; 10511 u8 event_sub_type[0x8]; 10512 10513 u8 reserved_at_20[0xe0]; 10514 10515 union mlx5_ifc_event_auto_bits event_data; 10516 10517 u8 reserved_at_1e0[0x10]; 10518 u8 signature[0x8]; 10519 u8 reserved_at_1f8[0x7]; 10520 u8 owner[0x1]; 10521 }; 10522 10523 enum { 10524 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10525 }; 10526 10527 struct mlx5_ifc_cmd_queue_entry_bits { 10528 u8 type[0x8]; 10529 u8 reserved_at_8[0x18]; 10530 10531 u8 input_length[0x20]; 10532 10533 u8 input_mailbox_pointer_63_32[0x20]; 10534 10535 u8 input_mailbox_pointer_31_9[0x17]; 10536 u8 reserved_at_77[0x9]; 10537 10538 u8 command_input_inline_data[16][0x8]; 10539 10540 u8 command_output_inline_data[16][0x8]; 10541 10542 u8 output_mailbox_pointer_63_32[0x20]; 10543 10544 u8 output_mailbox_pointer_31_9[0x17]; 10545 u8 reserved_at_1b7[0x9]; 10546 10547 u8 output_length[0x20]; 10548 10549 u8 token[0x8]; 10550 u8 signature[0x8]; 10551 u8 reserved_at_1f0[0x8]; 10552 u8 status[0x7]; 10553 u8 ownership[0x1]; 10554 }; 10555 10556 struct mlx5_ifc_cmd_out_bits { 10557 u8 status[0x8]; 10558 u8 reserved_at_8[0x18]; 10559 10560 u8 syndrome[0x20]; 10561 10562 u8 command_output[0x20]; 10563 }; 10564 10565 struct mlx5_ifc_cmd_in_bits { 10566 u8 opcode[0x10]; 10567 u8 reserved_at_10[0x10]; 10568 10569 u8 reserved_at_20[0x10]; 10570 u8 op_mod[0x10]; 10571 10572 u8 command[][0x20]; 10573 }; 10574 10575 struct mlx5_ifc_cmd_if_box_bits { 10576 u8 mailbox_data[512][0x8]; 10577 10578 u8 reserved_at_1000[0x180]; 10579 10580 u8 next_pointer_63_32[0x20]; 10581 10582 u8 next_pointer_31_10[0x16]; 10583 u8 reserved_at_11b6[0xa]; 10584 10585 u8 block_number[0x20]; 10586 10587 u8 reserved_at_11e0[0x8]; 10588 u8 token[0x8]; 10589 u8 ctrl_signature[0x8]; 10590 u8 signature[0x8]; 10591 }; 10592 10593 struct mlx5_ifc_mtt_bits { 10594 u8 ptag_63_32[0x20]; 10595 10596 u8 ptag_31_8[0x18]; 10597 u8 reserved_at_38[0x6]; 10598 u8 wr_en[0x1]; 10599 u8 rd_en[0x1]; 10600 }; 10601 10602 struct mlx5_ifc_query_wol_rol_out_bits { 10603 u8 status[0x8]; 10604 u8 reserved_at_8[0x18]; 10605 10606 u8 syndrome[0x20]; 10607 10608 u8 reserved_at_40[0x10]; 10609 u8 rol_mode[0x8]; 10610 u8 wol_mode[0x8]; 10611 10612 u8 reserved_at_60[0x20]; 10613 }; 10614 10615 struct mlx5_ifc_query_wol_rol_in_bits { 10616 u8 opcode[0x10]; 10617 u8 reserved_at_10[0x10]; 10618 10619 u8 reserved_at_20[0x10]; 10620 u8 op_mod[0x10]; 10621 10622 u8 reserved_at_40[0x40]; 10623 }; 10624 10625 struct mlx5_ifc_set_wol_rol_out_bits { 10626 u8 status[0x8]; 10627 u8 reserved_at_8[0x18]; 10628 10629 u8 syndrome[0x20]; 10630 10631 u8 reserved_at_40[0x40]; 10632 }; 10633 10634 struct mlx5_ifc_set_wol_rol_in_bits { 10635 u8 opcode[0x10]; 10636 u8 reserved_at_10[0x10]; 10637 10638 u8 reserved_at_20[0x10]; 10639 u8 op_mod[0x10]; 10640 10641 u8 rol_mode_valid[0x1]; 10642 u8 wol_mode_valid[0x1]; 10643 u8 reserved_at_42[0xe]; 10644 u8 rol_mode[0x8]; 10645 u8 wol_mode[0x8]; 10646 10647 u8 reserved_at_60[0x20]; 10648 }; 10649 10650 enum { 10651 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10652 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10653 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10654 }; 10655 10656 enum { 10657 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10658 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10659 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10660 }; 10661 10662 enum { 10663 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10664 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10665 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10666 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10667 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10668 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10669 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10670 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10671 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10672 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10673 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10674 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 10675 }; 10676 10677 struct mlx5_ifc_initial_seg_bits { 10678 u8 fw_rev_minor[0x10]; 10679 u8 fw_rev_major[0x10]; 10680 10681 u8 cmd_interface_rev[0x10]; 10682 u8 fw_rev_subminor[0x10]; 10683 10684 u8 reserved_at_40[0x40]; 10685 10686 u8 cmdq_phy_addr_63_32[0x20]; 10687 10688 u8 cmdq_phy_addr_31_12[0x14]; 10689 u8 reserved_at_b4[0x2]; 10690 u8 nic_interface[0x2]; 10691 u8 log_cmdq_size[0x4]; 10692 u8 log_cmdq_stride[0x4]; 10693 10694 u8 command_doorbell_vector[0x20]; 10695 10696 u8 reserved_at_e0[0xf00]; 10697 10698 u8 initializing[0x1]; 10699 u8 reserved_at_fe1[0x4]; 10700 u8 nic_interface_supported[0x3]; 10701 u8 embedded_cpu[0x1]; 10702 u8 reserved_at_fe9[0x17]; 10703 10704 struct mlx5_ifc_health_buffer_bits health_buffer; 10705 10706 u8 no_dram_nic_offset[0x20]; 10707 10708 u8 reserved_at_1220[0x6e40]; 10709 10710 u8 reserved_at_8060[0x1f]; 10711 u8 clear_int[0x1]; 10712 10713 u8 health_syndrome[0x8]; 10714 u8 health_counter[0x18]; 10715 10716 u8 reserved_at_80a0[0x17fc0]; 10717 }; 10718 10719 struct mlx5_ifc_mtpps_reg_bits { 10720 u8 reserved_at_0[0xc]; 10721 u8 cap_number_of_pps_pins[0x4]; 10722 u8 reserved_at_10[0x4]; 10723 u8 cap_max_num_of_pps_in_pins[0x4]; 10724 u8 reserved_at_18[0x4]; 10725 u8 cap_max_num_of_pps_out_pins[0x4]; 10726 10727 u8 reserved_at_20[0x13]; 10728 u8 cap_log_min_npps_period[0x5]; 10729 u8 reserved_at_38[0x3]; 10730 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10731 10732 u8 reserved_at_40[0x4]; 10733 u8 cap_pin_3_mode[0x4]; 10734 u8 reserved_at_48[0x4]; 10735 u8 cap_pin_2_mode[0x4]; 10736 u8 reserved_at_50[0x4]; 10737 u8 cap_pin_1_mode[0x4]; 10738 u8 reserved_at_58[0x4]; 10739 u8 cap_pin_0_mode[0x4]; 10740 10741 u8 reserved_at_60[0x4]; 10742 u8 cap_pin_7_mode[0x4]; 10743 u8 reserved_at_68[0x4]; 10744 u8 cap_pin_6_mode[0x4]; 10745 u8 reserved_at_70[0x4]; 10746 u8 cap_pin_5_mode[0x4]; 10747 u8 reserved_at_78[0x4]; 10748 u8 cap_pin_4_mode[0x4]; 10749 10750 u8 field_select[0x20]; 10751 u8 reserved_at_a0[0x20]; 10752 10753 u8 npps_period[0x40]; 10754 10755 u8 enable[0x1]; 10756 u8 reserved_at_101[0xb]; 10757 u8 pattern[0x4]; 10758 u8 reserved_at_110[0x4]; 10759 u8 pin_mode[0x4]; 10760 u8 pin[0x8]; 10761 10762 u8 reserved_at_120[0x2]; 10763 u8 out_pulse_duration_ns[0x1e]; 10764 10765 u8 time_stamp[0x40]; 10766 10767 u8 out_pulse_duration[0x10]; 10768 u8 out_periodic_adjustment[0x10]; 10769 u8 enhanced_out_periodic_adjustment[0x20]; 10770 10771 u8 reserved_at_1c0[0x20]; 10772 }; 10773 10774 struct mlx5_ifc_mtppse_reg_bits { 10775 u8 reserved_at_0[0x18]; 10776 u8 pin[0x8]; 10777 u8 event_arm[0x1]; 10778 u8 reserved_at_21[0x1b]; 10779 u8 event_generation_mode[0x4]; 10780 u8 reserved_at_40[0x40]; 10781 }; 10782 10783 struct mlx5_ifc_mcqs_reg_bits { 10784 u8 last_index_flag[0x1]; 10785 u8 reserved_at_1[0x7]; 10786 u8 fw_device[0x8]; 10787 u8 component_index[0x10]; 10788 10789 u8 reserved_at_20[0x10]; 10790 u8 identifier[0x10]; 10791 10792 u8 reserved_at_40[0x17]; 10793 u8 component_status[0x5]; 10794 u8 component_update_state[0x4]; 10795 10796 u8 last_update_state_changer_type[0x4]; 10797 u8 last_update_state_changer_host_id[0x4]; 10798 u8 reserved_at_68[0x18]; 10799 }; 10800 10801 struct mlx5_ifc_mcqi_cap_bits { 10802 u8 supported_info_bitmask[0x20]; 10803 10804 u8 component_size[0x20]; 10805 10806 u8 max_component_size[0x20]; 10807 10808 u8 log_mcda_word_size[0x4]; 10809 u8 reserved_at_64[0xc]; 10810 u8 mcda_max_write_size[0x10]; 10811 10812 u8 rd_en[0x1]; 10813 u8 reserved_at_81[0x1]; 10814 u8 match_chip_id[0x1]; 10815 u8 match_psid[0x1]; 10816 u8 check_user_timestamp[0x1]; 10817 u8 match_base_guid_mac[0x1]; 10818 u8 reserved_at_86[0x1a]; 10819 }; 10820 10821 struct mlx5_ifc_mcqi_version_bits { 10822 u8 reserved_at_0[0x2]; 10823 u8 build_time_valid[0x1]; 10824 u8 user_defined_time_valid[0x1]; 10825 u8 reserved_at_4[0x14]; 10826 u8 version_string_length[0x8]; 10827 10828 u8 version[0x20]; 10829 10830 u8 build_time[0x40]; 10831 10832 u8 user_defined_time[0x40]; 10833 10834 u8 build_tool_version[0x20]; 10835 10836 u8 reserved_at_e0[0x20]; 10837 10838 u8 version_string[92][0x8]; 10839 }; 10840 10841 struct mlx5_ifc_mcqi_activation_method_bits { 10842 u8 pending_server_ac_power_cycle[0x1]; 10843 u8 pending_server_dc_power_cycle[0x1]; 10844 u8 pending_server_reboot[0x1]; 10845 u8 pending_fw_reset[0x1]; 10846 u8 auto_activate[0x1]; 10847 u8 all_hosts_sync[0x1]; 10848 u8 device_hw_reset[0x1]; 10849 u8 reserved_at_7[0x19]; 10850 }; 10851 10852 union mlx5_ifc_mcqi_reg_data_bits { 10853 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10854 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10855 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10856 }; 10857 10858 struct mlx5_ifc_mcqi_reg_bits { 10859 u8 read_pending_component[0x1]; 10860 u8 reserved_at_1[0xf]; 10861 u8 component_index[0x10]; 10862 10863 u8 reserved_at_20[0x20]; 10864 10865 u8 reserved_at_40[0x1b]; 10866 u8 info_type[0x5]; 10867 10868 u8 info_size[0x20]; 10869 10870 u8 offset[0x20]; 10871 10872 u8 reserved_at_a0[0x10]; 10873 u8 data_size[0x10]; 10874 10875 union mlx5_ifc_mcqi_reg_data_bits data[]; 10876 }; 10877 10878 struct mlx5_ifc_mcc_reg_bits { 10879 u8 reserved_at_0[0x4]; 10880 u8 time_elapsed_since_last_cmd[0xc]; 10881 u8 reserved_at_10[0x8]; 10882 u8 instruction[0x8]; 10883 10884 u8 reserved_at_20[0x10]; 10885 u8 component_index[0x10]; 10886 10887 u8 reserved_at_40[0x8]; 10888 u8 update_handle[0x18]; 10889 10890 u8 handle_owner_type[0x4]; 10891 u8 handle_owner_host_id[0x4]; 10892 u8 reserved_at_68[0x1]; 10893 u8 control_progress[0x7]; 10894 u8 error_code[0x8]; 10895 u8 reserved_at_78[0x4]; 10896 u8 control_state[0x4]; 10897 10898 u8 component_size[0x20]; 10899 10900 u8 reserved_at_a0[0x60]; 10901 }; 10902 10903 struct mlx5_ifc_mcda_reg_bits { 10904 u8 reserved_at_0[0x8]; 10905 u8 update_handle[0x18]; 10906 10907 u8 offset[0x20]; 10908 10909 u8 reserved_at_40[0x10]; 10910 u8 size[0x10]; 10911 10912 u8 reserved_at_60[0x20]; 10913 10914 u8 data[][0x20]; 10915 }; 10916 10917 enum { 10918 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10919 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10920 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10921 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 10922 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10923 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 10924 }; 10925 10926 enum { 10927 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10928 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10929 }; 10930 10931 enum { 10932 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10933 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10934 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10935 }; 10936 10937 struct mlx5_ifc_mfrl_reg_bits { 10938 u8 reserved_at_0[0x20]; 10939 10940 u8 reserved_at_20[0x2]; 10941 u8 pci_sync_for_fw_update_start[0x1]; 10942 u8 pci_sync_for_fw_update_resp[0x2]; 10943 u8 rst_type_sel[0x3]; 10944 u8 reserved_at_28[0x4]; 10945 u8 reset_state[0x4]; 10946 u8 reset_type[0x8]; 10947 u8 reset_level[0x8]; 10948 }; 10949 10950 struct mlx5_ifc_mirc_reg_bits { 10951 u8 reserved_at_0[0x18]; 10952 u8 status_code[0x8]; 10953 10954 u8 reserved_at_20[0x20]; 10955 }; 10956 10957 struct mlx5_ifc_pddr_monitor_opcode_bits { 10958 u8 reserved_at_0[0x10]; 10959 u8 monitor_opcode[0x10]; 10960 }; 10961 10962 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10963 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10964 u8 reserved_at_0[0x20]; 10965 }; 10966 10967 enum { 10968 /* Monitor opcodes */ 10969 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10970 }; 10971 10972 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10973 u8 reserved_at_0[0x10]; 10974 u8 group_opcode[0x10]; 10975 10976 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10977 10978 u8 reserved_at_40[0x20]; 10979 10980 u8 status_message[59][0x20]; 10981 }; 10982 10983 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10984 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10985 u8 reserved_at_0[0x7c0]; 10986 }; 10987 10988 enum { 10989 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10990 }; 10991 10992 struct mlx5_ifc_pddr_reg_bits { 10993 u8 reserved_at_0[0x8]; 10994 u8 local_port[0x8]; 10995 u8 pnat[0x2]; 10996 u8 reserved_at_12[0xe]; 10997 10998 u8 reserved_at_20[0x18]; 10999 u8 page_select[0x8]; 11000 11001 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11002 }; 11003 11004 struct mlx5_ifc_mrtc_reg_bits { 11005 u8 time_synced[0x1]; 11006 u8 reserved_at_1[0x1f]; 11007 11008 u8 reserved_at_20[0x20]; 11009 11010 u8 time_h[0x20]; 11011 11012 u8 time_l[0x20]; 11013 }; 11014 11015 struct mlx5_ifc_mtcap_reg_bits { 11016 u8 reserved_at_0[0x19]; 11017 u8 sensor_count[0x7]; 11018 11019 u8 reserved_at_20[0x20]; 11020 11021 u8 sensor_map[0x40]; 11022 }; 11023 11024 struct mlx5_ifc_mtmp_reg_bits { 11025 u8 reserved_at_0[0x14]; 11026 u8 sensor_index[0xc]; 11027 11028 u8 reserved_at_20[0x10]; 11029 u8 temperature[0x10]; 11030 11031 u8 mte[0x1]; 11032 u8 mtr[0x1]; 11033 u8 reserved_at_42[0xe]; 11034 u8 max_temperature[0x10]; 11035 11036 u8 tee[0x2]; 11037 u8 reserved_at_62[0xe]; 11038 u8 temp_threshold_hi[0x10]; 11039 11040 u8 reserved_at_80[0x10]; 11041 u8 temp_threshold_lo[0x10]; 11042 11043 u8 reserved_at_a0[0x20]; 11044 11045 u8 sensor_name_hi[0x20]; 11046 u8 sensor_name_lo[0x20]; 11047 }; 11048 11049 union mlx5_ifc_ports_control_registers_document_bits { 11050 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11051 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11052 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11053 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11054 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11055 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11056 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11057 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11058 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11059 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11060 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11061 struct mlx5_ifc_paos_reg_bits paos_reg; 11062 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11063 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11064 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11065 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11066 struct mlx5_ifc_peir_reg_bits peir_reg; 11067 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11068 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11069 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11070 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11071 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11072 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11073 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11074 struct mlx5_ifc_plib_reg_bits plib_reg; 11075 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11076 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11077 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11078 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11079 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11080 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11081 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11082 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11083 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11084 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11085 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11086 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11087 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11088 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11089 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11090 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11091 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11092 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11093 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11094 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11095 struct mlx5_ifc_pude_reg_bits pude_reg; 11096 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11097 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11098 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11099 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11100 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11101 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11102 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11103 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11104 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11105 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11106 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11107 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11108 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11109 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11110 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11111 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11112 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11113 u8 reserved_at_0[0x60e0]; 11114 }; 11115 11116 union mlx5_ifc_debug_enhancements_document_bits { 11117 struct mlx5_ifc_health_buffer_bits health_buffer; 11118 u8 reserved_at_0[0x200]; 11119 }; 11120 11121 union mlx5_ifc_uplink_pci_interface_document_bits { 11122 struct mlx5_ifc_initial_seg_bits initial_seg; 11123 u8 reserved_at_0[0x20060]; 11124 }; 11125 11126 struct mlx5_ifc_set_flow_table_root_out_bits { 11127 u8 status[0x8]; 11128 u8 reserved_at_8[0x18]; 11129 11130 u8 syndrome[0x20]; 11131 11132 u8 reserved_at_40[0x40]; 11133 }; 11134 11135 struct mlx5_ifc_set_flow_table_root_in_bits { 11136 u8 opcode[0x10]; 11137 u8 reserved_at_10[0x10]; 11138 11139 u8 reserved_at_20[0x10]; 11140 u8 op_mod[0x10]; 11141 11142 u8 other_vport[0x1]; 11143 u8 reserved_at_41[0xf]; 11144 u8 vport_number[0x10]; 11145 11146 u8 reserved_at_60[0x20]; 11147 11148 u8 table_type[0x8]; 11149 u8 reserved_at_88[0x7]; 11150 u8 table_of_other_vport[0x1]; 11151 u8 table_vport_number[0x10]; 11152 11153 u8 reserved_at_a0[0x8]; 11154 u8 table_id[0x18]; 11155 11156 u8 reserved_at_c0[0x8]; 11157 u8 underlay_qpn[0x18]; 11158 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11159 u8 reserved_at_e1[0xf]; 11160 u8 table_eswitch_owner_vhca_id[0x10]; 11161 u8 reserved_at_100[0x100]; 11162 }; 11163 11164 enum { 11165 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11166 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11167 }; 11168 11169 struct mlx5_ifc_modify_flow_table_out_bits { 11170 u8 status[0x8]; 11171 u8 reserved_at_8[0x18]; 11172 11173 u8 syndrome[0x20]; 11174 11175 u8 reserved_at_40[0x40]; 11176 }; 11177 11178 struct mlx5_ifc_modify_flow_table_in_bits { 11179 u8 opcode[0x10]; 11180 u8 reserved_at_10[0x10]; 11181 11182 u8 reserved_at_20[0x10]; 11183 u8 op_mod[0x10]; 11184 11185 u8 other_vport[0x1]; 11186 u8 reserved_at_41[0xf]; 11187 u8 vport_number[0x10]; 11188 11189 u8 reserved_at_60[0x10]; 11190 u8 modify_field_select[0x10]; 11191 11192 u8 table_type[0x8]; 11193 u8 reserved_at_88[0x18]; 11194 11195 u8 reserved_at_a0[0x8]; 11196 u8 table_id[0x18]; 11197 11198 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11199 }; 11200 11201 struct mlx5_ifc_ets_tcn_config_reg_bits { 11202 u8 g[0x1]; 11203 u8 b[0x1]; 11204 u8 r[0x1]; 11205 u8 reserved_at_3[0x9]; 11206 u8 group[0x4]; 11207 u8 reserved_at_10[0x9]; 11208 u8 bw_allocation[0x7]; 11209 11210 u8 reserved_at_20[0xc]; 11211 u8 max_bw_units[0x4]; 11212 u8 reserved_at_30[0x8]; 11213 u8 max_bw_value[0x8]; 11214 }; 11215 11216 struct mlx5_ifc_ets_global_config_reg_bits { 11217 u8 reserved_at_0[0x2]; 11218 u8 r[0x1]; 11219 u8 reserved_at_3[0x1d]; 11220 11221 u8 reserved_at_20[0xc]; 11222 u8 max_bw_units[0x4]; 11223 u8 reserved_at_30[0x8]; 11224 u8 max_bw_value[0x8]; 11225 }; 11226 11227 struct mlx5_ifc_qetc_reg_bits { 11228 u8 reserved_at_0[0x8]; 11229 u8 port_number[0x8]; 11230 u8 reserved_at_10[0x30]; 11231 11232 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11233 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11234 }; 11235 11236 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11237 u8 e[0x1]; 11238 u8 reserved_at_01[0x0b]; 11239 u8 prio[0x04]; 11240 }; 11241 11242 struct mlx5_ifc_qpdpm_reg_bits { 11243 u8 reserved_at_0[0x8]; 11244 u8 local_port[0x8]; 11245 u8 reserved_at_10[0x10]; 11246 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11247 }; 11248 11249 struct mlx5_ifc_qpts_reg_bits { 11250 u8 reserved_at_0[0x8]; 11251 u8 local_port[0x8]; 11252 u8 reserved_at_10[0x2d]; 11253 u8 trust_state[0x3]; 11254 }; 11255 11256 struct mlx5_ifc_pptb_reg_bits { 11257 u8 reserved_at_0[0x2]; 11258 u8 mm[0x2]; 11259 u8 reserved_at_4[0x4]; 11260 u8 local_port[0x8]; 11261 u8 reserved_at_10[0x6]; 11262 u8 cm[0x1]; 11263 u8 um[0x1]; 11264 u8 pm[0x8]; 11265 11266 u8 prio_x_buff[0x20]; 11267 11268 u8 pm_msb[0x8]; 11269 u8 reserved_at_48[0x10]; 11270 u8 ctrl_buff[0x4]; 11271 u8 untagged_buff[0x4]; 11272 }; 11273 11274 struct mlx5_ifc_sbcam_reg_bits { 11275 u8 reserved_at_0[0x8]; 11276 u8 feature_group[0x8]; 11277 u8 reserved_at_10[0x8]; 11278 u8 access_reg_group[0x8]; 11279 11280 u8 reserved_at_20[0x20]; 11281 11282 u8 sb_access_reg_cap_mask[4][0x20]; 11283 11284 u8 reserved_at_c0[0x80]; 11285 11286 u8 sb_feature_cap_mask[4][0x20]; 11287 11288 u8 reserved_at_1c0[0x40]; 11289 11290 u8 cap_total_buffer_size[0x20]; 11291 11292 u8 cap_cell_size[0x10]; 11293 u8 cap_max_pg_buffers[0x8]; 11294 u8 cap_num_pool_supported[0x8]; 11295 11296 u8 reserved_at_240[0x8]; 11297 u8 cap_sbsr_stat_size[0x8]; 11298 u8 cap_max_tclass_data[0x8]; 11299 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11300 }; 11301 11302 struct mlx5_ifc_pbmc_reg_bits { 11303 u8 reserved_at_0[0x8]; 11304 u8 local_port[0x8]; 11305 u8 reserved_at_10[0x10]; 11306 11307 u8 xoff_timer_value[0x10]; 11308 u8 xoff_refresh[0x10]; 11309 11310 u8 reserved_at_40[0x9]; 11311 u8 fullness_threshold[0x7]; 11312 u8 port_buffer_size[0x10]; 11313 11314 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11315 11316 u8 reserved_at_2e0[0x80]; 11317 }; 11318 11319 struct mlx5_ifc_sbpr_reg_bits { 11320 u8 desc[0x1]; 11321 u8 snap[0x1]; 11322 u8 reserved_at_2[0x4]; 11323 u8 dir[0x2]; 11324 u8 reserved_at_8[0x14]; 11325 u8 pool[0x4]; 11326 11327 u8 infi_size[0x1]; 11328 u8 reserved_at_21[0x7]; 11329 u8 size[0x18]; 11330 11331 u8 reserved_at_40[0x1c]; 11332 u8 mode[0x4]; 11333 11334 u8 reserved_at_60[0x8]; 11335 u8 buff_occupancy[0x18]; 11336 11337 u8 clr[0x1]; 11338 u8 reserved_at_81[0x7]; 11339 u8 max_buff_occupancy[0x18]; 11340 11341 u8 reserved_at_a0[0x8]; 11342 u8 ext_buff_occupancy[0x18]; 11343 }; 11344 11345 struct mlx5_ifc_sbcm_reg_bits { 11346 u8 desc[0x1]; 11347 u8 snap[0x1]; 11348 u8 reserved_at_2[0x6]; 11349 u8 local_port[0x8]; 11350 u8 pnat[0x2]; 11351 u8 pg_buff[0x6]; 11352 u8 reserved_at_18[0x6]; 11353 u8 dir[0x2]; 11354 11355 u8 reserved_at_20[0x1f]; 11356 u8 exc[0x1]; 11357 11358 u8 reserved_at_40[0x40]; 11359 11360 u8 reserved_at_80[0x8]; 11361 u8 buff_occupancy[0x18]; 11362 11363 u8 clr[0x1]; 11364 u8 reserved_at_a1[0x7]; 11365 u8 max_buff_occupancy[0x18]; 11366 11367 u8 reserved_at_c0[0x8]; 11368 u8 min_buff[0x18]; 11369 11370 u8 infi_max[0x1]; 11371 u8 reserved_at_e1[0x7]; 11372 u8 max_buff[0x18]; 11373 11374 u8 reserved_at_100[0x20]; 11375 11376 u8 reserved_at_120[0x1c]; 11377 u8 pool[0x4]; 11378 }; 11379 11380 struct mlx5_ifc_qtct_reg_bits { 11381 u8 reserved_at_0[0x8]; 11382 u8 port_number[0x8]; 11383 u8 reserved_at_10[0xd]; 11384 u8 prio[0x3]; 11385 11386 u8 reserved_at_20[0x1d]; 11387 u8 tclass[0x3]; 11388 }; 11389 11390 struct mlx5_ifc_mcia_reg_bits { 11391 u8 l[0x1]; 11392 u8 reserved_at_1[0x7]; 11393 u8 module[0x8]; 11394 u8 reserved_at_10[0x8]; 11395 u8 status[0x8]; 11396 11397 u8 i2c_device_address[0x8]; 11398 u8 page_number[0x8]; 11399 u8 device_address[0x10]; 11400 11401 u8 reserved_at_40[0x10]; 11402 u8 size[0x10]; 11403 11404 u8 reserved_at_60[0x20]; 11405 11406 u8 dword_0[0x20]; 11407 u8 dword_1[0x20]; 11408 u8 dword_2[0x20]; 11409 u8 dword_3[0x20]; 11410 u8 dword_4[0x20]; 11411 u8 dword_5[0x20]; 11412 u8 dword_6[0x20]; 11413 u8 dword_7[0x20]; 11414 u8 dword_8[0x20]; 11415 u8 dword_9[0x20]; 11416 u8 dword_10[0x20]; 11417 u8 dword_11[0x20]; 11418 }; 11419 11420 struct mlx5_ifc_dcbx_param_bits { 11421 u8 dcbx_cee_cap[0x1]; 11422 u8 dcbx_ieee_cap[0x1]; 11423 u8 dcbx_standby_cap[0x1]; 11424 u8 reserved_at_3[0x5]; 11425 u8 port_number[0x8]; 11426 u8 reserved_at_10[0xa]; 11427 u8 max_application_table_size[6]; 11428 u8 reserved_at_20[0x15]; 11429 u8 version_oper[0x3]; 11430 u8 reserved_at_38[5]; 11431 u8 version_admin[0x3]; 11432 u8 willing_admin[0x1]; 11433 u8 reserved_at_41[0x3]; 11434 u8 pfc_cap_oper[0x4]; 11435 u8 reserved_at_48[0x4]; 11436 u8 pfc_cap_admin[0x4]; 11437 u8 reserved_at_50[0x4]; 11438 u8 num_of_tc_oper[0x4]; 11439 u8 reserved_at_58[0x4]; 11440 u8 num_of_tc_admin[0x4]; 11441 u8 remote_willing[0x1]; 11442 u8 reserved_at_61[3]; 11443 u8 remote_pfc_cap[4]; 11444 u8 reserved_at_68[0x14]; 11445 u8 remote_num_of_tc[0x4]; 11446 u8 reserved_at_80[0x18]; 11447 u8 error[0x8]; 11448 u8 reserved_at_a0[0x160]; 11449 }; 11450 11451 enum { 11452 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11453 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11454 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11455 }; 11456 11457 struct mlx5_ifc_lagc_bits { 11458 u8 fdb_selection_mode[0x1]; 11459 u8 reserved_at_1[0x14]; 11460 u8 port_select_mode[0x3]; 11461 u8 reserved_at_18[0x5]; 11462 u8 lag_state[0x3]; 11463 11464 u8 reserved_at_20[0xc]; 11465 u8 active_port[0x4]; 11466 u8 reserved_at_30[0x4]; 11467 u8 tx_remap_affinity_2[0x4]; 11468 u8 reserved_at_38[0x4]; 11469 u8 tx_remap_affinity_1[0x4]; 11470 }; 11471 11472 struct mlx5_ifc_create_lag_out_bits { 11473 u8 status[0x8]; 11474 u8 reserved_at_8[0x18]; 11475 11476 u8 syndrome[0x20]; 11477 11478 u8 reserved_at_40[0x40]; 11479 }; 11480 11481 struct mlx5_ifc_create_lag_in_bits { 11482 u8 opcode[0x10]; 11483 u8 reserved_at_10[0x10]; 11484 11485 u8 reserved_at_20[0x10]; 11486 u8 op_mod[0x10]; 11487 11488 struct mlx5_ifc_lagc_bits ctx; 11489 }; 11490 11491 struct mlx5_ifc_modify_lag_out_bits { 11492 u8 status[0x8]; 11493 u8 reserved_at_8[0x18]; 11494 11495 u8 syndrome[0x20]; 11496 11497 u8 reserved_at_40[0x40]; 11498 }; 11499 11500 struct mlx5_ifc_modify_lag_in_bits { 11501 u8 opcode[0x10]; 11502 u8 reserved_at_10[0x10]; 11503 11504 u8 reserved_at_20[0x10]; 11505 u8 op_mod[0x10]; 11506 11507 u8 reserved_at_40[0x20]; 11508 u8 field_select[0x20]; 11509 11510 struct mlx5_ifc_lagc_bits ctx; 11511 }; 11512 11513 struct mlx5_ifc_query_lag_out_bits { 11514 u8 status[0x8]; 11515 u8 reserved_at_8[0x18]; 11516 11517 u8 syndrome[0x20]; 11518 11519 struct mlx5_ifc_lagc_bits ctx; 11520 }; 11521 11522 struct mlx5_ifc_query_lag_in_bits { 11523 u8 opcode[0x10]; 11524 u8 reserved_at_10[0x10]; 11525 11526 u8 reserved_at_20[0x10]; 11527 u8 op_mod[0x10]; 11528 11529 u8 reserved_at_40[0x40]; 11530 }; 11531 11532 struct mlx5_ifc_destroy_lag_out_bits { 11533 u8 status[0x8]; 11534 u8 reserved_at_8[0x18]; 11535 11536 u8 syndrome[0x20]; 11537 11538 u8 reserved_at_40[0x40]; 11539 }; 11540 11541 struct mlx5_ifc_destroy_lag_in_bits { 11542 u8 opcode[0x10]; 11543 u8 reserved_at_10[0x10]; 11544 11545 u8 reserved_at_20[0x10]; 11546 u8 op_mod[0x10]; 11547 11548 u8 reserved_at_40[0x40]; 11549 }; 11550 11551 struct mlx5_ifc_create_vport_lag_out_bits { 11552 u8 status[0x8]; 11553 u8 reserved_at_8[0x18]; 11554 11555 u8 syndrome[0x20]; 11556 11557 u8 reserved_at_40[0x40]; 11558 }; 11559 11560 struct mlx5_ifc_create_vport_lag_in_bits { 11561 u8 opcode[0x10]; 11562 u8 reserved_at_10[0x10]; 11563 11564 u8 reserved_at_20[0x10]; 11565 u8 op_mod[0x10]; 11566 11567 u8 reserved_at_40[0x40]; 11568 }; 11569 11570 struct mlx5_ifc_destroy_vport_lag_out_bits { 11571 u8 status[0x8]; 11572 u8 reserved_at_8[0x18]; 11573 11574 u8 syndrome[0x20]; 11575 11576 u8 reserved_at_40[0x40]; 11577 }; 11578 11579 struct mlx5_ifc_destroy_vport_lag_in_bits { 11580 u8 opcode[0x10]; 11581 u8 reserved_at_10[0x10]; 11582 11583 u8 reserved_at_20[0x10]; 11584 u8 op_mod[0x10]; 11585 11586 u8 reserved_at_40[0x40]; 11587 }; 11588 11589 enum { 11590 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11591 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11592 }; 11593 11594 struct mlx5_ifc_modify_memic_in_bits { 11595 u8 opcode[0x10]; 11596 u8 uid[0x10]; 11597 11598 u8 reserved_at_20[0x10]; 11599 u8 op_mod[0x10]; 11600 11601 u8 reserved_at_40[0x20]; 11602 11603 u8 reserved_at_60[0x18]; 11604 u8 memic_operation_type[0x8]; 11605 11606 u8 memic_start_addr[0x40]; 11607 11608 u8 reserved_at_c0[0x140]; 11609 }; 11610 11611 struct mlx5_ifc_modify_memic_out_bits { 11612 u8 status[0x8]; 11613 u8 reserved_at_8[0x18]; 11614 11615 u8 syndrome[0x20]; 11616 11617 u8 reserved_at_40[0x40]; 11618 11619 u8 memic_operation_addr[0x40]; 11620 11621 u8 reserved_at_c0[0x140]; 11622 }; 11623 11624 struct mlx5_ifc_alloc_memic_in_bits { 11625 u8 opcode[0x10]; 11626 u8 reserved_at_10[0x10]; 11627 11628 u8 reserved_at_20[0x10]; 11629 u8 op_mod[0x10]; 11630 11631 u8 reserved_at_30[0x20]; 11632 11633 u8 reserved_at_40[0x18]; 11634 u8 log_memic_addr_alignment[0x8]; 11635 11636 u8 range_start_addr[0x40]; 11637 11638 u8 range_size[0x20]; 11639 11640 u8 memic_size[0x20]; 11641 }; 11642 11643 struct mlx5_ifc_alloc_memic_out_bits { 11644 u8 status[0x8]; 11645 u8 reserved_at_8[0x18]; 11646 11647 u8 syndrome[0x20]; 11648 11649 u8 memic_start_addr[0x40]; 11650 }; 11651 11652 struct mlx5_ifc_dealloc_memic_in_bits { 11653 u8 opcode[0x10]; 11654 u8 reserved_at_10[0x10]; 11655 11656 u8 reserved_at_20[0x10]; 11657 u8 op_mod[0x10]; 11658 11659 u8 reserved_at_40[0x40]; 11660 11661 u8 memic_start_addr[0x40]; 11662 11663 u8 memic_size[0x20]; 11664 11665 u8 reserved_at_e0[0x20]; 11666 }; 11667 11668 struct mlx5_ifc_dealloc_memic_out_bits { 11669 u8 status[0x8]; 11670 u8 reserved_at_8[0x18]; 11671 11672 u8 syndrome[0x20]; 11673 11674 u8 reserved_at_40[0x40]; 11675 }; 11676 11677 struct mlx5_ifc_umem_bits { 11678 u8 reserved_at_0[0x80]; 11679 11680 u8 ats[0x1]; 11681 u8 reserved_at_81[0x1a]; 11682 u8 log_page_size[0x5]; 11683 11684 u8 page_offset[0x20]; 11685 11686 u8 num_of_mtt[0x40]; 11687 11688 struct mlx5_ifc_mtt_bits mtt[]; 11689 }; 11690 11691 struct mlx5_ifc_uctx_bits { 11692 u8 cap[0x20]; 11693 11694 u8 reserved_at_20[0x160]; 11695 }; 11696 11697 struct mlx5_ifc_sw_icm_bits { 11698 u8 modify_field_select[0x40]; 11699 11700 u8 reserved_at_40[0x18]; 11701 u8 log_sw_icm_size[0x8]; 11702 11703 u8 reserved_at_60[0x20]; 11704 11705 u8 sw_icm_start_addr[0x40]; 11706 11707 u8 reserved_at_c0[0x140]; 11708 }; 11709 11710 struct mlx5_ifc_geneve_tlv_option_bits { 11711 u8 modify_field_select[0x40]; 11712 11713 u8 reserved_at_40[0x18]; 11714 u8 geneve_option_fte_index[0x8]; 11715 11716 u8 option_class[0x10]; 11717 u8 option_type[0x8]; 11718 u8 reserved_at_78[0x3]; 11719 u8 option_data_length[0x5]; 11720 11721 u8 reserved_at_80[0x180]; 11722 }; 11723 11724 struct mlx5_ifc_create_umem_in_bits { 11725 u8 opcode[0x10]; 11726 u8 uid[0x10]; 11727 11728 u8 reserved_at_20[0x10]; 11729 u8 op_mod[0x10]; 11730 11731 u8 reserved_at_40[0x40]; 11732 11733 struct mlx5_ifc_umem_bits umem; 11734 }; 11735 11736 struct mlx5_ifc_create_umem_out_bits { 11737 u8 status[0x8]; 11738 u8 reserved_at_8[0x18]; 11739 11740 u8 syndrome[0x20]; 11741 11742 u8 reserved_at_40[0x8]; 11743 u8 umem_id[0x18]; 11744 11745 u8 reserved_at_60[0x20]; 11746 }; 11747 11748 struct mlx5_ifc_destroy_umem_in_bits { 11749 u8 opcode[0x10]; 11750 u8 uid[0x10]; 11751 11752 u8 reserved_at_20[0x10]; 11753 u8 op_mod[0x10]; 11754 11755 u8 reserved_at_40[0x8]; 11756 u8 umem_id[0x18]; 11757 11758 u8 reserved_at_60[0x20]; 11759 }; 11760 11761 struct mlx5_ifc_destroy_umem_out_bits { 11762 u8 status[0x8]; 11763 u8 reserved_at_8[0x18]; 11764 11765 u8 syndrome[0x20]; 11766 11767 u8 reserved_at_40[0x40]; 11768 }; 11769 11770 struct mlx5_ifc_create_uctx_in_bits { 11771 u8 opcode[0x10]; 11772 u8 reserved_at_10[0x10]; 11773 11774 u8 reserved_at_20[0x10]; 11775 u8 op_mod[0x10]; 11776 11777 u8 reserved_at_40[0x40]; 11778 11779 struct mlx5_ifc_uctx_bits uctx; 11780 }; 11781 11782 struct mlx5_ifc_create_uctx_out_bits { 11783 u8 status[0x8]; 11784 u8 reserved_at_8[0x18]; 11785 11786 u8 syndrome[0x20]; 11787 11788 u8 reserved_at_40[0x10]; 11789 u8 uid[0x10]; 11790 11791 u8 reserved_at_60[0x20]; 11792 }; 11793 11794 struct mlx5_ifc_destroy_uctx_in_bits { 11795 u8 opcode[0x10]; 11796 u8 reserved_at_10[0x10]; 11797 11798 u8 reserved_at_20[0x10]; 11799 u8 op_mod[0x10]; 11800 11801 u8 reserved_at_40[0x10]; 11802 u8 uid[0x10]; 11803 11804 u8 reserved_at_60[0x20]; 11805 }; 11806 11807 struct mlx5_ifc_destroy_uctx_out_bits { 11808 u8 status[0x8]; 11809 u8 reserved_at_8[0x18]; 11810 11811 u8 syndrome[0x20]; 11812 11813 u8 reserved_at_40[0x40]; 11814 }; 11815 11816 struct mlx5_ifc_create_sw_icm_in_bits { 11817 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11818 struct mlx5_ifc_sw_icm_bits sw_icm; 11819 }; 11820 11821 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11822 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11823 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11824 }; 11825 11826 struct mlx5_ifc_mtrc_string_db_param_bits { 11827 u8 string_db_base_address[0x20]; 11828 11829 u8 reserved_at_20[0x8]; 11830 u8 string_db_size[0x18]; 11831 }; 11832 11833 struct mlx5_ifc_mtrc_cap_bits { 11834 u8 trace_owner[0x1]; 11835 u8 trace_to_memory[0x1]; 11836 u8 reserved_at_2[0x4]; 11837 u8 trc_ver[0x2]; 11838 u8 reserved_at_8[0x14]; 11839 u8 num_string_db[0x4]; 11840 11841 u8 first_string_trace[0x8]; 11842 u8 num_string_trace[0x8]; 11843 u8 reserved_at_30[0x28]; 11844 11845 u8 log_max_trace_buffer_size[0x8]; 11846 11847 u8 reserved_at_60[0x20]; 11848 11849 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11850 11851 u8 reserved_at_280[0x180]; 11852 }; 11853 11854 struct mlx5_ifc_mtrc_conf_bits { 11855 u8 reserved_at_0[0x1c]; 11856 u8 trace_mode[0x4]; 11857 u8 reserved_at_20[0x18]; 11858 u8 log_trace_buffer_size[0x8]; 11859 u8 trace_mkey[0x20]; 11860 u8 reserved_at_60[0x3a0]; 11861 }; 11862 11863 struct mlx5_ifc_mtrc_stdb_bits { 11864 u8 string_db_index[0x4]; 11865 u8 reserved_at_4[0x4]; 11866 u8 read_size[0x18]; 11867 u8 start_offset[0x20]; 11868 u8 string_db_data[]; 11869 }; 11870 11871 struct mlx5_ifc_mtrc_ctrl_bits { 11872 u8 trace_status[0x2]; 11873 u8 reserved_at_2[0x2]; 11874 u8 arm_event[0x1]; 11875 u8 reserved_at_5[0xb]; 11876 u8 modify_field_select[0x10]; 11877 u8 reserved_at_20[0x2b]; 11878 u8 current_timestamp52_32[0x15]; 11879 u8 current_timestamp31_0[0x20]; 11880 u8 reserved_at_80[0x180]; 11881 }; 11882 11883 struct mlx5_ifc_host_params_context_bits { 11884 u8 host_number[0x8]; 11885 u8 reserved_at_8[0x7]; 11886 u8 host_pf_disabled[0x1]; 11887 u8 host_num_of_vfs[0x10]; 11888 11889 u8 host_total_vfs[0x10]; 11890 u8 host_pci_bus[0x10]; 11891 11892 u8 reserved_at_40[0x10]; 11893 u8 host_pci_device[0x10]; 11894 11895 u8 reserved_at_60[0x10]; 11896 u8 host_pci_function[0x10]; 11897 11898 u8 reserved_at_80[0x180]; 11899 }; 11900 11901 struct mlx5_ifc_query_esw_functions_in_bits { 11902 u8 opcode[0x10]; 11903 u8 reserved_at_10[0x10]; 11904 11905 u8 reserved_at_20[0x10]; 11906 u8 op_mod[0x10]; 11907 11908 u8 reserved_at_40[0x40]; 11909 }; 11910 11911 struct mlx5_ifc_query_esw_functions_out_bits { 11912 u8 status[0x8]; 11913 u8 reserved_at_8[0x18]; 11914 11915 u8 syndrome[0x20]; 11916 11917 u8 reserved_at_40[0x40]; 11918 11919 struct mlx5_ifc_host_params_context_bits host_params_context; 11920 11921 u8 reserved_at_280[0x180]; 11922 u8 host_sf_enable[][0x40]; 11923 }; 11924 11925 struct mlx5_ifc_sf_partition_bits { 11926 u8 reserved_at_0[0x10]; 11927 u8 log_num_sf[0x8]; 11928 u8 log_sf_bar_size[0x8]; 11929 }; 11930 11931 struct mlx5_ifc_query_sf_partitions_out_bits { 11932 u8 status[0x8]; 11933 u8 reserved_at_8[0x18]; 11934 11935 u8 syndrome[0x20]; 11936 11937 u8 reserved_at_40[0x18]; 11938 u8 num_sf_partitions[0x8]; 11939 11940 u8 reserved_at_60[0x20]; 11941 11942 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11943 }; 11944 11945 struct mlx5_ifc_query_sf_partitions_in_bits { 11946 u8 opcode[0x10]; 11947 u8 reserved_at_10[0x10]; 11948 11949 u8 reserved_at_20[0x10]; 11950 u8 op_mod[0x10]; 11951 11952 u8 reserved_at_40[0x40]; 11953 }; 11954 11955 struct mlx5_ifc_dealloc_sf_out_bits { 11956 u8 status[0x8]; 11957 u8 reserved_at_8[0x18]; 11958 11959 u8 syndrome[0x20]; 11960 11961 u8 reserved_at_40[0x40]; 11962 }; 11963 11964 struct mlx5_ifc_dealloc_sf_in_bits { 11965 u8 opcode[0x10]; 11966 u8 reserved_at_10[0x10]; 11967 11968 u8 reserved_at_20[0x10]; 11969 u8 op_mod[0x10]; 11970 11971 u8 reserved_at_40[0x10]; 11972 u8 function_id[0x10]; 11973 11974 u8 reserved_at_60[0x20]; 11975 }; 11976 11977 struct mlx5_ifc_alloc_sf_out_bits { 11978 u8 status[0x8]; 11979 u8 reserved_at_8[0x18]; 11980 11981 u8 syndrome[0x20]; 11982 11983 u8 reserved_at_40[0x40]; 11984 }; 11985 11986 struct mlx5_ifc_alloc_sf_in_bits { 11987 u8 opcode[0x10]; 11988 u8 reserved_at_10[0x10]; 11989 11990 u8 reserved_at_20[0x10]; 11991 u8 op_mod[0x10]; 11992 11993 u8 reserved_at_40[0x10]; 11994 u8 function_id[0x10]; 11995 11996 u8 reserved_at_60[0x20]; 11997 }; 11998 11999 struct mlx5_ifc_affiliated_event_header_bits { 12000 u8 reserved_at_0[0x10]; 12001 u8 obj_type[0x10]; 12002 12003 u8 obj_id[0x20]; 12004 }; 12005 12006 enum { 12007 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 12008 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 12009 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 12010 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 12011 }; 12012 12013 enum { 12014 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12015 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12016 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12017 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12018 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12019 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12020 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12021 }; 12022 12023 enum { 12024 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12025 }; 12026 12027 enum { 12028 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12029 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12030 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12031 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12032 }; 12033 12034 enum { 12035 MLX5_IPSEC_ASO_MODE = 0x0, 12036 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12037 MLX5_IPSEC_ASO_INC_SN = 0x2, 12038 }; 12039 12040 enum { 12041 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12042 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12043 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12044 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12045 }; 12046 12047 struct mlx5_ifc_ipsec_aso_bits { 12048 u8 valid[0x1]; 12049 u8 reserved_at_201[0x1]; 12050 u8 mode[0x2]; 12051 u8 window_sz[0x2]; 12052 u8 soft_lft_arm[0x1]; 12053 u8 hard_lft_arm[0x1]; 12054 u8 remove_flow_enable[0x1]; 12055 u8 esn_event_arm[0x1]; 12056 u8 reserved_at_20a[0x16]; 12057 12058 u8 remove_flow_pkt_cnt[0x20]; 12059 12060 u8 remove_flow_soft_lft[0x20]; 12061 12062 u8 reserved_at_260[0x80]; 12063 12064 u8 mode_parameter[0x20]; 12065 12066 u8 replay_protection_window[0x100]; 12067 }; 12068 12069 struct mlx5_ifc_ipsec_obj_bits { 12070 u8 modify_field_select[0x40]; 12071 u8 full_offload[0x1]; 12072 u8 reserved_at_41[0x1]; 12073 u8 esn_en[0x1]; 12074 u8 esn_overlap[0x1]; 12075 u8 reserved_at_44[0x2]; 12076 u8 icv_length[0x2]; 12077 u8 reserved_at_48[0x4]; 12078 u8 aso_return_reg[0x4]; 12079 u8 reserved_at_50[0x10]; 12080 12081 u8 esn_msb[0x20]; 12082 12083 u8 reserved_at_80[0x8]; 12084 u8 dekn[0x18]; 12085 12086 u8 salt[0x20]; 12087 12088 u8 implicit_iv[0x40]; 12089 12090 u8 reserved_at_100[0x8]; 12091 u8 ipsec_aso_access_pd[0x18]; 12092 u8 reserved_at_120[0xe0]; 12093 12094 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12095 }; 12096 12097 struct mlx5_ifc_create_ipsec_obj_in_bits { 12098 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12099 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12100 }; 12101 12102 enum { 12103 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12104 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12105 }; 12106 12107 struct mlx5_ifc_query_ipsec_obj_out_bits { 12108 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12109 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12110 }; 12111 12112 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12113 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12114 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12115 }; 12116 12117 enum { 12118 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12119 }; 12120 12121 enum { 12122 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12123 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12124 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12125 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12126 }; 12127 12128 #define MLX5_MACSEC_ASO_INC_SN 0x2 12129 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12130 12131 struct mlx5_ifc_macsec_aso_bits { 12132 u8 valid[0x1]; 12133 u8 reserved_at_1[0x1]; 12134 u8 mode[0x2]; 12135 u8 window_size[0x2]; 12136 u8 soft_lifetime_arm[0x1]; 12137 u8 hard_lifetime_arm[0x1]; 12138 u8 remove_flow_enable[0x1]; 12139 u8 epn_event_arm[0x1]; 12140 u8 reserved_at_a[0x16]; 12141 12142 u8 remove_flow_packet_count[0x20]; 12143 12144 u8 remove_flow_soft_lifetime[0x20]; 12145 12146 u8 reserved_at_60[0x80]; 12147 12148 u8 mode_parameter[0x20]; 12149 12150 u8 replay_protection_window[8][0x20]; 12151 }; 12152 12153 struct mlx5_ifc_macsec_offload_obj_bits { 12154 u8 modify_field_select[0x40]; 12155 12156 u8 confidentiality_en[0x1]; 12157 u8 reserved_at_41[0x1]; 12158 u8 epn_en[0x1]; 12159 u8 epn_overlap[0x1]; 12160 u8 reserved_at_44[0x2]; 12161 u8 confidentiality_offset[0x2]; 12162 u8 reserved_at_48[0x4]; 12163 u8 aso_return_reg[0x4]; 12164 u8 reserved_at_50[0x10]; 12165 12166 u8 epn_msb[0x20]; 12167 12168 u8 reserved_at_80[0x8]; 12169 u8 dekn[0x18]; 12170 12171 u8 reserved_at_a0[0x20]; 12172 12173 u8 sci[0x40]; 12174 12175 u8 reserved_at_100[0x8]; 12176 u8 macsec_aso_access_pd[0x18]; 12177 12178 u8 reserved_at_120[0x60]; 12179 12180 u8 salt[3][0x20]; 12181 12182 u8 reserved_at_1e0[0x20]; 12183 12184 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12185 }; 12186 12187 struct mlx5_ifc_create_macsec_obj_in_bits { 12188 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12189 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12190 }; 12191 12192 struct mlx5_ifc_modify_macsec_obj_in_bits { 12193 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12194 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12195 }; 12196 12197 enum { 12198 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12199 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12200 }; 12201 12202 struct mlx5_ifc_query_macsec_obj_out_bits { 12203 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12204 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12205 }; 12206 12207 struct mlx5_ifc_wrapped_dek_bits { 12208 u8 gcm_iv[0x60]; 12209 12210 u8 reserved_at_60[0x20]; 12211 12212 u8 const0[0x1]; 12213 u8 key_size[0x1]; 12214 u8 reserved_at_82[0x2]; 12215 u8 key2_invalid[0x1]; 12216 u8 reserved_at_85[0x3]; 12217 u8 pd[0x18]; 12218 12219 u8 key_purpose[0x5]; 12220 u8 reserved_at_a5[0x13]; 12221 u8 kek_id[0x8]; 12222 12223 u8 reserved_at_c0[0x40]; 12224 12225 u8 key1[0x8][0x20]; 12226 12227 u8 key2[0x8][0x20]; 12228 12229 u8 reserved_at_300[0x40]; 12230 12231 u8 const1[0x1]; 12232 u8 reserved_at_341[0x1f]; 12233 12234 u8 reserved_at_360[0x20]; 12235 12236 u8 auth_tag[0x80]; 12237 }; 12238 12239 struct mlx5_ifc_encryption_key_obj_bits { 12240 u8 modify_field_select[0x40]; 12241 12242 u8 state[0x8]; 12243 u8 sw_wrapped[0x1]; 12244 u8 reserved_at_49[0xb]; 12245 u8 key_size[0x4]; 12246 u8 reserved_at_58[0x4]; 12247 u8 key_purpose[0x4]; 12248 12249 u8 reserved_at_60[0x8]; 12250 u8 pd[0x18]; 12251 12252 u8 reserved_at_80[0x100]; 12253 12254 u8 opaque[0x40]; 12255 12256 u8 reserved_at_1c0[0x40]; 12257 12258 u8 key[8][0x80]; 12259 12260 u8 sw_wrapped_dek[8][0x80]; 12261 12262 u8 reserved_at_a00[0x600]; 12263 }; 12264 12265 struct mlx5_ifc_create_encryption_key_in_bits { 12266 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12267 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12268 }; 12269 12270 struct mlx5_ifc_modify_encryption_key_in_bits { 12271 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12272 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12273 }; 12274 12275 enum { 12276 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12277 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12278 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12279 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12280 }; 12281 12282 struct mlx5_ifc_flow_meter_parameters_bits { 12283 u8 valid[0x1]; 12284 u8 bucket_overflow[0x1]; 12285 u8 start_color[0x2]; 12286 u8 both_buckets_on_green[0x1]; 12287 u8 reserved_at_5[0x1]; 12288 u8 meter_mode[0x2]; 12289 u8 reserved_at_8[0x18]; 12290 12291 u8 reserved_at_20[0x20]; 12292 12293 u8 reserved_at_40[0x3]; 12294 u8 cbs_exponent[0x5]; 12295 u8 cbs_mantissa[0x8]; 12296 u8 reserved_at_50[0x3]; 12297 u8 cir_exponent[0x5]; 12298 u8 cir_mantissa[0x8]; 12299 12300 u8 reserved_at_60[0x20]; 12301 12302 u8 reserved_at_80[0x3]; 12303 u8 ebs_exponent[0x5]; 12304 u8 ebs_mantissa[0x8]; 12305 u8 reserved_at_90[0x3]; 12306 u8 eir_exponent[0x5]; 12307 u8 eir_mantissa[0x8]; 12308 12309 u8 reserved_at_a0[0x60]; 12310 }; 12311 12312 struct mlx5_ifc_flow_meter_aso_obj_bits { 12313 u8 modify_field_select[0x40]; 12314 12315 u8 reserved_at_40[0x40]; 12316 12317 u8 reserved_at_80[0x8]; 12318 u8 meter_aso_access_pd[0x18]; 12319 12320 u8 reserved_at_a0[0x160]; 12321 12322 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12323 }; 12324 12325 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12326 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12327 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12328 }; 12329 12330 struct mlx5_ifc_int_kek_obj_bits { 12331 u8 modify_field_select[0x40]; 12332 12333 u8 state[0x8]; 12334 u8 auto_gen[0x1]; 12335 u8 reserved_at_49[0xb]; 12336 u8 key_size[0x4]; 12337 u8 reserved_at_58[0x8]; 12338 12339 u8 reserved_at_60[0x8]; 12340 u8 pd[0x18]; 12341 12342 u8 reserved_at_80[0x180]; 12343 u8 key[8][0x80]; 12344 12345 u8 reserved_at_600[0x200]; 12346 }; 12347 12348 struct mlx5_ifc_create_int_kek_obj_in_bits { 12349 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12350 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12351 }; 12352 12353 struct mlx5_ifc_create_int_kek_obj_out_bits { 12354 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12355 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12356 }; 12357 12358 struct mlx5_ifc_sampler_obj_bits { 12359 u8 modify_field_select[0x40]; 12360 12361 u8 table_type[0x8]; 12362 u8 level[0x8]; 12363 u8 reserved_at_50[0xf]; 12364 u8 ignore_flow_level[0x1]; 12365 12366 u8 sample_ratio[0x20]; 12367 12368 u8 reserved_at_80[0x8]; 12369 u8 sample_table_id[0x18]; 12370 12371 u8 reserved_at_a0[0x8]; 12372 u8 default_table_id[0x18]; 12373 12374 u8 sw_steering_icm_address_rx[0x40]; 12375 u8 sw_steering_icm_address_tx[0x40]; 12376 12377 u8 reserved_at_140[0xa0]; 12378 }; 12379 12380 struct mlx5_ifc_create_sampler_obj_in_bits { 12381 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12382 struct mlx5_ifc_sampler_obj_bits sampler_object; 12383 }; 12384 12385 struct mlx5_ifc_query_sampler_obj_out_bits { 12386 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12387 struct mlx5_ifc_sampler_obj_bits sampler_object; 12388 }; 12389 12390 enum { 12391 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12392 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12393 }; 12394 12395 enum { 12396 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12397 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12398 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12399 }; 12400 12401 struct mlx5_ifc_tls_static_params_bits { 12402 u8 const_2[0x2]; 12403 u8 tls_version[0x4]; 12404 u8 const_1[0x2]; 12405 u8 reserved_at_8[0x14]; 12406 u8 encryption_standard[0x4]; 12407 12408 u8 reserved_at_20[0x20]; 12409 12410 u8 initial_record_number[0x40]; 12411 12412 u8 resync_tcp_sn[0x20]; 12413 12414 u8 gcm_iv[0x20]; 12415 12416 u8 implicit_iv[0x40]; 12417 12418 u8 reserved_at_100[0x8]; 12419 u8 dek_index[0x18]; 12420 12421 u8 reserved_at_120[0xe0]; 12422 }; 12423 12424 struct mlx5_ifc_tls_progress_params_bits { 12425 u8 next_record_tcp_sn[0x20]; 12426 12427 u8 hw_resync_tcp_sn[0x20]; 12428 12429 u8 record_tracker_state[0x2]; 12430 u8 auth_state[0x2]; 12431 u8 reserved_at_44[0x4]; 12432 u8 hw_offset_record_number[0x18]; 12433 }; 12434 12435 enum { 12436 MLX5_MTT_PERM_READ = 1 << 0, 12437 MLX5_MTT_PERM_WRITE = 1 << 1, 12438 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12439 }; 12440 12441 enum { 12442 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12443 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12444 }; 12445 12446 struct mlx5_ifc_suspend_vhca_in_bits { 12447 u8 opcode[0x10]; 12448 u8 uid[0x10]; 12449 12450 u8 reserved_at_20[0x10]; 12451 u8 op_mod[0x10]; 12452 12453 u8 reserved_at_40[0x10]; 12454 u8 vhca_id[0x10]; 12455 12456 u8 reserved_at_60[0x20]; 12457 }; 12458 12459 struct mlx5_ifc_suspend_vhca_out_bits { 12460 u8 status[0x8]; 12461 u8 reserved_at_8[0x18]; 12462 12463 u8 syndrome[0x20]; 12464 12465 u8 reserved_at_40[0x40]; 12466 }; 12467 12468 enum { 12469 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12470 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12471 }; 12472 12473 struct mlx5_ifc_resume_vhca_in_bits { 12474 u8 opcode[0x10]; 12475 u8 uid[0x10]; 12476 12477 u8 reserved_at_20[0x10]; 12478 u8 op_mod[0x10]; 12479 12480 u8 reserved_at_40[0x10]; 12481 u8 vhca_id[0x10]; 12482 12483 u8 reserved_at_60[0x20]; 12484 }; 12485 12486 struct mlx5_ifc_resume_vhca_out_bits { 12487 u8 status[0x8]; 12488 u8 reserved_at_8[0x18]; 12489 12490 u8 syndrome[0x20]; 12491 12492 u8 reserved_at_40[0x40]; 12493 }; 12494 12495 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12496 u8 opcode[0x10]; 12497 u8 uid[0x10]; 12498 12499 u8 reserved_at_20[0x10]; 12500 u8 op_mod[0x10]; 12501 12502 u8 incremental[0x1]; 12503 u8 chunk[0x1]; 12504 u8 reserved_at_42[0xe]; 12505 u8 vhca_id[0x10]; 12506 12507 u8 reserved_at_60[0x20]; 12508 }; 12509 12510 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12511 u8 status[0x8]; 12512 u8 reserved_at_8[0x18]; 12513 12514 u8 syndrome[0x20]; 12515 12516 u8 reserved_at_40[0x40]; 12517 12518 u8 required_umem_size[0x20]; 12519 12520 u8 reserved_at_a0[0x20]; 12521 12522 u8 remaining_total_size[0x40]; 12523 12524 u8 reserved_at_100[0x100]; 12525 }; 12526 12527 struct mlx5_ifc_save_vhca_state_in_bits { 12528 u8 opcode[0x10]; 12529 u8 uid[0x10]; 12530 12531 u8 reserved_at_20[0x10]; 12532 u8 op_mod[0x10]; 12533 12534 u8 incremental[0x1]; 12535 u8 set_track[0x1]; 12536 u8 reserved_at_42[0xe]; 12537 u8 vhca_id[0x10]; 12538 12539 u8 reserved_at_60[0x20]; 12540 12541 u8 va[0x40]; 12542 12543 u8 mkey[0x20]; 12544 12545 u8 size[0x20]; 12546 }; 12547 12548 struct mlx5_ifc_save_vhca_state_out_bits { 12549 u8 status[0x8]; 12550 u8 reserved_at_8[0x18]; 12551 12552 u8 syndrome[0x20]; 12553 12554 u8 actual_image_size[0x20]; 12555 12556 u8 next_required_umem_size[0x20]; 12557 }; 12558 12559 struct mlx5_ifc_load_vhca_state_in_bits { 12560 u8 opcode[0x10]; 12561 u8 uid[0x10]; 12562 12563 u8 reserved_at_20[0x10]; 12564 u8 op_mod[0x10]; 12565 12566 u8 reserved_at_40[0x10]; 12567 u8 vhca_id[0x10]; 12568 12569 u8 reserved_at_60[0x20]; 12570 12571 u8 va[0x40]; 12572 12573 u8 mkey[0x20]; 12574 12575 u8 size[0x20]; 12576 }; 12577 12578 struct mlx5_ifc_load_vhca_state_out_bits { 12579 u8 status[0x8]; 12580 u8 reserved_at_8[0x18]; 12581 12582 u8 syndrome[0x20]; 12583 12584 u8 reserved_at_40[0x40]; 12585 }; 12586 12587 struct mlx5_ifc_adv_virtualization_cap_bits { 12588 u8 reserved_at_0[0x3]; 12589 u8 pg_track_log_max_num[0x5]; 12590 u8 pg_track_max_num_range[0x8]; 12591 u8 pg_track_log_min_addr_space[0x8]; 12592 u8 pg_track_log_max_addr_space[0x8]; 12593 12594 u8 reserved_at_20[0x3]; 12595 u8 pg_track_log_min_msg_size[0x5]; 12596 u8 reserved_at_28[0x3]; 12597 u8 pg_track_log_max_msg_size[0x5]; 12598 u8 reserved_at_30[0x3]; 12599 u8 pg_track_log_min_page_size[0x5]; 12600 u8 reserved_at_38[0x3]; 12601 u8 pg_track_log_max_page_size[0x5]; 12602 12603 u8 reserved_at_40[0x7c0]; 12604 }; 12605 12606 struct mlx5_ifc_page_track_report_entry_bits { 12607 u8 dirty_address_high[0x20]; 12608 12609 u8 dirty_address_low[0x20]; 12610 }; 12611 12612 enum { 12613 MLX5_PAGE_TRACK_STATE_TRACKING, 12614 MLX5_PAGE_TRACK_STATE_REPORTING, 12615 MLX5_PAGE_TRACK_STATE_ERROR, 12616 }; 12617 12618 struct mlx5_ifc_page_track_range_bits { 12619 u8 start_address[0x40]; 12620 12621 u8 length[0x40]; 12622 }; 12623 12624 struct mlx5_ifc_page_track_bits { 12625 u8 modify_field_select[0x40]; 12626 12627 u8 reserved_at_40[0x10]; 12628 u8 vhca_id[0x10]; 12629 12630 u8 reserved_at_60[0x20]; 12631 12632 u8 state[0x4]; 12633 u8 track_type[0x4]; 12634 u8 log_addr_space_size[0x8]; 12635 u8 reserved_at_90[0x3]; 12636 u8 log_page_size[0x5]; 12637 u8 reserved_at_98[0x3]; 12638 u8 log_msg_size[0x5]; 12639 12640 u8 reserved_at_a0[0x8]; 12641 u8 reporting_qpn[0x18]; 12642 12643 u8 reserved_at_c0[0x18]; 12644 u8 num_ranges[0x8]; 12645 12646 u8 reserved_at_e0[0x20]; 12647 12648 u8 range_start_address[0x40]; 12649 12650 u8 length[0x40]; 12651 12652 struct mlx5_ifc_page_track_range_bits track_range[0]; 12653 }; 12654 12655 struct mlx5_ifc_create_page_track_obj_in_bits { 12656 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12657 struct mlx5_ifc_page_track_bits obj_context; 12658 }; 12659 12660 struct mlx5_ifc_modify_page_track_obj_in_bits { 12661 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12662 struct mlx5_ifc_page_track_bits obj_context; 12663 }; 12664 12665 struct mlx5_ifc_msecq_reg_bits { 12666 u8 reserved_at_0[0x20]; 12667 12668 u8 reserved_at_20[0x12]; 12669 u8 network_option[0x2]; 12670 u8 local_ssm_code[0x4]; 12671 u8 local_enhanced_ssm_code[0x8]; 12672 12673 u8 local_clock_identity[0x40]; 12674 12675 u8 reserved_at_80[0x180]; 12676 }; 12677 12678 enum { 12679 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 12680 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 12681 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 12682 }; 12683 12684 enum mlx5_msees_admin_status { 12685 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 12686 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 12687 }; 12688 12689 enum mlx5_msees_oper_status { 12690 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 12691 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 12692 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 12693 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 12694 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 12695 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 12696 }; 12697 12698 struct mlx5_ifc_msees_reg_bits { 12699 u8 reserved_at_0[0x8]; 12700 u8 local_port[0x8]; 12701 u8 pnat[0x2]; 12702 u8 lp_msb[0x2]; 12703 u8 reserved_at_14[0xc]; 12704 12705 u8 field_select[0x20]; 12706 12707 u8 admin_status[0x4]; 12708 u8 oper_status[0x4]; 12709 u8 ho_acq[0x1]; 12710 u8 reserved_at_49[0xc]; 12711 u8 admin_freq_measure[0x1]; 12712 u8 oper_freq_measure[0x1]; 12713 u8 failure_reason[0x9]; 12714 12715 u8 frequency_diff[0x20]; 12716 12717 u8 reserved_at_80[0x180]; 12718 }; 12719 12720 #endif /* MLX5_IFC_H */ 12721