1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 97 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 98 MLX5_OBJ_TYPE_MKEY = 0xff01, 99 MLX5_OBJ_TYPE_QP = 0xff02, 100 MLX5_OBJ_TYPE_PSV = 0xff03, 101 MLX5_OBJ_TYPE_RMP = 0xff04, 102 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 103 MLX5_OBJ_TYPE_RQ = 0xff06, 104 MLX5_OBJ_TYPE_SQ = 0xff07, 105 MLX5_OBJ_TYPE_TIR = 0xff08, 106 MLX5_OBJ_TYPE_TIS = 0xff09, 107 MLX5_OBJ_TYPE_DCT = 0xff0a, 108 MLX5_OBJ_TYPE_XRQ = 0xff0b, 109 MLX5_OBJ_TYPE_RQT = 0xff0e, 110 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 111 MLX5_OBJ_TYPE_CQ = 0xff10, 112 }; 113 114 enum { 115 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 116 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 117 MLX5_CMD_OP_INIT_HCA = 0x102, 118 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 119 MLX5_CMD_OP_ENABLE_HCA = 0x104, 120 MLX5_CMD_OP_DISABLE_HCA = 0x105, 121 MLX5_CMD_OP_QUERY_PAGES = 0x107, 122 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 123 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 124 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 125 MLX5_CMD_OP_SET_ISSI = 0x10b, 126 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 127 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 128 MLX5_CMD_OP_ALLOC_SF = 0x113, 129 MLX5_CMD_OP_DEALLOC_SF = 0x114, 130 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 131 MLX5_CMD_OP_RESUME_VHCA = 0x116, 132 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 133 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 134 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 135 MLX5_CMD_OP_CREATE_MKEY = 0x200, 136 MLX5_CMD_OP_QUERY_MKEY = 0x201, 137 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 138 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 139 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 140 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 141 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 142 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 143 MLX5_CMD_OP_CREATE_EQ = 0x301, 144 MLX5_CMD_OP_DESTROY_EQ = 0x302, 145 MLX5_CMD_OP_QUERY_EQ = 0x303, 146 MLX5_CMD_OP_GEN_EQE = 0x304, 147 MLX5_CMD_OP_CREATE_CQ = 0x400, 148 MLX5_CMD_OP_DESTROY_CQ = 0x401, 149 MLX5_CMD_OP_QUERY_CQ = 0x402, 150 MLX5_CMD_OP_MODIFY_CQ = 0x403, 151 MLX5_CMD_OP_CREATE_QP = 0x500, 152 MLX5_CMD_OP_DESTROY_QP = 0x501, 153 MLX5_CMD_OP_RST2INIT_QP = 0x502, 154 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 155 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 156 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 157 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 158 MLX5_CMD_OP_2ERR_QP = 0x507, 159 MLX5_CMD_OP_2RST_QP = 0x50a, 160 MLX5_CMD_OP_QUERY_QP = 0x50b, 161 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 162 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 163 MLX5_CMD_OP_CREATE_PSV = 0x600, 164 MLX5_CMD_OP_DESTROY_PSV = 0x601, 165 MLX5_CMD_OP_CREATE_SRQ = 0x700, 166 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 167 MLX5_CMD_OP_QUERY_SRQ = 0x702, 168 MLX5_CMD_OP_ARM_RQ = 0x703, 169 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 170 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 171 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 172 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 173 MLX5_CMD_OP_CREATE_DCT = 0x710, 174 MLX5_CMD_OP_DESTROY_DCT = 0x711, 175 MLX5_CMD_OP_DRAIN_DCT = 0x712, 176 MLX5_CMD_OP_QUERY_DCT = 0x713, 177 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 178 MLX5_CMD_OP_CREATE_XRQ = 0x717, 179 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 180 MLX5_CMD_OP_QUERY_XRQ = 0x719, 181 MLX5_CMD_OP_ARM_XRQ = 0x71a, 182 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 183 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 184 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 185 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 186 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 187 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 188 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 189 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 190 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 191 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 192 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 193 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 194 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 195 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 196 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 197 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 198 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 200 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 201 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 202 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 203 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 204 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 205 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 206 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 207 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 208 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 209 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 210 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 211 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 212 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 213 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 214 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 215 MLX5_CMD_OP_ALLOC_PD = 0x800, 216 MLX5_CMD_OP_DEALLOC_PD = 0x801, 217 MLX5_CMD_OP_ALLOC_UAR = 0x802, 218 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 219 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 220 MLX5_CMD_OP_ACCESS_REG = 0x805, 221 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 222 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 223 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 224 MLX5_CMD_OP_MAD_IFC = 0x50d, 225 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 226 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 227 MLX5_CMD_OP_NOP = 0x80d, 228 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 229 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 230 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 231 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 232 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 233 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 234 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 235 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 236 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 237 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 238 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 239 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 240 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 241 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 242 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 243 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 244 MLX5_CMD_OP_CREATE_LAG = 0x840, 245 MLX5_CMD_OP_MODIFY_LAG = 0x841, 246 MLX5_CMD_OP_QUERY_LAG = 0x842, 247 MLX5_CMD_OP_DESTROY_LAG = 0x843, 248 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 249 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 250 MLX5_CMD_OP_CREATE_TIR = 0x900, 251 MLX5_CMD_OP_MODIFY_TIR = 0x901, 252 MLX5_CMD_OP_DESTROY_TIR = 0x902, 253 MLX5_CMD_OP_QUERY_TIR = 0x903, 254 MLX5_CMD_OP_CREATE_SQ = 0x904, 255 MLX5_CMD_OP_MODIFY_SQ = 0x905, 256 MLX5_CMD_OP_DESTROY_SQ = 0x906, 257 MLX5_CMD_OP_QUERY_SQ = 0x907, 258 MLX5_CMD_OP_CREATE_RQ = 0x908, 259 MLX5_CMD_OP_MODIFY_RQ = 0x909, 260 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 261 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 262 MLX5_CMD_OP_QUERY_RQ = 0x90b, 263 MLX5_CMD_OP_CREATE_RMP = 0x90c, 264 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 265 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 266 MLX5_CMD_OP_QUERY_RMP = 0x90f, 267 MLX5_CMD_OP_CREATE_TIS = 0x912, 268 MLX5_CMD_OP_MODIFY_TIS = 0x913, 269 MLX5_CMD_OP_DESTROY_TIS = 0x914, 270 MLX5_CMD_OP_QUERY_TIS = 0x915, 271 MLX5_CMD_OP_CREATE_RQT = 0x916, 272 MLX5_CMD_OP_MODIFY_RQT = 0x917, 273 MLX5_CMD_OP_DESTROY_RQT = 0x918, 274 MLX5_CMD_OP_QUERY_RQT = 0x919, 275 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 276 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 277 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 278 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 279 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 280 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 281 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 282 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 283 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 284 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 285 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 286 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 287 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 288 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 289 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 290 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 291 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 292 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 293 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 294 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 295 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 296 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 297 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 298 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 299 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 300 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 301 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 302 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 303 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 304 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 305 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 306 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 307 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 308 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 309 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 310 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 311 MLX5_CMD_OP_MAX 312 }; 313 314 /* Valid range for general commands that don't work over an object */ 315 enum { 316 MLX5_CMD_OP_GENERAL_START = 0xb00, 317 MLX5_CMD_OP_GENERAL_END = 0xd00, 318 }; 319 320 struct mlx5_ifc_flow_table_fields_supported_bits { 321 u8 outer_dmac[0x1]; 322 u8 outer_smac[0x1]; 323 u8 outer_ether_type[0x1]; 324 u8 outer_ip_version[0x1]; 325 u8 outer_first_prio[0x1]; 326 u8 outer_first_cfi[0x1]; 327 u8 outer_first_vid[0x1]; 328 u8 outer_ipv4_ttl[0x1]; 329 u8 outer_second_prio[0x1]; 330 u8 outer_second_cfi[0x1]; 331 u8 outer_second_vid[0x1]; 332 u8 reserved_at_b[0x1]; 333 u8 outer_sip[0x1]; 334 u8 outer_dip[0x1]; 335 u8 outer_frag[0x1]; 336 u8 outer_ip_protocol[0x1]; 337 u8 outer_ip_ecn[0x1]; 338 u8 outer_ip_dscp[0x1]; 339 u8 outer_udp_sport[0x1]; 340 u8 outer_udp_dport[0x1]; 341 u8 outer_tcp_sport[0x1]; 342 u8 outer_tcp_dport[0x1]; 343 u8 outer_tcp_flags[0x1]; 344 u8 outer_gre_protocol[0x1]; 345 u8 outer_gre_key[0x1]; 346 u8 outer_vxlan_vni[0x1]; 347 u8 outer_geneve_vni[0x1]; 348 u8 outer_geneve_oam[0x1]; 349 u8 outer_geneve_protocol_type[0x1]; 350 u8 outer_geneve_opt_len[0x1]; 351 u8 source_vhca_port[0x1]; 352 u8 source_eswitch_port[0x1]; 353 354 u8 inner_dmac[0x1]; 355 u8 inner_smac[0x1]; 356 u8 inner_ether_type[0x1]; 357 u8 inner_ip_version[0x1]; 358 u8 inner_first_prio[0x1]; 359 u8 inner_first_cfi[0x1]; 360 u8 inner_first_vid[0x1]; 361 u8 reserved_at_27[0x1]; 362 u8 inner_second_prio[0x1]; 363 u8 inner_second_cfi[0x1]; 364 u8 inner_second_vid[0x1]; 365 u8 reserved_at_2b[0x1]; 366 u8 inner_sip[0x1]; 367 u8 inner_dip[0x1]; 368 u8 inner_frag[0x1]; 369 u8 inner_ip_protocol[0x1]; 370 u8 inner_ip_ecn[0x1]; 371 u8 inner_ip_dscp[0x1]; 372 u8 inner_udp_sport[0x1]; 373 u8 inner_udp_dport[0x1]; 374 u8 inner_tcp_sport[0x1]; 375 u8 inner_tcp_dport[0x1]; 376 u8 inner_tcp_flags[0x1]; 377 u8 reserved_at_37[0x9]; 378 379 u8 geneve_tlv_option_0_data[0x1]; 380 u8 geneve_tlv_option_0_exist[0x1]; 381 u8 reserved_at_42[0x3]; 382 u8 outer_first_mpls_over_udp[0x4]; 383 u8 outer_first_mpls_over_gre[0x4]; 384 u8 inner_first_mpls[0x4]; 385 u8 outer_first_mpls[0x4]; 386 u8 reserved_at_55[0x2]; 387 u8 outer_esp_spi[0x1]; 388 u8 reserved_at_58[0x2]; 389 u8 bth_dst_qp[0x1]; 390 u8 reserved_at_5b[0x5]; 391 392 u8 reserved_at_60[0x18]; 393 u8 metadata_reg_c_7[0x1]; 394 u8 metadata_reg_c_6[0x1]; 395 u8 metadata_reg_c_5[0x1]; 396 u8 metadata_reg_c_4[0x1]; 397 u8 metadata_reg_c_3[0x1]; 398 u8 metadata_reg_c_2[0x1]; 399 u8 metadata_reg_c_1[0x1]; 400 u8 metadata_reg_c_0[0x1]; 401 }; 402 403 struct mlx5_ifc_flow_table_fields_supported_2_bits { 404 u8 reserved_at_0[0xe]; 405 u8 bth_opcode[0x1]; 406 u8 reserved_at_f[0x11]; 407 408 u8 reserved_at_20[0x60]; 409 }; 410 411 struct mlx5_ifc_flow_table_prop_layout_bits { 412 u8 ft_support[0x1]; 413 u8 reserved_at_1[0x1]; 414 u8 flow_counter[0x1]; 415 u8 flow_modify_en[0x1]; 416 u8 modify_root[0x1]; 417 u8 identified_miss_table_mode[0x1]; 418 u8 flow_table_modify[0x1]; 419 u8 reformat[0x1]; 420 u8 decap[0x1]; 421 u8 reserved_at_9[0x1]; 422 u8 pop_vlan[0x1]; 423 u8 push_vlan[0x1]; 424 u8 reserved_at_c[0x1]; 425 u8 pop_vlan_2[0x1]; 426 u8 push_vlan_2[0x1]; 427 u8 reformat_and_vlan_action[0x1]; 428 u8 reserved_at_10[0x1]; 429 u8 sw_owner[0x1]; 430 u8 reformat_l3_tunnel_to_l2[0x1]; 431 u8 reformat_l2_to_l3_tunnel[0x1]; 432 u8 reformat_and_modify_action[0x1]; 433 u8 ignore_flow_level[0x1]; 434 u8 reserved_at_16[0x1]; 435 u8 table_miss_action_domain[0x1]; 436 u8 termination_table[0x1]; 437 u8 reformat_and_fwd_to_table[0x1]; 438 u8 reserved_at_1a[0x2]; 439 u8 ipsec_encrypt[0x1]; 440 u8 ipsec_decrypt[0x1]; 441 u8 sw_owner_v2[0x1]; 442 u8 reserved_at_1f[0x1]; 443 444 u8 termination_table_raw_traffic[0x1]; 445 u8 reserved_at_21[0x1]; 446 u8 log_max_ft_size[0x6]; 447 u8 log_max_modify_header_context[0x8]; 448 u8 max_modify_header_actions[0x8]; 449 u8 max_ft_level[0x8]; 450 451 u8 reserved_at_40[0x20]; 452 453 u8 reserved_at_60[0x2]; 454 u8 reformat_insert[0x1]; 455 u8 reformat_remove[0x1]; 456 u8 reserver_at_64[0x14]; 457 u8 log_max_ft_num[0x8]; 458 459 u8 reserved_at_80[0x10]; 460 u8 log_max_flow_counter[0x8]; 461 u8 log_max_destination[0x8]; 462 463 u8 reserved_at_a0[0x18]; 464 u8 log_max_flow[0x8]; 465 466 u8 reserved_at_c0[0x40]; 467 468 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 469 470 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 471 }; 472 473 struct mlx5_ifc_odp_per_transport_service_cap_bits { 474 u8 send[0x1]; 475 u8 receive[0x1]; 476 u8 write[0x1]; 477 u8 read[0x1]; 478 u8 atomic[0x1]; 479 u8 srq_receive[0x1]; 480 u8 reserved_at_6[0x1a]; 481 }; 482 483 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 484 u8 smac_47_16[0x20]; 485 486 u8 smac_15_0[0x10]; 487 u8 ethertype[0x10]; 488 489 u8 dmac_47_16[0x20]; 490 491 u8 dmac_15_0[0x10]; 492 u8 first_prio[0x3]; 493 u8 first_cfi[0x1]; 494 u8 first_vid[0xc]; 495 496 u8 ip_protocol[0x8]; 497 u8 ip_dscp[0x6]; 498 u8 ip_ecn[0x2]; 499 u8 cvlan_tag[0x1]; 500 u8 svlan_tag[0x1]; 501 u8 frag[0x1]; 502 u8 ip_version[0x4]; 503 u8 tcp_flags[0x9]; 504 505 u8 tcp_sport[0x10]; 506 u8 tcp_dport[0x10]; 507 508 u8 reserved_at_c0[0x18]; 509 u8 ttl_hoplimit[0x8]; 510 511 u8 udp_sport[0x10]; 512 u8 udp_dport[0x10]; 513 514 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 515 516 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 517 }; 518 519 struct mlx5_ifc_nvgre_key_bits { 520 u8 hi[0x18]; 521 u8 lo[0x8]; 522 }; 523 524 union mlx5_ifc_gre_key_bits { 525 struct mlx5_ifc_nvgre_key_bits nvgre; 526 u8 key[0x20]; 527 }; 528 529 struct mlx5_ifc_fte_match_set_misc_bits { 530 u8 gre_c_present[0x1]; 531 u8 reserved_at_1[0x1]; 532 u8 gre_k_present[0x1]; 533 u8 gre_s_present[0x1]; 534 u8 source_vhca_port[0x4]; 535 u8 source_sqn[0x18]; 536 537 u8 source_eswitch_owner_vhca_id[0x10]; 538 u8 source_port[0x10]; 539 540 u8 outer_second_prio[0x3]; 541 u8 outer_second_cfi[0x1]; 542 u8 outer_second_vid[0xc]; 543 u8 inner_second_prio[0x3]; 544 u8 inner_second_cfi[0x1]; 545 u8 inner_second_vid[0xc]; 546 547 u8 outer_second_cvlan_tag[0x1]; 548 u8 inner_second_cvlan_tag[0x1]; 549 u8 outer_second_svlan_tag[0x1]; 550 u8 inner_second_svlan_tag[0x1]; 551 u8 reserved_at_64[0xc]; 552 u8 gre_protocol[0x10]; 553 554 union mlx5_ifc_gre_key_bits gre_key; 555 556 u8 vxlan_vni[0x18]; 557 u8 bth_opcode[0x8]; 558 559 u8 geneve_vni[0x18]; 560 u8 reserved_at_d8[0x6]; 561 u8 geneve_tlv_option_0_exist[0x1]; 562 u8 geneve_oam[0x1]; 563 564 u8 reserved_at_e0[0xc]; 565 u8 outer_ipv6_flow_label[0x14]; 566 567 u8 reserved_at_100[0xc]; 568 u8 inner_ipv6_flow_label[0x14]; 569 570 u8 reserved_at_120[0xa]; 571 u8 geneve_opt_len[0x6]; 572 u8 geneve_protocol_type[0x10]; 573 574 u8 reserved_at_140[0x8]; 575 u8 bth_dst_qp[0x18]; 576 u8 reserved_at_160[0x20]; 577 u8 outer_esp_spi[0x20]; 578 u8 reserved_at_1a0[0x60]; 579 }; 580 581 struct mlx5_ifc_fte_match_mpls_bits { 582 u8 mpls_label[0x14]; 583 u8 mpls_exp[0x3]; 584 u8 mpls_s_bos[0x1]; 585 u8 mpls_ttl[0x8]; 586 }; 587 588 struct mlx5_ifc_fte_match_set_misc2_bits { 589 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 590 591 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 592 593 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 594 595 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 596 597 u8 metadata_reg_c_7[0x20]; 598 599 u8 metadata_reg_c_6[0x20]; 600 601 u8 metadata_reg_c_5[0x20]; 602 603 u8 metadata_reg_c_4[0x20]; 604 605 u8 metadata_reg_c_3[0x20]; 606 607 u8 metadata_reg_c_2[0x20]; 608 609 u8 metadata_reg_c_1[0x20]; 610 611 u8 metadata_reg_c_0[0x20]; 612 613 u8 metadata_reg_a[0x20]; 614 615 u8 reserved_at_1a0[0x60]; 616 }; 617 618 struct mlx5_ifc_fte_match_set_misc3_bits { 619 u8 inner_tcp_seq_num[0x20]; 620 621 u8 outer_tcp_seq_num[0x20]; 622 623 u8 inner_tcp_ack_num[0x20]; 624 625 u8 outer_tcp_ack_num[0x20]; 626 627 u8 reserved_at_80[0x8]; 628 u8 outer_vxlan_gpe_vni[0x18]; 629 630 u8 outer_vxlan_gpe_next_protocol[0x8]; 631 u8 outer_vxlan_gpe_flags[0x8]; 632 u8 reserved_at_b0[0x10]; 633 634 u8 icmp_header_data[0x20]; 635 636 u8 icmpv6_header_data[0x20]; 637 638 u8 icmp_type[0x8]; 639 u8 icmp_code[0x8]; 640 u8 icmpv6_type[0x8]; 641 u8 icmpv6_code[0x8]; 642 643 u8 geneve_tlv_option_0_data[0x20]; 644 645 u8 gtpu_teid[0x20]; 646 647 u8 gtpu_msg_type[0x8]; 648 u8 gtpu_msg_flags[0x8]; 649 u8 reserved_at_170[0x10]; 650 651 u8 gtpu_dw_2[0x20]; 652 653 u8 gtpu_first_ext_dw_0[0x20]; 654 655 u8 gtpu_dw_0[0x20]; 656 657 u8 reserved_at_1e0[0x20]; 658 }; 659 660 struct mlx5_ifc_fte_match_set_misc4_bits { 661 u8 prog_sample_field_value_0[0x20]; 662 663 u8 prog_sample_field_id_0[0x20]; 664 665 u8 prog_sample_field_value_1[0x20]; 666 667 u8 prog_sample_field_id_1[0x20]; 668 669 u8 prog_sample_field_value_2[0x20]; 670 671 u8 prog_sample_field_id_2[0x20]; 672 673 u8 prog_sample_field_value_3[0x20]; 674 675 u8 prog_sample_field_id_3[0x20]; 676 677 u8 reserved_at_100[0x100]; 678 }; 679 680 struct mlx5_ifc_fte_match_set_misc5_bits { 681 u8 macsec_tag_0[0x20]; 682 683 u8 macsec_tag_1[0x20]; 684 685 u8 macsec_tag_2[0x20]; 686 687 u8 macsec_tag_3[0x20]; 688 689 u8 tunnel_header_0[0x20]; 690 691 u8 tunnel_header_1[0x20]; 692 693 u8 tunnel_header_2[0x20]; 694 695 u8 tunnel_header_3[0x20]; 696 697 u8 reserved_at_100[0x100]; 698 }; 699 700 struct mlx5_ifc_cmd_pas_bits { 701 u8 pa_h[0x20]; 702 703 u8 pa_l[0x14]; 704 u8 reserved_at_34[0xc]; 705 }; 706 707 struct mlx5_ifc_uint64_bits { 708 u8 hi[0x20]; 709 710 u8 lo[0x20]; 711 }; 712 713 enum { 714 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 715 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 716 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 717 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 718 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 719 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 720 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 721 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 722 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 723 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 724 }; 725 726 struct mlx5_ifc_ads_bits { 727 u8 fl[0x1]; 728 u8 free_ar[0x1]; 729 u8 reserved_at_2[0xe]; 730 u8 pkey_index[0x10]; 731 732 u8 reserved_at_20[0x8]; 733 u8 grh[0x1]; 734 u8 mlid[0x7]; 735 u8 rlid[0x10]; 736 737 u8 ack_timeout[0x5]; 738 u8 reserved_at_45[0x3]; 739 u8 src_addr_index[0x8]; 740 u8 reserved_at_50[0x4]; 741 u8 stat_rate[0x4]; 742 u8 hop_limit[0x8]; 743 744 u8 reserved_at_60[0x4]; 745 u8 tclass[0x8]; 746 u8 flow_label[0x14]; 747 748 u8 rgid_rip[16][0x8]; 749 750 u8 reserved_at_100[0x4]; 751 u8 f_dscp[0x1]; 752 u8 f_ecn[0x1]; 753 u8 reserved_at_106[0x1]; 754 u8 f_eth_prio[0x1]; 755 u8 ecn[0x2]; 756 u8 dscp[0x6]; 757 u8 udp_sport[0x10]; 758 759 u8 dei_cfi[0x1]; 760 u8 eth_prio[0x3]; 761 u8 sl[0x4]; 762 u8 vhca_port_num[0x8]; 763 u8 rmac_47_32[0x10]; 764 765 u8 rmac_31_0[0x20]; 766 }; 767 768 struct mlx5_ifc_flow_table_nic_cap_bits { 769 u8 nic_rx_multi_path_tirs[0x1]; 770 u8 nic_rx_multi_path_tirs_fts[0x1]; 771 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 772 u8 reserved_at_3[0x4]; 773 u8 sw_owner_reformat_supported[0x1]; 774 u8 reserved_at_8[0x18]; 775 776 u8 encap_general_header[0x1]; 777 u8 reserved_at_21[0xa]; 778 u8 log_max_packet_reformat_context[0x5]; 779 u8 reserved_at_30[0x6]; 780 u8 max_encap_header_size[0xa]; 781 u8 reserved_at_40[0x1c0]; 782 783 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 784 785 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 786 787 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 788 789 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 790 791 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 792 793 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 794 795 u8 reserved_at_e00[0x700]; 796 797 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 798 799 u8 reserved_at_1580[0x280]; 800 801 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 802 803 u8 reserved_at_1880[0x780]; 804 805 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 806 807 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 808 809 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 810 811 u8 reserved_at_20c0[0x5f40]; 812 }; 813 814 struct mlx5_ifc_port_selection_cap_bits { 815 u8 reserved_at_0[0x10]; 816 u8 port_select_flow_table[0x1]; 817 u8 reserved_at_11[0xf]; 818 819 u8 reserved_at_20[0x1e0]; 820 821 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 822 823 u8 reserved_at_400[0x7c00]; 824 }; 825 826 enum { 827 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 828 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 829 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 830 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 831 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 832 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 833 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 834 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 835 }; 836 837 struct mlx5_ifc_flow_table_eswitch_cap_bits { 838 u8 fdb_to_vport_reg_c_id[0x8]; 839 u8 reserved_at_8[0xd]; 840 u8 fdb_modify_header_fwd_to_table[0x1]; 841 u8 fdb_ipv4_ttl_modify[0x1]; 842 u8 flow_source[0x1]; 843 u8 reserved_at_18[0x2]; 844 u8 multi_fdb_encap[0x1]; 845 u8 egress_acl_forward_to_vport[0x1]; 846 u8 fdb_multi_path_to_table[0x1]; 847 u8 reserved_at_1d[0x3]; 848 849 u8 reserved_at_20[0x1e0]; 850 851 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 852 853 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 854 855 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 856 857 u8 reserved_at_800[0x1000]; 858 859 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 860 861 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 862 863 u8 sw_steering_uplink_icm_address_rx[0x40]; 864 865 u8 sw_steering_uplink_icm_address_tx[0x40]; 866 867 u8 reserved_at_1900[0x6700]; 868 }; 869 870 enum { 871 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 872 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 873 }; 874 875 struct mlx5_ifc_e_switch_cap_bits { 876 u8 vport_svlan_strip[0x1]; 877 u8 vport_cvlan_strip[0x1]; 878 u8 vport_svlan_insert[0x1]; 879 u8 vport_cvlan_insert_if_not_exist[0x1]; 880 u8 vport_cvlan_insert_overwrite[0x1]; 881 u8 reserved_at_5[0x2]; 882 u8 esw_shared_ingress_acl[0x1]; 883 u8 esw_uplink_ingress_acl[0x1]; 884 u8 root_ft_on_other_esw[0x1]; 885 u8 reserved_at_a[0xf]; 886 u8 esw_functions_changed[0x1]; 887 u8 reserved_at_1a[0x1]; 888 u8 ecpf_vport_exists[0x1]; 889 u8 counter_eswitch_affinity[0x1]; 890 u8 merged_eswitch[0x1]; 891 u8 nic_vport_node_guid_modify[0x1]; 892 u8 nic_vport_port_guid_modify[0x1]; 893 894 u8 vxlan_encap_decap[0x1]; 895 u8 nvgre_encap_decap[0x1]; 896 u8 reserved_at_22[0x1]; 897 u8 log_max_fdb_encap_uplink[0x5]; 898 u8 reserved_at_21[0x3]; 899 u8 log_max_packet_reformat_context[0x5]; 900 u8 reserved_2b[0x6]; 901 u8 max_encap_header_size[0xa]; 902 903 u8 reserved_at_40[0xb]; 904 u8 log_max_esw_sf[0x5]; 905 u8 esw_sf_base_id[0x10]; 906 907 u8 reserved_at_60[0x7a0]; 908 909 }; 910 911 struct mlx5_ifc_qos_cap_bits { 912 u8 packet_pacing[0x1]; 913 u8 esw_scheduling[0x1]; 914 u8 esw_bw_share[0x1]; 915 u8 esw_rate_limit[0x1]; 916 u8 reserved_at_4[0x1]; 917 u8 packet_pacing_burst_bound[0x1]; 918 u8 packet_pacing_typical_size[0x1]; 919 u8 reserved_at_7[0x1]; 920 u8 nic_sq_scheduling[0x1]; 921 u8 nic_bw_share[0x1]; 922 u8 nic_rate_limit[0x1]; 923 u8 packet_pacing_uid[0x1]; 924 u8 log_esw_max_sched_depth[0x4]; 925 u8 reserved_at_10[0x10]; 926 927 u8 reserved_at_20[0xb]; 928 u8 log_max_qos_nic_queue_group[0x5]; 929 u8 reserved_at_30[0x10]; 930 931 u8 packet_pacing_max_rate[0x20]; 932 933 u8 packet_pacing_min_rate[0x20]; 934 935 u8 reserved_at_80[0x10]; 936 u8 packet_pacing_rate_table_size[0x10]; 937 938 u8 esw_element_type[0x10]; 939 u8 esw_tsar_type[0x10]; 940 941 u8 reserved_at_c0[0x10]; 942 u8 max_qos_para_vport[0x10]; 943 944 u8 max_tsar_bw_share[0x20]; 945 946 u8 reserved_at_100[0x700]; 947 }; 948 949 struct mlx5_ifc_debug_cap_bits { 950 u8 core_dump_general[0x1]; 951 u8 core_dump_qp[0x1]; 952 u8 reserved_at_2[0x7]; 953 u8 resource_dump[0x1]; 954 u8 reserved_at_a[0x16]; 955 956 u8 reserved_at_20[0x2]; 957 u8 stall_detect[0x1]; 958 u8 reserved_at_23[0x1d]; 959 960 u8 reserved_at_40[0x7c0]; 961 }; 962 963 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 964 u8 csum_cap[0x1]; 965 u8 vlan_cap[0x1]; 966 u8 lro_cap[0x1]; 967 u8 lro_psh_flag[0x1]; 968 u8 lro_time_stamp[0x1]; 969 u8 reserved_at_5[0x2]; 970 u8 wqe_vlan_insert[0x1]; 971 u8 self_lb_en_modifiable[0x1]; 972 u8 reserved_at_9[0x2]; 973 u8 max_lso_cap[0x5]; 974 u8 multi_pkt_send_wqe[0x2]; 975 u8 wqe_inline_mode[0x2]; 976 u8 rss_ind_tbl_cap[0x4]; 977 u8 reg_umr_sq[0x1]; 978 u8 scatter_fcs[0x1]; 979 u8 enhanced_multi_pkt_send_wqe[0x1]; 980 u8 tunnel_lso_const_out_ip_id[0x1]; 981 u8 tunnel_lro_gre[0x1]; 982 u8 tunnel_lro_vxlan[0x1]; 983 u8 tunnel_stateless_gre[0x1]; 984 u8 tunnel_stateless_vxlan[0x1]; 985 986 u8 swp[0x1]; 987 u8 swp_csum[0x1]; 988 u8 swp_lso[0x1]; 989 u8 cqe_checksum_full[0x1]; 990 u8 tunnel_stateless_geneve_tx[0x1]; 991 u8 tunnel_stateless_mpls_over_udp[0x1]; 992 u8 tunnel_stateless_mpls_over_gre[0x1]; 993 u8 tunnel_stateless_vxlan_gpe[0x1]; 994 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 995 u8 tunnel_stateless_ip_over_ip[0x1]; 996 u8 insert_trailer[0x1]; 997 u8 reserved_at_2b[0x1]; 998 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 999 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1000 u8 reserved_at_2e[0x2]; 1001 u8 max_vxlan_udp_ports[0x8]; 1002 u8 reserved_at_38[0x6]; 1003 u8 max_geneve_opt_len[0x1]; 1004 u8 tunnel_stateless_geneve_rx[0x1]; 1005 1006 u8 reserved_at_40[0x10]; 1007 u8 lro_min_mss_size[0x10]; 1008 1009 u8 reserved_at_60[0x120]; 1010 1011 u8 lro_timer_supported_periods[4][0x20]; 1012 1013 u8 reserved_at_200[0x600]; 1014 }; 1015 1016 enum { 1017 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1018 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1019 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1020 }; 1021 1022 struct mlx5_ifc_roce_cap_bits { 1023 u8 roce_apm[0x1]; 1024 u8 reserved_at_1[0x3]; 1025 u8 sw_r_roce_src_udp_port[0x1]; 1026 u8 fl_rc_qp_when_roce_disabled[0x1]; 1027 u8 fl_rc_qp_when_roce_enabled[0x1]; 1028 u8 reserved_at_7[0x17]; 1029 u8 qp_ts_format[0x2]; 1030 1031 u8 reserved_at_20[0x60]; 1032 1033 u8 reserved_at_80[0xc]; 1034 u8 l3_type[0x4]; 1035 u8 reserved_at_90[0x8]; 1036 u8 roce_version[0x8]; 1037 1038 u8 reserved_at_a0[0x10]; 1039 u8 r_roce_dest_udp_port[0x10]; 1040 1041 u8 r_roce_max_src_udp_port[0x10]; 1042 u8 r_roce_min_src_udp_port[0x10]; 1043 1044 u8 reserved_at_e0[0x10]; 1045 u8 roce_address_table_size[0x10]; 1046 1047 u8 reserved_at_100[0x700]; 1048 }; 1049 1050 struct mlx5_ifc_sync_steering_in_bits { 1051 u8 opcode[0x10]; 1052 u8 uid[0x10]; 1053 1054 u8 reserved_at_20[0x10]; 1055 u8 op_mod[0x10]; 1056 1057 u8 reserved_at_40[0xc0]; 1058 }; 1059 1060 struct mlx5_ifc_sync_steering_out_bits { 1061 u8 status[0x8]; 1062 u8 reserved_at_8[0x18]; 1063 1064 u8 syndrome[0x20]; 1065 1066 u8 reserved_at_40[0x40]; 1067 }; 1068 1069 struct mlx5_ifc_device_mem_cap_bits { 1070 u8 memic[0x1]; 1071 u8 reserved_at_1[0x1f]; 1072 1073 u8 reserved_at_20[0xb]; 1074 u8 log_min_memic_alloc_size[0x5]; 1075 u8 reserved_at_30[0x8]; 1076 u8 log_max_memic_addr_alignment[0x8]; 1077 1078 u8 memic_bar_start_addr[0x40]; 1079 1080 u8 memic_bar_size[0x20]; 1081 1082 u8 max_memic_size[0x20]; 1083 1084 u8 steering_sw_icm_start_address[0x40]; 1085 1086 u8 reserved_at_100[0x8]; 1087 u8 log_header_modify_sw_icm_size[0x8]; 1088 u8 reserved_at_110[0x2]; 1089 u8 log_sw_icm_alloc_granularity[0x6]; 1090 u8 log_steering_sw_icm_size[0x8]; 1091 1092 u8 reserved_at_120[0x20]; 1093 1094 u8 header_modify_sw_icm_start_address[0x40]; 1095 1096 u8 reserved_at_180[0x80]; 1097 1098 u8 memic_operations[0x20]; 1099 1100 u8 reserved_at_220[0x5e0]; 1101 }; 1102 1103 struct mlx5_ifc_device_event_cap_bits { 1104 u8 user_affiliated_events[4][0x40]; 1105 1106 u8 user_unaffiliated_events[4][0x40]; 1107 }; 1108 1109 struct mlx5_ifc_virtio_emulation_cap_bits { 1110 u8 desc_tunnel_offload_type[0x1]; 1111 u8 eth_frame_offload_type[0x1]; 1112 u8 virtio_version_1_0[0x1]; 1113 u8 device_features_bits_mask[0xd]; 1114 u8 event_mode[0x8]; 1115 u8 virtio_queue_type[0x8]; 1116 1117 u8 max_tunnel_desc[0x10]; 1118 u8 reserved_at_30[0x3]; 1119 u8 log_doorbell_stride[0x5]; 1120 u8 reserved_at_38[0x3]; 1121 u8 log_doorbell_bar_size[0x5]; 1122 1123 u8 doorbell_bar_offset[0x40]; 1124 1125 u8 max_emulated_devices[0x8]; 1126 u8 max_num_virtio_queues[0x18]; 1127 1128 u8 reserved_at_a0[0x60]; 1129 1130 u8 umem_1_buffer_param_a[0x20]; 1131 1132 u8 umem_1_buffer_param_b[0x20]; 1133 1134 u8 umem_2_buffer_param_a[0x20]; 1135 1136 u8 umem_2_buffer_param_b[0x20]; 1137 1138 u8 umem_3_buffer_param_a[0x20]; 1139 1140 u8 umem_3_buffer_param_b[0x20]; 1141 1142 u8 reserved_at_1c0[0x640]; 1143 }; 1144 1145 enum { 1146 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1147 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1148 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1149 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1150 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1151 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1152 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1153 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1154 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1155 }; 1156 1157 enum { 1158 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1159 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1160 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1161 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1162 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1163 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1164 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1165 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1166 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1167 }; 1168 1169 struct mlx5_ifc_atomic_caps_bits { 1170 u8 reserved_at_0[0x40]; 1171 1172 u8 atomic_req_8B_endianness_mode[0x2]; 1173 u8 reserved_at_42[0x4]; 1174 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1175 1176 u8 reserved_at_47[0x19]; 1177 1178 u8 reserved_at_60[0x20]; 1179 1180 u8 reserved_at_80[0x10]; 1181 u8 atomic_operations[0x10]; 1182 1183 u8 reserved_at_a0[0x10]; 1184 u8 atomic_size_qp[0x10]; 1185 1186 u8 reserved_at_c0[0x10]; 1187 u8 atomic_size_dc[0x10]; 1188 1189 u8 reserved_at_e0[0x720]; 1190 }; 1191 1192 struct mlx5_ifc_odp_cap_bits { 1193 u8 reserved_at_0[0x40]; 1194 1195 u8 sig[0x1]; 1196 u8 reserved_at_41[0x1f]; 1197 1198 u8 reserved_at_60[0x20]; 1199 1200 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1201 1202 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1203 1204 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1205 1206 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1207 1208 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1209 1210 u8 reserved_at_120[0x6E0]; 1211 }; 1212 1213 struct mlx5_ifc_calc_op { 1214 u8 reserved_at_0[0x10]; 1215 u8 reserved_at_10[0x9]; 1216 u8 op_swap_endianness[0x1]; 1217 u8 op_min[0x1]; 1218 u8 op_xor[0x1]; 1219 u8 op_or[0x1]; 1220 u8 op_and[0x1]; 1221 u8 op_max[0x1]; 1222 u8 op_add[0x1]; 1223 }; 1224 1225 struct mlx5_ifc_vector_calc_cap_bits { 1226 u8 calc_matrix[0x1]; 1227 u8 reserved_at_1[0x1f]; 1228 u8 reserved_at_20[0x8]; 1229 u8 max_vec_count[0x8]; 1230 u8 reserved_at_30[0xd]; 1231 u8 max_chunk_size[0x3]; 1232 struct mlx5_ifc_calc_op calc0; 1233 struct mlx5_ifc_calc_op calc1; 1234 struct mlx5_ifc_calc_op calc2; 1235 struct mlx5_ifc_calc_op calc3; 1236 1237 u8 reserved_at_c0[0x720]; 1238 }; 1239 1240 struct mlx5_ifc_tls_cap_bits { 1241 u8 tls_1_2_aes_gcm_128[0x1]; 1242 u8 tls_1_3_aes_gcm_128[0x1]; 1243 u8 tls_1_2_aes_gcm_256[0x1]; 1244 u8 tls_1_3_aes_gcm_256[0x1]; 1245 u8 reserved_at_4[0x1c]; 1246 1247 u8 reserved_at_20[0x7e0]; 1248 }; 1249 1250 struct mlx5_ifc_ipsec_cap_bits { 1251 u8 ipsec_full_offload[0x1]; 1252 u8 ipsec_crypto_offload[0x1]; 1253 u8 ipsec_esn[0x1]; 1254 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1255 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1256 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1257 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1258 u8 reserved_at_7[0x4]; 1259 u8 log_max_ipsec_offload[0x5]; 1260 u8 reserved_at_10[0x10]; 1261 1262 u8 min_log_ipsec_full_replay_window[0x8]; 1263 u8 max_log_ipsec_full_replay_window[0x8]; 1264 u8 reserved_at_30[0x7d0]; 1265 }; 1266 1267 enum { 1268 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1269 MLX5_WQ_TYPE_CYCLIC = 0x1, 1270 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1271 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1272 }; 1273 1274 enum { 1275 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1276 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1277 }; 1278 1279 enum { 1280 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1281 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1282 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1283 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1284 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1285 }; 1286 1287 enum { 1288 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1289 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1290 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1291 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1292 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1293 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1294 }; 1295 1296 enum { 1297 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1298 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1299 }; 1300 1301 enum { 1302 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1303 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1304 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1305 }; 1306 1307 enum { 1308 MLX5_CAP_PORT_TYPE_IB = 0x0, 1309 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1310 }; 1311 1312 enum { 1313 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1314 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1315 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1316 }; 1317 1318 enum { 1319 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1320 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1321 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1322 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1323 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1324 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1325 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1326 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1327 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1328 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1329 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1330 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1331 }; 1332 1333 enum { 1334 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1335 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1336 }; 1337 1338 #define MLX5_FC_BULK_SIZE_FACTOR 128 1339 1340 enum mlx5_fc_bulk_alloc_bitmask { 1341 MLX5_FC_BULK_128 = (1 << 0), 1342 MLX5_FC_BULK_256 = (1 << 1), 1343 MLX5_FC_BULK_512 = (1 << 2), 1344 MLX5_FC_BULK_1024 = (1 << 3), 1345 MLX5_FC_BULK_2048 = (1 << 4), 1346 MLX5_FC_BULK_4096 = (1 << 5), 1347 MLX5_FC_BULK_8192 = (1 << 6), 1348 MLX5_FC_BULK_16384 = (1 << 7), 1349 }; 1350 1351 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1352 1353 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1354 1355 enum { 1356 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1357 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1358 }; 1359 1360 struct mlx5_ifc_cmd_hca_cap_bits { 1361 u8 reserved_at_0[0x1f]; 1362 u8 vhca_resource_manager[0x1]; 1363 1364 u8 hca_cap_2[0x1]; 1365 u8 reserved_at_21[0x1]; 1366 u8 dtor[0x1]; 1367 u8 event_on_vhca_state_teardown_request[0x1]; 1368 u8 event_on_vhca_state_in_use[0x1]; 1369 u8 event_on_vhca_state_active[0x1]; 1370 u8 event_on_vhca_state_allocated[0x1]; 1371 u8 event_on_vhca_state_invalid[0x1]; 1372 u8 reserved_at_28[0x8]; 1373 u8 vhca_id[0x10]; 1374 1375 u8 reserved_at_40[0x40]; 1376 1377 u8 log_max_srq_sz[0x8]; 1378 u8 log_max_qp_sz[0x8]; 1379 u8 event_cap[0x1]; 1380 u8 reserved_at_91[0x2]; 1381 u8 isolate_vl_tc_new[0x1]; 1382 u8 reserved_at_94[0x4]; 1383 u8 prio_tag_required[0x1]; 1384 u8 reserved_at_99[0x2]; 1385 u8 log_max_qp[0x5]; 1386 1387 u8 reserved_at_a0[0x3]; 1388 u8 ece_support[0x1]; 1389 u8 reserved_at_a4[0x5]; 1390 u8 reg_c_preserve[0x1]; 1391 u8 reserved_at_aa[0x1]; 1392 u8 log_max_srq[0x5]; 1393 u8 reserved_at_b0[0x1]; 1394 u8 uplink_follow[0x1]; 1395 u8 ts_cqe_to_dest_cqn[0x1]; 1396 u8 reserved_at_b3[0x7]; 1397 u8 shampo[0x1]; 1398 u8 reserved_at_bb[0x5]; 1399 1400 u8 max_sgl_for_optimized_performance[0x8]; 1401 u8 log_max_cq_sz[0x8]; 1402 u8 relaxed_ordering_write_umr[0x1]; 1403 u8 relaxed_ordering_read_umr[0x1]; 1404 u8 reserved_at_d2[0x7]; 1405 u8 virtio_net_device_emualtion_manager[0x1]; 1406 u8 virtio_blk_device_emualtion_manager[0x1]; 1407 u8 log_max_cq[0x5]; 1408 1409 u8 log_max_eq_sz[0x8]; 1410 u8 relaxed_ordering_write[0x1]; 1411 u8 relaxed_ordering_read[0x1]; 1412 u8 log_max_mkey[0x6]; 1413 u8 reserved_at_f0[0x8]; 1414 u8 dump_fill_mkey[0x1]; 1415 u8 reserved_at_f9[0x2]; 1416 u8 fast_teardown[0x1]; 1417 u8 log_max_eq[0x4]; 1418 1419 u8 max_indirection[0x8]; 1420 u8 fixed_buffer_size[0x1]; 1421 u8 log_max_mrw_sz[0x7]; 1422 u8 force_teardown[0x1]; 1423 u8 reserved_at_111[0x1]; 1424 u8 log_max_bsf_list_size[0x6]; 1425 u8 umr_extended_translation_offset[0x1]; 1426 u8 null_mkey[0x1]; 1427 u8 log_max_klm_list_size[0x6]; 1428 1429 u8 reserved_at_120[0xa]; 1430 u8 log_max_ra_req_dc[0x6]; 1431 u8 reserved_at_130[0xa]; 1432 u8 log_max_ra_res_dc[0x6]; 1433 1434 u8 reserved_at_140[0x6]; 1435 u8 release_all_pages[0x1]; 1436 u8 reserved_at_147[0x2]; 1437 u8 roce_accl[0x1]; 1438 u8 log_max_ra_req_qp[0x6]; 1439 u8 reserved_at_150[0xa]; 1440 u8 log_max_ra_res_qp[0x6]; 1441 1442 u8 end_pad[0x1]; 1443 u8 cc_query_allowed[0x1]; 1444 u8 cc_modify_allowed[0x1]; 1445 u8 start_pad[0x1]; 1446 u8 cache_line_128byte[0x1]; 1447 u8 reserved_at_165[0x4]; 1448 u8 rts2rts_qp_counters_set_id[0x1]; 1449 u8 reserved_at_16a[0x2]; 1450 u8 vnic_env_int_rq_oob[0x1]; 1451 u8 sbcam_reg[0x1]; 1452 u8 reserved_at_16e[0x1]; 1453 u8 qcam_reg[0x1]; 1454 u8 gid_table_size[0x10]; 1455 1456 u8 out_of_seq_cnt[0x1]; 1457 u8 vport_counters[0x1]; 1458 u8 retransmission_q_counters[0x1]; 1459 u8 debug[0x1]; 1460 u8 modify_rq_counter_set_id[0x1]; 1461 u8 rq_delay_drop[0x1]; 1462 u8 max_qp_cnt[0xa]; 1463 u8 pkey_table_size[0x10]; 1464 1465 u8 vport_group_manager[0x1]; 1466 u8 vhca_group_manager[0x1]; 1467 u8 ib_virt[0x1]; 1468 u8 eth_virt[0x1]; 1469 u8 vnic_env_queue_counters[0x1]; 1470 u8 ets[0x1]; 1471 u8 nic_flow_table[0x1]; 1472 u8 eswitch_manager[0x1]; 1473 u8 device_memory[0x1]; 1474 u8 mcam_reg[0x1]; 1475 u8 pcam_reg[0x1]; 1476 u8 local_ca_ack_delay[0x5]; 1477 u8 port_module_event[0x1]; 1478 u8 enhanced_error_q_counters[0x1]; 1479 u8 ports_check[0x1]; 1480 u8 reserved_at_1b3[0x1]; 1481 u8 disable_link_up[0x1]; 1482 u8 beacon_led[0x1]; 1483 u8 port_type[0x2]; 1484 u8 num_ports[0x8]; 1485 1486 u8 reserved_at_1c0[0x1]; 1487 u8 pps[0x1]; 1488 u8 pps_modify[0x1]; 1489 u8 log_max_msg[0x5]; 1490 u8 reserved_at_1c8[0x4]; 1491 u8 max_tc[0x4]; 1492 u8 temp_warn_event[0x1]; 1493 u8 dcbx[0x1]; 1494 u8 general_notification_event[0x1]; 1495 u8 reserved_at_1d3[0x2]; 1496 u8 fpga[0x1]; 1497 u8 rol_s[0x1]; 1498 u8 rol_g[0x1]; 1499 u8 reserved_at_1d8[0x1]; 1500 u8 wol_s[0x1]; 1501 u8 wol_g[0x1]; 1502 u8 wol_a[0x1]; 1503 u8 wol_b[0x1]; 1504 u8 wol_m[0x1]; 1505 u8 wol_u[0x1]; 1506 u8 wol_p[0x1]; 1507 1508 u8 stat_rate_support[0x10]; 1509 u8 reserved_at_1f0[0x1]; 1510 u8 pci_sync_for_fw_update_event[0x1]; 1511 u8 reserved_at_1f2[0x6]; 1512 u8 init2_lag_tx_port_affinity[0x1]; 1513 u8 reserved_at_1fa[0x3]; 1514 u8 cqe_version[0x4]; 1515 1516 u8 compact_address_vector[0x1]; 1517 u8 striding_rq[0x1]; 1518 u8 reserved_at_202[0x1]; 1519 u8 ipoib_enhanced_offloads[0x1]; 1520 u8 ipoib_basic_offloads[0x1]; 1521 u8 reserved_at_205[0x1]; 1522 u8 repeated_block_disabled[0x1]; 1523 u8 umr_modify_entity_size_disabled[0x1]; 1524 u8 umr_modify_atomic_disabled[0x1]; 1525 u8 umr_indirect_mkey_disabled[0x1]; 1526 u8 umr_fence[0x2]; 1527 u8 dc_req_scat_data_cqe[0x1]; 1528 u8 reserved_at_20d[0x2]; 1529 u8 drain_sigerr[0x1]; 1530 u8 cmdif_checksum[0x2]; 1531 u8 sigerr_cqe[0x1]; 1532 u8 reserved_at_213[0x1]; 1533 u8 wq_signature[0x1]; 1534 u8 sctr_data_cqe[0x1]; 1535 u8 reserved_at_216[0x1]; 1536 u8 sho[0x1]; 1537 u8 tph[0x1]; 1538 u8 rf[0x1]; 1539 u8 dct[0x1]; 1540 u8 qos[0x1]; 1541 u8 eth_net_offloads[0x1]; 1542 u8 roce[0x1]; 1543 u8 atomic[0x1]; 1544 u8 reserved_at_21f[0x1]; 1545 1546 u8 cq_oi[0x1]; 1547 u8 cq_resize[0x1]; 1548 u8 cq_moderation[0x1]; 1549 u8 reserved_at_223[0x3]; 1550 u8 cq_eq_remap[0x1]; 1551 u8 pg[0x1]; 1552 u8 block_lb_mc[0x1]; 1553 u8 reserved_at_229[0x1]; 1554 u8 scqe_break_moderation[0x1]; 1555 u8 cq_period_start_from_cqe[0x1]; 1556 u8 cd[0x1]; 1557 u8 reserved_at_22d[0x1]; 1558 u8 apm[0x1]; 1559 u8 vector_calc[0x1]; 1560 u8 umr_ptr_rlky[0x1]; 1561 u8 imaicl[0x1]; 1562 u8 qp_packet_based[0x1]; 1563 u8 reserved_at_233[0x3]; 1564 u8 qkv[0x1]; 1565 u8 pkv[0x1]; 1566 u8 set_deth_sqpn[0x1]; 1567 u8 reserved_at_239[0x3]; 1568 u8 xrc[0x1]; 1569 u8 ud[0x1]; 1570 u8 uc[0x1]; 1571 u8 rc[0x1]; 1572 1573 u8 uar_4k[0x1]; 1574 u8 reserved_at_241[0x9]; 1575 u8 uar_sz[0x6]; 1576 u8 port_selection_cap[0x1]; 1577 u8 reserved_at_248[0x1]; 1578 u8 umem_uid_0[0x1]; 1579 u8 reserved_at_250[0x5]; 1580 u8 log_pg_sz[0x8]; 1581 1582 u8 bf[0x1]; 1583 u8 driver_version[0x1]; 1584 u8 pad_tx_eth_packet[0x1]; 1585 u8 reserved_at_263[0x3]; 1586 u8 mkey_by_name[0x1]; 1587 u8 reserved_at_267[0x4]; 1588 1589 u8 log_bf_reg_size[0x5]; 1590 1591 u8 reserved_at_270[0x6]; 1592 u8 lag_dct[0x2]; 1593 u8 lag_tx_port_affinity[0x1]; 1594 u8 lag_native_fdb_selection[0x1]; 1595 u8 reserved_at_27a[0x1]; 1596 u8 lag_master[0x1]; 1597 u8 num_lag_ports[0x4]; 1598 1599 u8 reserved_at_280[0x10]; 1600 u8 max_wqe_sz_sq[0x10]; 1601 1602 u8 reserved_at_2a0[0x10]; 1603 u8 max_wqe_sz_rq[0x10]; 1604 1605 u8 max_flow_counter_31_16[0x10]; 1606 u8 max_wqe_sz_sq_dc[0x10]; 1607 1608 u8 reserved_at_2e0[0x7]; 1609 u8 max_qp_mcg[0x19]; 1610 1611 u8 reserved_at_300[0x10]; 1612 u8 flow_counter_bulk_alloc[0x8]; 1613 u8 log_max_mcg[0x8]; 1614 1615 u8 reserved_at_320[0x3]; 1616 u8 log_max_transport_domain[0x5]; 1617 u8 reserved_at_328[0x3]; 1618 u8 log_max_pd[0x5]; 1619 u8 reserved_at_330[0xb]; 1620 u8 log_max_xrcd[0x5]; 1621 1622 u8 nic_receive_steering_discard[0x1]; 1623 u8 receive_discard_vport_down[0x1]; 1624 u8 transmit_discard_vport_down[0x1]; 1625 u8 reserved_at_343[0x5]; 1626 u8 log_max_flow_counter_bulk[0x8]; 1627 u8 max_flow_counter_15_0[0x10]; 1628 1629 1630 u8 reserved_at_360[0x3]; 1631 u8 log_max_rq[0x5]; 1632 u8 reserved_at_368[0x3]; 1633 u8 log_max_sq[0x5]; 1634 u8 reserved_at_370[0x3]; 1635 u8 log_max_tir[0x5]; 1636 u8 reserved_at_378[0x3]; 1637 u8 log_max_tis[0x5]; 1638 1639 u8 basic_cyclic_rcv_wqe[0x1]; 1640 u8 reserved_at_381[0x2]; 1641 u8 log_max_rmp[0x5]; 1642 u8 reserved_at_388[0x3]; 1643 u8 log_max_rqt[0x5]; 1644 u8 reserved_at_390[0x3]; 1645 u8 log_max_rqt_size[0x5]; 1646 u8 reserved_at_398[0x3]; 1647 u8 log_max_tis_per_sq[0x5]; 1648 1649 u8 ext_stride_num_range[0x1]; 1650 u8 roce_rw_supported[0x1]; 1651 u8 log_max_current_uc_list_wr_supported[0x1]; 1652 u8 log_max_stride_sz_rq[0x5]; 1653 u8 reserved_at_3a8[0x3]; 1654 u8 log_min_stride_sz_rq[0x5]; 1655 u8 reserved_at_3b0[0x3]; 1656 u8 log_max_stride_sz_sq[0x5]; 1657 u8 reserved_at_3b8[0x3]; 1658 u8 log_min_stride_sz_sq[0x5]; 1659 1660 u8 hairpin[0x1]; 1661 u8 reserved_at_3c1[0x2]; 1662 u8 log_max_hairpin_queues[0x5]; 1663 u8 reserved_at_3c8[0x3]; 1664 u8 log_max_hairpin_wq_data_sz[0x5]; 1665 u8 reserved_at_3d0[0x3]; 1666 u8 log_max_hairpin_num_packets[0x5]; 1667 u8 reserved_at_3d8[0x3]; 1668 u8 log_max_wq_sz[0x5]; 1669 1670 u8 nic_vport_change_event[0x1]; 1671 u8 disable_local_lb_uc[0x1]; 1672 u8 disable_local_lb_mc[0x1]; 1673 u8 log_min_hairpin_wq_data_sz[0x5]; 1674 u8 reserved_at_3e8[0x2]; 1675 u8 vhca_state[0x1]; 1676 u8 log_max_vlan_list[0x5]; 1677 u8 reserved_at_3f0[0x3]; 1678 u8 log_max_current_mc_list[0x5]; 1679 u8 reserved_at_3f8[0x3]; 1680 u8 log_max_current_uc_list[0x5]; 1681 1682 u8 general_obj_types[0x40]; 1683 1684 u8 sq_ts_format[0x2]; 1685 u8 rq_ts_format[0x2]; 1686 u8 steering_format_version[0x4]; 1687 u8 create_qp_start_hint[0x18]; 1688 1689 u8 reserved_at_460[0x3]; 1690 u8 log_max_uctx[0x5]; 1691 u8 reserved_at_468[0x2]; 1692 u8 ipsec_offload[0x1]; 1693 u8 log_max_umem[0x5]; 1694 u8 max_num_eqs[0x10]; 1695 1696 u8 reserved_at_480[0x1]; 1697 u8 tls_tx[0x1]; 1698 u8 tls_rx[0x1]; 1699 u8 log_max_l2_table[0x5]; 1700 u8 reserved_at_488[0x8]; 1701 u8 log_uar_page_sz[0x10]; 1702 1703 u8 reserved_at_4a0[0x20]; 1704 u8 device_frequency_mhz[0x20]; 1705 u8 device_frequency_khz[0x20]; 1706 1707 u8 reserved_at_500[0x20]; 1708 u8 num_of_uars_per_page[0x20]; 1709 1710 u8 flex_parser_protocols[0x20]; 1711 1712 u8 max_geneve_tlv_options[0x8]; 1713 u8 reserved_at_568[0x3]; 1714 u8 max_geneve_tlv_option_data_len[0x5]; 1715 u8 reserved_at_570[0x10]; 1716 1717 u8 reserved_at_580[0xb]; 1718 u8 log_max_dci_stream_channels[0x5]; 1719 u8 reserved_at_590[0x3]; 1720 u8 log_max_dci_errored_streams[0x5]; 1721 u8 reserved_at_598[0x8]; 1722 1723 u8 reserved_at_5a0[0x13]; 1724 u8 log_max_dek[0x5]; 1725 u8 reserved_at_5b8[0x4]; 1726 u8 mini_cqe_resp_stride_index[0x1]; 1727 u8 cqe_128_always[0x1]; 1728 u8 cqe_compression_128[0x1]; 1729 u8 cqe_compression[0x1]; 1730 1731 u8 cqe_compression_timeout[0x10]; 1732 u8 cqe_compression_max_num[0x10]; 1733 1734 u8 reserved_at_5e0[0x8]; 1735 u8 flex_parser_id_gtpu_dw_0[0x4]; 1736 u8 reserved_at_5ec[0x4]; 1737 u8 tag_matching[0x1]; 1738 u8 rndv_offload_rc[0x1]; 1739 u8 rndv_offload_dc[0x1]; 1740 u8 log_tag_matching_list_sz[0x5]; 1741 u8 reserved_at_5f8[0x3]; 1742 u8 log_max_xrq[0x5]; 1743 1744 u8 affiliate_nic_vport_criteria[0x8]; 1745 u8 native_port_num[0x8]; 1746 u8 num_vhca_ports[0x8]; 1747 u8 flex_parser_id_gtpu_teid[0x4]; 1748 u8 reserved_at_61c[0x2]; 1749 u8 sw_owner_id[0x1]; 1750 u8 reserved_at_61f[0x1]; 1751 1752 u8 max_num_of_monitor_counters[0x10]; 1753 u8 num_ppcnt_monitor_counters[0x10]; 1754 1755 u8 max_num_sf[0x10]; 1756 u8 num_q_monitor_counters[0x10]; 1757 1758 u8 reserved_at_660[0x20]; 1759 1760 u8 sf[0x1]; 1761 u8 sf_set_partition[0x1]; 1762 u8 reserved_at_682[0x1]; 1763 u8 log_max_sf[0x5]; 1764 u8 apu[0x1]; 1765 u8 reserved_at_689[0x4]; 1766 u8 migration[0x1]; 1767 u8 reserved_at_68e[0x2]; 1768 u8 log_min_sf_size[0x8]; 1769 u8 max_num_sf_partitions[0x8]; 1770 1771 u8 uctx_cap[0x20]; 1772 1773 u8 reserved_at_6c0[0x4]; 1774 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1775 u8 flex_parser_id_icmp_dw1[0x4]; 1776 u8 flex_parser_id_icmp_dw0[0x4]; 1777 u8 flex_parser_id_icmpv6_dw1[0x4]; 1778 u8 flex_parser_id_icmpv6_dw0[0x4]; 1779 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1780 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1781 1782 u8 max_num_match_definer[0x10]; 1783 u8 sf_base_id[0x10]; 1784 1785 u8 flex_parser_id_gtpu_dw_2[0x4]; 1786 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1787 u8 num_total_dynamic_vf_msix[0x18]; 1788 u8 reserved_at_720[0x14]; 1789 u8 dynamic_msix_table_size[0xc]; 1790 u8 reserved_at_740[0xc]; 1791 u8 min_dynamic_vf_msix_table_size[0x4]; 1792 u8 reserved_at_750[0x4]; 1793 u8 max_dynamic_vf_msix_table_size[0xc]; 1794 1795 u8 reserved_at_760[0x20]; 1796 u8 vhca_tunnel_commands[0x40]; 1797 u8 match_definer_format_supported[0x40]; 1798 }; 1799 1800 struct mlx5_ifc_cmd_hca_cap_2_bits { 1801 u8 reserved_at_0[0xa0]; 1802 1803 u8 max_reformat_insert_size[0x8]; 1804 u8 max_reformat_insert_offset[0x8]; 1805 u8 max_reformat_remove_size[0x8]; 1806 u8 max_reformat_remove_offset[0x8]; 1807 1808 u8 reserved_at_c0[0x740]; 1809 }; 1810 1811 enum mlx5_flow_destination_type { 1812 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1813 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1814 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1815 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1816 MLX5_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1817 1818 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1819 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1820 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1821 }; 1822 1823 enum mlx5_flow_table_miss_action { 1824 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1825 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1826 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1827 }; 1828 1829 struct mlx5_ifc_dest_format_struct_bits { 1830 u8 destination_type[0x8]; 1831 u8 destination_id[0x18]; 1832 1833 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1834 u8 packet_reformat[0x1]; 1835 u8 reserved_at_22[0xe]; 1836 u8 destination_eswitch_owner_vhca_id[0x10]; 1837 }; 1838 1839 struct mlx5_ifc_flow_counter_list_bits { 1840 u8 flow_counter_id[0x20]; 1841 1842 u8 reserved_at_20[0x20]; 1843 }; 1844 1845 struct mlx5_ifc_extended_dest_format_bits { 1846 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1847 1848 u8 packet_reformat_id[0x20]; 1849 1850 u8 reserved_at_60[0x20]; 1851 }; 1852 1853 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1854 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1855 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1856 }; 1857 1858 struct mlx5_ifc_fte_match_param_bits { 1859 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1860 1861 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1862 1863 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1864 1865 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1866 1867 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1868 1869 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1870 1871 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1872 1873 u8 reserved_at_e00[0x200]; 1874 }; 1875 1876 enum { 1877 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1878 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1879 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1880 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1881 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1882 }; 1883 1884 struct mlx5_ifc_rx_hash_field_select_bits { 1885 u8 l3_prot_type[0x1]; 1886 u8 l4_prot_type[0x1]; 1887 u8 selected_fields[0x1e]; 1888 }; 1889 1890 enum { 1891 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1892 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1893 }; 1894 1895 enum { 1896 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1897 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1898 }; 1899 1900 struct mlx5_ifc_wq_bits { 1901 u8 wq_type[0x4]; 1902 u8 wq_signature[0x1]; 1903 u8 end_padding_mode[0x2]; 1904 u8 cd_slave[0x1]; 1905 u8 reserved_at_8[0x18]; 1906 1907 u8 hds_skip_first_sge[0x1]; 1908 u8 log2_hds_buf_size[0x3]; 1909 u8 reserved_at_24[0x7]; 1910 u8 page_offset[0x5]; 1911 u8 lwm[0x10]; 1912 1913 u8 reserved_at_40[0x8]; 1914 u8 pd[0x18]; 1915 1916 u8 reserved_at_60[0x8]; 1917 u8 uar_page[0x18]; 1918 1919 u8 dbr_addr[0x40]; 1920 1921 u8 hw_counter[0x20]; 1922 1923 u8 sw_counter[0x20]; 1924 1925 u8 reserved_at_100[0xc]; 1926 u8 log_wq_stride[0x4]; 1927 u8 reserved_at_110[0x3]; 1928 u8 log_wq_pg_sz[0x5]; 1929 u8 reserved_at_118[0x3]; 1930 u8 log_wq_sz[0x5]; 1931 1932 u8 dbr_umem_valid[0x1]; 1933 u8 wq_umem_valid[0x1]; 1934 u8 reserved_at_122[0x1]; 1935 u8 log_hairpin_num_packets[0x5]; 1936 u8 reserved_at_128[0x3]; 1937 u8 log_hairpin_data_sz[0x5]; 1938 1939 u8 reserved_at_130[0x4]; 1940 u8 log_wqe_num_of_strides[0x4]; 1941 u8 two_byte_shift_en[0x1]; 1942 u8 reserved_at_139[0x4]; 1943 u8 log_wqe_stride_size[0x3]; 1944 1945 u8 reserved_at_140[0x80]; 1946 1947 u8 headers_mkey[0x20]; 1948 1949 u8 shampo_enable[0x1]; 1950 u8 reserved_at_1e1[0x4]; 1951 u8 log_reservation_size[0x3]; 1952 u8 reserved_at_1e8[0x5]; 1953 u8 log_max_num_of_packets_per_reservation[0x3]; 1954 u8 reserved_at_1f0[0x6]; 1955 u8 log_headers_entry_size[0x2]; 1956 u8 reserved_at_1f8[0x4]; 1957 u8 log_headers_buffer_entry_num[0x4]; 1958 1959 u8 reserved_at_200[0x400]; 1960 1961 struct mlx5_ifc_cmd_pas_bits pas[]; 1962 }; 1963 1964 struct mlx5_ifc_rq_num_bits { 1965 u8 reserved_at_0[0x8]; 1966 u8 rq_num[0x18]; 1967 }; 1968 1969 struct mlx5_ifc_mac_address_layout_bits { 1970 u8 reserved_at_0[0x10]; 1971 u8 mac_addr_47_32[0x10]; 1972 1973 u8 mac_addr_31_0[0x20]; 1974 }; 1975 1976 struct mlx5_ifc_vlan_layout_bits { 1977 u8 reserved_at_0[0x14]; 1978 u8 vlan[0x0c]; 1979 1980 u8 reserved_at_20[0x20]; 1981 }; 1982 1983 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1984 u8 reserved_at_0[0xa0]; 1985 1986 u8 min_time_between_cnps[0x20]; 1987 1988 u8 reserved_at_c0[0x12]; 1989 u8 cnp_dscp[0x6]; 1990 u8 reserved_at_d8[0x4]; 1991 u8 cnp_prio_mode[0x1]; 1992 u8 cnp_802p_prio[0x3]; 1993 1994 u8 reserved_at_e0[0x720]; 1995 }; 1996 1997 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1998 u8 reserved_at_0[0x60]; 1999 2000 u8 reserved_at_60[0x4]; 2001 u8 clamp_tgt_rate[0x1]; 2002 u8 reserved_at_65[0x3]; 2003 u8 clamp_tgt_rate_after_time_inc[0x1]; 2004 u8 reserved_at_69[0x17]; 2005 2006 u8 reserved_at_80[0x20]; 2007 2008 u8 rpg_time_reset[0x20]; 2009 2010 u8 rpg_byte_reset[0x20]; 2011 2012 u8 rpg_threshold[0x20]; 2013 2014 u8 rpg_max_rate[0x20]; 2015 2016 u8 rpg_ai_rate[0x20]; 2017 2018 u8 rpg_hai_rate[0x20]; 2019 2020 u8 rpg_gd[0x20]; 2021 2022 u8 rpg_min_dec_fac[0x20]; 2023 2024 u8 rpg_min_rate[0x20]; 2025 2026 u8 reserved_at_1c0[0xe0]; 2027 2028 u8 rate_to_set_on_first_cnp[0x20]; 2029 2030 u8 dce_tcp_g[0x20]; 2031 2032 u8 dce_tcp_rtt[0x20]; 2033 2034 u8 rate_reduce_monitor_period[0x20]; 2035 2036 u8 reserved_at_320[0x20]; 2037 2038 u8 initial_alpha_value[0x20]; 2039 2040 u8 reserved_at_360[0x4a0]; 2041 }; 2042 2043 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2044 u8 reserved_at_0[0x80]; 2045 2046 u8 rppp_max_rps[0x20]; 2047 2048 u8 rpg_time_reset[0x20]; 2049 2050 u8 rpg_byte_reset[0x20]; 2051 2052 u8 rpg_threshold[0x20]; 2053 2054 u8 rpg_max_rate[0x20]; 2055 2056 u8 rpg_ai_rate[0x20]; 2057 2058 u8 rpg_hai_rate[0x20]; 2059 2060 u8 rpg_gd[0x20]; 2061 2062 u8 rpg_min_dec_fac[0x20]; 2063 2064 u8 rpg_min_rate[0x20]; 2065 2066 u8 reserved_at_1c0[0x640]; 2067 }; 2068 2069 enum { 2070 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2071 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2072 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2073 }; 2074 2075 struct mlx5_ifc_resize_field_select_bits { 2076 u8 resize_field_select[0x20]; 2077 }; 2078 2079 struct mlx5_ifc_resource_dump_bits { 2080 u8 more_dump[0x1]; 2081 u8 inline_dump[0x1]; 2082 u8 reserved_at_2[0xa]; 2083 u8 seq_num[0x4]; 2084 u8 segment_type[0x10]; 2085 2086 u8 reserved_at_20[0x10]; 2087 u8 vhca_id[0x10]; 2088 2089 u8 index1[0x20]; 2090 2091 u8 index2[0x20]; 2092 2093 u8 num_of_obj1[0x10]; 2094 u8 num_of_obj2[0x10]; 2095 2096 u8 reserved_at_a0[0x20]; 2097 2098 u8 device_opaque[0x40]; 2099 2100 u8 mkey[0x20]; 2101 2102 u8 size[0x20]; 2103 2104 u8 address[0x40]; 2105 2106 u8 inline_data[52][0x20]; 2107 }; 2108 2109 struct mlx5_ifc_resource_dump_menu_record_bits { 2110 u8 reserved_at_0[0x4]; 2111 u8 num_of_obj2_supports_active[0x1]; 2112 u8 num_of_obj2_supports_all[0x1]; 2113 u8 must_have_num_of_obj2[0x1]; 2114 u8 support_num_of_obj2[0x1]; 2115 u8 num_of_obj1_supports_active[0x1]; 2116 u8 num_of_obj1_supports_all[0x1]; 2117 u8 must_have_num_of_obj1[0x1]; 2118 u8 support_num_of_obj1[0x1]; 2119 u8 must_have_index2[0x1]; 2120 u8 support_index2[0x1]; 2121 u8 must_have_index1[0x1]; 2122 u8 support_index1[0x1]; 2123 u8 segment_type[0x10]; 2124 2125 u8 segment_name[4][0x20]; 2126 2127 u8 index1_name[4][0x20]; 2128 2129 u8 index2_name[4][0x20]; 2130 }; 2131 2132 struct mlx5_ifc_resource_dump_segment_header_bits { 2133 u8 length_dw[0x10]; 2134 u8 segment_type[0x10]; 2135 }; 2136 2137 struct mlx5_ifc_resource_dump_command_segment_bits { 2138 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2139 2140 u8 segment_called[0x10]; 2141 u8 vhca_id[0x10]; 2142 2143 u8 index1[0x20]; 2144 2145 u8 index2[0x20]; 2146 2147 u8 num_of_obj1[0x10]; 2148 u8 num_of_obj2[0x10]; 2149 }; 2150 2151 struct mlx5_ifc_resource_dump_error_segment_bits { 2152 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2153 2154 u8 reserved_at_20[0x10]; 2155 u8 syndrome_id[0x10]; 2156 2157 u8 reserved_at_40[0x40]; 2158 2159 u8 error[8][0x20]; 2160 }; 2161 2162 struct mlx5_ifc_resource_dump_info_segment_bits { 2163 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2164 2165 u8 reserved_at_20[0x18]; 2166 u8 dump_version[0x8]; 2167 2168 u8 hw_version[0x20]; 2169 2170 u8 fw_version[0x20]; 2171 }; 2172 2173 struct mlx5_ifc_resource_dump_menu_segment_bits { 2174 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2175 2176 u8 reserved_at_20[0x10]; 2177 u8 num_of_records[0x10]; 2178 2179 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2180 }; 2181 2182 struct mlx5_ifc_resource_dump_resource_segment_bits { 2183 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2184 2185 u8 reserved_at_20[0x20]; 2186 2187 u8 index1[0x20]; 2188 2189 u8 index2[0x20]; 2190 2191 u8 payload[][0x20]; 2192 }; 2193 2194 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2195 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2196 }; 2197 2198 struct mlx5_ifc_menu_resource_dump_response_bits { 2199 struct mlx5_ifc_resource_dump_info_segment_bits info; 2200 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2201 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2202 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2203 }; 2204 2205 enum { 2206 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2207 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2208 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2209 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2210 }; 2211 2212 struct mlx5_ifc_modify_field_select_bits { 2213 u8 modify_field_select[0x20]; 2214 }; 2215 2216 struct mlx5_ifc_field_select_r_roce_np_bits { 2217 u8 field_select_r_roce_np[0x20]; 2218 }; 2219 2220 struct mlx5_ifc_field_select_r_roce_rp_bits { 2221 u8 field_select_r_roce_rp[0x20]; 2222 }; 2223 2224 enum { 2225 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2226 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2227 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2228 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2229 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2230 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2231 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2232 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2233 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2234 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2235 }; 2236 2237 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2238 u8 field_select_8021qaurp[0x20]; 2239 }; 2240 2241 struct mlx5_ifc_phys_layer_cntrs_bits { 2242 u8 time_since_last_clear_high[0x20]; 2243 2244 u8 time_since_last_clear_low[0x20]; 2245 2246 u8 symbol_errors_high[0x20]; 2247 2248 u8 symbol_errors_low[0x20]; 2249 2250 u8 sync_headers_errors_high[0x20]; 2251 2252 u8 sync_headers_errors_low[0x20]; 2253 2254 u8 edpl_bip_errors_lane0_high[0x20]; 2255 2256 u8 edpl_bip_errors_lane0_low[0x20]; 2257 2258 u8 edpl_bip_errors_lane1_high[0x20]; 2259 2260 u8 edpl_bip_errors_lane1_low[0x20]; 2261 2262 u8 edpl_bip_errors_lane2_high[0x20]; 2263 2264 u8 edpl_bip_errors_lane2_low[0x20]; 2265 2266 u8 edpl_bip_errors_lane3_high[0x20]; 2267 2268 u8 edpl_bip_errors_lane3_low[0x20]; 2269 2270 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2271 2272 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2273 2274 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2275 2276 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2277 2278 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2279 2280 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2281 2282 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2283 2284 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2285 2286 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2287 2288 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2289 2290 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2291 2292 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2293 2294 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2295 2296 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2297 2298 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2299 2300 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2301 2302 u8 rs_fec_corrected_blocks_high[0x20]; 2303 2304 u8 rs_fec_corrected_blocks_low[0x20]; 2305 2306 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2307 2308 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2309 2310 u8 rs_fec_no_errors_blocks_high[0x20]; 2311 2312 u8 rs_fec_no_errors_blocks_low[0x20]; 2313 2314 u8 rs_fec_single_error_blocks_high[0x20]; 2315 2316 u8 rs_fec_single_error_blocks_low[0x20]; 2317 2318 u8 rs_fec_corrected_symbols_total_high[0x20]; 2319 2320 u8 rs_fec_corrected_symbols_total_low[0x20]; 2321 2322 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2323 2324 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2325 2326 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2327 2328 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2329 2330 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2331 2332 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2333 2334 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2335 2336 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2337 2338 u8 link_down_events[0x20]; 2339 2340 u8 successful_recovery_events[0x20]; 2341 2342 u8 reserved_at_640[0x180]; 2343 }; 2344 2345 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2346 u8 time_since_last_clear_high[0x20]; 2347 2348 u8 time_since_last_clear_low[0x20]; 2349 2350 u8 phy_received_bits_high[0x20]; 2351 2352 u8 phy_received_bits_low[0x20]; 2353 2354 u8 phy_symbol_errors_high[0x20]; 2355 2356 u8 phy_symbol_errors_low[0x20]; 2357 2358 u8 phy_corrected_bits_high[0x20]; 2359 2360 u8 phy_corrected_bits_low[0x20]; 2361 2362 u8 phy_corrected_bits_lane0_high[0x20]; 2363 2364 u8 phy_corrected_bits_lane0_low[0x20]; 2365 2366 u8 phy_corrected_bits_lane1_high[0x20]; 2367 2368 u8 phy_corrected_bits_lane1_low[0x20]; 2369 2370 u8 phy_corrected_bits_lane2_high[0x20]; 2371 2372 u8 phy_corrected_bits_lane2_low[0x20]; 2373 2374 u8 phy_corrected_bits_lane3_high[0x20]; 2375 2376 u8 phy_corrected_bits_lane3_low[0x20]; 2377 2378 u8 reserved_at_200[0x5c0]; 2379 }; 2380 2381 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2382 u8 symbol_error_counter[0x10]; 2383 2384 u8 link_error_recovery_counter[0x8]; 2385 2386 u8 link_downed_counter[0x8]; 2387 2388 u8 port_rcv_errors[0x10]; 2389 2390 u8 port_rcv_remote_physical_errors[0x10]; 2391 2392 u8 port_rcv_switch_relay_errors[0x10]; 2393 2394 u8 port_xmit_discards[0x10]; 2395 2396 u8 port_xmit_constraint_errors[0x8]; 2397 2398 u8 port_rcv_constraint_errors[0x8]; 2399 2400 u8 reserved_at_70[0x8]; 2401 2402 u8 link_overrun_errors[0x8]; 2403 2404 u8 reserved_at_80[0x10]; 2405 2406 u8 vl_15_dropped[0x10]; 2407 2408 u8 reserved_at_a0[0x80]; 2409 2410 u8 port_xmit_wait[0x20]; 2411 }; 2412 2413 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2414 u8 transmit_queue_high[0x20]; 2415 2416 u8 transmit_queue_low[0x20]; 2417 2418 u8 no_buffer_discard_uc_high[0x20]; 2419 2420 u8 no_buffer_discard_uc_low[0x20]; 2421 2422 u8 reserved_at_80[0x740]; 2423 }; 2424 2425 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2426 u8 wred_discard_high[0x20]; 2427 2428 u8 wred_discard_low[0x20]; 2429 2430 u8 ecn_marked_tc_high[0x20]; 2431 2432 u8 ecn_marked_tc_low[0x20]; 2433 2434 u8 reserved_at_80[0x740]; 2435 }; 2436 2437 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2438 u8 rx_octets_high[0x20]; 2439 2440 u8 rx_octets_low[0x20]; 2441 2442 u8 reserved_at_40[0xc0]; 2443 2444 u8 rx_frames_high[0x20]; 2445 2446 u8 rx_frames_low[0x20]; 2447 2448 u8 tx_octets_high[0x20]; 2449 2450 u8 tx_octets_low[0x20]; 2451 2452 u8 reserved_at_180[0xc0]; 2453 2454 u8 tx_frames_high[0x20]; 2455 2456 u8 tx_frames_low[0x20]; 2457 2458 u8 rx_pause_high[0x20]; 2459 2460 u8 rx_pause_low[0x20]; 2461 2462 u8 rx_pause_duration_high[0x20]; 2463 2464 u8 rx_pause_duration_low[0x20]; 2465 2466 u8 tx_pause_high[0x20]; 2467 2468 u8 tx_pause_low[0x20]; 2469 2470 u8 tx_pause_duration_high[0x20]; 2471 2472 u8 tx_pause_duration_low[0x20]; 2473 2474 u8 rx_pause_transition_high[0x20]; 2475 2476 u8 rx_pause_transition_low[0x20]; 2477 2478 u8 rx_discards_high[0x20]; 2479 2480 u8 rx_discards_low[0x20]; 2481 2482 u8 device_stall_minor_watermark_cnt_high[0x20]; 2483 2484 u8 device_stall_minor_watermark_cnt_low[0x20]; 2485 2486 u8 device_stall_critical_watermark_cnt_high[0x20]; 2487 2488 u8 device_stall_critical_watermark_cnt_low[0x20]; 2489 2490 u8 reserved_at_480[0x340]; 2491 }; 2492 2493 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2494 u8 port_transmit_wait_high[0x20]; 2495 2496 u8 port_transmit_wait_low[0x20]; 2497 2498 u8 reserved_at_40[0x100]; 2499 2500 u8 rx_buffer_almost_full_high[0x20]; 2501 2502 u8 rx_buffer_almost_full_low[0x20]; 2503 2504 u8 rx_buffer_full_high[0x20]; 2505 2506 u8 rx_buffer_full_low[0x20]; 2507 2508 u8 rx_icrc_encapsulated_high[0x20]; 2509 2510 u8 rx_icrc_encapsulated_low[0x20]; 2511 2512 u8 reserved_at_200[0x5c0]; 2513 }; 2514 2515 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2516 u8 dot3stats_alignment_errors_high[0x20]; 2517 2518 u8 dot3stats_alignment_errors_low[0x20]; 2519 2520 u8 dot3stats_fcs_errors_high[0x20]; 2521 2522 u8 dot3stats_fcs_errors_low[0x20]; 2523 2524 u8 dot3stats_single_collision_frames_high[0x20]; 2525 2526 u8 dot3stats_single_collision_frames_low[0x20]; 2527 2528 u8 dot3stats_multiple_collision_frames_high[0x20]; 2529 2530 u8 dot3stats_multiple_collision_frames_low[0x20]; 2531 2532 u8 dot3stats_sqe_test_errors_high[0x20]; 2533 2534 u8 dot3stats_sqe_test_errors_low[0x20]; 2535 2536 u8 dot3stats_deferred_transmissions_high[0x20]; 2537 2538 u8 dot3stats_deferred_transmissions_low[0x20]; 2539 2540 u8 dot3stats_late_collisions_high[0x20]; 2541 2542 u8 dot3stats_late_collisions_low[0x20]; 2543 2544 u8 dot3stats_excessive_collisions_high[0x20]; 2545 2546 u8 dot3stats_excessive_collisions_low[0x20]; 2547 2548 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2549 2550 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2551 2552 u8 dot3stats_carrier_sense_errors_high[0x20]; 2553 2554 u8 dot3stats_carrier_sense_errors_low[0x20]; 2555 2556 u8 dot3stats_frame_too_longs_high[0x20]; 2557 2558 u8 dot3stats_frame_too_longs_low[0x20]; 2559 2560 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2561 2562 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2563 2564 u8 dot3stats_symbol_errors_high[0x20]; 2565 2566 u8 dot3stats_symbol_errors_low[0x20]; 2567 2568 u8 dot3control_in_unknown_opcodes_high[0x20]; 2569 2570 u8 dot3control_in_unknown_opcodes_low[0x20]; 2571 2572 u8 dot3in_pause_frames_high[0x20]; 2573 2574 u8 dot3in_pause_frames_low[0x20]; 2575 2576 u8 dot3out_pause_frames_high[0x20]; 2577 2578 u8 dot3out_pause_frames_low[0x20]; 2579 2580 u8 reserved_at_400[0x3c0]; 2581 }; 2582 2583 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2584 u8 ether_stats_drop_events_high[0x20]; 2585 2586 u8 ether_stats_drop_events_low[0x20]; 2587 2588 u8 ether_stats_octets_high[0x20]; 2589 2590 u8 ether_stats_octets_low[0x20]; 2591 2592 u8 ether_stats_pkts_high[0x20]; 2593 2594 u8 ether_stats_pkts_low[0x20]; 2595 2596 u8 ether_stats_broadcast_pkts_high[0x20]; 2597 2598 u8 ether_stats_broadcast_pkts_low[0x20]; 2599 2600 u8 ether_stats_multicast_pkts_high[0x20]; 2601 2602 u8 ether_stats_multicast_pkts_low[0x20]; 2603 2604 u8 ether_stats_crc_align_errors_high[0x20]; 2605 2606 u8 ether_stats_crc_align_errors_low[0x20]; 2607 2608 u8 ether_stats_undersize_pkts_high[0x20]; 2609 2610 u8 ether_stats_undersize_pkts_low[0x20]; 2611 2612 u8 ether_stats_oversize_pkts_high[0x20]; 2613 2614 u8 ether_stats_oversize_pkts_low[0x20]; 2615 2616 u8 ether_stats_fragments_high[0x20]; 2617 2618 u8 ether_stats_fragments_low[0x20]; 2619 2620 u8 ether_stats_jabbers_high[0x20]; 2621 2622 u8 ether_stats_jabbers_low[0x20]; 2623 2624 u8 ether_stats_collisions_high[0x20]; 2625 2626 u8 ether_stats_collisions_low[0x20]; 2627 2628 u8 ether_stats_pkts64octets_high[0x20]; 2629 2630 u8 ether_stats_pkts64octets_low[0x20]; 2631 2632 u8 ether_stats_pkts65to127octets_high[0x20]; 2633 2634 u8 ether_stats_pkts65to127octets_low[0x20]; 2635 2636 u8 ether_stats_pkts128to255octets_high[0x20]; 2637 2638 u8 ether_stats_pkts128to255octets_low[0x20]; 2639 2640 u8 ether_stats_pkts256to511octets_high[0x20]; 2641 2642 u8 ether_stats_pkts256to511octets_low[0x20]; 2643 2644 u8 ether_stats_pkts512to1023octets_high[0x20]; 2645 2646 u8 ether_stats_pkts512to1023octets_low[0x20]; 2647 2648 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2649 2650 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2651 2652 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2653 2654 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2655 2656 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2657 2658 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2659 2660 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2661 2662 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2663 2664 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2665 2666 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2667 2668 u8 reserved_at_540[0x280]; 2669 }; 2670 2671 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2672 u8 if_in_octets_high[0x20]; 2673 2674 u8 if_in_octets_low[0x20]; 2675 2676 u8 if_in_ucast_pkts_high[0x20]; 2677 2678 u8 if_in_ucast_pkts_low[0x20]; 2679 2680 u8 if_in_discards_high[0x20]; 2681 2682 u8 if_in_discards_low[0x20]; 2683 2684 u8 if_in_errors_high[0x20]; 2685 2686 u8 if_in_errors_low[0x20]; 2687 2688 u8 if_in_unknown_protos_high[0x20]; 2689 2690 u8 if_in_unknown_protos_low[0x20]; 2691 2692 u8 if_out_octets_high[0x20]; 2693 2694 u8 if_out_octets_low[0x20]; 2695 2696 u8 if_out_ucast_pkts_high[0x20]; 2697 2698 u8 if_out_ucast_pkts_low[0x20]; 2699 2700 u8 if_out_discards_high[0x20]; 2701 2702 u8 if_out_discards_low[0x20]; 2703 2704 u8 if_out_errors_high[0x20]; 2705 2706 u8 if_out_errors_low[0x20]; 2707 2708 u8 if_in_multicast_pkts_high[0x20]; 2709 2710 u8 if_in_multicast_pkts_low[0x20]; 2711 2712 u8 if_in_broadcast_pkts_high[0x20]; 2713 2714 u8 if_in_broadcast_pkts_low[0x20]; 2715 2716 u8 if_out_multicast_pkts_high[0x20]; 2717 2718 u8 if_out_multicast_pkts_low[0x20]; 2719 2720 u8 if_out_broadcast_pkts_high[0x20]; 2721 2722 u8 if_out_broadcast_pkts_low[0x20]; 2723 2724 u8 reserved_at_340[0x480]; 2725 }; 2726 2727 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2728 u8 a_frames_transmitted_ok_high[0x20]; 2729 2730 u8 a_frames_transmitted_ok_low[0x20]; 2731 2732 u8 a_frames_received_ok_high[0x20]; 2733 2734 u8 a_frames_received_ok_low[0x20]; 2735 2736 u8 a_frame_check_sequence_errors_high[0x20]; 2737 2738 u8 a_frame_check_sequence_errors_low[0x20]; 2739 2740 u8 a_alignment_errors_high[0x20]; 2741 2742 u8 a_alignment_errors_low[0x20]; 2743 2744 u8 a_octets_transmitted_ok_high[0x20]; 2745 2746 u8 a_octets_transmitted_ok_low[0x20]; 2747 2748 u8 a_octets_received_ok_high[0x20]; 2749 2750 u8 a_octets_received_ok_low[0x20]; 2751 2752 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2753 2754 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2755 2756 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2757 2758 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2759 2760 u8 a_multicast_frames_received_ok_high[0x20]; 2761 2762 u8 a_multicast_frames_received_ok_low[0x20]; 2763 2764 u8 a_broadcast_frames_received_ok_high[0x20]; 2765 2766 u8 a_broadcast_frames_received_ok_low[0x20]; 2767 2768 u8 a_in_range_length_errors_high[0x20]; 2769 2770 u8 a_in_range_length_errors_low[0x20]; 2771 2772 u8 a_out_of_range_length_field_high[0x20]; 2773 2774 u8 a_out_of_range_length_field_low[0x20]; 2775 2776 u8 a_frame_too_long_errors_high[0x20]; 2777 2778 u8 a_frame_too_long_errors_low[0x20]; 2779 2780 u8 a_symbol_error_during_carrier_high[0x20]; 2781 2782 u8 a_symbol_error_during_carrier_low[0x20]; 2783 2784 u8 a_mac_control_frames_transmitted_high[0x20]; 2785 2786 u8 a_mac_control_frames_transmitted_low[0x20]; 2787 2788 u8 a_mac_control_frames_received_high[0x20]; 2789 2790 u8 a_mac_control_frames_received_low[0x20]; 2791 2792 u8 a_unsupported_opcodes_received_high[0x20]; 2793 2794 u8 a_unsupported_opcodes_received_low[0x20]; 2795 2796 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2797 2798 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2799 2800 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2801 2802 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2803 2804 u8 reserved_at_4c0[0x300]; 2805 }; 2806 2807 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2808 u8 life_time_counter_high[0x20]; 2809 2810 u8 life_time_counter_low[0x20]; 2811 2812 u8 rx_errors[0x20]; 2813 2814 u8 tx_errors[0x20]; 2815 2816 u8 l0_to_recovery_eieos[0x20]; 2817 2818 u8 l0_to_recovery_ts[0x20]; 2819 2820 u8 l0_to_recovery_framing[0x20]; 2821 2822 u8 l0_to_recovery_retrain[0x20]; 2823 2824 u8 crc_error_dllp[0x20]; 2825 2826 u8 crc_error_tlp[0x20]; 2827 2828 u8 tx_overflow_buffer_pkt_high[0x20]; 2829 2830 u8 tx_overflow_buffer_pkt_low[0x20]; 2831 2832 u8 outbound_stalled_reads[0x20]; 2833 2834 u8 outbound_stalled_writes[0x20]; 2835 2836 u8 outbound_stalled_reads_events[0x20]; 2837 2838 u8 outbound_stalled_writes_events[0x20]; 2839 2840 u8 reserved_at_200[0x5c0]; 2841 }; 2842 2843 struct mlx5_ifc_cmd_inter_comp_event_bits { 2844 u8 command_completion_vector[0x20]; 2845 2846 u8 reserved_at_20[0xc0]; 2847 }; 2848 2849 struct mlx5_ifc_stall_vl_event_bits { 2850 u8 reserved_at_0[0x18]; 2851 u8 port_num[0x1]; 2852 u8 reserved_at_19[0x3]; 2853 u8 vl[0x4]; 2854 2855 u8 reserved_at_20[0xa0]; 2856 }; 2857 2858 struct mlx5_ifc_db_bf_congestion_event_bits { 2859 u8 event_subtype[0x8]; 2860 u8 reserved_at_8[0x8]; 2861 u8 congestion_level[0x8]; 2862 u8 reserved_at_18[0x8]; 2863 2864 u8 reserved_at_20[0xa0]; 2865 }; 2866 2867 struct mlx5_ifc_gpio_event_bits { 2868 u8 reserved_at_0[0x60]; 2869 2870 u8 gpio_event_hi[0x20]; 2871 2872 u8 gpio_event_lo[0x20]; 2873 2874 u8 reserved_at_a0[0x40]; 2875 }; 2876 2877 struct mlx5_ifc_port_state_change_event_bits { 2878 u8 reserved_at_0[0x40]; 2879 2880 u8 port_num[0x4]; 2881 u8 reserved_at_44[0x1c]; 2882 2883 u8 reserved_at_60[0x80]; 2884 }; 2885 2886 struct mlx5_ifc_dropped_packet_logged_bits { 2887 u8 reserved_at_0[0xe0]; 2888 }; 2889 2890 struct mlx5_ifc_default_timeout_bits { 2891 u8 to_multiplier[0x3]; 2892 u8 reserved_at_3[0x9]; 2893 u8 to_value[0x14]; 2894 }; 2895 2896 struct mlx5_ifc_dtor_reg_bits { 2897 u8 reserved_at_0[0x20]; 2898 2899 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2900 2901 u8 reserved_at_40[0x60]; 2902 2903 struct mlx5_ifc_default_timeout_bits health_poll_to; 2904 2905 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2906 2907 struct mlx5_ifc_default_timeout_bits fw_reset_to; 2908 2909 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 2910 2911 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 2912 2913 struct mlx5_ifc_default_timeout_bits tear_down_to; 2914 2915 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 2916 2917 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 2918 2919 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 2920 2921 u8 reserved_at_1c0[0x40]; 2922 }; 2923 2924 enum { 2925 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2926 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2927 }; 2928 2929 struct mlx5_ifc_cq_error_bits { 2930 u8 reserved_at_0[0x8]; 2931 u8 cqn[0x18]; 2932 2933 u8 reserved_at_20[0x20]; 2934 2935 u8 reserved_at_40[0x18]; 2936 u8 syndrome[0x8]; 2937 2938 u8 reserved_at_60[0x80]; 2939 }; 2940 2941 struct mlx5_ifc_rdma_page_fault_event_bits { 2942 u8 bytes_committed[0x20]; 2943 2944 u8 r_key[0x20]; 2945 2946 u8 reserved_at_40[0x10]; 2947 u8 packet_len[0x10]; 2948 2949 u8 rdma_op_len[0x20]; 2950 2951 u8 rdma_va[0x40]; 2952 2953 u8 reserved_at_c0[0x5]; 2954 u8 rdma[0x1]; 2955 u8 write[0x1]; 2956 u8 requestor[0x1]; 2957 u8 qp_number[0x18]; 2958 }; 2959 2960 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2961 u8 bytes_committed[0x20]; 2962 2963 u8 reserved_at_20[0x10]; 2964 u8 wqe_index[0x10]; 2965 2966 u8 reserved_at_40[0x10]; 2967 u8 len[0x10]; 2968 2969 u8 reserved_at_60[0x60]; 2970 2971 u8 reserved_at_c0[0x5]; 2972 u8 rdma[0x1]; 2973 u8 write_read[0x1]; 2974 u8 requestor[0x1]; 2975 u8 qpn[0x18]; 2976 }; 2977 2978 struct mlx5_ifc_qp_events_bits { 2979 u8 reserved_at_0[0xa0]; 2980 2981 u8 type[0x8]; 2982 u8 reserved_at_a8[0x18]; 2983 2984 u8 reserved_at_c0[0x8]; 2985 u8 qpn_rqn_sqn[0x18]; 2986 }; 2987 2988 struct mlx5_ifc_dct_events_bits { 2989 u8 reserved_at_0[0xc0]; 2990 2991 u8 reserved_at_c0[0x8]; 2992 u8 dct_number[0x18]; 2993 }; 2994 2995 struct mlx5_ifc_comp_event_bits { 2996 u8 reserved_at_0[0xc0]; 2997 2998 u8 reserved_at_c0[0x8]; 2999 u8 cq_number[0x18]; 3000 }; 3001 3002 enum { 3003 MLX5_QPC_STATE_RST = 0x0, 3004 MLX5_QPC_STATE_INIT = 0x1, 3005 MLX5_QPC_STATE_RTR = 0x2, 3006 MLX5_QPC_STATE_RTS = 0x3, 3007 MLX5_QPC_STATE_SQER = 0x4, 3008 MLX5_QPC_STATE_ERR = 0x6, 3009 MLX5_QPC_STATE_SQD = 0x7, 3010 MLX5_QPC_STATE_SUSPENDED = 0x9, 3011 }; 3012 3013 enum { 3014 MLX5_QPC_ST_RC = 0x0, 3015 MLX5_QPC_ST_UC = 0x1, 3016 MLX5_QPC_ST_UD = 0x2, 3017 MLX5_QPC_ST_XRC = 0x3, 3018 MLX5_QPC_ST_DCI = 0x5, 3019 MLX5_QPC_ST_QP0 = 0x7, 3020 MLX5_QPC_ST_QP1 = 0x8, 3021 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3022 MLX5_QPC_ST_REG_UMR = 0xc, 3023 }; 3024 3025 enum { 3026 MLX5_QPC_PM_STATE_ARMED = 0x0, 3027 MLX5_QPC_PM_STATE_REARM = 0x1, 3028 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3029 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3030 }; 3031 3032 enum { 3033 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3034 }; 3035 3036 enum { 3037 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3038 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3039 }; 3040 3041 enum { 3042 MLX5_QPC_MTU_256_BYTES = 0x1, 3043 MLX5_QPC_MTU_512_BYTES = 0x2, 3044 MLX5_QPC_MTU_1K_BYTES = 0x3, 3045 MLX5_QPC_MTU_2K_BYTES = 0x4, 3046 MLX5_QPC_MTU_4K_BYTES = 0x5, 3047 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3048 }; 3049 3050 enum { 3051 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3052 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3053 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3054 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3055 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3056 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3057 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3058 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3059 }; 3060 3061 enum { 3062 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3063 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3064 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3065 }; 3066 3067 enum { 3068 MLX5_QPC_CS_RES_DISABLE = 0x0, 3069 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3070 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3071 }; 3072 3073 enum { 3074 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3075 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3076 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3077 }; 3078 3079 struct mlx5_ifc_qpc_bits { 3080 u8 state[0x4]; 3081 u8 lag_tx_port_affinity[0x4]; 3082 u8 st[0x8]; 3083 u8 reserved_at_10[0x2]; 3084 u8 isolate_vl_tc[0x1]; 3085 u8 pm_state[0x2]; 3086 u8 reserved_at_15[0x1]; 3087 u8 req_e2e_credit_mode[0x2]; 3088 u8 offload_type[0x4]; 3089 u8 end_padding_mode[0x2]; 3090 u8 reserved_at_1e[0x2]; 3091 3092 u8 wq_signature[0x1]; 3093 u8 block_lb_mc[0x1]; 3094 u8 atomic_like_write_en[0x1]; 3095 u8 latency_sensitive[0x1]; 3096 u8 reserved_at_24[0x1]; 3097 u8 drain_sigerr[0x1]; 3098 u8 reserved_at_26[0x2]; 3099 u8 pd[0x18]; 3100 3101 u8 mtu[0x3]; 3102 u8 log_msg_max[0x5]; 3103 u8 reserved_at_48[0x1]; 3104 u8 log_rq_size[0x4]; 3105 u8 log_rq_stride[0x3]; 3106 u8 no_sq[0x1]; 3107 u8 log_sq_size[0x4]; 3108 u8 reserved_at_55[0x3]; 3109 u8 ts_format[0x2]; 3110 u8 reserved_at_5a[0x1]; 3111 u8 rlky[0x1]; 3112 u8 ulp_stateless_offload_mode[0x4]; 3113 3114 u8 counter_set_id[0x8]; 3115 u8 uar_page[0x18]; 3116 3117 u8 reserved_at_80[0x8]; 3118 u8 user_index[0x18]; 3119 3120 u8 reserved_at_a0[0x3]; 3121 u8 log_page_size[0x5]; 3122 u8 remote_qpn[0x18]; 3123 3124 struct mlx5_ifc_ads_bits primary_address_path; 3125 3126 struct mlx5_ifc_ads_bits secondary_address_path; 3127 3128 u8 log_ack_req_freq[0x4]; 3129 u8 reserved_at_384[0x4]; 3130 u8 log_sra_max[0x3]; 3131 u8 reserved_at_38b[0x2]; 3132 u8 retry_count[0x3]; 3133 u8 rnr_retry[0x3]; 3134 u8 reserved_at_393[0x1]; 3135 u8 fre[0x1]; 3136 u8 cur_rnr_retry[0x3]; 3137 u8 cur_retry_count[0x3]; 3138 u8 reserved_at_39b[0x5]; 3139 3140 u8 reserved_at_3a0[0x20]; 3141 3142 u8 reserved_at_3c0[0x8]; 3143 u8 next_send_psn[0x18]; 3144 3145 u8 reserved_at_3e0[0x3]; 3146 u8 log_num_dci_stream_channels[0x5]; 3147 u8 cqn_snd[0x18]; 3148 3149 u8 reserved_at_400[0x3]; 3150 u8 log_num_dci_errored_streams[0x5]; 3151 u8 deth_sqpn[0x18]; 3152 3153 u8 reserved_at_420[0x20]; 3154 3155 u8 reserved_at_440[0x8]; 3156 u8 last_acked_psn[0x18]; 3157 3158 u8 reserved_at_460[0x8]; 3159 u8 ssn[0x18]; 3160 3161 u8 reserved_at_480[0x8]; 3162 u8 log_rra_max[0x3]; 3163 u8 reserved_at_48b[0x1]; 3164 u8 atomic_mode[0x4]; 3165 u8 rre[0x1]; 3166 u8 rwe[0x1]; 3167 u8 rae[0x1]; 3168 u8 reserved_at_493[0x1]; 3169 u8 page_offset[0x6]; 3170 u8 reserved_at_49a[0x3]; 3171 u8 cd_slave_receive[0x1]; 3172 u8 cd_slave_send[0x1]; 3173 u8 cd_master[0x1]; 3174 3175 u8 reserved_at_4a0[0x3]; 3176 u8 min_rnr_nak[0x5]; 3177 u8 next_rcv_psn[0x18]; 3178 3179 u8 reserved_at_4c0[0x8]; 3180 u8 xrcd[0x18]; 3181 3182 u8 reserved_at_4e0[0x8]; 3183 u8 cqn_rcv[0x18]; 3184 3185 u8 dbr_addr[0x40]; 3186 3187 u8 q_key[0x20]; 3188 3189 u8 reserved_at_560[0x5]; 3190 u8 rq_type[0x3]; 3191 u8 srqn_rmpn_xrqn[0x18]; 3192 3193 u8 reserved_at_580[0x8]; 3194 u8 rmsn[0x18]; 3195 3196 u8 hw_sq_wqebb_counter[0x10]; 3197 u8 sw_sq_wqebb_counter[0x10]; 3198 3199 u8 hw_rq_counter[0x20]; 3200 3201 u8 sw_rq_counter[0x20]; 3202 3203 u8 reserved_at_600[0x20]; 3204 3205 u8 reserved_at_620[0xf]; 3206 u8 cgs[0x1]; 3207 u8 cs_req[0x8]; 3208 u8 cs_res[0x8]; 3209 3210 u8 dc_access_key[0x40]; 3211 3212 u8 reserved_at_680[0x3]; 3213 u8 dbr_umem_valid[0x1]; 3214 3215 u8 reserved_at_684[0xbc]; 3216 }; 3217 3218 struct mlx5_ifc_roce_addr_layout_bits { 3219 u8 source_l3_address[16][0x8]; 3220 3221 u8 reserved_at_80[0x3]; 3222 u8 vlan_valid[0x1]; 3223 u8 vlan_id[0xc]; 3224 u8 source_mac_47_32[0x10]; 3225 3226 u8 source_mac_31_0[0x20]; 3227 3228 u8 reserved_at_c0[0x14]; 3229 u8 roce_l3_type[0x4]; 3230 u8 roce_version[0x8]; 3231 3232 u8 reserved_at_e0[0x20]; 3233 }; 3234 3235 struct mlx5_ifc_shampo_cap_bits { 3236 u8 reserved_at_0[0x3]; 3237 u8 shampo_log_max_reservation_size[0x5]; 3238 u8 reserved_at_8[0x3]; 3239 u8 shampo_log_min_reservation_size[0x5]; 3240 u8 shampo_min_mss_size[0x10]; 3241 3242 u8 reserved_at_20[0x3]; 3243 u8 shampo_max_log_headers_entry_size[0x5]; 3244 u8 reserved_at_28[0x18]; 3245 3246 u8 reserved_at_40[0x7c0]; 3247 }; 3248 3249 union mlx5_ifc_hca_cap_union_bits { 3250 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3251 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3252 struct mlx5_ifc_odp_cap_bits odp_cap; 3253 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3254 struct mlx5_ifc_roce_cap_bits roce_cap; 3255 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3256 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3257 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3258 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3259 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3260 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3261 struct mlx5_ifc_qos_cap_bits qos_cap; 3262 struct mlx5_ifc_debug_cap_bits debug_cap; 3263 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3264 struct mlx5_ifc_tls_cap_bits tls_cap; 3265 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3266 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3267 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3268 u8 reserved_at_0[0x8000]; 3269 }; 3270 3271 enum { 3272 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3273 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3274 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3275 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3276 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3277 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3278 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3279 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3280 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3281 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3282 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3283 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3284 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3285 }; 3286 3287 enum { 3288 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3289 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3290 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3291 }; 3292 3293 struct mlx5_ifc_vlan_bits { 3294 u8 ethtype[0x10]; 3295 u8 prio[0x3]; 3296 u8 cfi[0x1]; 3297 u8 vid[0xc]; 3298 }; 3299 3300 struct mlx5_ifc_flow_context_bits { 3301 struct mlx5_ifc_vlan_bits push_vlan; 3302 3303 u8 group_id[0x20]; 3304 3305 u8 reserved_at_40[0x8]; 3306 u8 flow_tag[0x18]; 3307 3308 u8 reserved_at_60[0x10]; 3309 u8 action[0x10]; 3310 3311 u8 extended_destination[0x1]; 3312 u8 reserved_at_81[0x1]; 3313 u8 flow_source[0x2]; 3314 u8 reserved_at_84[0x4]; 3315 u8 destination_list_size[0x18]; 3316 3317 u8 reserved_at_a0[0x8]; 3318 u8 flow_counter_list_size[0x18]; 3319 3320 u8 packet_reformat_id[0x20]; 3321 3322 u8 modify_header_id[0x20]; 3323 3324 struct mlx5_ifc_vlan_bits push_vlan_2; 3325 3326 u8 ipsec_obj_id[0x20]; 3327 u8 reserved_at_140[0xc0]; 3328 3329 struct mlx5_ifc_fte_match_param_bits match_value; 3330 3331 u8 reserved_at_1200[0x600]; 3332 3333 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3334 }; 3335 3336 enum { 3337 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3338 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3339 }; 3340 3341 struct mlx5_ifc_xrc_srqc_bits { 3342 u8 state[0x4]; 3343 u8 log_xrc_srq_size[0x4]; 3344 u8 reserved_at_8[0x18]; 3345 3346 u8 wq_signature[0x1]; 3347 u8 cont_srq[0x1]; 3348 u8 reserved_at_22[0x1]; 3349 u8 rlky[0x1]; 3350 u8 basic_cyclic_rcv_wqe[0x1]; 3351 u8 log_rq_stride[0x3]; 3352 u8 xrcd[0x18]; 3353 3354 u8 page_offset[0x6]; 3355 u8 reserved_at_46[0x1]; 3356 u8 dbr_umem_valid[0x1]; 3357 u8 cqn[0x18]; 3358 3359 u8 reserved_at_60[0x20]; 3360 3361 u8 user_index_equal_xrc_srqn[0x1]; 3362 u8 reserved_at_81[0x1]; 3363 u8 log_page_size[0x6]; 3364 u8 user_index[0x18]; 3365 3366 u8 reserved_at_a0[0x20]; 3367 3368 u8 reserved_at_c0[0x8]; 3369 u8 pd[0x18]; 3370 3371 u8 lwm[0x10]; 3372 u8 wqe_cnt[0x10]; 3373 3374 u8 reserved_at_100[0x40]; 3375 3376 u8 db_record_addr_h[0x20]; 3377 3378 u8 db_record_addr_l[0x1e]; 3379 u8 reserved_at_17e[0x2]; 3380 3381 u8 reserved_at_180[0x80]; 3382 }; 3383 3384 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3385 u8 counter_error_queues[0x20]; 3386 3387 u8 total_error_queues[0x20]; 3388 3389 u8 send_queue_priority_update_flow[0x20]; 3390 3391 u8 reserved_at_60[0x20]; 3392 3393 u8 nic_receive_steering_discard[0x40]; 3394 3395 u8 receive_discard_vport_down[0x40]; 3396 3397 u8 transmit_discard_vport_down[0x40]; 3398 3399 u8 reserved_at_140[0xa0]; 3400 3401 u8 internal_rq_out_of_buffer[0x20]; 3402 3403 u8 reserved_at_200[0xe00]; 3404 }; 3405 3406 struct mlx5_ifc_traffic_counter_bits { 3407 u8 packets[0x40]; 3408 3409 u8 octets[0x40]; 3410 }; 3411 3412 struct mlx5_ifc_tisc_bits { 3413 u8 strict_lag_tx_port_affinity[0x1]; 3414 u8 tls_en[0x1]; 3415 u8 reserved_at_2[0x2]; 3416 u8 lag_tx_port_affinity[0x04]; 3417 3418 u8 reserved_at_8[0x4]; 3419 u8 prio[0x4]; 3420 u8 reserved_at_10[0x10]; 3421 3422 u8 reserved_at_20[0x100]; 3423 3424 u8 reserved_at_120[0x8]; 3425 u8 transport_domain[0x18]; 3426 3427 u8 reserved_at_140[0x8]; 3428 u8 underlay_qpn[0x18]; 3429 3430 u8 reserved_at_160[0x8]; 3431 u8 pd[0x18]; 3432 3433 u8 reserved_at_180[0x380]; 3434 }; 3435 3436 enum { 3437 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3438 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3439 }; 3440 3441 enum { 3442 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3443 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3444 MLX5_TIRC_PACKET_MERGE_MASK_SHAMPO = BIT(2), 3445 }; 3446 3447 enum { 3448 MLX5_RX_HASH_FN_NONE = 0x0, 3449 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3450 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3451 }; 3452 3453 enum { 3454 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3455 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3456 }; 3457 3458 struct mlx5_ifc_tirc_bits { 3459 u8 reserved_at_0[0x20]; 3460 3461 u8 disp_type[0x4]; 3462 u8 tls_en[0x1]; 3463 u8 reserved_at_25[0x1b]; 3464 3465 u8 reserved_at_40[0x40]; 3466 3467 u8 reserved_at_80[0x4]; 3468 u8 lro_timeout_period_usecs[0x10]; 3469 u8 packet_merge_mask[0x4]; 3470 u8 lro_max_ip_payload_size[0x8]; 3471 3472 u8 reserved_at_a0[0x40]; 3473 3474 u8 reserved_at_e0[0x8]; 3475 u8 inline_rqn[0x18]; 3476 3477 u8 rx_hash_symmetric[0x1]; 3478 u8 reserved_at_101[0x1]; 3479 u8 tunneled_offload_en[0x1]; 3480 u8 reserved_at_103[0x5]; 3481 u8 indirect_table[0x18]; 3482 3483 u8 rx_hash_fn[0x4]; 3484 u8 reserved_at_124[0x2]; 3485 u8 self_lb_block[0x2]; 3486 u8 transport_domain[0x18]; 3487 3488 u8 rx_hash_toeplitz_key[10][0x20]; 3489 3490 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3491 3492 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3493 3494 u8 reserved_at_2c0[0x4c0]; 3495 }; 3496 3497 enum { 3498 MLX5_SRQC_STATE_GOOD = 0x0, 3499 MLX5_SRQC_STATE_ERROR = 0x1, 3500 }; 3501 3502 struct mlx5_ifc_srqc_bits { 3503 u8 state[0x4]; 3504 u8 log_srq_size[0x4]; 3505 u8 reserved_at_8[0x18]; 3506 3507 u8 wq_signature[0x1]; 3508 u8 cont_srq[0x1]; 3509 u8 reserved_at_22[0x1]; 3510 u8 rlky[0x1]; 3511 u8 reserved_at_24[0x1]; 3512 u8 log_rq_stride[0x3]; 3513 u8 xrcd[0x18]; 3514 3515 u8 page_offset[0x6]; 3516 u8 reserved_at_46[0x2]; 3517 u8 cqn[0x18]; 3518 3519 u8 reserved_at_60[0x20]; 3520 3521 u8 reserved_at_80[0x2]; 3522 u8 log_page_size[0x6]; 3523 u8 reserved_at_88[0x18]; 3524 3525 u8 reserved_at_a0[0x20]; 3526 3527 u8 reserved_at_c0[0x8]; 3528 u8 pd[0x18]; 3529 3530 u8 lwm[0x10]; 3531 u8 wqe_cnt[0x10]; 3532 3533 u8 reserved_at_100[0x40]; 3534 3535 u8 dbr_addr[0x40]; 3536 3537 u8 reserved_at_180[0x80]; 3538 }; 3539 3540 enum { 3541 MLX5_SQC_STATE_RST = 0x0, 3542 MLX5_SQC_STATE_RDY = 0x1, 3543 MLX5_SQC_STATE_ERR = 0x3, 3544 }; 3545 3546 struct mlx5_ifc_sqc_bits { 3547 u8 rlky[0x1]; 3548 u8 cd_master[0x1]; 3549 u8 fre[0x1]; 3550 u8 flush_in_error_en[0x1]; 3551 u8 allow_multi_pkt_send_wqe[0x1]; 3552 u8 min_wqe_inline_mode[0x3]; 3553 u8 state[0x4]; 3554 u8 reg_umr[0x1]; 3555 u8 allow_swp[0x1]; 3556 u8 hairpin[0x1]; 3557 u8 reserved_at_f[0xb]; 3558 u8 ts_format[0x2]; 3559 u8 reserved_at_1c[0x4]; 3560 3561 u8 reserved_at_20[0x8]; 3562 u8 user_index[0x18]; 3563 3564 u8 reserved_at_40[0x8]; 3565 u8 cqn[0x18]; 3566 3567 u8 reserved_at_60[0x8]; 3568 u8 hairpin_peer_rq[0x18]; 3569 3570 u8 reserved_at_80[0x10]; 3571 u8 hairpin_peer_vhca[0x10]; 3572 3573 u8 reserved_at_a0[0x20]; 3574 3575 u8 reserved_at_c0[0x8]; 3576 u8 ts_cqe_to_dest_cqn[0x18]; 3577 3578 u8 reserved_at_e0[0x10]; 3579 u8 packet_pacing_rate_limit_index[0x10]; 3580 u8 tis_lst_sz[0x10]; 3581 u8 qos_queue_group_id[0x10]; 3582 3583 u8 reserved_at_120[0x40]; 3584 3585 u8 reserved_at_160[0x8]; 3586 u8 tis_num_0[0x18]; 3587 3588 struct mlx5_ifc_wq_bits wq; 3589 }; 3590 3591 enum { 3592 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3593 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3594 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3595 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3596 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3597 }; 3598 3599 enum { 3600 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3601 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3602 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3603 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3604 }; 3605 3606 struct mlx5_ifc_scheduling_context_bits { 3607 u8 element_type[0x8]; 3608 u8 reserved_at_8[0x18]; 3609 3610 u8 element_attributes[0x20]; 3611 3612 u8 parent_element_id[0x20]; 3613 3614 u8 reserved_at_60[0x40]; 3615 3616 u8 bw_share[0x20]; 3617 3618 u8 max_average_bw[0x20]; 3619 3620 u8 reserved_at_e0[0x120]; 3621 }; 3622 3623 struct mlx5_ifc_rqtc_bits { 3624 u8 reserved_at_0[0xa0]; 3625 3626 u8 reserved_at_a0[0x5]; 3627 u8 list_q_type[0x3]; 3628 u8 reserved_at_a8[0x8]; 3629 u8 rqt_max_size[0x10]; 3630 3631 u8 rq_vhca_id_format[0x1]; 3632 u8 reserved_at_c1[0xf]; 3633 u8 rqt_actual_size[0x10]; 3634 3635 u8 reserved_at_e0[0x6a0]; 3636 3637 struct mlx5_ifc_rq_num_bits rq_num[]; 3638 }; 3639 3640 enum { 3641 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3642 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3643 }; 3644 3645 enum { 3646 MLX5_RQC_STATE_RST = 0x0, 3647 MLX5_RQC_STATE_RDY = 0x1, 3648 MLX5_RQC_STATE_ERR = 0x3, 3649 }; 3650 3651 enum { 3652 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3653 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3654 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3655 }; 3656 3657 enum { 3658 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3659 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3660 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3661 }; 3662 3663 struct mlx5_ifc_rqc_bits { 3664 u8 rlky[0x1]; 3665 u8 delay_drop_en[0x1]; 3666 u8 scatter_fcs[0x1]; 3667 u8 vsd[0x1]; 3668 u8 mem_rq_type[0x4]; 3669 u8 state[0x4]; 3670 u8 reserved_at_c[0x1]; 3671 u8 flush_in_error_en[0x1]; 3672 u8 hairpin[0x1]; 3673 u8 reserved_at_f[0xb]; 3674 u8 ts_format[0x2]; 3675 u8 reserved_at_1c[0x4]; 3676 3677 u8 reserved_at_20[0x8]; 3678 u8 user_index[0x18]; 3679 3680 u8 reserved_at_40[0x8]; 3681 u8 cqn[0x18]; 3682 3683 u8 counter_set_id[0x8]; 3684 u8 reserved_at_68[0x18]; 3685 3686 u8 reserved_at_80[0x8]; 3687 u8 rmpn[0x18]; 3688 3689 u8 reserved_at_a0[0x8]; 3690 u8 hairpin_peer_sq[0x18]; 3691 3692 u8 reserved_at_c0[0x10]; 3693 u8 hairpin_peer_vhca[0x10]; 3694 3695 u8 reserved_at_e0[0x46]; 3696 u8 shampo_no_match_alignment_granularity[0x2]; 3697 u8 reserved_at_128[0x6]; 3698 u8 shampo_match_criteria_type[0x2]; 3699 u8 reservation_timeout[0x10]; 3700 3701 u8 reserved_at_140[0x40]; 3702 3703 struct mlx5_ifc_wq_bits wq; 3704 }; 3705 3706 enum { 3707 MLX5_RMPC_STATE_RDY = 0x1, 3708 MLX5_RMPC_STATE_ERR = 0x3, 3709 }; 3710 3711 struct mlx5_ifc_rmpc_bits { 3712 u8 reserved_at_0[0x8]; 3713 u8 state[0x4]; 3714 u8 reserved_at_c[0x14]; 3715 3716 u8 basic_cyclic_rcv_wqe[0x1]; 3717 u8 reserved_at_21[0x1f]; 3718 3719 u8 reserved_at_40[0x140]; 3720 3721 struct mlx5_ifc_wq_bits wq; 3722 }; 3723 3724 struct mlx5_ifc_nic_vport_context_bits { 3725 u8 reserved_at_0[0x5]; 3726 u8 min_wqe_inline_mode[0x3]; 3727 u8 reserved_at_8[0x15]; 3728 u8 disable_mc_local_lb[0x1]; 3729 u8 disable_uc_local_lb[0x1]; 3730 u8 roce_en[0x1]; 3731 3732 u8 arm_change_event[0x1]; 3733 u8 reserved_at_21[0x1a]; 3734 u8 event_on_mtu[0x1]; 3735 u8 event_on_promisc_change[0x1]; 3736 u8 event_on_vlan_change[0x1]; 3737 u8 event_on_mc_address_change[0x1]; 3738 u8 event_on_uc_address_change[0x1]; 3739 3740 u8 reserved_at_40[0xc]; 3741 3742 u8 affiliation_criteria[0x4]; 3743 u8 affiliated_vhca_id[0x10]; 3744 3745 u8 reserved_at_60[0xd0]; 3746 3747 u8 mtu[0x10]; 3748 3749 u8 system_image_guid[0x40]; 3750 u8 port_guid[0x40]; 3751 u8 node_guid[0x40]; 3752 3753 u8 reserved_at_200[0x140]; 3754 u8 qkey_violation_counter[0x10]; 3755 u8 reserved_at_350[0x430]; 3756 3757 u8 promisc_uc[0x1]; 3758 u8 promisc_mc[0x1]; 3759 u8 promisc_all[0x1]; 3760 u8 reserved_at_783[0x2]; 3761 u8 allowed_list_type[0x3]; 3762 u8 reserved_at_788[0xc]; 3763 u8 allowed_list_size[0xc]; 3764 3765 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3766 3767 u8 reserved_at_7e0[0x20]; 3768 3769 u8 current_uc_mac_address[][0x40]; 3770 }; 3771 3772 enum { 3773 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3774 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3775 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3776 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3777 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3778 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3779 }; 3780 3781 struct mlx5_ifc_mkc_bits { 3782 u8 reserved_at_0[0x1]; 3783 u8 free[0x1]; 3784 u8 reserved_at_2[0x1]; 3785 u8 access_mode_4_2[0x3]; 3786 u8 reserved_at_6[0x7]; 3787 u8 relaxed_ordering_write[0x1]; 3788 u8 reserved_at_e[0x1]; 3789 u8 small_fence_on_rdma_read_response[0x1]; 3790 u8 umr_en[0x1]; 3791 u8 a[0x1]; 3792 u8 rw[0x1]; 3793 u8 rr[0x1]; 3794 u8 lw[0x1]; 3795 u8 lr[0x1]; 3796 u8 access_mode_1_0[0x2]; 3797 u8 reserved_at_18[0x8]; 3798 3799 u8 qpn[0x18]; 3800 u8 mkey_7_0[0x8]; 3801 3802 u8 reserved_at_40[0x20]; 3803 3804 u8 length64[0x1]; 3805 u8 bsf_en[0x1]; 3806 u8 sync_umr[0x1]; 3807 u8 reserved_at_63[0x2]; 3808 u8 expected_sigerr_count[0x1]; 3809 u8 reserved_at_66[0x1]; 3810 u8 en_rinval[0x1]; 3811 u8 pd[0x18]; 3812 3813 u8 start_addr[0x40]; 3814 3815 u8 len[0x40]; 3816 3817 u8 bsf_octword_size[0x20]; 3818 3819 u8 reserved_at_120[0x80]; 3820 3821 u8 translations_octword_size[0x20]; 3822 3823 u8 reserved_at_1c0[0x19]; 3824 u8 relaxed_ordering_read[0x1]; 3825 u8 reserved_at_1d9[0x1]; 3826 u8 log_page_size[0x5]; 3827 3828 u8 reserved_at_1e0[0x20]; 3829 }; 3830 3831 struct mlx5_ifc_pkey_bits { 3832 u8 reserved_at_0[0x10]; 3833 u8 pkey[0x10]; 3834 }; 3835 3836 struct mlx5_ifc_array128_auto_bits { 3837 u8 array128_auto[16][0x8]; 3838 }; 3839 3840 struct mlx5_ifc_hca_vport_context_bits { 3841 u8 field_select[0x20]; 3842 3843 u8 reserved_at_20[0xe0]; 3844 3845 u8 sm_virt_aware[0x1]; 3846 u8 has_smi[0x1]; 3847 u8 has_raw[0x1]; 3848 u8 grh_required[0x1]; 3849 u8 reserved_at_104[0xc]; 3850 u8 port_physical_state[0x4]; 3851 u8 vport_state_policy[0x4]; 3852 u8 port_state[0x4]; 3853 u8 vport_state[0x4]; 3854 3855 u8 reserved_at_120[0x20]; 3856 3857 u8 system_image_guid[0x40]; 3858 3859 u8 port_guid[0x40]; 3860 3861 u8 node_guid[0x40]; 3862 3863 u8 cap_mask1[0x20]; 3864 3865 u8 cap_mask1_field_select[0x20]; 3866 3867 u8 cap_mask2[0x20]; 3868 3869 u8 cap_mask2_field_select[0x20]; 3870 3871 u8 reserved_at_280[0x80]; 3872 3873 u8 lid[0x10]; 3874 u8 reserved_at_310[0x4]; 3875 u8 init_type_reply[0x4]; 3876 u8 lmc[0x3]; 3877 u8 subnet_timeout[0x5]; 3878 3879 u8 sm_lid[0x10]; 3880 u8 sm_sl[0x4]; 3881 u8 reserved_at_334[0xc]; 3882 3883 u8 qkey_violation_counter[0x10]; 3884 u8 pkey_violation_counter[0x10]; 3885 3886 u8 reserved_at_360[0xca0]; 3887 }; 3888 3889 struct mlx5_ifc_esw_vport_context_bits { 3890 u8 fdb_to_vport_reg_c[0x1]; 3891 u8 reserved_at_1[0x2]; 3892 u8 vport_svlan_strip[0x1]; 3893 u8 vport_cvlan_strip[0x1]; 3894 u8 vport_svlan_insert[0x1]; 3895 u8 vport_cvlan_insert[0x2]; 3896 u8 fdb_to_vport_reg_c_id[0x8]; 3897 u8 reserved_at_10[0x10]; 3898 3899 u8 reserved_at_20[0x20]; 3900 3901 u8 svlan_cfi[0x1]; 3902 u8 svlan_pcp[0x3]; 3903 u8 svlan_id[0xc]; 3904 u8 cvlan_cfi[0x1]; 3905 u8 cvlan_pcp[0x3]; 3906 u8 cvlan_id[0xc]; 3907 3908 u8 reserved_at_60[0x720]; 3909 3910 u8 sw_steering_vport_icm_address_rx[0x40]; 3911 3912 u8 sw_steering_vport_icm_address_tx[0x40]; 3913 }; 3914 3915 enum { 3916 MLX5_EQC_STATUS_OK = 0x0, 3917 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3918 }; 3919 3920 enum { 3921 MLX5_EQC_ST_ARMED = 0x9, 3922 MLX5_EQC_ST_FIRED = 0xa, 3923 }; 3924 3925 struct mlx5_ifc_eqc_bits { 3926 u8 status[0x4]; 3927 u8 reserved_at_4[0x9]; 3928 u8 ec[0x1]; 3929 u8 oi[0x1]; 3930 u8 reserved_at_f[0x5]; 3931 u8 st[0x4]; 3932 u8 reserved_at_18[0x8]; 3933 3934 u8 reserved_at_20[0x20]; 3935 3936 u8 reserved_at_40[0x14]; 3937 u8 page_offset[0x6]; 3938 u8 reserved_at_5a[0x6]; 3939 3940 u8 reserved_at_60[0x3]; 3941 u8 log_eq_size[0x5]; 3942 u8 uar_page[0x18]; 3943 3944 u8 reserved_at_80[0x20]; 3945 3946 u8 reserved_at_a0[0x14]; 3947 u8 intr[0xc]; 3948 3949 u8 reserved_at_c0[0x3]; 3950 u8 log_page_size[0x5]; 3951 u8 reserved_at_c8[0x18]; 3952 3953 u8 reserved_at_e0[0x60]; 3954 3955 u8 reserved_at_140[0x8]; 3956 u8 consumer_counter[0x18]; 3957 3958 u8 reserved_at_160[0x8]; 3959 u8 producer_counter[0x18]; 3960 3961 u8 reserved_at_180[0x80]; 3962 }; 3963 3964 enum { 3965 MLX5_DCTC_STATE_ACTIVE = 0x0, 3966 MLX5_DCTC_STATE_DRAINING = 0x1, 3967 MLX5_DCTC_STATE_DRAINED = 0x2, 3968 }; 3969 3970 enum { 3971 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3972 MLX5_DCTC_CS_RES_NA = 0x1, 3973 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3974 }; 3975 3976 enum { 3977 MLX5_DCTC_MTU_256_BYTES = 0x1, 3978 MLX5_DCTC_MTU_512_BYTES = 0x2, 3979 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3980 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3981 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3982 }; 3983 3984 struct mlx5_ifc_dctc_bits { 3985 u8 reserved_at_0[0x4]; 3986 u8 state[0x4]; 3987 u8 reserved_at_8[0x18]; 3988 3989 u8 reserved_at_20[0x8]; 3990 u8 user_index[0x18]; 3991 3992 u8 reserved_at_40[0x8]; 3993 u8 cqn[0x18]; 3994 3995 u8 counter_set_id[0x8]; 3996 u8 atomic_mode[0x4]; 3997 u8 rre[0x1]; 3998 u8 rwe[0x1]; 3999 u8 rae[0x1]; 4000 u8 atomic_like_write_en[0x1]; 4001 u8 latency_sensitive[0x1]; 4002 u8 rlky[0x1]; 4003 u8 free_ar[0x1]; 4004 u8 reserved_at_73[0xd]; 4005 4006 u8 reserved_at_80[0x8]; 4007 u8 cs_res[0x8]; 4008 u8 reserved_at_90[0x3]; 4009 u8 min_rnr_nak[0x5]; 4010 u8 reserved_at_98[0x8]; 4011 4012 u8 reserved_at_a0[0x8]; 4013 u8 srqn_xrqn[0x18]; 4014 4015 u8 reserved_at_c0[0x8]; 4016 u8 pd[0x18]; 4017 4018 u8 tclass[0x8]; 4019 u8 reserved_at_e8[0x4]; 4020 u8 flow_label[0x14]; 4021 4022 u8 dc_access_key[0x40]; 4023 4024 u8 reserved_at_140[0x5]; 4025 u8 mtu[0x3]; 4026 u8 port[0x8]; 4027 u8 pkey_index[0x10]; 4028 4029 u8 reserved_at_160[0x8]; 4030 u8 my_addr_index[0x8]; 4031 u8 reserved_at_170[0x8]; 4032 u8 hop_limit[0x8]; 4033 4034 u8 dc_access_key_violation_count[0x20]; 4035 4036 u8 reserved_at_1a0[0x14]; 4037 u8 dei_cfi[0x1]; 4038 u8 eth_prio[0x3]; 4039 u8 ecn[0x2]; 4040 u8 dscp[0x6]; 4041 4042 u8 reserved_at_1c0[0x20]; 4043 u8 ece[0x20]; 4044 }; 4045 4046 enum { 4047 MLX5_CQC_STATUS_OK = 0x0, 4048 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4049 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4050 }; 4051 4052 enum { 4053 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4054 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4055 }; 4056 4057 enum { 4058 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4059 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4060 MLX5_CQC_ST_FIRED = 0xa, 4061 }; 4062 4063 enum { 4064 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4065 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4066 MLX5_CQ_PERIOD_NUM_MODES 4067 }; 4068 4069 struct mlx5_ifc_cqc_bits { 4070 u8 status[0x4]; 4071 u8 reserved_at_4[0x2]; 4072 u8 dbr_umem_valid[0x1]; 4073 u8 apu_cq[0x1]; 4074 u8 cqe_sz[0x3]; 4075 u8 cc[0x1]; 4076 u8 reserved_at_c[0x1]; 4077 u8 scqe_break_moderation_en[0x1]; 4078 u8 oi[0x1]; 4079 u8 cq_period_mode[0x2]; 4080 u8 cqe_comp_en[0x1]; 4081 u8 mini_cqe_res_format[0x2]; 4082 u8 st[0x4]; 4083 u8 reserved_at_18[0x8]; 4084 4085 u8 reserved_at_20[0x20]; 4086 4087 u8 reserved_at_40[0x14]; 4088 u8 page_offset[0x6]; 4089 u8 reserved_at_5a[0x6]; 4090 4091 u8 reserved_at_60[0x3]; 4092 u8 log_cq_size[0x5]; 4093 u8 uar_page[0x18]; 4094 4095 u8 reserved_at_80[0x4]; 4096 u8 cq_period[0xc]; 4097 u8 cq_max_count[0x10]; 4098 4099 u8 c_eqn_or_apu_element[0x20]; 4100 4101 u8 reserved_at_c0[0x3]; 4102 u8 log_page_size[0x5]; 4103 u8 reserved_at_c8[0x18]; 4104 4105 u8 reserved_at_e0[0x20]; 4106 4107 u8 reserved_at_100[0x8]; 4108 u8 last_notified_index[0x18]; 4109 4110 u8 reserved_at_120[0x8]; 4111 u8 last_solicit_index[0x18]; 4112 4113 u8 reserved_at_140[0x8]; 4114 u8 consumer_counter[0x18]; 4115 4116 u8 reserved_at_160[0x8]; 4117 u8 producer_counter[0x18]; 4118 4119 u8 reserved_at_180[0x40]; 4120 4121 u8 dbr_addr[0x40]; 4122 }; 4123 4124 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4125 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4126 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4127 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4128 u8 reserved_at_0[0x800]; 4129 }; 4130 4131 struct mlx5_ifc_query_adapter_param_block_bits { 4132 u8 reserved_at_0[0xc0]; 4133 4134 u8 reserved_at_c0[0x8]; 4135 u8 ieee_vendor_id[0x18]; 4136 4137 u8 reserved_at_e0[0x10]; 4138 u8 vsd_vendor_id[0x10]; 4139 4140 u8 vsd[208][0x8]; 4141 4142 u8 vsd_contd_psid[16][0x8]; 4143 }; 4144 4145 enum { 4146 MLX5_XRQC_STATE_GOOD = 0x0, 4147 MLX5_XRQC_STATE_ERROR = 0x1, 4148 }; 4149 4150 enum { 4151 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4152 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4153 }; 4154 4155 enum { 4156 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4157 }; 4158 4159 struct mlx5_ifc_tag_matching_topology_context_bits { 4160 u8 log_matching_list_sz[0x4]; 4161 u8 reserved_at_4[0xc]; 4162 u8 append_next_index[0x10]; 4163 4164 u8 sw_phase_cnt[0x10]; 4165 u8 hw_phase_cnt[0x10]; 4166 4167 u8 reserved_at_40[0x40]; 4168 }; 4169 4170 struct mlx5_ifc_xrqc_bits { 4171 u8 state[0x4]; 4172 u8 rlkey[0x1]; 4173 u8 reserved_at_5[0xf]; 4174 u8 topology[0x4]; 4175 u8 reserved_at_18[0x4]; 4176 u8 offload[0x4]; 4177 4178 u8 reserved_at_20[0x8]; 4179 u8 user_index[0x18]; 4180 4181 u8 reserved_at_40[0x8]; 4182 u8 cqn[0x18]; 4183 4184 u8 reserved_at_60[0xa0]; 4185 4186 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4187 4188 u8 reserved_at_180[0x280]; 4189 4190 struct mlx5_ifc_wq_bits wq; 4191 }; 4192 4193 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4194 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4195 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4196 u8 reserved_at_0[0x20]; 4197 }; 4198 4199 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4200 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4201 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4202 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4203 u8 reserved_at_0[0x20]; 4204 }; 4205 4206 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4207 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4208 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4209 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4210 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4211 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4212 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4213 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4214 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4215 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4216 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4217 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4218 u8 reserved_at_0[0x7c0]; 4219 }; 4220 4221 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4222 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4223 u8 reserved_at_0[0x7c0]; 4224 }; 4225 4226 union mlx5_ifc_event_auto_bits { 4227 struct mlx5_ifc_comp_event_bits comp_event; 4228 struct mlx5_ifc_dct_events_bits dct_events; 4229 struct mlx5_ifc_qp_events_bits qp_events; 4230 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4231 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4232 struct mlx5_ifc_cq_error_bits cq_error; 4233 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4234 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4235 struct mlx5_ifc_gpio_event_bits gpio_event; 4236 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4237 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4238 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4239 u8 reserved_at_0[0xe0]; 4240 }; 4241 4242 struct mlx5_ifc_health_buffer_bits { 4243 u8 reserved_at_0[0x100]; 4244 4245 u8 assert_existptr[0x20]; 4246 4247 u8 assert_callra[0x20]; 4248 4249 u8 reserved_at_140[0x20]; 4250 4251 u8 time[0x20]; 4252 4253 u8 fw_version[0x20]; 4254 4255 u8 hw_id[0x20]; 4256 4257 u8 rfr[0x1]; 4258 u8 reserved_at_1c1[0x3]; 4259 u8 valid[0x1]; 4260 u8 severity[0x3]; 4261 u8 reserved_at_1c8[0x18]; 4262 4263 u8 irisc_index[0x8]; 4264 u8 synd[0x8]; 4265 u8 ext_synd[0x10]; 4266 }; 4267 4268 struct mlx5_ifc_register_loopback_control_bits { 4269 u8 no_lb[0x1]; 4270 u8 reserved_at_1[0x7]; 4271 u8 port[0x8]; 4272 u8 reserved_at_10[0x10]; 4273 4274 u8 reserved_at_20[0x60]; 4275 }; 4276 4277 struct mlx5_ifc_vport_tc_element_bits { 4278 u8 traffic_class[0x4]; 4279 u8 reserved_at_4[0xc]; 4280 u8 vport_number[0x10]; 4281 }; 4282 4283 struct mlx5_ifc_vport_element_bits { 4284 u8 reserved_at_0[0x10]; 4285 u8 vport_number[0x10]; 4286 }; 4287 4288 enum { 4289 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4290 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4291 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4292 }; 4293 4294 struct mlx5_ifc_tsar_element_bits { 4295 u8 reserved_at_0[0x8]; 4296 u8 tsar_type[0x8]; 4297 u8 reserved_at_10[0x10]; 4298 }; 4299 4300 enum { 4301 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4302 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4303 }; 4304 4305 struct mlx5_ifc_teardown_hca_out_bits { 4306 u8 status[0x8]; 4307 u8 reserved_at_8[0x18]; 4308 4309 u8 syndrome[0x20]; 4310 4311 u8 reserved_at_40[0x3f]; 4312 4313 u8 state[0x1]; 4314 }; 4315 4316 enum { 4317 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4318 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4319 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4320 }; 4321 4322 struct mlx5_ifc_teardown_hca_in_bits { 4323 u8 opcode[0x10]; 4324 u8 reserved_at_10[0x10]; 4325 4326 u8 reserved_at_20[0x10]; 4327 u8 op_mod[0x10]; 4328 4329 u8 reserved_at_40[0x10]; 4330 u8 profile[0x10]; 4331 4332 u8 reserved_at_60[0x20]; 4333 }; 4334 4335 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4336 u8 status[0x8]; 4337 u8 reserved_at_8[0x18]; 4338 4339 u8 syndrome[0x20]; 4340 4341 u8 reserved_at_40[0x40]; 4342 }; 4343 4344 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4345 u8 opcode[0x10]; 4346 u8 uid[0x10]; 4347 4348 u8 reserved_at_20[0x10]; 4349 u8 op_mod[0x10]; 4350 4351 u8 reserved_at_40[0x8]; 4352 u8 qpn[0x18]; 4353 4354 u8 reserved_at_60[0x20]; 4355 4356 u8 opt_param_mask[0x20]; 4357 4358 u8 reserved_at_a0[0x20]; 4359 4360 struct mlx5_ifc_qpc_bits qpc; 4361 4362 u8 reserved_at_800[0x80]; 4363 }; 4364 4365 struct mlx5_ifc_sqd2rts_qp_out_bits { 4366 u8 status[0x8]; 4367 u8 reserved_at_8[0x18]; 4368 4369 u8 syndrome[0x20]; 4370 4371 u8 reserved_at_40[0x40]; 4372 }; 4373 4374 struct mlx5_ifc_sqd2rts_qp_in_bits { 4375 u8 opcode[0x10]; 4376 u8 uid[0x10]; 4377 4378 u8 reserved_at_20[0x10]; 4379 u8 op_mod[0x10]; 4380 4381 u8 reserved_at_40[0x8]; 4382 u8 qpn[0x18]; 4383 4384 u8 reserved_at_60[0x20]; 4385 4386 u8 opt_param_mask[0x20]; 4387 4388 u8 reserved_at_a0[0x20]; 4389 4390 struct mlx5_ifc_qpc_bits qpc; 4391 4392 u8 reserved_at_800[0x80]; 4393 }; 4394 4395 struct mlx5_ifc_set_roce_address_out_bits { 4396 u8 status[0x8]; 4397 u8 reserved_at_8[0x18]; 4398 4399 u8 syndrome[0x20]; 4400 4401 u8 reserved_at_40[0x40]; 4402 }; 4403 4404 struct mlx5_ifc_set_roce_address_in_bits { 4405 u8 opcode[0x10]; 4406 u8 reserved_at_10[0x10]; 4407 4408 u8 reserved_at_20[0x10]; 4409 u8 op_mod[0x10]; 4410 4411 u8 roce_address_index[0x10]; 4412 u8 reserved_at_50[0xc]; 4413 u8 vhca_port_num[0x4]; 4414 4415 u8 reserved_at_60[0x20]; 4416 4417 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4418 }; 4419 4420 struct mlx5_ifc_set_mad_demux_out_bits { 4421 u8 status[0x8]; 4422 u8 reserved_at_8[0x18]; 4423 4424 u8 syndrome[0x20]; 4425 4426 u8 reserved_at_40[0x40]; 4427 }; 4428 4429 enum { 4430 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4431 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4432 }; 4433 4434 struct mlx5_ifc_set_mad_demux_in_bits { 4435 u8 opcode[0x10]; 4436 u8 reserved_at_10[0x10]; 4437 4438 u8 reserved_at_20[0x10]; 4439 u8 op_mod[0x10]; 4440 4441 u8 reserved_at_40[0x20]; 4442 4443 u8 reserved_at_60[0x6]; 4444 u8 demux_mode[0x2]; 4445 u8 reserved_at_68[0x18]; 4446 }; 4447 4448 struct mlx5_ifc_set_l2_table_entry_out_bits { 4449 u8 status[0x8]; 4450 u8 reserved_at_8[0x18]; 4451 4452 u8 syndrome[0x20]; 4453 4454 u8 reserved_at_40[0x40]; 4455 }; 4456 4457 struct mlx5_ifc_set_l2_table_entry_in_bits { 4458 u8 opcode[0x10]; 4459 u8 reserved_at_10[0x10]; 4460 4461 u8 reserved_at_20[0x10]; 4462 u8 op_mod[0x10]; 4463 4464 u8 reserved_at_40[0x60]; 4465 4466 u8 reserved_at_a0[0x8]; 4467 u8 table_index[0x18]; 4468 4469 u8 reserved_at_c0[0x20]; 4470 4471 u8 reserved_at_e0[0x13]; 4472 u8 vlan_valid[0x1]; 4473 u8 vlan[0xc]; 4474 4475 struct mlx5_ifc_mac_address_layout_bits mac_address; 4476 4477 u8 reserved_at_140[0xc0]; 4478 }; 4479 4480 struct mlx5_ifc_set_issi_out_bits { 4481 u8 status[0x8]; 4482 u8 reserved_at_8[0x18]; 4483 4484 u8 syndrome[0x20]; 4485 4486 u8 reserved_at_40[0x40]; 4487 }; 4488 4489 struct mlx5_ifc_set_issi_in_bits { 4490 u8 opcode[0x10]; 4491 u8 reserved_at_10[0x10]; 4492 4493 u8 reserved_at_20[0x10]; 4494 u8 op_mod[0x10]; 4495 4496 u8 reserved_at_40[0x10]; 4497 u8 current_issi[0x10]; 4498 4499 u8 reserved_at_60[0x20]; 4500 }; 4501 4502 struct mlx5_ifc_set_hca_cap_out_bits { 4503 u8 status[0x8]; 4504 u8 reserved_at_8[0x18]; 4505 4506 u8 syndrome[0x20]; 4507 4508 u8 reserved_at_40[0x40]; 4509 }; 4510 4511 struct mlx5_ifc_set_hca_cap_in_bits { 4512 u8 opcode[0x10]; 4513 u8 reserved_at_10[0x10]; 4514 4515 u8 reserved_at_20[0x10]; 4516 u8 op_mod[0x10]; 4517 4518 u8 other_function[0x1]; 4519 u8 reserved_at_41[0xf]; 4520 u8 function_id[0x10]; 4521 4522 u8 reserved_at_60[0x20]; 4523 4524 union mlx5_ifc_hca_cap_union_bits capability; 4525 }; 4526 4527 enum { 4528 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4529 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4530 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4531 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4532 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4533 }; 4534 4535 struct mlx5_ifc_set_fte_out_bits { 4536 u8 status[0x8]; 4537 u8 reserved_at_8[0x18]; 4538 4539 u8 syndrome[0x20]; 4540 4541 u8 reserved_at_40[0x40]; 4542 }; 4543 4544 struct mlx5_ifc_set_fte_in_bits { 4545 u8 opcode[0x10]; 4546 u8 reserved_at_10[0x10]; 4547 4548 u8 reserved_at_20[0x10]; 4549 u8 op_mod[0x10]; 4550 4551 u8 other_vport[0x1]; 4552 u8 reserved_at_41[0xf]; 4553 u8 vport_number[0x10]; 4554 4555 u8 reserved_at_60[0x20]; 4556 4557 u8 table_type[0x8]; 4558 u8 reserved_at_88[0x18]; 4559 4560 u8 reserved_at_a0[0x8]; 4561 u8 table_id[0x18]; 4562 4563 u8 ignore_flow_level[0x1]; 4564 u8 reserved_at_c1[0x17]; 4565 u8 modify_enable_mask[0x8]; 4566 4567 u8 reserved_at_e0[0x20]; 4568 4569 u8 flow_index[0x20]; 4570 4571 u8 reserved_at_120[0xe0]; 4572 4573 struct mlx5_ifc_flow_context_bits flow_context; 4574 }; 4575 4576 struct mlx5_ifc_rts2rts_qp_out_bits { 4577 u8 status[0x8]; 4578 u8 reserved_at_8[0x18]; 4579 4580 u8 syndrome[0x20]; 4581 4582 u8 reserved_at_40[0x20]; 4583 u8 ece[0x20]; 4584 }; 4585 4586 struct mlx5_ifc_rts2rts_qp_in_bits { 4587 u8 opcode[0x10]; 4588 u8 uid[0x10]; 4589 4590 u8 reserved_at_20[0x10]; 4591 u8 op_mod[0x10]; 4592 4593 u8 reserved_at_40[0x8]; 4594 u8 qpn[0x18]; 4595 4596 u8 reserved_at_60[0x20]; 4597 4598 u8 opt_param_mask[0x20]; 4599 4600 u8 ece[0x20]; 4601 4602 struct mlx5_ifc_qpc_bits qpc; 4603 4604 u8 reserved_at_800[0x80]; 4605 }; 4606 4607 struct mlx5_ifc_rtr2rts_qp_out_bits { 4608 u8 status[0x8]; 4609 u8 reserved_at_8[0x18]; 4610 4611 u8 syndrome[0x20]; 4612 4613 u8 reserved_at_40[0x20]; 4614 u8 ece[0x20]; 4615 }; 4616 4617 struct mlx5_ifc_rtr2rts_qp_in_bits { 4618 u8 opcode[0x10]; 4619 u8 uid[0x10]; 4620 4621 u8 reserved_at_20[0x10]; 4622 u8 op_mod[0x10]; 4623 4624 u8 reserved_at_40[0x8]; 4625 u8 qpn[0x18]; 4626 4627 u8 reserved_at_60[0x20]; 4628 4629 u8 opt_param_mask[0x20]; 4630 4631 u8 ece[0x20]; 4632 4633 struct mlx5_ifc_qpc_bits qpc; 4634 4635 u8 reserved_at_800[0x80]; 4636 }; 4637 4638 struct mlx5_ifc_rst2init_qp_out_bits { 4639 u8 status[0x8]; 4640 u8 reserved_at_8[0x18]; 4641 4642 u8 syndrome[0x20]; 4643 4644 u8 reserved_at_40[0x20]; 4645 u8 ece[0x20]; 4646 }; 4647 4648 struct mlx5_ifc_rst2init_qp_in_bits { 4649 u8 opcode[0x10]; 4650 u8 uid[0x10]; 4651 4652 u8 reserved_at_20[0x10]; 4653 u8 op_mod[0x10]; 4654 4655 u8 reserved_at_40[0x8]; 4656 u8 qpn[0x18]; 4657 4658 u8 reserved_at_60[0x20]; 4659 4660 u8 opt_param_mask[0x20]; 4661 4662 u8 ece[0x20]; 4663 4664 struct mlx5_ifc_qpc_bits qpc; 4665 4666 u8 reserved_at_800[0x80]; 4667 }; 4668 4669 struct mlx5_ifc_query_xrq_out_bits { 4670 u8 status[0x8]; 4671 u8 reserved_at_8[0x18]; 4672 4673 u8 syndrome[0x20]; 4674 4675 u8 reserved_at_40[0x40]; 4676 4677 struct mlx5_ifc_xrqc_bits xrq_context; 4678 }; 4679 4680 struct mlx5_ifc_query_xrq_in_bits { 4681 u8 opcode[0x10]; 4682 u8 reserved_at_10[0x10]; 4683 4684 u8 reserved_at_20[0x10]; 4685 u8 op_mod[0x10]; 4686 4687 u8 reserved_at_40[0x8]; 4688 u8 xrqn[0x18]; 4689 4690 u8 reserved_at_60[0x20]; 4691 }; 4692 4693 struct mlx5_ifc_query_xrc_srq_out_bits { 4694 u8 status[0x8]; 4695 u8 reserved_at_8[0x18]; 4696 4697 u8 syndrome[0x20]; 4698 4699 u8 reserved_at_40[0x40]; 4700 4701 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4702 4703 u8 reserved_at_280[0x600]; 4704 4705 u8 pas[][0x40]; 4706 }; 4707 4708 struct mlx5_ifc_query_xrc_srq_in_bits { 4709 u8 opcode[0x10]; 4710 u8 reserved_at_10[0x10]; 4711 4712 u8 reserved_at_20[0x10]; 4713 u8 op_mod[0x10]; 4714 4715 u8 reserved_at_40[0x8]; 4716 u8 xrc_srqn[0x18]; 4717 4718 u8 reserved_at_60[0x20]; 4719 }; 4720 4721 enum { 4722 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4723 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4724 }; 4725 4726 struct mlx5_ifc_query_vport_state_out_bits { 4727 u8 status[0x8]; 4728 u8 reserved_at_8[0x18]; 4729 4730 u8 syndrome[0x20]; 4731 4732 u8 reserved_at_40[0x20]; 4733 4734 u8 reserved_at_60[0x18]; 4735 u8 admin_state[0x4]; 4736 u8 state[0x4]; 4737 }; 4738 4739 enum { 4740 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4741 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4742 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4743 }; 4744 4745 struct mlx5_ifc_arm_monitor_counter_in_bits { 4746 u8 opcode[0x10]; 4747 u8 uid[0x10]; 4748 4749 u8 reserved_at_20[0x10]; 4750 u8 op_mod[0x10]; 4751 4752 u8 reserved_at_40[0x20]; 4753 4754 u8 reserved_at_60[0x20]; 4755 }; 4756 4757 struct mlx5_ifc_arm_monitor_counter_out_bits { 4758 u8 status[0x8]; 4759 u8 reserved_at_8[0x18]; 4760 4761 u8 syndrome[0x20]; 4762 4763 u8 reserved_at_40[0x40]; 4764 }; 4765 4766 enum { 4767 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4768 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4769 }; 4770 4771 enum mlx5_monitor_counter_ppcnt { 4772 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4773 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4774 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4775 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4776 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4777 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4778 }; 4779 4780 enum { 4781 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4782 }; 4783 4784 struct mlx5_ifc_monitor_counter_output_bits { 4785 u8 reserved_at_0[0x4]; 4786 u8 type[0x4]; 4787 u8 reserved_at_8[0x8]; 4788 u8 counter[0x10]; 4789 4790 u8 counter_group_id[0x20]; 4791 }; 4792 4793 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4794 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4795 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4796 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4797 4798 struct mlx5_ifc_set_monitor_counter_in_bits { 4799 u8 opcode[0x10]; 4800 u8 uid[0x10]; 4801 4802 u8 reserved_at_20[0x10]; 4803 u8 op_mod[0x10]; 4804 4805 u8 reserved_at_40[0x10]; 4806 u8 num_of_counters[0x10]; 4807 4808 u8 reserved_at_60[0x20]; 4809 4810 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4811 }; 4812 4813 struct mlx5_ifc_set_monitor_counter_out_bits { 4814 u8 status[0x8]; 4815 u8 reserved_at_8[0x18]; 4816 4817 u8 syndrome[0x20]; 4818 4819 u8 reserved_at_40[0x40]; 4820 }; 4821 4822 struct mlx5_ifc_query_vport_state_in_bits { 4823 u8 opcode[0x10]; 4824 u8 reserved_at_10[0x10]; 4825 4826 u8 reserved_at_20[0x10]; 4827 u8 op_mod[0x10]; 4828 4829 u8 other_vport[0x1]; 4830 u8 reserved_at_41[0xf]; 4831 u8 vport_number[0x10]; 4832 4833 u8 reserved_at_60[0x20]; 4834 }; 4835 4836 struct mlx5_ifc_query_vnic_env_out_bits { 4837 u8 status[0x8]; 4838 u8 reserved_at_8[0x18]; 4839 4840 u8 syndrome[0x20]; 4841 4842 u8 reserved_at_40[0x40]; 4843 4844 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4845 }; 4846 4847 enum { 4848 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4849 }; 4850 4851 struct mlx5_ifc_query_vnic_env_in_bits { 4852 u8 opcode[0x10]; 4853 u8 reserved_at_10[0x10]; 4854 4855 u8 reserved_at_20[0x10]; 4856 u8 op_mod[0x10]; 4857 4858 u8 other_vport[0x1]; 4859 u8 reserved_at_41[0xf]; 4860 u8 vport_number[0x10]; 4861 4862 u8 reserved_at_60[0x20]; 4863 }; 4864 4865 struct mlx5_ifc_query_vport_counter_out_bits { 4866 u8 status[0x8]; 4867 u8 reserved_at_8[0x18]; 4868 4869 u8 syndrome[0x20]; 4870 4871 u8 reserved_at_40[0x40]; 4872 4873 struct mlx5_ifc_traffic_counter_bits received_errors; 4874 4875 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4876 4877 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4878 4879 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4880 4881 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4882 4883 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4884 4885 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4886 4887 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4888 4889 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4890 4891 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4892 4893 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4894 4895 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4896 4897 u8 reserved_at_680[0xa00]; 4898 }; 4899 4900 enum { 4901 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4902 }; 4903 4904 struct mlx5_ifc_query_vport_counter_in_bits { 4905 u8 opcode[0x10]; 4906 u8 reserved_at_10[0x10]; 4907 4908 u8 reserved_at_20[0x10]; 4909 u8 op_mod[0x10]; 4910 4911 u8 other_vport[0x1]; 4912 u8 reserved_at_41[0xb]; 4913 u8 port_num[0x4]; 4914 u8 vport_number[0x10]; 4915 4916 u8 reserved_at_60[0x60]; 4917 4918 u8 clear[0x1]; 4919 u8 reserved_at_c1[0x1f]; 4920 4921 u8 reserved_at_e0[0x20]; 4922 }; 4923 4924 struct mlx5_ifc_query_tis_out_bits { 4925 u8 status[0x8]; 4926 u8 reserved_at_8[0x18]; 4927 4928 u8 syndrome[0x20]; 4929 4930 u8 reserved_at_40[0x40]; 4931 4932 struct mlx5_ifc_tisc_bits tis_context; 4933 }; 4934 4935 struct mlx5_ifc_query_tis_in_bits { 4936 u8 opcode[0x10]; 4937 u8 reserved_at_10[0x10]; 4938 4939 u8 reserved_at_20[0x10]; 4940 u8 op_mod[0x10]; 4941 4942 u8 reserved_at_40[0x8]; 4943 u8 tisn[0x18]; 4944 4945 u8 reserved_at_60[0x20]; 4946 }; 4947 4948 struct mlx5_ifc_query_tir_out_bits { 4949 u8 status[0x8]; 4950 u8 reserved_at_8[0x18]; 4951 4952 u8 syndrome[0x20]; 4953 4954 u8 reserved_at_40[0xc0]; 4955 4956 struct mlx5_ifc_tirc_bits tir_context; 4957 }; 4958 4959 struct mlx5_ifc_query_tir_in_bits { 4960 u8 opcode[0x10]; 4961 u8 reserved_at_10[0x10]; 4962 4963 u8 reserved_at_20[0x10]; 4964 u8 op_mod[0x10]; 4965 4966 u8 reserved_at_40[0x8]; 4967 u8 tirn[0x18]; 4968 4969 u8 reserved_at_60[0x20]; 4970 }; 4971 4972 struct mlx5_ifc_query_srq_out_bits { 4973 u8 status[0x8]; 4974 u8 reserved_at_8[0x18]; 4975 4976 u8 syndrome[0x20]; 4977 4978 u8 reserved_at_40[0x40]; 4979 4980 struct mlx5_ifc_srqc_bits srq_context_entry; 4981 4982 u8 reserved_at_280[0x600]; 4983 4984 u8 pas[][0x40]; 4985 }; 4986 4987 struct mlx5_ifc_query_srq_in_bits { 4988 u8 opcode[0x10]; 4989 u8 reserved_at_10[0x10]; 4990 4991 u8 reserved_at_20[0x10]; 4992 u8 op_mod[0x10]; 4993 4994 u8 reserved_at_40[0x8]; 4995 u8 srqn[0x18]; 4996 4997 u8 reserved_at_60[0x20]; 4998 }; 4999 5000 struct mlx5_ifc_query_sq_out_bits { 5001 u8 status[0x8]; 5002 u8 reserved_at_8[0x18]; 5003 5004 u8 syndrome[0x20]; 5005 5006 u8 reserved_at_40[0xc0]; 5007 5008 struct mlx5_ifc_sqc_bits sq_context; 5009 }; 5010 5011 struct mlx5_ifc_query_sq_in_bits { 5012 u8 opcode[0x10]; 5013 u8 reserved_at_10[0x10]; 5014 5015 u8 reserved_at_20[0x10]; 5016 u8 op_mod[0x10]; 5017 5018 u8 reserved_at_40[0x8]; 5019 u8 sqn[0x18]; 5020 5021 u8 reserved_at_60[0x20]; 5022 }; 5023 5024 struct mlx5_ifc_query_special_contexts_out_bits { 5025 u8 status[0x8]; 5026 u8 reserved_at_8[0x18]; 5027 5028 u8 syndrome[0x20]; 5029 5030 u8 dump_fill_mkey[0x20]; 5031 5032 u8 resd_lkey[0x20]; 5033 5034 u8 null_mkey[0x20]; 5035 5036 u8 reserved_at_a0[0x60]; 5037 }; 5038 5039 struct mlx5_ifc_query_special_contexts_in_bits { 5040 u8 opcode[0x10]; 5041 u8 reserved_at_10[0x10]; 5042 5043 u8 reserved_at_20[0x10]; 5044 u8 op_mod[0x10]; 5045 5046 u8 reserved_at_40[0x40]; 5047 }; 5048 5049 struct mlx5_ifc_query_scheduling_element_out_bits { 5050 u8 opcode[0x10]; 5051 u8 reserved_at_10[0x10]; 5052 5053 u8 reserved_at_20[0x10]; 5054 u8 op_mod[0x10]; 5055 5056 u8 reserved_at_40[0xc0]; 5057 5058 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5059 5060 u8 reserved_at_300[0x100]; 5061 }; 5062 5063 enum { 5064 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5065 SCHEDULING_HIERARCHY_NIC = 0x3, 5066 }; 5067 5068 struct mlx5_ifc_query_scheduling_element_in_bits { 5069 u8 opcode[0x10]; 5070 u8 reserved_at_10[0x10]; 5071 5072 u8 reserved_at_20[0x10]; 5073 u8 op_mod[0x10]; 5074 5075 u8 scheduling_hierarchy[0x8]; 5076 u8 reserved_at_48[0x18]; 5077 5078 u8 scheduling_element_id[0x20]; 5079 5080 u8 reserved_at_80[0x180]; 5081 }; 5082 5083 struct mlx5_ifc_query_rqt_out_bits { 5084 u8 status[0x8]; 5085 u8 reserved_at_8[0x18]; 5086 5087 u8 syndrome[0x20]; 5088 5089 u8 reserved_at_40[0xc0]; 5090 5091 struct mlx5_ifc_rqtc_bits rqt_context; 5092 }; 5093 5094 struct mlx5_ifc_query_rqt_in_bits { 5095 u8 opcode[0x10]; 5096 u8 reserved_at_10[0x10]; 5097 5098 u8 reserved_at_20[0x10]; 5099 u8 op_mod[0x10]; 5100 5101 u8 reserved_at_40[0x8]; 5102 u8 rqtn[0x18]; 5103 5104 u8 reserved_at_60[0x20]; 5105 }; 5106 5107 struct mlx5_ifc_query_rq_out_bits { 5108 u8 status[0x8]; 5109 u8 reserved_at_8[0x18]; 5110 5111 u8 syndrome[0x20]; 5112 5113 u8 reserved_at_40[0xc0]; 5114 5115 struct mlx5_ifc_rqc_bits rq_context; 5116 }; 5117 5118 struct mlx5_ifc_query_rq_in_bits { 5119 u8 opcode[0x10]; 5120 u8 reserved_at_10[0x10]; 5121 5122 u8 reserved_at_20[0x10]; 5123 u8 op_mod[0x10]; 5124 5125 u8 reserved_at_40[0x8]; 5126 u8 rqn[0x18]; 5127 5128 u8 reserved_at_60[0x20]; 5129 }; 5130 5131 struct mlx5_ifc_query_roce_address_out_bits { 5132 u8 status[0x8]; 5133 u8 reserved_at_8[0x18]; 5134 5135 u8 syndrome[0x20]; 5136 5137 u8 reserved_at_40[0x40]; 5138 5139 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5140 }; 5141 5142 struct mlx5_ifc_query_roce_address_in_bits { 5143 u8 opcode[0x10]; 5144 u8 reserved_at_10[0x10]; 5145 5146 u8 reserved_at_20[0x10]; 5147 u8 op_mod[0x10]; 5148 5149 u8 roce_address_index[0x10]; 5150 u8 reserved_at_50[0xc]; 5151 u8 vhca_port_num[0x4]; 5152 5153 u8 reserved_at_60[0x20]; 5154 }; 5155 5156 struct mlx5_ifc_query_rmp_out_bits { 5157 u8 status[0x8]; 5158 u8 reserved_at_8[0x18]; 5159 5160 u8 syndrome[0x20]; 5161 5162 u8 reserved_at_40[0xc0]; 5163 5164 struct mlx5_ifc_rmpc_bits rmp_context; 5165 }; 5166 5167 struct mlx5_ifc_query_rmp_in_bits { 5168 u8 opcode[0x10]; 5169 u8 reserved_at_10[0x10]; 5170 5171 u8 reserved_at_20[0x10]; 5172 u8 op_mod[0x10]; 5173 5174 u8 reserved_at_40[0x8]; 5175 u8 rmpn[0x18]; 5176 5177 u8 reserved_at_60[0x20]; 5178 }; 5179 5180 struct mlx5_ifc_query_qp_out_bits { 5181 u8 status[0x8]; 5182 u8 reserved_at_8[0x18]; 5183 5184 u8 syndrome[0x20]; 5185 5186 u8 reserved_at_40[0x20]; 5187 u8 ece[0x20]; 5188 5189 u8 opt_param_mask[0x20]; 5190 5191 u8 reserved_at_a0[0x20]; 5192 5193 struct mlx5_ifc_qpc_bits qpc; 5194 5195 u8 reserved_at_800[0x80]; 5196 5197 u8 pas[][0x40]; 5198 }; 5199 5200 struct mlx5_ifc_query_qp_in_bits { 5201 u8 opcode[0x10]; 5202 u8 reserved_at_10[0x10]; 5203 5204 u8 reserved_at_20[0x10]; 5205 u8 op_mod[0x10]; 5206 5207 u8 reserved_at_40[0x8]; 5208 u8 qpn[0x18]; 5209 5210 u8 reserved_at_60[0x20]; 5211 }; 5212 5213 struct mlx5_ifc_query_q_counter_out_bits { 5214 u8 status[0x8]; 5215 u8 reserved_at_8[0x18]; 5216 5217 u8 syndrome[0x20]; 5218 5219 u8 reserved_at_40[0x40]; 5220 5221 u8 rx_write_requests[0x20]; 5222 5223 u8 reserved_at_a0[0x20]; 5224 5225 u8 rx_read_requests[0x20]; 5226 5227 u8 reserved_at_e0[0x20]; 5228 5229 u8 rx_atomic_requests[0x20]; 5230 5231 u8 reserved_at_120[0x20]; 5232 5233 u8 rx_dct_connect[0x20]; 5234 5235 u8 reserved_at_160[0x20]; 5236 5237 u8 out_of_buffer[0x20]; 5238 5239 u8 reserved_at_1a0[0x20]; 5240 5241 u8 out_of_sequence[0x20]; 5242 5243 u8 reserved_at_1e0[0x20]; 5244 5245 u8 duplicate_request[0x20]; 5246 5247 u8 reserved_at_220[0x20]; 5248 5249 u8 rnr_nak_retry_err[0x20]; 5250 5251 u8 reserved_at_260[0x20]; 5252 5253 u8 packet_seq_err[0x20]; 5254 5255 u8 reserved_at_2a0[0x20]; 5256 5257 u8 implied_nak_seq_err[0x20]; 5258 5259 u8 reserved_at_2e0[0x20]; 5260 5261 u8 local_ack_timeout_err[0x20]; 5262 5263 u8 reserved_at_320[0xa0]; 5264 5265 u8 resp_local_length_error[0x20]; 5266 5267 u8 req_local_length_error[0x20]; 5268 5269 u8 resp_local_qp_error[0x20]; 5270 5271 u8 local_operation_error[0x20]; 5272 5273 u8 resp_local_protection[0x20]; 5274 5275 u8 req_local_protection[0x20]; 5276 5277 u8 resp_cqe_error[0x20]; 5278 5279 u8 req_cqe_error[0x20]; 5280 5281 u8 req_mw_binding[0x20]; 5282 5283 u8 req_bad_response[0x20]; 5284 5285 u8 req_remote_invalid_request[0x20]; 5286 5287 u8 resp_remote_invalid_request[0x20]; 5288 5289 u8 req_remote_access_errors[0x20]; 5290 5291 u8 resp_remote_access_errors[0x20]; 5292 5293 u8 req_remote_operation_errors[0x20]; 5294 5295 u8 req_transport_retries_exceeded[0x20]; 5296 5297 u8 cq_overflow[0x20]; 5298 5299 u8 resp_cqe_flush_error[0x20]; 5300 5301 u8 req_cqe_flush_error[0x20]; 5302 5303 u8 reserved_at_620[0x20]; 5304 5305 u8 roce_adp_retrans[0x20]; 5306 5307 u8 roce_adp_retrans_to[0x20]; 5308 5309 u8 roce_slow_restart[0x20]; 5310 5311 u8 roce_slow_restart_cnps[0x20]; 5312 5313 u8 roce_slow_restart_trans[0x20]; 5314 5315 u8 reserved_at_6e0[0x120]; 5316 }; 5317 5318 struct mlx5_ifc_query_q_counter_in_bits { 5319 u8 opcode[0x10]; 5320 u8 reserved_at_10[0x10]; 5321 5322 u8 reserved_at_20[0x10]; 5323 u8 op_mod[0x10]; 5324 5325 u8 reserved_at_40[0x80]; 5326 5327 u8 clear[0x1]; 5328 u8 reserved_at_c1[0x1f]; 5329 5330 u8 reserved_at_e0[0x18]; 5331 u8 counter_set_id[0x8]; 5332 }; 5333 5334 struct mlx5_ifc_query_pages_out_bits { 5335 u8 status[0x8]; 5336 u8 reserved_at_8[0x18]; 5337 5338 u8 syndrome[0x20]; 5339 5340 u8 embedded_cpu_function[0x1]; 5341 u8 reserved_at_41[0xf]; 5342 u8 function_id[0x10]; 5343 5344 u8 num_pages[0x20]; 5345 }; 5346 5347 enum { 5348 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5349 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5350 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5351 }; 5352 5353 struct mlx5_ifc_query_pages_in_bits { 5354 u8 opcode[0x10]; 5355 u8 reserved_at_10[0x10]; 5356 5357 u8 reserved_at_20[0x10]; 5358 u8 op_mod[0x10]; 5359 5360 u8 embedded_cpu_function[0x1]; 5361 u8 reserved_at_41[0xf]; 5362 u8 function_id[0x10]; 5363 5364 u8 reserved_at_60[0x20]; 5365 }; 5366 5367 struct mlx5_ifc_query_nic_vport_context_out_bits { 5368 u8 status[0x8]; 5369 u8 reserved_at_8[0x18]; 5370 5371 u8 syndrome[0x20]; 5372 5373 u8 reserved_at_40[0x40]; 5374 5375 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5376 }; 5377 5378 struct mlx5_ifc_query_nic_vport_context_in_bits { 5379 u8 opcode[0x10]; 5380 u8 reserved_at_10[0x10]; 5381 5382 u8 reserved_at_20[0x10]; 5383 u8 op_mod[0x10]; 5384 5385 u8 other_vport[0x1]; 5386 u8 reserved_at_41[0xf]; 5387 u8 vport_number[0x10]; 5388 5389 u8 reserved_at_60[0x5]; 5390 u8 allowed_list_type[0x3]; 5391 u8 reserved_at_68[0x18]; 5392 }; 5393 5394 struct mlx5_ifc_query_mkey_out_bits { 5395 u8 status[0x8]; 5396 u8 reserved_at_8[0x18]; 5397 5398 u8 syndrome[0x20]; 5399 5400 u8 reserved_at_40[0x40]; 5401 5402 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5403 5404 u8 reserved_at_280[0x600]; 5405 5406 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5407 5408 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5409 }; 5410 5411 struct mlx5_ifc_query_mkey_in_bits { 5412 u8 opcode[0x10]; 5413 u8 reserved_at_10[0x10]; 5414 5415 u8 reserved_at_20[0x10]; 5416 u8 op_mod[0x10]; 5417 5418 u8 reserved_at_40[0x8]; 5419 u8 mkey_index[0x18]; 5420 5421 u8 pg_access[0x1]; 5422 u8 reserved_at_61[0x1f]; 5423 }; 5424 5425 struct mlx5_ifc_query_mad_demux_out_bits { 5426 u8 status[0x8]; 5427 u8 reserved_at_8[0x18]; 5428 5429 u8 syndrome[0x20]; 5430 5431 u8 reserved_at_40[0x40]; 5432 5433 u8 mad_dumux_parameters_block[0x20]; 5434 }; 5435 5436 struct mlx5_ifc_query_mad_demux_in_bits { 5437 u8 opcode[0x10]; 5438 u8 reserved_at_10[0x10]; 5439 5440 u8 reserved_at_20[0x10]; 5441 u8 op_mod[0x10]; 5442 5443 u8 reserved_at_40[0x40]; 5444 }; 5445 5446 struct mlx5_ifc_query_l2_table_entry_out_bits { 5447 u8 status[0x8]; 5448 u8 reserved_at_8[0x18]; 5449 5450 u8 syndrome[0x20]; 5451 5452 u8 reserved_at_40[0xa0]; 5453 5454 u8 reserved_at_e0[0x13]; 5455 u8 vlan_valid[0x1]; 5456 u8 vlan[0xc]; 5457 5458 struct mlx5_ifc_mac_address_layout_bits mac_address; 5459 5460 u8 reserved_at_140[0xc0]; 5461 }; 5462 5463 struct mlx5_ifc_query_l2_table_entry_in_bits { 5464 u8 opcode[0x10]; 5465 u8 reserved_at_10[0x10]; 5466 5467 u8 reserved_at_20[0x10]; 5468 u8 op_mod[0x10]; 5469 5470 u8 reserved_at_40[0x60]; 5471 5472 u8 reserved_at_a0[0x8]; 5473 u8 table_index[0x18]; 5474 5475 u8 reserved_at_c0[0x140]; 5476 }; 5477 5478 struct mlx5_ifc_query_issi_out_bits { 5479 u8 status[0x8]; 5480 u8 reserved_at_8[0x18]; 5481 5482 u8 syndrome[0x20]; 5483 5484 u8 reserved_at_40[0x10]; 5485 u8 current_issi[0x10]; 5486 5487 u8 reserved_at_60[0xa0]; 5488 5489 u8 reserved_at_100[76][0x8]; 5490 u8 supported_issi_dw0[0x20]; 5491 }; 5492 5493 struct mlx5_ifc_query_issi_in_bits { 5494 u8 opcode[0x10]; 5495 u8 reserved_at_10[0x10]; 5496 5497 u8 reserved_at_20[0x10]; 5498 u8 op_mod[0x10]; 5499 5500 u8 reserved_at_40[0x40]; 5501 }; 5502 5503 struct mlx5_ifc_set_driver_version_out_bits { 5504 u8 status[0x8]; 5505 u8 reserved_0[0x18]; 5506 5507 u8 syndrome[0x20]; 5508 u8 reserved_1[0x40]; 5509 }; 5510 5511 struct mlx5_ifc_set_driver_version_in_bits { 5512 u8 opcode[0x10]; 5513 u8 reserved_0[0x10]; 5514 5515 u8 reserved_1[0x10]; 5516 u8 op_mod[0x10]; 5517 5518 u8 reserved_2[0x40]; 5519 u8 driver_version[64][0x8]; 5520 }; 5521 5522 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5523 u8 status[0x8]; 5524 u8 reserved_at_8[0x18]; 5525 5526 u8 syndrome[0x20]; 5527 5528 u8 reserved_at_40[0x40]; 5529 5530 struct mlx5_ifc_pkey_bits pkey[]; 5531 }; 5532 5533 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5534 u8 opcode[0x10]; 5535 u8 reserved_at_10[0x10]; 5536 5537 u8 reserved_at_20[0x10]; 5538 u8 op_mod[0x10]; 5539 5540 u8 other_vport[0x1]; 5541 u8 reserved_at_41[0xb]; 5542 u8 port_num[0x4]; 5543 u8 vport_number[0x10]; 5544 5545 u8 reserved_at_60[0x10]; 5546 u8 pkey_index[0x10]; 5547 }; 5548 5549 enum { 5550 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5551 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5552 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5553 }; 5554 5555 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5556 u8 status[0x8]; 5557 u8 reserved_at_8[0x18]; 5558 5559 u8 syndrome[0x20]; 5560 5561 u8 reserved_at_40[0x20]; 5562 5563 u8 gids_num[0x10]; 5564 u8 reserved_at_70[0x10]; 5565 5566 struct mlx5_ifc_array128_auto_bits gid[]; 5567 }; 5568 5569 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5570 u8 opcode[0x10]; 5571 u8 reserved_at_10[0x10]; 5572 5573 u8 reserved_at_20[0x10]; 5574 u8 op_mod[0x10]; 5575 5576 u8 other_vport[0x1]; 5577 u8 reserved_at_41[0xb]; 5578 u8 port_num[0x4]; 5579 u8 vport_number[0x10]; 5580 5581 u8 reserved_at_60[0x10]; 5582 u8 gid_index[0x10]; 5583 }; 5584 5585 struct mlx5_ifc_query_hca_vport_context_out_bits { 5586 u8 status[0x8]; 5587 u8 reserved_at_8[0x18]; 5588 5589 u8 syndrome[0x20]; 5590 5591 u8 reserved_at_40[0x40]; 5592 5593 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5594 }; 5595 5596 struct mlx5_ifc_query_hca_vport_context_in_bits { 5597 u8 opcode[0x10]; 5598 u8 reserved_at_10[0x10]; 5599 5600 u8 reserved_at_20[0x10]; 5601 u8 op_mod[0x10]; 5602 5603 u8 other_vport[0x1]; 5604 u8 reserved_at_41[0xb]; 5605 u8 port_num[0x4]; 5606 u8 vport_number[0x10]; 5607 5608 u8 reserved_at_60[0x20]; 5609 }; 5610 5611 struct mlx5_ifc_query_hca_cap_out_bits { 5612 u8 status[0x8]; 5613 u8 reserved_at_8[0x18]; 5614 5615 u8 syndrome[0x20]; 5616 5617 u8 reserved_at_40[0x40]; 5618 5619 union mlx5_ifc_hca_cap_union_bits capability; 5620 }; 5621 5622 struct mlx5_ifc_query_hca_cap_in_bits { 5623 u8 opcode[0x10]; 5624 u8 reserved_at_10[0x10]; 5625 5626 u8 reserved_at_20[0x10]; 5627 u8 op_mod[0x10]; 5628 5629 u8 other_function[0x1]; 5630 u8 reserved_at_41[0xf]; 5631 u8 function_id[0x10]; 5632 5633 u8 reserved_at_60[0x20]; 5634 }; 5635 5636 struct mlx5_ifc_other_hca_cap_bits { 5637 u8 roce[0x1]; 5638 u8 reserved_at_1[0x27f]; 5639 }; 5640 5641 struct mlx5_ifc_query_other_hca_cap_out_bits { 5642 u8 status[0x8]; 5643 u8 reserved_at_8[0x18]; 5644 5645 u8 syndrome[0x20]; 5646 5647 u8 reserved_at_40[0x40]; 5648 5649 struct mlx5_ifc_other_hca_cap_bits other_capability; 5650 }; 5651 5652 struct mlx5_ifc_query_other_hca_cap_in_bits { 5653 u8 opcode[0x10]; 5654 u8 reserved_at_10[0x10]; 5655 5656 u8 reserved_at_20[0x10]; 5657 u8 op_mod[0x10]; 5658 5659 u8 reserved_at_40[0x10]; 5660 u8 function_id[0x10]; 5661 5662 u8 reserved_at_60[0x20]; 5663 }; 5664 5665 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5666 u8 status[0x8]; 5667 u8 reserved_at_8[0x18]; 5668 5669 u8 syndrome[0x20]; 5670 5671 u8 reserved_at_40[0x40]; 5672 }; 5673 5674 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5675 u8 opcode[0x10]; 5676 u8 reserved_at_10[0x10]; 5677 5678 u8 reserved_at_20[0x10]; 5679 u8 op_mod[0x10]; 5680 5681 u8 reserved_at_40[0x10]; 5682 u8 function_id[0x10]; 5683 u8 field_select[0x20]; 5684 5685 struct mlx5_ifc_other_hca_cap_bits other_capability; 5686 }; 5687 5688 struct mlx5_ifc_flow_table_context_bits { 5689 u8 reformat_en[0x1]; 5690 u8 decap_en[0x1]; 5691 u8 sw_owner[0x1]; 5692 u8 termination_table[0x1]; 5693 u8 table_miss_action[0x4]; 5694 u8 level[0x8]; 5695 u8 reserved_at_10[0x8]; 5696 u8 log_size[0x8]; 5697 5698 u8 reserved_at_20[0x8]; 5699 u8 table_miss_id[0x18]; 5700 5701 u8 reserved_at_40[0x8]; 5702 u8 lag_master_next_table_id[0x18]; 5703 5704 u8 reserved_at_60[0x60]; 5705 5706 u8 sw_owner_icm_root_1[0x40]; 5707 5708 u8 sw_owner_icm_root_0[0x40]; 5709 5710 }; 5711 5712 struct mlx5_ifc_query_flow_table_out_bits { 5713 u8 status[0x8]; 5714 u8 reserved_at_8[0x18]; 5715 5716 u8 syndrome[0x20]; 5717 5718 u8 reserved_at_40[0x80]; 5719 5720 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5721 }; 5722 5723 struct mlx5_ifc_query_flow_table_in_bits { 5724 u8 opcode[0x10]; 5725 u8 reserved_at_10[0x10]; 5726 5727 u8 reserved_at_20[0x10]; 5728 u8 op_mod[0x10]; 5729 5730 u8 reserved_at_40[0x40]; 5731 5732 u8 table_type[0x8]; 5733 u8 reserved_at_88[0x18]; 5734 5735 u8 reserved_at_a0[0x8]; 5736 u8 table_id[0x18]; 5737 5738 u8 reserved_at_c0[0x140]; 5739 }; 5740 5741 struct mlx5_ifc_query_fte_out_bits { 5742 u8 status[0x8]; 5743 u8 reserved_at_8[0x18]; 5744 5745 u8 syndrome[0x20]; 5746 5747 u8 reserved_at_40[0x1c0]; 5748 5749 struct mlx5_ifc_flow_context_bits flow_context; 5750 }; 5751 5752 struct mlx5_ifc_query_fte_in_bits { 5753 u8 opcode[0x10]; 5754 u8 reserved_at_10[0x10]; 5755 5756 u8 reserved_at_20[0x10]; 5757 u8 op_mod[0x10]; 5758 5759 u8 reserved_at_40[0x40]; 5760 5761 u8 table_type[0x8]; 5762 u8 reserved_at_88[0x18]; 5763 5764 u8 reserved_at_a0[0x8]; 5765 u8 table_id[0x18]; 5766 5767 u8 reserved_at_c0[0x40]; 5768 5769 u8 flow_index[0x20]; 5770 5771 u8 reserved_at_120[0xe0]; 5772 }; 5773 5774 struct mlx5_ifc_match_definer_format_0_bits { 5775 u8 reserved_at_0[0x100]; 5776 5777 u8 metadata_reg_c_0[0x20]; 5778 5779 u8 metadata_reg_c_1[0x20]; 5780 5781 u8 outer_dmac_47_16[0x20]; 5782 5783 u8 outer_dmac_15_0[0x10]; 5784 u8 outer_ethertype[0x10]; 5785 5786 u8 reserved_at_180[0x1]; 5787 u8 sx_sniffer[0x1]; 5788 u8 functional_lb[0x1]; 5789 u8 outer_ip_frag[0x1]; 5790 u8 outer_qp_type[0x2]; 5791 u8 outer_encap_type[0x2]; 5792 u8 port_number[0x2]; 5793 u8 outer_l3_type[0x2]; 5794 u8 outer_l4_type[0x2]; 5795 u8 outer_first_vlan_type[0x2]; 5796 u8 outer_first_vlan_prio[0x3]; 5797 u8 outer_first_vlan_cfi[0x1]; 5798 u8 outer_first_vlan_vid[0xc]; 5799 5800 u8 outer_l4_type_ext[0x4]; 5801 u8 reserved_at_1a4[0x2]; 5802 u8 outer_ipsec_layer[0x2]; 5803 u8 outer_l2_type[0x2]; 5804 u8 force_lb[0x1]; 5805 u8 outer_l2_ok[0x1]; 5806 u8 outer_l3_ok[0x1]; 5807 u8 outer_l4_ok[0x1]; 5808 u8 outer_second_vlan_type[0x2]; 5809 u8 outer_second_vlan_prio[0x3]; 5810 u8 outer_second_vlan_cfi[0x1]; 5811 u8 outer_second_vlan_vid[0xc]; 5812 5813 u8 outer_smac_47_16[0x20]; 5814 5815 u8 outer_smac_15_0[0x10]; 5816 u8 inner_ipv4_checksum_ok[0x1]; 5817 u8 inner_l4_checksum_ok[0x1]; 5818 u8 outer_ipv4_checksum_ok[0x1]; 5819 u8 outer_l4_checksum_ok[0x1]; 5820 u8 inner_l3_ok[0x1]; 5821 u8 inner_l4_ok[0x1]; 5822 u8 outer_l3_ok_duplicate[0x1]; 5823 u8 outer_l4_ok_duplicate[0x1]; 5824 u8 outer_tcp_cwr[0x1]; 5825 u8 outer_tcp_ece[0x1]; 5826 u8 outer_tcp_urg[0x1]; 5827 u8 outer_tcp_ack[0x1]; 5828 u8 outer_tcp_psh[0x1]; 5829 u8 outer_tcp_rst[0x1]; 5830 u8 outer_tcp_syn[0x1]; 5831 u8 outer_tcp_fin[0x1]; 5832 }; 5833 5834 struct mlx5_ifc_match_definer_format_22_bits { 5835 u8 reserved_at_0[0x100]; 5836 5837 u8 outer_ip_src_addr[0x20]; 5838 5839 u8 outer_ip_dest_addr[0x20]; 5840 5841 u8 outer_l4_sport[0x10]; 5842 u8 outer_l4_dport[0x10]; 5843 5844 u8 reserved_at_160[0x1]; 5845 u8 sx_sniffer[0x1]; 5846 u8 functional_lb[0x1]; 5847 u8 outer_ip_frag[0x1]; 5848 u8 outer_qp_type[0x2]; 5849 u8 outer_encap_type[0x2]; 5850 u8 port_number[0x2]; 5851 u8 outer_l3_type[0x2]; 5852 u8 outer_l4_type[0x2]; 5853 u8 outer_first_vlan_type[0x2]; 5854 u8 outer_first_vlan_prio[0x3]; 5855 u8 outer_first_vlan_cfi[0x1]; 5856 u8 outer_first_vlan_vid[0xc]; 5857 5858 u8 metadata_reg_c_0[0x20]; 5859 5860 u8 outer_dmac_47_16[0x20]; 5861 5862 u8 outer_smac_47_16[0x20]; 5863 5864 u8 outer_smac_15_0[0x10]; 5865 u8 outer_dmac_15_0[0x10]; 5866 }; 5867 5868 struct mlx5_ifc_match_definer_format_23_bits { 5869 u8 reserved_at_0[0x100]; 5870 5871 u8 inner_ip_src_addr[0x20]; 5872 5873 u8 inner_ip_dest_addr[0x20]; 5874 5875 u8 inner_l4_sport[0x10]; 5876 u8 inner_l4_dport[0x10]; 5877 5878 u8 reserved_at_160[0x1]; 5879 u8 sx_sniffer[0x1]; 5880 u8 functional_lb[0x1]; 5881 u8 inner_ip_frag[0x1]; 5882 u8 inner_qp_type[0x2]; 5883 u8 inner_encap_type[0x2]; 5884 u8 port_number[0x2]; 5885 u8 inner_l3_type[0x2]; 5886 u8 inner_l4_type[0x2]; 5887 u8 inner_first_vlan_type[0x2]; 5888 u8 inner_first_vlan_prio[0x3]; 5889 u8 inner_first_vlan_cfi[0x1]; 5890 u8 inner_first_vlan_vid[0xc]; 5891 5892 u8 tunnel_header_0[0x20]; 5893 5894 u8 inner_dmac_47_16[0x20]; 5895 5896 u8 inner_smac_47_16[0x20]; 5897 5898 u8 inner_smac_15_0[0x10]; 5899 u8 inner_dmac_15_0[0x10]; 5900 }; 5901 5902 struct mlx5_ifc_match_definer_format_29_bits { 5903 u8 reserved_at_0[0xc0]; 5904 5905 u8 outer_ip_dest_addr[0x80]; 5906 5907 u8 outer_ip_src_addr[0x80]; 5908 5909 u8 outer_l4_sport[0x10]; 5910 u8 outer_l4_dport[0x10]; 5911 5912 u8 reserved_at_1e0[0x20]; 5913 }; 5914 5915 struct mlx5_ifc_match_definer_format_30_bits { 5916 u8 reserved_at_0[0xa0]; 5917 5918 u8 outer_ip_dest_addr[0x80]; 5919 5920 u8 outer_ip_src_addr[0x80]; 5921 5922 u8 outer_dmac_47_16[0x20]; 5923 5924 u8 outer_smac_47_16[0x20]; 5925 5926 u8 outer_smac_15_0[0x10]; 5927 u8 outer_dmac_15_0[0x10]; 5928 }; 5929 5930 struct mlx5_ifc_match_definer_format_31_bits { 5931 u8 reserved_at_0[0xc0]; 5932 5933 u8 inner_ip_dest_addr[0x80]; 5934 5935 u8 inner_ip_src_addr[0x80]; 5936 5937 u8 inner_l4_sport[0x10]; 5938 u8 inner_l4_dport[0x10]; 5939 5940 u8 reserved_at_1e0[0x20]; 5941 }; 5942 5943 struct mlx5_ifc_match_definer_format_32_bits { 5944 u8 reserved_at_0[0xa0]; 5945 5946 u8 inner_ip_dest_addr[0x80]; 5947 5948 u8 inner_ip_src_addr[0x80]; 5949 5950 u8 inner_dmac_47_16[0x20]; 5951 5952 u8 inner_smac_47_16[0x20]; 5953 5954 u8 inner_smac_15_0[0x10]; 5955 u8 inner_dmac_15_0[0x10]; 5956 }; 5957 5958 struct mlx5_ifc_match_definer_bits { 5959 u8 modify_field_select[0x40]; 5960 5961 u8 reserved_at_40[0x40]; 5962 5963 u8 reserved_at_80[0x10]; 5964 u8 format_id[0x10]; 5965 5966 u8 reserved_at_a0[0x160]; 5967 5968 u8 match_mask[16][0x20]; 5969 }; 5970 5971 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 5972 u8 opcode[0x10]; 5973 u8 uid[0x10]; 5974 5975 u8 vhca_tunnel_id[0x10]; 5976 u8 obj_type[0x10]; 5977 5978 u8 obj_id[0x20]; 5979 5980 u8 reserved_at_60[0x20]; 5981 }; 5982 5983 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 5984 u8 status[0x8]; 5985 u8 reserved_at_8[0x18]; 5986 5987 u8 syndrome[0x20]; 5988 5989 u8 obj_id[0x20]; 5990 5991 u8 reserved_at_60[0x20]; 5992 }; 5993 5994 struct mlx5_ifc_create_match_definer_in_bits { 5995 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 5996 5997 struct mlx5_ifc_match_definer_bits obj_context; 5998 }; 5999 6000 struct mlx5_ifc_create_match_definer_out_bits { 6001 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6002 }; 6003 6004 enum { 6005 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6006 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6007 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6008 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6009 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6010 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6011 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6012 }; 6013 6014 struct mlx5_ifc_query_flow_group_out_bits { 6015 u8 status[0x8]; 6016 u8 reserved_at_8[0x18]; 6017 6018 u8 syndrome[0x20]; 6019 6020 u8 reserved_at_40[0xa0]; 6021 6022 u8 start_flow_index[0x20]; 6023 6024 u8 reserved_at_100[0x20]; 6025 6026 u8 end_flow_index[0x20]; 6027 6028 u8 reserved_at_140[0xa0]; 6029 6030 u8 reserved_at_1e0[0x18]; 6031 u8 match_criteria_enable[0x8]; 6032 6033 struct mlx5_ifc_fte_match_param_bits match_criteria; 6034 6035 u8 reserved_at_1200[0xe00]; 6036 }; 6037 6038 struct mlx5_ifc_query_flow_group_in_bits { 6039 u8 opcode[0x10]; 6040 u8 reserved_at_10[0x10]; 6041 6042 u8 reserved_at_20[0x10]; 6043 u8 op_mod[0x10]; 6044 6045 u8 reserved_at_40[0x40]; 6046 6047 u8 table_type[0x8]; 6048 u8 reserved_at_88[0x18]; 6049 6050 u8 reserved_at_a0[0x8]; 6051 u8 table_id[0x18]; 6052 6053 u8 group_id[0x20]; 6054 6055 u8 reserved_at_e0[0x120]; 6056 }; 6057 6058 struct mlx5_ifc_query_flow_counter_out_bits { 6059 u8 status[0x8]; 6060 u8 reserved_at_8[0x18]; 6061 6062 u8 syndrome[0x20]; 6063 6064 u8 reserved_at_40[0x40]; 6065 6066 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6067 }; 6068 6069 struct mlx5_ifc_query_flow_counter_in_bits { 6070 u8 opcode[0x10]; 6071 u8 reserved_at_10[0x10]; 6072 6073 u8 reserved_at_20[0x10]; 6074 u8 op_mod[0x10]; 6075 6076 u8 reserved_at_40[0x80]; 6077 6078 u8 clear[0x1]; 6079 u8 reserved_at_c1[0xf]; 6080 u8 num_of_counters[0x10]; 6081 6082 u8 flow_counter_id[0x20]; 6083 }; 6084 6085 struct mlx5_ifc_query_esw_vport_context_out_bits { 6086 u8 status[0x8]; 6087 u8 reserved_at_8[0x18]; 6088 6089 u8 syndrome[0x20]; 6090 6091 u8 reserved_at_40[0x40]; 6092 6093 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6094 }; 6095 6096 struct mlx5_ifc_query_esw_vport_context_in_bits { 6097 u8 opcode[0x10]; 6098 u8 reserved_at_10[0x10]; 6099 6100 u8 reserved_at_20[0x10]; 6101 u8 op_mod[0x10]; 6102 6103 u8 other_vport[0x1]; 6104 u8 reserved_at_41[0xf]; 6105 u8 vport_number[0x10]; 6106 6107 u8 reserved_at_60[0x20]; 6108 }; 6109 6110 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6111 u8 status[0x8]; 6112 u8 reserved_at_8[0x18]; 6113 6114 u8 syndrome[0x20]; 6115 6116 u8 reserved_at_40[0x40]; 6117 }; 6118 6119 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6120 u8 reserved_at_0[0x1b]; 6121 u8 fdb_to_vport_reg_c_id[0x1]; 6122 u8 vport_cvlan_insert[0x1]; 6123 u8 vport_svlan_insert[0x1]; 6124 u8 vport_cvlan_strip[0x1]; 6125 u8 vport_svlan_strip[0x1]; 6126 }; 6127 6128 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6129 u8 opcode[0x10]; 6130 u8 reserved_at_10[0x10]; 6131 6132 u8 reserved_at_20[0x10]; 6133 u8 op_mod[0x10]; 6134 6135 u8 other_vport[0x1]; 6136 u8 reserved_at_41[0xf]; 6137 u8 vport_number[0x10]; 6138 6139 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6140 6141 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6142 }; 6143 6144 struct mlx5_ifc_query_eq_out_bits { 6145 u8 status[0x8]; 6146 u8 reserved_at_8[0x18]; 6147 6148 u8 syndrome[0x20]; 6149 6150 u8 reserved_at_40[0x40]; 6151 6152 struct mlx5_ifc_eqc_bits eq_context_entry; 6153 6154 u8 reserved_at_280[0x40]; 6155 6156 u8 event_bitmask[0x40]; 6157 6158 u8 reserved_at_300[0x580]; 6159 6160 u8 pas[][0x40]; 6161 }; 6162 6163 struct mlx5_ifc_query_eq_in_bits { 6164 u8 opcode[0x10]; 6165 u8 reserved_at_10[0x10]; 6166 6167 u8 reserved_at_20[0x10]; 6168 u8 op_mod[0x10]; 6169 6170 u8 reserved_at_40[0x18]; 6171 u8 eq_number[0x8]; 6172 6173 u8 reserved_at_60[0x20]; 6174 }; 6175 6176 struct mlx5_ifc_packet_reformat_context_in_bits { 6177 u8 reformat_type[0x8]; 6178 u8 reserved_at_8[0x4]; 6179 u8 reformat_param_0[0x4]; 6180 u8 reserved_at_10[0x6]; 6181 u8 reformat_data_size[0xa]; 6182 6183 u8 reformat_param_1[0x8]; 6184 u8 reserved_at_28[0x8]; 6185 u8 reformat_data[2][0x8]; 6186 6187 u8 more_reformat_data[][0x8]; 6188 }; 6189 6190 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6191 u8 status[0x8]; 6192 u8 reserved_at_8[0x18]; 6193 6194 u8 syndrome[0x20]; 6195 6196 u8 reserved_at_40[0xa0]; 6197 6198 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6199 }; 6200 6201 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6202 u8 opcode[0x10]; 6203 u8 reserved_at_10[0x10]; 6204 6205 u8 reserved_at_20[0x10]; 6206 u8 op_mod[0x10]; 6207 6208 u8 packet_reformat_id[0x20]; 6209 6210 u8 reserved_at_60[0xa0]; 6211 }; 6212 6213 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6214 u8 status[0x8]; 6215 u8 reserved_at_8[0x18]; 6216 6217 u8 syndrome[0x20]; 6218 6219 u8 packet_reformat_id[0x20]; 6220 6221 u8 reserved_at_60[0x20]; 6222 }; 6223 6224 enum { 6225 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6226 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6227 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6228 }; 6229 6230 enum mlx5_reformat_ctx_type { 6231 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6232 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6233 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6234 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6235 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6236 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6237 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6238 }; 6239 6240 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6241 u8 opcode[0x10]; 6242 u8 reserved_at_10[0x10]; 6243 6244 u8 reserved_at_20[0x10]; 6245 u8 op_mod[0x10]; 6246 6247 u8 reserved_at_40[0xa0]; 6248 6249 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6250 }; 6251 6252 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6253 u8 status[0x8]; 6254 u8 reserved_at_8[0x18]; 6255 6256 u8 syndrome[0x20]; 6257 6258 u8 reserved_at_40[0x40]; 6259 }; 6260 6261 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6262 u8 opcode[0x10]; 6263 u8 reserved_at_10[0x10]; 6264 6265 u8 reserved_20[0x10]; 6266 u8 op_mod[0x10]; 6267 6268 u8 packet_reformat_id[0x20]; 6269 6270 u8 reserved_60[0x20]; 6271 }; 6272 6273 struct mlx5_ifc_set_action_in_bits { 6274 u8 action_type[0x4]; 6275 u8 field[0xc]; 6276 u8 reserved_at_10[0x3]; 6277 u8 offset[0x5]; 6278 u8 reserved_at_18[0x3]; 6279 u8 length[0x5]; 6280 6281 u8 data[0x20]; 6282 }; 6283 6284 struct mlx5_ifc_add_action_in_bits { 6285 u8 action_type[0x4]; 6286 u8 field[0xc]; 6287 u8 reserved_at_10[0x10]; 6288 6289 u8 data[0x20]; 6290 }; 6291 6292 struct mlx5_ifc_copy_action_in_bits { 6293 u8 action_type[0x4]; 6294 u8 src_field[0xc]; 6295 u8 reserved_at_10[0x3]; 6296 u8 src_offset[0x5]; 6297 u8 reserved_at_18[0x3]; 6298 u8 length[0x5]; 6299 6300 u8 reserved_at_20[0x4]; 6301 u8 dst_field[0xc]; 6302 u8 reserved_at_30[0x3]; 6303 u8 dst_offset[0x5]; 6304 u8 reserved_at_38[0x8]; 6305 }; 6306 6307 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6308 struct mlx5_ifc_set_action_in_bits set_action_in; 6309 struct mlx5_ifc_add_action_in_bits add_action_in; 6310 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6311 u8 reserved_at_0[0x40]; 6312 }; 6313 6314 enum { 6315 MLX5_ACTION_TYPE_SET = 0x1, 6316 MLX5_ACTION_TYPE_ADD = 0x2, 6317 MLX5_ACTION_TYPE_COPY = 0x3, 6318 }; 6319 6320 enum { 6321 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6322 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6323 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6324 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6325 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6326 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6327 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6328 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6329 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6330 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6331 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6332 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6333 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6334 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6335 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6336 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6337 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6338 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6339 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6340 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6341 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6342 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6343 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6344 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6345 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6346 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6347 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6348 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6349 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6350 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6351 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6352 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6353 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6354 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6355 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6356 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6357 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6358 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6359 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6360 }; 6361 6362 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6363 u8 status[0x8]; 6364 u8 reserved_at_8[0x18]; 6365 6366 u8 syndrome[0x20]; 6367 6368 u8 modify_header_id[0x20]; 6369 6370 u8 reserved_at_60[0x20]; 6371 }; 6372 6373 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6374 u8 opcode[0x10]; 6375 u8 reserved_at_10[0x10]; 6376 6377 u8 reserved_at_20[0x10]; 6378 u8 op_mod[0x10]; 6379 6380 u8 reserved_at_40[0x20]; 6381 6382 u8 table_type[0x8]; 6383 u8 reserved_at_68[0x10]; 6384 u8 num_of_actions[0x8]; 6385 6386 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6387 }; 6388 6389 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6390 u8 status[0x8]; 6391 u8 reserved_at_8[0x18]; 6392 6393 u8 syndrome[0x20]; 6394 6395 u8 reserved_at_40[0x40]; 6396 }; 6397 6398 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6399 u8 opcode[0x10]; 6400 u8 reserved_at_10[0x10]; 6401 6402 u8 reserved_at_20[0x10]; 6403 u8 op_mod[0x10]; 6404 6405 u8 modify_header_id[0x20]; 6406 6407 u8 reserved_at_60[0x20]; 6408 }; 6409 6410 struct mlx5_ifc_query_modify_header_context_in_bits { 6411 u8 opcode[0x10]; 6412 u8 uid[0x10]; 6413 6414 u8 reserved_at_20[0x10]; 6415 u8 op_mod[0x10]; 6416 6417 u8 modify_header_id[0x20]; 6418 6419 u8 reserved_at_60[0xa0]; 6420 }; 6421 6422 struct mlx5_ifc_query_dct_out_bits { 6423 u8 status[0x8]; 6424 u8 reserved_at_8[0x18]; 6425 6426 u8 syndrome[0x20]; 6427 6428 u8 reserved_at_40[0x40]; 6429 6430 struct mlx5_ifc_dctc_bits dct_context_entry; 6431 6432 u8 reserved_at_280[0x180]; 6433 }; 6434 6435 struct mlx5_ifc_query_dct_in_bits { 6436 u8 opcode[0x10]; 6437 u8 reserved_at_10[0x10]; 6438 6439 u8 reserved_at_20[0x10]; 6440 u8 op_mod[0x10]; 6441 6442 u8 reserved_at_40[0x8]; 6443 u8 dctn[0x18]; 6444 6445 u8 reserved_at_60[0x20]; 6446 }; 6447 6448 struct mlx5_ifc_query_cq_out_bits { 6449 u8 status[0x8]; 6450 u8 reserved_at_8[0x18]; 6451 6452 u8 syndrome[0x20]; 6453 6454 u8 reserved_at_40[0x40]; 6455 6456 struct mlx5_ifc_cqc_bits cq_context; 6457 6458 u8 reserved_at_280[0x600]; 6459 6460 u8 pas[][0x40]; 6461 }; 6462 6463 struct mlx5_ifc_query_cq_in_bits { 6464 u8 opcode[0x10]; 6465 u8 reserved_at_10[0x10]; 6466 6467 u8 reserved_at_20[0x10]; 6468 u8 op_mod[0x10]; 6469 6470 u8 reserved_at_40[0x8]; 6471 u8 cqn[0x18]; 6472 6473 u8 reserved_at_60[0x20]; 6474 }; 6475 6476 struct mlx5_ifc_query_cong_status_out_bits { 6477 u8 status[0x8]; 6478 u8 reserved_at_8[0x18]; 6479 6480 u8 syndrome[0x20]; 6481 6482 u8 reserved_at_40[0x20]; 6483 6484 u8 enable[0x1]; 6485 u8 tag_enable[0x1]; 6486 u8 reserved_at_62[0x1e]; 6487 }; 6488 6489 struct mlx5_ifc_query_cong_status_in_bits { 6490 u8 opcode[0x10]; 6491 u8 reserved_at_10[0x10]; 6492 6493 u8 reserved_at_20[0x10]; 6494 u8 op_mod[0x10]; 6495 6496 u8 reserved_at_40[0x18]; 6497 u8 priority[0x4]; 6498 u8 cong_protocol[0x4]; 6499 6500 u8 reserved_at_60[0x20]; 6501 }; 6502 6503 struct mlx5_ifc_query_cong_statistics_out_bits { 6504 u8 status[0x8]; 6505 u8 reserved_at_8[0x18]; 6506 6507 u8 syndrome[0x20]; 6508 6509 u8 reserved_at_40[0x40]; 6510 6511 u8 rp_cur_flows[0x20]; 6512 6513 u8 sum_flows[0x20]; 6514 6515 u8 rp_cnp_ignored_high[0x20]; 6516 6517 u8 rp_cnp_ignored_low[0x20]; 6518 6519 u8 rp_cnp_handled_high[0x20]; 6520 6521 u8 rp_cnp_handled_low[0x20]; 6522 6523 u8 reserved_at_140[0x100]; 6524 6525 u8 time_stamp_high[0x20]; 6526 6527 u8 time_stamp_low[0x20]; 6528 6529 u8 accumulators_period[0x20]; 6530 6531 u8 np_ecn_marked_roce_packets_high[0x20]; 6532 6533 u8 np_ecn_marked_roce_packets_low[0x20]; 6534 6535 u8 np_cnp_sent_high[0x20]; 6536 6537 u8 np_cnp_sent_low[0x20]; 6538 6539 u8 reserved_at_320[0x560]; 6540 }; 6541 6542 struct mlx5_ifc_query_cong_statistics_in_bits { 6543 u8 opcode[0x10]; 6544 u8 reserved_at_10[0x10]; 6545 6546 u8 reserved_at_20[0x10]; 6547 u8 op_mod[0x10]; 6548 6549 u8 clear[0x1]; 6550 u8 reserved_at_41[0x1f]; 6551 6552 u8 reserved_at_60[0x20]; 6553 }; 6554 6555 struct mlx5_ifc_query_cong_params_out_bits { 6556 u8 status[0x8]; 6557 u8 reserved_at_8[0x18]; 6558 6559 u8 syndrome[0x20]; 6560 6561 u8 reserved_at_40[0x40]; 6562 6563 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6564 }; 6565 6566 struct mlx5_ifc_query_cong_params_in_bits { 6567 u8 opcode[0x10]; 6568 u8 reserved_at_10[0x10]; 6569 6570 u8 reserved_at_20[0x10]; 6571 u8 op_mod[0x10]; 6572 6573 u8 reserved_at_40[0x1c]; 6574 u8 cong_protocol[0x4]; 6575 6576 u8 reserved_at_60[0x20]; 6577 }; 6578 6579 struct mlx5_ifc_query_adapter_out_bits { 6580 u8 status[0x8]; 6581 u8 reserved_at_8[0x18]; 6582 6583 u8 syndrome[0x20]; 6584 6585 u8 reserved_at_40[0x40]; 6586 6587 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6588 }; 6589 6590 struct mlx5_ifc_query_adapter_in_bits { 6591 u8 opcode[0x10]; 6592 u8 reserved_at_10[0x10]; 6593 6594 u8 reserved_at_20[0x10]; 6595 u8 op_mod[0x10]; 6596 6597 u8 reserved_at_40[0x40]; 6598 }; 6599 6600 struct mlx5_ifc_qp_2rst_out_bits { 6601 u8 status[0x8]; 6602 u8 reserved_at_8[0x18]; 6603 6604 u8 syndrome[0x20]; 6605 6606 u8 reserved_at_40[0x40]; 6607 }; 6608 6609 struct mlx5_ifc_qp_2rst_in_bits { 6610 u8 opcode[0x10]; 6611 u8 uid[0x10]; 6612 6613 u8 reserved_at_20[0x10]; 6614 u8 op_mod[0x10]; 6615 6616 u8 reserved_at_40[0x8]; 6617 u8 qpn[0x18]; 6618 6619 u8 reserved_at_60[0x20]; 6620 }; 6621 6622 struct mlx5_ifc_qp_2err_out_bits { 6623 u8 status[0x8]; 6624 u8 reserved_at_8[0x18]; 6625 6626 u8 syndrome[0x20]; 6627 6628 u8 reserved_at_40[0x40]; 6629 }; 6630 6631 struct mlx5_ifc_qp_2err_in_bits { 6632 u8 opcode[0x10]; 6633 u8 uid[0x10]; 6634 6635 u8 reserved_at_20[0x10]; 6636 u8 op_mod[0x10]; 6637 6638 u8 reserved_at_40[0x8]; 6639 u8 qpn[0x18]; 6640 6641 u8 reserved_at_60[0x20]; 6642 }; 6643 6644 struct mlx5_ifc_page_fault_resume_out_bits { 6645 u8 status[0x8]; 6646 u8 reserved_at_8[0x18]; 6647 6648 u8 syndrome[0x20]; 6649 6650 u8 reserved_at_40[0x40]; 6651 }; 6652 6653 struct mlx5_ifc_page_fault_resume_in_bits { 6654 u8 opcode[0x10]; 6655 u8 reserved_at_10[0x10]; 6656 6657 u8 reserved_at_20[0x10]; 6658 u8 op_mod[0x10]; 6659 6660 u8 error[0x1]; 6661 u8 reserved_at_41[0x4]; 6662 u8 page_fault_type[0x3]; 6663 u8 wq_number[0x18]; 6664 6665 u8 reserved_at_60[0x8]; 6666 u8 token[0x18]; 6667 }; 6668 6669 struct mlx5_ifc_nop_out_bits { 6670 u8 status[0x8]; 6671 u8 reserved_at_8[0x18]; 6672 6673 u8 syndrome[0x20]; 6674 6675 u8 reserved_at_40[0x40]; 6676 }; 6677 6678 struct mlx5_ifc_nop_in_bits { 6679 u8 opcode[0x10]; 6680 u8 reserved_at_10[0x10]; 6681 6682 u8 reserved_at_20[0x10]; 6683 u8 op_mod[0x10]; 6684 6685 u8 reserved_at_40[0x40]; 6686 }; 6687 6688 struct mlx5_ifc_modify_vport_state_out_bits { 6689 u8 status[0x8]; 6690 u8 reserved_at_8[0x18]; 6691 6692 u8 syndrome[0x20]; 6693 6694 u8 reserved_at_40[0x40]; 6695 }; 6696 6697 struct mlx5_ifc_modify_vport_state_in_bits { 6698 u8 opcode[0x10]; 6699 u8 reserved_at_10[0x10]; 6700 6701 u8 reserved_at_20[0x10]; 6702 u8 op_mod[0x10]; 6703 6704 u8 other_vport[0x1]; 6705 u8 reserved_at_41[0xf]; 6706 u8 vport_number[0x10]; 6707 6708 u8 reserved_at_60[0x18]; 6709 u8 admin_state[0x4]; 6710 u8 reserved_at_7c[0x4]; 6711 }; 6712 6713 struct mlx5_ifc_modify_tis_out_bits { 6714 u8 status[0x8]; 6715 u8 reserved_at_8[0x18]; 6716 6717 u8 syndrome[0x20]; 6718 6719 u8 reserved_at_40[0x40]; 6720 }; 6721 6722 struct mlx5_ifc_modify_tis_bitmask_bits { 6723 u8 reserved_at_0[0x20]; 6724 6725 u8 reserved_at_20[0x1d]; 6726 u8 lag_tx_port_affinity[0x1]; 6727 u8 strict_lag_tx_port_affinity[0x1]; 6728 u8 prio[0x1]; 6729 }; 6730 6731 struct mlx5_ifc_modify_tis_in_bits { 6732 u8 opcode[0x10]; 6733 u8 uid[0x10]; 6734 6735 u8 reserved_at_20[0x10]; 6736 u8 op_mod[0x10]; 6737 6738 u8 reserved_at_40[0x8]; 6739 u8 tisn[0x18]; 6740 6741 u8 reserved_at_60[0x20]; 6742 6743 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6744 6745 u8 reserved_at_c0[0x40]; 6746 6747 struct mlx5_ifc_tisc_bits ctx; 6748 }; 6749 6750 struct mlx5_ifc_modify_tir_bitmask_bits { 6751 u8 reserved_at_0[0x20]; 6752 6753 u8 reserved_at_20[0x1b]; 6754 u8 self_lb_en[0x1]; 6755 u8 reserved_at_3c[0x1]; 6756 u8 hash[0x1]; 6757 u8 reserved_at_3e[0x1]; 6758 u8 packet_merge[0x1]; 6759 }; 6760 6761 struct mlx5_ifc_modify_tir_out_bits { 6762 u8 status[0x8]; 6763 u8 reserved_at_8[0x18]; 6764 6765 u8 syndrome[0x20]; 6766 6767 u8 reserved_at_40[0x40]; 6768 }; 6769 6770 struct mlx5_ifc_modify_tir_in_bits { 6771 u8 opcode[0x10]; 6772 u8 uid[0x10]; 6773 6774 u8 reserved_at_20[0x10]; 6775 u8 op_mod[0x10]; 6776 6777 u8 reserved_at_40[0x8]; 6778 u8 tirn[0x18]; 6779 6780 u8 reserved_at_60[0x20]; 6781 6782 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6783 6784 u8 reserved_at_c0[0x40]; 6785 6786 struct mlx5_ifc_tirc_bits ctx; 6787 }; 6788 6789 struct mlx5_ifc_modify_sq_out_bits { 6790 u8 status[0x8]; 6791 u8 reserved_at_8[0x18]; 6792 6793 u8 syndrome[0x20]; 6794 6795 u8 reserved_at_40[0x40]; 6796 }; 6797 6798 struct mlx5_ifc_modify_sq_in_bits { 6799 u8 opcode[0x10]; 6800 u8 uid[0x10]; 6801 6802 u8 reserved_at_20[0x10]; 6803 u8 op_mod[0x10]; 6804 6805 u8 sq_state[0x4]; 6806 u8 reserved_at_44[0x4]; 6807 u8 sqn[0x18]; 6808 6809 u8 reserved_at_60[0x20]; 6810 6811 u8 modify_bitmask[0x40]; 6812 6813 u8 reserved_at_c0[0x40]; 6814 6815 struct mlx5_ifc_sqc_bits ctx; 6816 }; 6817 6818 struct mlx5_ifc_modify_scheduling_element_out_bits { 6819 u8 status[0x8]; 6820 u8 reserved_at_8[0x18]; 6821 6822 u8 syndrome[0x20]; 6823 6824 u8 reserved_at_40[0x1c0]; 6825 }; 6826 6827 enum { 6828 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6829 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6830 }; 6831 6832 struct mlx5_ifc_modify_scheduling_element_in_bits { 6833 u8 opcode[0x10]; 6834 u8 reserved_at_10[0x10]; 6835 6836 u8 reserved_at_20[0x10]; 6837 u8 op_mod[0x10]; 6838 6839 u8 scheduling_hierarchy[0x8]; 6840 u8 reserved_at_48[0x18]; 6841 6842 u8 scheduling_element_id[0x20]; 6843 6844 u8 reserved_at_80[0x20]; 6845 6846 u8 modify_bitmask[0x20]; 6847 6848 u8 reserved_at_c0[0x40]; 6849 6850 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6851 6852 u8 reserved_at_300[0x100]; 6853 }; 6854 6855 struct mlx5_ifc_modify_rqt_out_bits { 6856 u8 status[0x8]; 6857 u8 reserved_at_8[0x18]; 6858 6859 u8 syndrome[0x20]; 6860 6861 u8 reserved_at_40[0x40]; 6862 }; 6863 6864 struct mlx5_ifc_rqt_bitmask_bits { 6865 u8 reserved_at_0[0x20]; 6866 6867 u8 reserved_at_20[0x1f]; 6868 u8 rqn_list[0x1]; 6869 }; 6870 6871 struct mlx5_ifc_modify_rqt_in_bits { 6872 u8 opcode[0x10]; 6873 u8 uid[0x10]; 6874 6875 u8 reserved_at_20[0x10]; 6876 u8 op_mod[0x10]; 6877 6878 u8 reserved_at_40[0x8]; 6879 u8 rqtn[0x18]; 6880 6881 u8 reserved_at_60[0x20]; 6882 6883 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6884 6885 u8 reserved_at_c0[0x40]; 6886 6887 struct mlx5_ifc_rqtc_bits ctx; 6888 }; 6889 6890 struct mlx5_ifc_modify_rq_out_bits { 6891 u8 status[0x8]; 6892 u8 reserved_at_8[0x18]; 6893 6894 u8 syndrome[0x20]; 6895 6896 u8 reserved_at_40[0x40]; 6897 }; 6898 6899 enum { 6900 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6901 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6902 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6903 }; 6904 6905 struct mlx5_ifc_modify_rq_in_bits { 6906 u8 opcode[0x10]; 6907 u8 uid[0x10]; 6908 6909 u8 reserved_at_20[0x10]; 6910 u8 op_mod[0x10]; 6911 6912 u8 rq_state[0x4]; 6913 u8 reserved_at_44[0x4]; 6914 u8 rqn[0x18]; 6915 6916 u8 reserved_at_60[0x20]; 6917 6918 u8 modify_bitmask[0x40]; 6919 6920 u8 reserved_at_c0[0x40]; 6921 6922 struct mlx5_ifc_rqc_bits ctx; 6923 }; 6924 6925 struct mlx5_ifc_modify_rmp_out_bits { 6926 u8 status[0x8]; 6927 u8 reserved_at_8[0x18]; 6928 6929 u8 syndrome[0x20]; 6930 6931 u8 reserved_at_40[0x40]; 6932 }; 6933 6934 struct mlx5_ifc_rmp_bitmask_bits { 6935 u8 reserved_at_0[0x20]; 6936 6937 u8 reserved_at_20[0x1f]; 6938 u8 lwm[0x1]; 6939 }; 6940 6941 struct mlx5_ifc_modify_rmp_in_bits { 6942 u8 opcode[0x10]; 6943 u8 uid[0x10]; 6944 6945 u8 reserved_at_20[0x10]; 6946 u8 op_mod[0x10]; 6947 6948 u8 rmp_state[0x4]; 6949 u8 reserved_at_44[0x4]; 6950 u8 rmpn[0x18]; 6951 6952 u8 reserved_at_60[0x20]; 6953 6954 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6955 6956 u8 reserved_at_c0[0x40]; 6957 6958 struct mlx5_ifc_rmpc_bits ctx; 6959 }; 6960 6961 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6962 u8 status[0x8]; 6963 u8 reserved_at_8[0x18]; 6964 6965 u8 syndrome[0x20]; 6966 6967 u8 reserved_at_40[0x40]; 6968 }; 6969 6970 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6971 u8 reserved_at_0[0x12]; 6972 u8 affiliation[0x1]; 6973 u8 reserved_at_13[0x1]; 6974 u8 disable_uc_local_lb[0x1]; 6975 u8 disable_mc_local_lb[0x1]; 6976 u8 node_guid[0x1]; 6977 u8 port_guid[0x1]; 6978 u8 min_inline[0x1]; 6979 u8 mtu[0x1]; 6980 u8 change_event[0x1]; 6981 u8 promisc[0x1]; 6982 u8 permanent_address[0x1]; 6983 u8 addresses_list[0x1]; 6984 u8 roce_en[0x1]; 6985 u8 reserved_at_1f[0x1]; 6986 }; 6987 6988 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6989 u8 opcode[0x10]; 6990 u8 reserved_at_10[0x10]; 6991 6992 u8 reserved_at_20[0x10]; 6993 u8 op_mod[0x10]; 6994 6995 u8 other_vport[0x1]; 6996 u8 reserved_at_41[0xf]; 6997 u8 vport_number[0x10]; 6998 6999 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7000 7001 u8 reserved_at_80[0x780]; 7002 7003 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7004 }; 7005 7006 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7007 u8 status[0x8]; 7008 u8 reserved_at_8[0x18]; 7009 7010 u8 syndrome[0x20]; 7011 7012 u8 reserved_at_40[0x40]; 7013 }; 7014 7015 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7016 u8 opcode[0x10]; 7017 u8 reserved_at_10[0x10]; 7018 7019 u8 reserved_at_20[0x10]; 7020 u8 op_mod[0x10]; 7021 7022 u8 other_vport[0x1]; 7023 u8 reserved_at_41[0xb]; 7024 u8 port_num[0x4]; 7025 u8 vport_number[0x10]; 7026 7027 u8 reserved_at_60[0x20]; 7028 7029 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7030 }; 7031 7032 struct mlx5_ifc_modify_cq_out_bits { 7033 u8 status[0x8]; 7034 u8 reserved_at_8[0x18]; 7035 7036 u8 syndrome[0x20]; 7037 7038 u8 reserved_at_40[0x40]; 7039 }; 7040 7041 enum { 7042 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7043 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7044 }; 7045 7046 struct mlx5_ifc_modify_cq_in_bits { 7047 u8 opcode[0x10]; 7048 u8 uid[0x10]; 7049 7050 u8 reserved_at_20[0x10]; 7051 u8 op_mod[0x10]; 7052 7053 u8 reserved_at_40[0x8]; 7054 u8 cqn[0x18]; 7055 7056 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7057 7058 struct mlx5_ifc_cqc_bits cq_context; 7059 7060 u8 reserved_at_280[0x60]; 7061 7062 u8 cq_umem_valid[0x1]; 7063 u8 reserved_at_2e1[0x1f]; 7064 7065 u8 reserved_at_300[0x580]; 7066 7067 u8 pas[][0x40]; 7068 }; 7069 7070 struct mlx5_ifc_modify_cong_status_out_bits { 7071 u8 status[0x8]; 7072 u8 reserved_at_8[0x18]; 7073 7074 u8 syndrome[0x20]; 7075 7076 u8 reserved_at_40[0x40]; 7077 }; 7078 7079 struct mlx5_ifc_modify_cong_status_in_bits { 7080 u8 opcode[0x10]; 7081 u8 reserved_at_10[0x10]; 7082 7083 u8 reserved_at_20[0x10]; 7084 u8 op_mod[0x10]; 7085 7086 u8 reserved_at_40[0x18]; 7087 u8 priority[0x4]; 7088 u8 cong_protocol[0x4]; 7089 7090 u8 enable[0x1]; 7091 u8 tag_enable[0x1]; 7092 u8 reserved_at_62[0x1e]; 7093 }; 7094 7095 struct mlx5_ifc_modify_cong_params_out_bits { 7096 u8 status[0x8]; 7097 u8 reserved_at_8[0x18]; 7098 7099 u8 syndrome[0x20]; 7100 7101 u8 reserved_at_40[0x40]; 7102 }; 7103 7104 struct mlx5_ifc_modify_cong_params_in_bits { 7105 u8 opcode[0x10]; 7106 u8 reserved_at_10[0x10]; 7107 7108 u8 reserved_at_20[0x10]; 7109 u8 op_mod[0x10]; 7110 7111 u8 reserved_at_40[0x1c]; 7112 u8 cong_protocol[0x4]; 7113 7114 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7115 7116 u8 reserved_at_80[0x80]; 7117 7118 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7119 }; 7120 7121 struct mlx5_ifc_manage_pages_out_bits { 7122 u8 status[0x8]; 7123 u8 reserved_at_8[0x18]; 7124 7125 u8 syndrome[0x20]; 7126 7127 u8 output_num_entries[0x20]; 7128 7129 u8 reserved_at_60[0x20]; 7130 7131 u8 pas[][0x40]; 7132 }; 7133 7134 enum { 7135 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7136 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7137 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7138 }; 7139 7140 struct mlx5_ifc_manage_pages_in_bits { 7141 u8 opcode[0x10]; 7142 u8 reserved_at_10[0x10]; 7143 7144 u8 reserved_at_20[0x10]; 7145 u8 op_mod[0x10]; 7146 7147 u8 embedded_cpu_function[0x1]; 7148 u8 reserved_at_41[0xf]; 7149 u8 function_id[0x10]; 7150 7151 u8 input_num_entries[0x20]; 7152 7153 u8 pas[][0x40]; 7154 }; 7155 7156 struct mlx5_ifc_mad_ifc_out_bits { 7157 u8 status[0x8]; 7158 u8 reserved_at_8[0x18]; 7159 7160 u8 syndrome[0x20]; 7161 7162 u8 reserved_at_40[0x40]; 7163 7164 u8 response_mad_packet[256][0x8]; 7165 }; 7166 7167 struct mlx5_ifc_mad_ifc_in_bits { 7168 u8 opcode[0x10]; 7169 u8 reserved_at_10[0x10]; 7170 7171 u8 reserved_at_20[0x10]; 7172 u8 op_mod[0x10]; 7173 7174 u8 remote_lid[0x10]; 7175 u8 reserved_at_50[0x8]; 7176 u8 port[0x8]; 7177 7178 u8 reserved_at_60[0x20]; 7179 7180 u8 mad[256][0x8]; 7181 }; 7182 7183 struct mlx5_ifc_init_hca_out_bits { 7184 u8 status[0x8]; 7185 u8 reserved_at_8[0x18]; 7186 7187 u8 syndrome[0x20]; 7188 7189 u8 reserved_at_40[0x40]; 7190 }; 7191 7192 struct mlx5_ifc_init_hca_in_bits { 7193 u8 opcode[0x10]; 7194 u8 reserved_at_10[0x10]; 7195 7196 u8 reserved_at_20[0x10]; 7197 u8 op_mod[0x10]; 7198 7199 u8 reserved_at_40[0x40]; 7200 u8 sw_owner_id[4][0x20]; 7201 }; 7202 7203 struct mlx5_ifc_init2rtr_qp_out_bits { 7204 u8 status[0x8]; 7205 u8 reserved_at_8[0x18]; 7206 7207 u8 syndrome[0x20]; 7208 7209 u8 reserved_at_40[0x20]; 7210 u8 ece[0x20]; 7211 }; 7212 7213 struct mlx5_ifc_init2rtr_qp_in_bits { 7214 u8 opcode[0x10]; 7215 u8 uid[0x10]; 7216 7217 u8 reserved_at_20[0x10]; 7218 u8 op_mod[0x10]; 7219 7220 u8 reserved_at_40[0x8]; 7221 u8 qpn[0x18]; 7222 7223 u8 reserved_at_60[0x20]; 7224 7225 u8 opt_param_mask[0x20]; 7226 7227 u8 ece[0x20]; 7228 7229 struct mlx5_ifc_qpc_bits qpc; 7230 7231 u8 reserved_at_800[0x80]; 7232 }; 7233 7234 struct mlx5_ifc_init2init_qp_out_bits { 7235 u8 status[0x8]; 7236 u8 reserved_at_8[0x18]; 7237 7238 u8 syndrome[0x20]; 7239 7240 u8 reserved_at_40[0x20]; 7241 u8 ece[0x20]; 7242 }; 7243 7244 struct mlx5_ifc_init2init_qp_in_bits { 7245 u8 opcode[0x10]; 7246 u8 uid[0x10]; 7247 7248 u8 reserved_at_20[0x10]; 7249 u8 op_mod[0x10]; 7250 7251 u8 reserved_at_40[0x8]; 7252 u8 qpn[0x18]; 7253 7254 u8 reserved_at_60[0x20]; 7255 7256 u8 opt_param_mask[0x20]; 7257 7258 u8 ece[0x20]; 7259 7260 struct mlx5_ifc_qpc_bits qpc; 7261 7262 u8 reserved_at_800[0x80]; 7263 }; 7264 7265 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7266 u8 status[0x8]; 7267 u8 reserved_at_8[0x18]; 7268 7269 u8 syndrome[0x20]; 7270 7271 u8 reserved_at_40[0x40]; 7272 7273 u8 packet_headers_log[128][0x8]; 7274 7275 u8 packet_syndrome[64][0x8]; 7276 }; 7277 7278 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7279 u8 opcode[0x10]; 7280 u8 reserved_at_10[0x10]; 7281 7282 u8 reserved_at_20[0x10]; 7283 u8 op_mod[0x10]; 7284 7285 u8 reserved_at_40[0x40]; 7286 }; 7287 7288 struct mlx5_ifc_gen_eqe_in_bits { 7289 u8 opcode[0x10]; 7290 u8 reserved_at_10[0x10]; 7291 7292 u8 reserved_at_20[0x10]; 7293 u8 op_mod[0x10]; 7294 7295 u8 reserved_at_40[0x18]; 7296 u8 eq_number[0x8]; 7297 7298 u8 reserved_at_60[0x20]; 7299 7300 u8 eqe[64][0x8]; 7301 }; 7302 7303 struct mlx5_ifc_gen_eq_out_bits { 7304 u8 status[0x8]; 7305 u8 reserved_at_8[0x18]; 7306 7307 u8 syndrome[0x20]; 7308 7309 u8 reserved_at_40[0x40]; 7310 }; 7311 7312 struct mlx5_ifc_enable_hca_out_bits { 7313 u8 status[0x8]; 7314 u8 reserved_at_8[0x18]; 7315 7316 u8 syndrome[0x20]; 7317 7318 u8 reserved_at_40[0x20]; 7319 }; 7320 7321 struct mlx5_ifc_enable_hca_in_bits { 7322 u8 opcode[0x10]; 7323 u8 reserved_at_10[0x10]; 7324 7325 u8 reserved_at_20[0x10]; 7326 u8 op_mod[0x10]; 7327 7328 u8 embedded_cpu_function[0x1]; 7329 u8 reserved_at_41[0xf]; 7330 u8 function_id[0x10]; 7331 7332 u8 reserved_at_60[0x20]; 7333 }; 7334 7335 struct mlx5_ifc_drain_dct_out_bits { 7336 u8 status[0x8]; 7337 u8 reserved_at_8[0x18]; 7338 7339 u8 syndrome[0x20]; 7340 7341 u8 reserved_at_40[0x40]; 7342 }; 7343 7344 struct mlx5_ifc_drain_dct_in_bits { 7345 u8 opcode[0x10]; 7346 u8 uid[0x10]; 7347 7348 u8 reserved_at_20[0x10]; 7349 u8 op_mod[0x10]; 7350 7351 u8 reserved_at_40[0x8]; 7352 u8 dctn[0x18]; 7353 7354 u8 reserved_at_60[0x20]; 7355 }; 7356 7357 struct mlx5_ifc_disable_hca_out_bits { 7358 u8 status[0x8]; 7359 u8 reserved_at_8[0x18]; 7360 7361 u8 syndrome[0x20]; 7362 7363 u8 reserved_at_40[0x20]; 7364 }; 7365 7366 struct mlx5_ifc_disable_hca_in_bits { 7367 u8 opcode[0x10]; 7368 u8 reserved_at_10[0x10]; 7369 7370 u8 reserved_at_20[0x10]; 7371 u8 op_mod[0x10]; 7372 7373 u8 embedded_cpu_function[0x1]; 7374 u8 reserved_at_41[0xf]; 7375 u8 function_id[0x10]; 7376 7377 u8 reserved_at_60[0x20]; 7378 }; 7379 7380 struct mlx5_ifc_detach_from_mcg_out_bits { 7381 u8 status[0x8]; 7382 u8 reserved_at_8[0x18]; 7383 7384 u8 syndrome[0x20]; 7385 7386 u8 reserved_at_40[0x40]; 7387 }; 7388 7389 struct mlx5_ifc_detach_from_mcg_in_bits { 7390 u8 opcode[0x10]; 7391 u8 uid[0x10]; 7392 7393 u8 reserved_at_20[0x10]; 7394 u8 op_mod[0x10]; 7395 7396 u8 reserved_at_40[0x8]; 7397 u8 qpn[0x18]; 7398 7399 u8 reserved_at_60[0x20]; 7400 7401 u8 multicast_gid[16][0x8]; 7402 }; 7403 7404 struct mlx5_ifc_destroy_xrq_out_bits { 7405 u8 status[0x8]; 7406 u8 reserved_at_8[0x18]; 7407 7408 u8 syndrome[0x20]; 7409 7410 u8 reserved_at_40[0x40]; 7411 }; 7412 7413 struct mlx5_ifc_destroy_xrq_in_bits { 7414 u8 opcode[0x10]; 7415 u8 uid[0x10]; 7416 7417 u8 reserved_at_20[0x10]; 7418 u8 op_mod[0x10]; 7419 7420 u8 reserved_at_40[0x8]; 7421 u8 xrqn[0x18]; 7422 7423 u8 reserved_at_60[0x20]; 7424 }; 7425 7426 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7427 u8 status[0x8]; 7428 u8 reserved_at_8[0x18]; 7429 7430 u8 syndrome[0x20]; 7431 7432 u8 reserved_at_40[0x40]; 7433 }; 7434 7435 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7436 u8 opcode[0x10]; 7437 u8 uid[0x10]; 7438 7439 u8 reserved_at_20[0x10]; 7440 u8 op_mod[0x10]; 7441 7442 u8 reserved_at_40[0x8]; 7443 u8 xrc_srqn[0x18]; 7444 7445 u8 reserved_at_60[0x20]; 7446 }; 7447 7448 struct mlx5_ifc_destroy_tis_out_bits { 7449 u8 status[0x8]; 7450 u8 reserved_at_8[0x18]; 7451 7452 u8 syndrome[0x20]; 7453 7454 u8 reserved_at_40[0x40]; 7455 }; 7456 7457 struct mlx5_ifc_destroy_tis_in_bits { 7458 u8 opcode[0x10]; 7459 u8 uid[0x10]; 7460 7461 u8 reserved_at_20[0x10]; 7462 u8 op_mod[0x10]; 7463 7464 u8 reserved_at_40[0x8]; 7465 u8 tisn[0x18]; 7466 7467 u8 reserved_at_60[0x20]; 7468 }; 7469 7470 struct mlx5_ifc_destroy_tir_out_bits { 7471 u8 status[0x8]; 7472 u8 reserved_at_8[0x18]; 7473 7474 u8 syndrome[0x20]; 7475 7476 u8 reserved_at_40[0x40]; 7477 }; 7478 7479 struct mlx5_ifc_destroy_tir_in_bits { 7480 u8 opcode[0x10]; 7481 u8 uid[0x10]; 7482 7483 u8 reserved_at_20[0x10]; 7484 u8 op_mod[0x10]; 7485 7486 u8 reserved_at_40[0x8]; 7487 u8 tirn[0x18]; 7488 7489 u8 reserved_at_60[0x20]; 7490 }; 7491 7492 struct mlx5_ifc_destroy_srq_out_bits { 7493 u8 status[0x8]; 7494 u8 reserved_at_8[0x18]; 7495 7496 u8 syndrome[0x20]; 7497 7498 u8 reserved_at_40[0x40]; 7499 }; 7500 7501 struct mlx5_ifc_destroy_srq_in_bits { 7502 u8 opcode[0x10]; 7503 u8 uid[0x10]; 7504 7505 u8 reserved_at_20[0x10]; 7506 u8 op_mod[0x10]; 7507 7508 u8 reserved_at_40[0x8]; 7509 u8 srqn[0x18]; 7510 7511 u8 reserved_at_60[0x20]; 7512 }; 7513 7514 struct mlx5_ifc_destroy_sq_out_bits { 7515 u8 status[0x8]; 7516 u8 reserved_at_8[0x18]; 7517 7518 u8 syndrome[0x20]; 7519 7520 u8 reserved_at_40[0x40]; 7521 }; 7522 7523 struct mlx5_ifc_destroy_sq_in_bits { 7524 u8 opcode[0x10]; 7525 u8 uid[0x10]; 7526 7527 u8 reserved_at_20[0x10]; 7528 u8 op_mod[0x10]; 7529 7530 u8 reserved_at_40[0x8]; 7531 u8 sqn[0x18]; 7532 7533 u8 reserved_at_60[0x20]; 7534 }; 7535 7536 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7537 u8 status[0x8]; 7538 u8 reserved_at_8[0x18]; 7539 7540 u8 syndrome[0x20]; 7541 7542 u8 reserved_at_40[0x1c0]; 7543 }; 7544 7545 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7546 u8 opcode[0x10]; 7547 u8 reserved_at_10[0x10]; 7548 7549 u8 reserved_at_20[0x10]; 7550 u8 op_mod[0x10]; 7551 7552 u8 scheduling_hierarchy[0x8]; 7553 u8 reserved_at_48[0x18]; 7554 7555 u8 scheduling_element_id[0x20]; 7556 7557 u8 reserved_at_80[0x180]; 7558 }; 7559 7560 struct mlx5_ifc_destroy_rqt_out_bits { 7561 u8 status[0x8]; 7562 u8 reserved_at_8[0x18]; 7563 7564 u8 syndrome[0x20]; 7565 7566 u8 reserved_at_40[0x40]; 7567 }; 7568 7569 struct mlx5_ifc_destroy_rqt_in_bits { 7570 u8 opcode[0x10]; 7571 u8 uid[0x10]; 7572 7573 u8 reserved_at_20[0x10]; 7574 u8 op_mod[0x10]; 7575 7576 u8 reserved_at_40[0x8]; 7577 u8 rqtn[0x18]; 7578 7579 u8 reserved_at_60[0x20]; 7580 }; 7581 7582 struct mlx5_ifc_destroy_rq_out_bits { 7583 u8 status[0x8]; 7584 u8 reserved_at_8[0x18]; 7585 7586 u8 syndrome[0x20]; 7587 7588 u8 reserved_at_40[0x40]; 7589 }; 7590 7591 struct mlx5_ifc_destroy_rq_in_bits { 7592 u8 opcode[0x10]; 7593 u8 uid[0x10]; 7594 7595 u8 reserved_at_20[0x10]; 7596 u8 op_mod[0x10]; 7597 7598 u8 reserved_at_40[0x8]; 7599 u8 rqn[0x18]; 7600 7601 u8 reserved_at_60[0x20]; 7602 }; 7603 7604 struct mlx5_ifc_set_delay_drop_params_in_bits { 7605 u8 opcode[0x10]; 7606 u8 reserved_at_10[0x10]; 7607 7608 u8 reserved_at_20[0x10]; 7609 u8 op_mod[0x10]; 7610 7611 u8 reserved_at_40[0x20]; 7612 7613 u8 reserved_at_60[0x10]; 7614 u8 delay_drop_timeout[0x10]; 7615 }; 7616 7617 struct mlx5_ifc_set_delay_drop_params_out_bits { 7618 u8 status[0x8]; 7619 u8 reserved_at_8[0x18]; 7620 7621 u8 syndrome[0x20]; 7622 7623 u8 reserved_at_40[0x40]; 7624 }; 7625 7626 struct mlx5_ifc_destroy_rmp_out_bits { 7627 u8 status[0x8]; 7628 u8 reserved_at_8[0x18]; 7629 7630 u8 syndrome[0x20]; 7631 7632 u8 reserved_at_40[0x40]; 7633 }; 7634 7635 struct mlx5_ifc_destroy_rmp_in_bits { 7636 u8 opcode[0x10]; 7637 u8 uid[0x10]; 7638 7639 u8 reserved_at_20[0x10]; 7640 u8 op_mod[0x10]; 7641 7642 u8 reserved_at_40[0x8]; 7643 u8 rmpn[0x18]; 7644 7645 u8 reserved_at_60[0x20]; 7646 }; 7647 7648 struct mlx5_ifc_destroy_qp_out_bits { 7649 u8 status[0x8]; 7650 u8 reserved_at_8[0x18]; 7651 7652 u8 syndrome[0x20]; 7653 7654 u8 reserved_at_40[0x40]; 7655 }; 7656 7657 struct mlx5_ifc_destroy_qp_in_bits { 7658 u8 opcode[0x10]; 7659 u8 uid[0x10]; 7660 7661 u8 reserved_at_20[0x10]; 7662 u8 op_mod[0x10]; 7663 7664 u8 reserved_at_40[0x8]; 7665 u8 qpn[0x18]; 7666 7667 u8 reserved_at_60[0x20]; 7668 }; 7669 7670 struct mlx5_ifc_destroy_psv_out_bits { 7671 u8 status[0x8]; 7672 u8 reserved_at_8[0x18]; 7673 7674 u8 syndrome[0x20]; 7675 7676 u8 reserved_at_40[0x40]; 7677 }; 7678 7679 struct mlx5_ifc_destroy_psv_in_bits { 7680 u8 opcode[0x10]; 7681 u8 reserved_at_10[0x10]; 7682 7683 u8 reserved_at_20[0x10]; 7684 u8 op_mod[0x10]; 7685 7686 u8 reserved_at_40[0x8]; 7687 u8 psvn[0x18]; 7688 7689 u8 reserved_at_60[0x20]; 7690 }; 7691 7692 struct mlx5_ifc_destroy_mkey_out_bits { 7693 u8 status[0x8]; 7694 u8 reserved_at_8[0x18]; 7695 7696 u8 syndrome[0x20]; 7697 7698 u8 reserved_at_40[0x40]; 7699 }; 7700 7701 struct mlx5_ifc_destroy_mkey_in_bits { 7702 u8 opcode[0x10]; 7703 u8 uid[0x10]; 7704 7705 u8 reserved_at_20[0x10]; 7706 u8 op_mod[0x10]; 7707 7708 u8 reserved_at_40[0x8]; 7709 u8 mkey_index[0x18]; 7710 7711 u8 reserved_at_60[0x20]; 7712 }; 7713 7714 struct mlx5_ifc_destroy_flow_table_out_bits { 7715 u8 status[0x8]; 7716 u8 reserved_at_8[0x18]; 7717 7718 u8 syndrome[0x20]; 7719 7720 u8 reserved_at_40[0x40]; 7721 }; 7722 7723 struct mlx5_ifc_destroy_flow_table_in_bits { 7724 u8 opcode[0x10]; 7725 u8 reserved_at_10[0x10]; 7726 7727 u8 reserved_at_20[0x10]; 7728 u8 op_mod[0x10]; 7729 7730 u8 other_vport[0x1]; 7731 u8 reserved_at_41[0xf]; 7732 u8 vport_number[0x10]; 7733 7734 u8 reserved_at_60[0x20]; 7735 7736 u8 table_type[0x8]; 7737 u8 reserved_at_88[0x18]; 7738 7739 u8 reserved_at_a0[0x8]; 7740 u8 table_id[0x18]; 7741 7742 u8 reserved_at_c0[0x140]; 7743 }; 7744 7745 struct mlx5_ifc_destroy_flow_group_out_bits { 7746 u8 status[0x8]; 7747 u8 reserved_at_8[0x18]; 7748 7749 u8 syndrome[0x20]; 7750 7751 u8 reserved_at_40[0x40]; 7752 }; 7753 7754 struct mlx5_ifc_destroy_flow_group_in_bits { 7755 u8 opcode[0x10]; 7756 u8 reserved_at_10[0x10]; 7757 7758 u8 reserved_at_20[0x10]; 7759 u8 op_mod[0x10]; 7760 7761 u8 other_vport[0x1]; 7762 u8 reserved_at_41[0xf]; 7763 u8 vport_number[0x10]; 7764 7765 u8 reserved_at_60[0x20]; 7766 7767 u8 table_type[0x8]; 7768 u8 reserved_at_88[0x18]; 7769 7770 u8 reserved_at_a0[0x8]; 7771 u8 table_id[0x18]; 7772 7773 u8 group_id[0x20]; 7774 7775 u8 reserved_at_e0[0x120]; 7776 }; 7777 7778 struct mlx5_ifc_destroy_eq_out_bits { 7779 u8 status[0x8]; 7780 u8 reserved_at_8[0x18]; 7781 7782 u8 syndrome[0x20]; 7783 7784 u8 reserved_at_40[0x40]; 7785 }; 7786 7787 struct mlx5_ifc_destroy_eq_in_bits { 7788 u8 opcode[0x10]; 7789 u8 reserved_at_10[0x10]; 7790 7791 u8 reserved_at_20[0x10]; 7792 u8 op_mod[0x10]; 7793 7794 u8 reserved_at_40[0x18]; 7795 u8 eq_number[0x8]; 7796 7797 u8 reserved_at_60[0x20]; 7798 }; 7799 7800 struct mlx5_ifc_destroy_dct_out_bits { 7801 u8 status[0x8]; 7802 u8 reserved_at_8[0x18]; 7803 7804 u8 syndrome[0x20]; 7805 7806 u8 reserved_at_40[0x40]; 7807 }; 7808 7809 struct mlx5_ifc_destroy_dct_in_bits { 7810 u8 opcode[0x10]; 7811 u8 uid[0x10]; 7812 7813 u8 reserved_at_20[0x10]; 7814 u8 op_mod[0x10]; 7815 7816 u8 reserved_at_40[0x8]; 7817 u8 dctn[0x18]; 7818 7819 u8 reserved_at_60[0x20]; 7820 }; 7821 7822 struct mlx5_ifc_destroy_cq_out_bits { 7823 u8 status[0x8]; 7824 u8 reserved_at_8[0x18]; 7825 7826 u8 syndrome[0x20]; 7827 7828 u8 reserved_at_40[0x40]; 7829 }; 7830 7831 struct mlx5_ifc_destroy_cq_in_bits { 7832 u8 opcode[0x10]; 7833 u8 uid[0x10]; 7834 7835 u8 reserved_at_20[0x10]; 7836 u8 op_mod[0x10]; 7837 7838 u8 reserved_at_40[0x8]; 7839 u8 cqn[0x18]; 7840 7841 u8 reserved_at_60[0x20]; 7842 }; 7843 7844 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7845 u8 status[0x8]; 7846 u8 reserved_at_8[0x18]; 7847 7848 u8 syndrome[0x20]; 7849 7850 u8 reserved_at_40[0x40]; 7851 }; 7852 7853 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7854 u8 opcode[0x10]; 7855 u8 reserved_at_10[0x10]; 7856 7857 u8 reserved_at_20[0x10]; 7858 u8 op_mod[0x10]; 7859 7860 u8 reserved_at_40[0x20]; 7861 7862 u8 reserved_at_60[0x10]; 7863 u8 vxlan_udp_port[0x10]; 7864 }; 7865 7866 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7867 u8 status[0x8]; 7868 u8 reserved_at_8[0x18]; 7869 7870 u8 syndrome[0x20]; 7871 7872 u8 reserved_at_40[0x40]; 7873 }; 7874 7875 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7876 u8 opcode[0x10]; 7877 u8 reserved_at_10[0x10]; 7878 7879 u8 reserved_at_20[0x10]; 7880 u8 op_mod[0x10]; 7881 7882 u8 reserved_at_40[0x60]; 7883 7884 u8 reserved_at_a0[0x8]; 7885 u8 table_index[0x18]; 7886 7887 u8 reserved_at_c0[0x140]; 7888 }; 7889 7890 struct mlx5_ifc_delete_fte_out_bits { 7891 u8 status[0x8]; 7892 u8 reserved_at_8[0x18]; 7893 7894 u8 syndrome[0x20]; 7895 7896 u8 reserved_at_40[0x40]; 7897 }; 7898 7899 struct mlx5_ifc_delete_fte_in_bits { 7900 u8 opcode[0x10]; 7901 u8 reserved_at_10[0x10]; 7902 7903 u8 reserved_at_20[0x10]; 7904 u8 op_mod[0x10]; 7905 7906 u8 other_vport[0x1]; 7907 u8 reserved_at_41[0xf]; 7908 u8 vport_number[0x10]; 7909 7910 u8 reserved_at_60[0x20]; 7911 7912 u8 table_type[0x8]; 7913 u8 reserved_at_88[0x18]; 7914 7915 u8 reserved_at_a0[0x8]; 7916 u8 table_id[0x18]; 7917 7918 u8 reserved_at_c0[0x40]; 7919 7920 u8 flow_index[0x20]; 7921 7922 u8 reserved_at_120[0xe0]; 7923 }; 7924 7925 struct mlx5_ifc_dealloc_xrcd_out_bits { 7926 u8 status[0x8]; 7927 u8 reserved_at_8[0x18]; 7928 7929 u8 syndrome[0x20]; 7930 7931 u8 reserved_at_40[0x40]; 7932 }; 7933 7934 struct mlx5_ifc_dealloc_xrcd_in_bits { 7935 u8 opcode[0x10]; 7936 u8 uid[0x10]; 7937 7938 u8 reserved_at_20[0x10]; 7939 u8 op_mod[0x10]; 7940 7941 u8 reserved_at_40[0x8]; 7942 u8 xrcd[0x18]; 7943 7944 u8 reserved_at_60[0x20]; 7945 }; 7946 7947 struct mlx5_ifc_dealloc_uar_out_bits { 7948 u8 status[0x8]; 7949 u8 reserved_at_8[0x18]; 7950 7951 u8 syndrome[0x20]; 7952 7953 u8 reserved_at_40[0x40]; 7954 }; 7955 7956 struct mlx5_ifc_dealloc_uar_in_bits { 7957 u8 opcode[0x10]; 7958 u8 uid[0x10]; 7959 7960 u8 reserved_at_20[0x10]; 7961 u8 op_mod[0x10]; 7962 7963 u8 reserved_at_40[0x8]; 7964 u8 uar[0x18]; 7965 7966 u8 reserved_at_60[0x20]; 7967 }; 7968 7969 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7970 u8 status[0x8]; 7971 u8 reserved_at_8[0x18]; 7972 7973 u8 syndrome[0x20]; 7974 7975 u8 reserved_at_40[0x40]; 7976 }; 7977 7978 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7979 u8 opcode[0x10]; 7980 u8 uid[0x10]; 7981 7982 u8 reserved_at_20[0x10]; 7983 u8 op_mod[0x10]; 7984 7985 u8 reserved_at_40[0x8]; 7986 u8 transport_domain[0x18]; 7987 7988 u8 reserved_at_60[0x20]; 7989 }; 7990 7991 struct mlx5_ifc_dealloc_q_counter_out_bits { 7992 u8 status[0x8]; 7993 u8 reserved_at_8[0x18]; 7994 7995 u8 syndrome[0x20]; 7996 7997 u8 reserved_at_40[0x40]; 7998 }; 7999 8000 struct mlx5_ifc_dealloc_q_counter_in_bits { 8001 u8 opcode[0x10]; 8002 u8 reserved_at_10[0x10]; 8003 8004 u8 reserved_at_20[0x10]; 8005 u8 op_mod[0x10]; 8006 8007 u8 reserved_at_40[0x18]; 8008 u8 counter_set_id[0x8]; 8009 8010 u8 reserved_at_60[0x20]; 8011 }; 8012 8013 struct mlx5_ifc_dealloc_pd_out_bits { 8014 u8 status[0x8]; 8015 u8 reserved_at_8[0x18]; 8016 8017 u8 syndrome[0x20]; 8018 8019 u8 reserved_at_40[0x40]; 8020 }; 8021 8022 struct mlx5_ifc_dealloc_pd_in_bits { 8023 u8 opcode[0x10]; 8024 u8 uid[0x10]; 8025 8026 u8 reserved_at_20[0x10]; 8027 u8 op_mod[0x10]; 8028 8029 u8 reserved_at_40[0x8]; 8030 u8 pd[0x18]; 8031 8032 u8 reserved_at_60[0x20]; 8033 }; 8034 8035 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8036 u8 status[0x8]; 8037 u8 reserved_at_8[0x18]; 8038 8039 u8 syndrome[0x20]; 8040 8041 u8 reserved_at_40[0x40]; 8042 }; 8043 8044 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8045 u8 opcode[0x10]; 8046 u8 reserved_at_10[0x10]; 8047 8048 u8 reserved_at_20[0x10]; 8049 u8 op_mod[0x10]; 8050 8051 u8 flow_counter_id[0x20]; 8052 8053 u8 reserved_at_60[0x20]; 8054 }; 8055 8056 struct mlx5_ifc_create_xrq_out_bits { 8057 u8 status[0x8]; 8058 u8 reserved_at_8[0x18]; 8059 8060 u8 syndrome[0x20]; 8061 8062 u8 reserved_at_40[0x8]; 8063 u8 xrqn[0x18]; 8064 8065 u8 reserved_at_60[0x20]; 8066 }; 8067 8068 struct mlx5_ifc_create_xrq_in_bits { 8069 u8 opcode[0x10]; 8070 u8 uid[0x10]; 8071 8072 u8 reserved_at_20[0x10]; 8073 u8 op_mod[0x10]; 8074 8075 u8 reserved_at_40[0x40]; 8076 8077 struct mlx5_ifc_xrqc_bits xrq_context; 8078 }; 8079 8080 struct mlx5_ifc_create_xrc_srq_out_bits { 8081 u8 status[0x8]; 8082 u8 reserved_at_8[0x18]; 8083 8084 u8 syndrome[0x20]; 8085 8086 u8 reserved_at_40[0x8]; 8087 u8 xrc_srqn[0x18]; 8088 8089 u8 reserved_at_60[0x20]; 8090 }; 8091 8092 struct mlx5_ifc_create_xrc_srq_in_bits { 8093 u8 opcode[0x10]; 8094 u8 uid[0x10]; 8095 8096 u8 reserved_at_20[0x10]; 8097 u8 op_mod[0x10]; 8098 8099 u8 reserved_at_40[0x40]; 8100 8101 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8102 8103 u8 reserved_at_280[0x60]; 8104 8105 u8 xrc_srq_umem_valid[0x1]; 8106 u8 reserved_at_2e1[0x1f]; 8107 8108 u8 reserved_at_300[0x580]; 8109 8110 u8 pas[][0x40]; 8111 }; 8112 8113 struct mlx5_ifc_create_tis_out_bits { 8114 u8 status[0x8]; 8115 u8 reserved_at_8[0x18]; 8116 8117 u8 syndrome[0x20]; 8118 8119 u8 reserved_at_40[0x8]; 8120 u8 tisn[0x18]; 8121 8122 u8 reserved_at_60[0x20]; 8123 }; 8124 8125 struct mlx5_ifc_create_tis_in_bits { 8126 u8 opcode[0x10]; 8127 u8 uid[0x10]; 8128 8129 u8 reserved_at_20[0x10]; 8130 u8 op_mod[0x10]; 8131 8132 u8 reserved_at_40[0xc0]; 8133 8134 struct mlx5_ifc_tisc_bits ctx; 8135 }; 8136 8137 struct mlx5_ifc_create_tir_out_bits { 8138 u8 status[0x8]; 8139 u8 icm_address_63_40[0x18]; 8140 8141 u8 syndrome[0x20]; 8142 8143 u8 icm_address_39_32[0x8]; 8144 u8 tirn[0x18]; 8145 8146 u8 icm_address_31_0[0x20]; 8147 }; 8148 8149 struct mlx5_ifc_create_tir_in_bits { 8150 u8 opcode[0x10]; 8151 u8 uid[0x10]; 8152 8153 u8 reserved_at_20[0x10]; 8154 u8 op_mod[0x10]; 8155 8156 u8 reserved_at_40[0xc0]; 8157 8158 struct mlx5_ifc_tirc_bits ctx; 8159 }; 8160 8161 struct mlx5_ifc_create_srq_out_bits { 8162 u8 status[0x8]; 8163 u8 reserved_at_8[0x18]; 8164 8165 u8 syndrome[0x20]; 8166 8167 u8 reserved_at_40[0x8]; 8168 u8 srqn[0x18]; 8169 8170 u8 reserved_at_60[0x20]; 8171 }; 8172 8173 struct mlx5_ifc_create_srq_in_bits { 8174 u8 opcode[0x10]; 8175 u8 uid[0x10]; 8176 8177 u8 reserved_at_20[0x10]; 8178 u8 op_mod[0x10]; 8179 8180 u8 reserved_at_40[0x40]; 8181 8182 struct mlx5_ifc_srqc_bits srq_context_entry; 8183 8184 u8 reserved_at_280[0x600]; 8185 8186 u8 pas[][0x40]; 8187 }; 8188 8189 struct mlx5_ifc_create_sq_out_bits { 8190 u8 status[0x8]; 8191 u8 reserved_at_8[0x18]; 8192 8193 u8 syndrome[0x20]; 8194 8195 u8 reserved_at_40[0x8]; 8196 u8 sqn[0x18]; 8197 8198 u8 reserved_at_60[0x20]; 8199 }; 8200 8201 struct mlx5_ifc_create_sq_in_bits { 8202 u8 opcode[0x10]; 8203 u8 uid[0x10]; 8204 8205 u8 reserved_at_20[0x10]; 8206 u8 op_mod[0x10]; 8207 8208 u8 reserved_at_40[0xc0]; 8209 8210 struct mlx5_ifc_sqc_bits ctx; 8211 }; 8212 8213 struct mlx5_ifc_create_scheduling_element_out_bits { 8214 u8 status[0x8]; 8215 u8 reserved_at_8[0x18]; 8216 8217 u8 syndrome[0x20]; 8218 8219 u8 reserved_at_40[0x40]; 8220 8221 u8 scheduling_element_id[0x20]; 8222 8223 u8 reserved_at_a0[0x160]; 8224 }; 8225 8226 struct mlx5_ifc_create_scheduling_element_in_bits { 8227 u8 opcode[0x10]; 8228 u8 reserved_at_10[0x10]; 8229 8230 u8 reserved_at_20[0x10]; 8231 u8 op_mod[0x10]; 8232 8233 u8 scheduling_hierarchy[0x8]; 8234 u8 reserved_at_48[0x18]; 8235 8236 u8 reserved_at_60[0xa0]; 8237 8238 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8239 8240 u8 reserved_at_300[0x100]; 8241 }; 8242 8243 struct mlx5_ifc_create_rqt_out_bits { 8244 u8 status[0x8]; 8245 u8 reserved_at_8[0x18]; 8246 8247 u8 syndrome[0x20]; 8248 8249 u8 reserved_at_40[0x8]; 8250 u8 rqtn[0x18]; 8251 8252 u8 reserved_at_60[0x20]; 8253 }; 8254 8255 struct mlx5_ifc_create_rqt_in_bits { 8256 u8 opcode[0x10]; 8257 u8 uid[0x10]; 8258 8259 u8 reserved_at_20[0x10]; 8260 u8 op_mod[0x10]; 8261 8262 u8 reserved_at_40[0xc0]; 8263 8264 struct mlx5_ifc_rqtc_bits rqt_context; 8265 }; 8266 8267 struct mlx5_ifc_create_rq_out_bits { 8268 u8 status[0x8]; 8269 u8 reserved_at_8[0x18]; 8270 8271 u8 syndrome[0x20]; 8272 8273 u8 reserved_at_40[0x8]; 8274 u8 rqn[0x18]; 8275 8276 u8 reserved_at_60[0x20]; 8277 }; 8278 8279 struct mlx5_ifc_create_rq_in_bits { 8280 u8 opcode[0x10]; 8281 u8 uid[0x10]; 8282 8283 u8 reserved_at_20[0x10]; 8284 u8 op_mod[0x10]; 8285 8286 u8 reserved_at_40[0xc0]; 8287 8288 struct mlx5_ifc_rqc_bits ctx; 8289 }; 8290 8291 struct mlx5_ifc_create_rmp_out_bits { 8292 u8 status[0x8]; 8293 u8 reserved_at_8[0x18]; 8294 8295 u8 syndrome[0x20]; 8296 8297 u8 reserved_at_40[0x8]; 8298 u8 rmpn[0x18]; 8299 8300 u8 reserved_at_60[0x20]; 8301 }; 8302 8303 struct mlx5_ifc_create_rmp_in_bits { 8304 u8 opcode[0x10]; 8305 u8 uid[0x10]; 8306 8307 u8 reserved_at_20[0x10]; 8308 u8 op_mod[0x10]; 8309 8310 u8 reserved_at_40[0xc0]; 8311 8312 struct mlx5_ifc_rmpc_bits ctx; 8313 }; 8314 8315 struct mlx5_ifc_create_qp_out_bits { 8316 u8 status[0x8]; 8317 u8 reserved_at_8[0x18]; 8318 8319 u8 syndrome[0x20]; 8320 8321 u8 reserved_at_40[0x8]; 8322 u8 qpn[0x18]; 8323 8324 u8 ece[0x20]; 8325 }; 8326 8327 struct mlx5_ifc_create_qp_in_bits { 8328 u8 opcode[0x10]; 8329 u8 uid[0x10]; 8330 8331 u8 reserved_at_20[0x10]; 8332 u8 op_mod[0x10]; 8333 8334 u8 reserved_at_40[0x8]; 8335 u8 input_qpn[0x18]; 8336 8337 u8 reserved_at_60[0x20]; 8338 u8 opt_param_mask[0x20]; 8339 8340 u8 ece[0x20]; 8341 8342 struct mlx5_ifc_qpc_bits qpc; 8343 8344 u8 reserved_at_800[0x60]; 8345 8346 u8 wq_umem_valid[0x1]; 8347 u8 reserved_at_861[0x1f]; 8348 8349 u8 pas[][0x40]; 8350 }; 8351 8352 struct mlx5_ifc_create_psv_out_bits { 8353 u8 status[0x8]; 8354 u8 reserved_at_8[0x18]; 8355 8356 u8 syndrome[0x20]; 8357 8358 u8 reserved_at_40[0x40]; 8359 8360 u8 reserved_at_80[0x8]; 8361 u8 psv0_index[0x18]; 8362 8363 u8 reserved_at_a0[0x8]; 8364 u8 psv1_index[0x18]; 8365 8366 u8 reserved_at_c0[0x8]; 8367 u8 psv2_index[0x18]; 8368 8369 u8 reserved_at_e0[0x8]; 8370 u8 psv3_index[0x18]; 8371 }; 8372 8373 struct mlx5_ifc_create_psv_in_bits { 8374 u8 opcode[0x10]; 8375 u8 reserved_at_10[0x10]; 8376 8377 u8 reserved_at_20[0x10]; 8378 u8 op_mod[0x10]; 8379 8380 u8 num_psv[0x4]; 8381 u8 reserved_at_44[0x4]; 8382 u8 pd[0x18]; 8383 8384 u8 reserved_at_60[0x20]; 8385 }; 8386 8387 struct mlx5_ifc_create_mkey_out_bits { 8388 u8 status[0x8]; 8389 u8 reserved_at_8[0x18]; 8390 8391 u8 syndrome[0x20]; 8392 8393 u8 reserved_at_40[0x8]; 8394 u8 mkey_index[0x18]; 8395 8396 u8 reserved_at_60[0x20]; 8397 }; 8398 8399 struct mlx5_ifc_create_mkey_in_bits { 8400 u8 opcode[0x10]; 8401 u8 uid[0x10]; 8402 8403 u8 reserved_at_20[0x10]; 8404 u8 op_mod[0x10]; 8405 8406 u8 reserved_at_40[0x20]; 8407 8408 u8 pg_access[0x1]; 8409 u8 mkey_umem_valid[0x1]; 8410 u8 reserved_at_62[0x1e]; 8411 8412 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8413 8414 u8 reserved_at_280[0x80]; 8415 8416 u8 translations_octword_actual_size[0x20]; 8417 8418 u8 reserved_at_320[0x560]; 8419 8420 u8 klm_pas_mtt[][0x20]; 8421 }; 8422 8423 enum { 8424 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8425 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8426 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8427 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8428 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8429 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8430 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8431 }; 8432 8433 struct mlx5_ifc_create_flow_table_out_bits { 8434 u8 status[0x8]; 8435 u8 icm_address_63_40[0x18]; 8436 8437 u8 syndrome[0x20]; 8438 8439 u8 icm_address_39_32[0x8]; 8440 u8 table_id[0x18]; 8441 8442 u8 icm_address_31_0[0x20]; 8443 }; 8444 8445 struct mlx5_ifc_create_flow_table_in_bits { 8446 u8 opcode[0x10]; 8447 u8 reserved_at_10[0x10]; 8448 8449 u8 reserved_at_20[0x10]; 8450 u8 op_mod[0x10]; 8451 8452 u8 other_vport[0x1]; 8453 u8 reserved_at_41[0xf]; 8454 u8 vport_number[0x10]; 8455 8456 u8 reserved_at_60[0x20]; 8457 8458 u8 table_type[0x8]; 8459 u8 reserved_at_88[0x18]; 8460 8461 u8 reserved_at_a0[0x20]; 8462 8463 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8464 }; 8465 8466 struct mlx5_ifc_create_flow_group_out_bits { 8467 u8 status[0x8]; 8468 u8 reserved_at_8[0x18]; 8469 8470 u8 syndrome[0x20]; 8471 8472 u8 reserved_at_40[0x8]; 8473 u8 group_id[0x18]; 8474 8475 u8 reserved_at_60[0x20]; 8476 }; 8477 8478 enum { 8479 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8480 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8481 }; 8482 8483 enum { 8484 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8485 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8486 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8487 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8488 }; 8489 8490 struct mlx5_ifc_create_flow_group_in_bits { 8491 u8 opcode[0x10]; 8492 u8 reserved_at_10[0x10]; 8493 8494 u8 reserved_at_20[0x10]; 8495 u8 op_mod[0x10]; 8496 8497 u8 other_vport[0x1]; 8498 u8 reserved_at_41[0xf]; 8499 u8 vport_number[0x10]; 8500 8501 u8 reserved_at_60[0x20]; 8502 8503 u8 table_type[0x8]; 8504 u8 reserved_at_88[0x4]; 8505 u8 group_type[0x4]; 8506 u8 reserved_at_90[0x10]; 8507 8508 u8 reserved_at_a0[0x8]; 8509 u8 table_id[0x18]; 8510 8511 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8512 8513 u8 reserved_at_c1[0x1f]; 8514 8515 u8 start_flow_index[0x20]; 8516 8517 u8 reserved_at_100[0x20]; 8518 8519 u8 end_flow_index[0x20]; 8520 8521 u8 reserved_at_140[0x10]; 8522 u8 match_definer_id[0x10]; 8523 8524 u8 reserved_at_160[0x80]; 8525 8526 u8 reserved_at_1e0[0x18]; 8527 u8 match_criteria_enable[0x8]; 8528 8529 struct mlx5_ifc_fte_match_param_bits match_criteria; 8530 8531 u8 reserved_at_1200[0xe00]; 8532 }; 8533 8534 struct mlx5_ifc_create_eq_out_bits { 8535 u8 status[0x8]; 8536 u8 reserved_at_8[0x18]; 8537 8538 u8 syndrome[0x20]; 8539 8540 u8 reserved_at_40[0x18]; 8541 u8 eq_number[0x8]; 8542 8543 u8 reserved_at_60[0x20]; 8544 }; 8545 8546 struct mlx5_ifc_create_eq_in_bits { 8547 u8 opcode[0x10]; 8548 u8 uid[0x10]; 8549 8550 u8 reserved_at_20[0x10]; 8551 u8 op_mod[0x10]; 8552 8553 u8 reserved_at_40[0x40]; 8554 8555 struct mlx5_ifc_eqc_bits eq_context_entry; 8556 8557 u8 reserved_at_280[0x40]; 8558 8559 u8 event_bitmask[4][0x40]; 8560 8561 u8 reserved_at_3c0[0x4c0]; 8562 8563 u8 pas[][0x40]; 8564 }; 8565 8566 struct mlx5_ifc_create_dct_out_bits { 8567 u8 status[0x8]; 8568 u8 reserved_at_8[0x18]; 8569 8570 u8 syndrome[0x20]; 8571 8572 u8 reserved_at_40[0x8]; 8573 u8 dctn[0x18]; 8574 8575 u8 ece[0x20]; 8576 }; 8577 8578 struct mlx5_ifc_create_dct_in_bits { 8579 u8 opcode[0x10]; 8580 u8 uid[0x10]; 8581 8582 u8 reserved_at_20[0x10]; 8583 u8 op_mod[0x10]; 8584 8585 u8 reserved_at_40[0x40]; 8586 8587 struct mlx5_ifc_dctc_bits dct_context_entry; 8588 8589 u8 reserved_at_280[0x180]; 8590 }; 8591 8592 struct mlx5_ifc_create_cq_out_bits { 8593 u8 status[0x8]; 8594 u8 reserved_at_8[0x18]; 8595 8596 u8 syndrome[0x20]; 8597 8598 u8 reserved_at_40[0x8]; 8599 u8 cqn[0x18]; 8600 8601 u8 reserved_at_60[0x20]; 8602 }; 8603 8604 struct mlx5_ifc_create_cq_in_bits { 8605 u8 opcode[0x10]; 8606 u8 uid[0x10]; 8607 8608 u8 reserved_at_20[0x10]; 8609 u8 op_mod[0x10]; 8610 8611 u8 reserved_at_40[0x40]; 8612 8613 struct mlx5_ifc_cqc_bits cq_context; 8614 8615 u8 reserved_at_280[0x60]; 8616 8617 u8 cq_umem_valid[0x1]; 8618 u8 reserved_at_2e1[0x59f]; 8619 8620 u8 pas[][0x40]; 8621 }; 8622 8623 struct mlx5_ifc_config_int_moderation_out_bits { 8624 u8 status[0x8]; 8625 u8 reserved_at_8[0x18]; 8626 8627 u8 syndrome[0x20]; 8628 8629 u8 reserved_at_40[0x4]; 8630 u8 min_delay[0xc]; 8631 u8 int_vector[0x10]; 8632 8633 u8 reserved_at_60[0x20]; 8634 }; 8635 8636 enum { 8637 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8638 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8639 }; 8640 8641 struct mlx5_ifc_config_int_moderation_in_bits { 8642 u8 opcode[0x10]; 8643 u8 reserved_at_10[0x10]; 8644 8645 u8 reserved_at_20[0x10]; 8646 u8 op_mod[0x10]; 8647 8648 u8 reserved_at_40[0x4]; 8649 u8 min_delay[0xc]; 8650 u8 int_vector[0x10]; 8651 8652 u8 reserved_at_60[0x20]; 8653 }; 8654 8655 struct mlx5_ifc_attach_to_mcg_out_bits { 8656 u8 status[0x8]; 8657 u8 reserved_at_8[0x18]; 8658 8659 u8 syndrome[0x20]; 8660 8661 u8 reserved_at_40[0x40]; 8662 }; 8663 8664 struct mlx5_ifc_attach_to_mcg_in_bits { 8665 u8 opcode[0x10]; 8666 u8 uid[0x10]; 8667 8668 u8 reserved_at_20[0x10]; 8669 u8 op_mod[0x10]; 8670 8671 u8 reserved_at_40[0x8]; 8672 u8 qpn[0x18]; 8673 8674 u8 reserved_at_60[0x20]; 8675 8676 u8 multicast_gid[16][0x8]; 8677 }; 8678 8679 struct mlx5_ifc_arm_xrq_out_bits { 8680 u8 status[0x8]; 8681 u8 reserved_at_8[0x18]; 8682 8683 u8 syndrome[0x20]; 8684 8685 u8 reserved_at_40[0x40]; 8686 }; 8687 8688 struct mlx5_ifc_arm_xrq_in_bits { 8689 u8 opcode[0x10]; 8690 u8 reserved_at_10[0x10]; 8691 8692 u8 reserved_at_20[0x10]; 8693 u8 op_mod[0x10]; 8694 8695 u8 reserved_at_40[0x8]; 8696 u8 xrqn[0x18]; 8697 8698 u8 reserved_at_60[0x10]; 8699 u8 lwm[0x10]; 8700 }; 8701 8702 struct mlx5_ifc_arm_xrc_srq_out_bits { 8703 u8 status[0x8]; 8704 u8 reserved_at_8[0x18]; 8705 8706 u8 syndrome[0x20]; 8707 8708 u8 reserved_at_40[0x40]; 8709 }; 8710 8711 enum { 8712 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8713 }; 8714 8715 struct mlx5_ifc_arm_xrc_srq_in_bits { 8716 u8 opcode[0x10]; 8717 u8 uid[0x10]; 8718 8719 u8 reserved_at_20[0x10]; 8720 u8 op_mod[0x10]; 8721 8722 u8 reserved_at_40[0x8]; 8723 u8 xrc_srqn[0x18]; 8724 8725 u8 reserved_at_60[0x10]; 8726 u8 lwm[0x10]; 8727 }; 8728 8729 struct mlx5_ifc_arm_rq_out_bits { 8730 u8 status[0x8]; 8731 u8 reserved_at_8[0x18]; 8732 8733 u8 syndrome[0x20]; 8734 8735 u8 reserved_at_40[0x40]; 8736 }; 8737 8738 enum { 8739 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8740 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8741 }; 8742 8743 struct mlx5_ifc_arm_rq_in_bits { 8744 u8 opcode[0x10]; 8745 u8 uid[0x10]; 8746 8747 u8 reserved_at_20[0x10]; 8748 u8 op_mod[0x10]; 8749 8750 u8 reserved_at_40[0x8]; 8751 u8 srq_number[0x18]; 8752 8753 u8 reserved_at_60[0x10]; 8754 u8 lwm[0x10]; 8755 }; 8756 8757 struct mlx5_ifc_arm_dct_out_bits { 8758 u8 status[0x8]; 8759 u8 reserved_at_8[0x18]; 8760 8761 u8 syndrome[0x20]; 8762 8763 u8 reserved_at_40[0x40]; 8764 }; 8765 8766 struct mlx5_ifc_arm_dct_in_bits { 8767 u8 opcode[0x10]; 8768 u8 reserved_at_10[0x10]; 8769 8770 u8 reserved_at_20[0x10]; 8771 u8 op_mod[0x10]; 8772 8773 u8 reserved_at_40[0x8]; 8774 u8 dct_number[0x18]; 8775 8776 u8 reserved_at_60[0x20]; 8777 }; 8778 8779 struct mlx5_ifc_alloc_xrcd_out_bits { 8780 u8 status[0x8]; 8781 u8 reserved_at_8[0x18]; 8782 8783 u8 syndrome[0x20]; 8784 8785 u8 reserved_at_40[0x8]; 8786 u8 xrcd[0x18]; 8787 8788 u8 reserved_at_60[0x20]; 8789 }; 8790 8791 struct mlx5_ifc_alloc_xrcd_in_bits { 8792 u8 opcode[0x10]; 8793 u8 uid[0x10]; 8794 8795 u8 reserved_at_20[0x10]; 8796 u8 op_mod[0x10]; 8797 8798 u8 reserved_at_40[0x40]; 8799 }; 8800 8801 struct mlx5_ifc_alloc_uar_out_bits { 8802 u8 status[0x8]; 8803 u8 reserved_at_8[0x18]; 8804 8805 u8 syndrome[0x20]; 8806 8807 u8 reserved_at_40[0x8]; 8808 u8 uar[0x18]; 8809 8810 u8 reserved_at_60[0x20]; 8811 }; 8812 8813 struct mlx5_ifc_alloc_uar_in_bits { 8814 u8 opcode[0x10]; 8815 u8 uid[0x10]; 8816 8817 u8 reserved_at_20[0x10]; 8818 u8 op_mod[0x10]; 8819 8820 u8 reserved_at_40[0x40]; 8821 }; 8822 8823 struct mlx5_ifc_alloc_transport_domain_out_bits { 8824 u8 status[0x8]; 8825 u8 reserved_at_8[0x18]; 8826 8827 u8 syndrome[0x20]; 8828 8829 u8 reserved_at_40[0x8]; 8830 u8 transport_domain[0x18]; 8831 8832 u8 reserved_at_60[0x20]; 8833 }; 8834 8835 struct mlx5_ifc_alloc_transport_domain_in_bits { 8836 u8 opcode[0x10]; 8837 u8 uid[0x10]; 8838 8839 u8 reserved_at_20[0x10]; 8840 u8 op_mod[0x10]; 8841 8842 u8 reserved_at_40[0x40]; 8843 }; 8844 8845 struct mlx5_ifc_alloc_q_counter_out_bits { 8846 u8 status[0x8]; 8847 u8 reserved_at_8[0x18]; 8848 8849 u8 syndrome[0x20]; 8850 8851 u8 reserved_at_40[0x18]; 8852 u8 counter_set_id[0x8]; 8853 8854 u8 reserved_at_60[0x20]; 8855 }; 8856 8857 struct mlx5_ifc_alloc_q_counter_in_bits { 8858 u8 opcode[0x10]; 8859 u8 uid[0x10]; 8860 8861 u8 reserved_at_20[0x10]; 8862 u8 op_mod[0x10]; 8863 8864 u8 reserved_at_40[0x40]; 8865 }; 8866 8867 struct mlx5_ifc_alloc_pd_out_bits { 8868 u8 status[0x8]; 8869 u8 reserved_at_8[0x18]; 8870 8871 u8 syndrome[0x20]; 8872 8873 u8 reserved_at_40[0x8]; 8874 u8 pd[0x18]; 8875 8876 u8 reserved_at_60[0x20]; 8877 }; 8878 8879 struct mlx5_ifc_alloc_pd_in_bits { 8880 u8 opcode[0x10]; 8881 u8 uid[0x10]; 8882 8883 u8 reserved_at_20[0x10]; 8884 u8 op_mod[0x10]; 8885 8886 u8 reserved_at_40[0x40]; 8887 }; 8888 8889 struct mlx5_ifc_alloc_flow_counter_out_bits { 8890 u8 status[0x8]; 8891 u8 reserved_at_8[0x18]; 8892 8893 u8 syndrome[0x20]; 8894 8895 u8 flow_counter_id[0x20]; 8896 8897 u8 reserved_at_60[0x20]; 8898 }; 8899 8900 struct mlx5_ifc_alloc_flow_counter_in_bits { 8901 u8 opcode[0x10]; 8902 u8 reserved_at_10[0x10]; 8903 8904 u8 reserved_at_20[0x10]; 8905 u8 op_mod[0x10]; 8906 8907 u8 reserved_at_40[0x38]; 8908 u8 flow_counter_bulk[0x8]; 8909 }; 8910 8911 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8912 u8 status[0x8]; 8913 u8 reserved_at_8[0x18]; 8914 8915 u8 syndrome[0x20]; 8916 8917 u8 reserved_at_40[0x40]; 8918 }; 8919 8920 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8921 u8 opcode[0x10]; 8922 u8 reserved_at_10[0x10]; 8923 8924 u8 reserved_at_20[0x10]; 8925 u8 op_mod[0x10]; 8926 8927 u8 reserved_at_40[0x20]; 8928 8929 u8 reserved_at_60[0x10]; 8930 u8 vxlan_udp_port[0x10]; 8931 }; 8932 8933 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8934 u8 status[0x8]; 8935 u8 reserved_at_8[0x18]; 8936 8937 u8 syndrome[0x20]; 8938 8939 u8 reserved_at_40[0x40]; 8940 }; 8941 8942 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8943 u8 rate_limit[0x20]; 8944 8945 u8 burst_upper_bound[0x20]; 8946 8947 u8 reserved_at_40[0x10]; 8948 u8 typical_packet_size[0x10]; 8949 8950 u8 reserved_at_60[0x120]; 8951 }; 8952 8953 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8954 u8 opcode[0x10]; 8955 u8 uid[0x10]; 8956 8957 u8 reserved_at_20[0x10]; 8958 u8 op_mod[0x10]; 8959 8960 u8 reserved_at_40[0x10]; 8961 u8 rate_limit_index[0x10]; 8962 8963 u8 reserved_at_60[0x20]; 8964 8965 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8966 }; 8967 8968 struct mlx5_ifc_access_register_out_bits { 8969 u8 status[0x8]; 8970 u8 reserved_at_8[0x18]; 8971 8972 u8 syndrome[0x20]; 8973 8974 u8 reserved_at_40[0x40]; 8975 8976 u8 register_data[][0x20]; 8977 }; 8978 8979 enum { 8980 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8981 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8982 }; 8983 8984 struct mlx5_ifc_access_register_in_bits { 8985 u8 opcode[0x10]; 8986 u8 reserved_at_10[0x10]; 8987 8988 u8 reserved_at_20[0x10]; 8989 u8 op_mod[0x10]; 8990 8991 u8 reserved_at_40[0x10]; 8992 u8 register_id[0x10]; 8993 8994 u8 argument[0x20]; 8995 8996 u8 register_data[][0x20]; 8997 }; 8998 8999 struct mlx5_ifc_sltp_reg_bits { 9000 u8 status[0x4]; 9001 u8 version[0x4]; 9002 u8 local_port[0x8]; 9003 u8 pnat[0x2]; 9004 u8 reserved_at_12[0x2]; 9005 u8 lane[0x4]; 9006 u8 reserved_at_18[0x8]; 9007 9008 u8 reserved_at_20[0x20]; 9009 9010 u8 reserved_at_40[0x7]; 9011 u8 polarity[0x1]; 9012 u8 ob_tap0[0x8]; 9013 u8 ob_tap1[0x8]; 9014 u8 ob_tap2[0x8]; 9015 9016 u8 reserved_at_60[0xc]; 9017 u8 ob_preemp_mode[0x4]; 9018 u8 ob_reg[0x8]; 9019 u8 ob_bias[0x8]; 9020 9021 u8 reserved_at_80[0x20]; 9022 }; 9023 9024 struct mlx5_ifc_slrg_reg_bits { 9025 u8 status[0x4]; 9026 u8 version[0x4]; 9027 u8 local_port[0x8]; 9028 u8 pnat[0x2]; 9029 u8 reserved_at_12[0x2]; 9030 u8 lane[0x4]; 9031 u8 reserved_at_18[0x8]; 9032 9033 u8 time_to_link_up[0x10]; 9034 u8 reserved_at_30[0xc]; 9035 u8 grade_lane_speed[0x4]; 9036 9037 u8 grade_version[0x8]; 9038 u8 grade[0x18]; 9039 9040 u8 reserved_at_60[0x4]; 9041 u8 height_grade_type[0x4]; 9042 u8 height_grade[0x18]; 9043 9044 u8 height_dz[0x10]; 9045 u8 height_dv[0x10]; 9046 9047 u8 reserved_at_a0[0x10]; 9048 u8 height_sigma[0x10]; 9049 9050 u8 reserved_at_c0[0x20]; 9051 9052 u8 reserved_at_e0[0x4]; 9053 u8 phase_grade_type[0x4]; 9054 u8 phase_grade[0x18]; 9055 9056 u8 reserved_at_100[0x8]; 9057 u8 phase_eo_pos[0x8]; 9058 u8 reserved_at_110[0x8]; 9059 u8 phase_eo_neg[0x8]; 9060 9061 u8 ffe_set_tested[0x10]; 9062 u8 test_errors_per_lane[0x10]; 9063 }; 9064 9065 struct mlx5_ifc_pvlc_reg_bits { 9066 u8 reserved_at_0[0x8]; 9067 u8 local_port[0x8]; 9068 u8 reserved_at_10[0x10]; 9069 9070 u8 reserved_at_20[0x1c]; 9071 u8 vl_hw_cap[0x4]; 9072 9073 u8 reserved_at_40[0x1c]; 9074 u8 vl_admin[0x4]; 9075 9076 u8 reserved_at_60[0x1c]; 9077 u8 vl_operational[0x4]; 9078 }; 9079 9080 struct mlx5_ifc_pude_reg_bits { 9081 u8 swid[0x8]; 9082 u8 local_port[0x8]; 9083 u8 reserved_at_10[0x4]; 9084 u8 admin_status[0x4]; 9085 u8 reserved_at_18[0x4]; 9086 u8 oper_status[0x4]; 9087 9088 u8 reserved_at_20[0x60]; 9089 }; 9090 9091 struct mlx5_ifc_ptys_reg_bits { 9092 u8 reserved_at_0[0x1]; 9093 u8 an_disable_admin[0x1]; 9094 u8 an_disable_cap[0x1]; 9095 u8 reserved_at_3[0x5]; 9096 u8 local_port[0x8]; 9097 u8 reserved_at_10[0xd]; 9098 u8 proto_mask[0x3]; 9099 9100 u8 an_status[0x4]; 9101 u8 reserved_at_24[0xc]; 9102 u8 data_rate_oper[0x10]; 9103 9104 u8 ext_eth_proto_capability[0x20]; 9105 9106 u8 eth_proto_capability[0x20]; 9107 9108 u8 ib_link_width_capability[0x10]; 9109 u8 ib_proto_capability[0x10]; 9110 9111 u8 ext_eth_proto_admin[0x20]; 9112 9113 u8 eth_proto_admin[0x20]; 9114 9115 u8 ib_link_width_admin[0x10]; 9116 u8 ib_proto_admin[0x10]; 9117 9118 u8 ext_eth_proto_oper[0x20]; 9119 9120 u8 eth_proto_oper[0x20]; 9121 9122 u8 ib_link_width_oper[0x10]; 9123 u8 ib_proto_oper[0x10]; 9124 9125 u8 reserved_at_160[0x1c]; 9126 u8 connector_type[0x4]; 9127 9128 u8 eth_proto_lp_advertise[0x20]; 9129 9130 u8 reserved_at_1a0[0x60]; 9131 }; 9132 9133 struct mlx5_ifc_mlcr_reg_bits { 9134 u8 reserved_at_0[0x8]; 9135 u8 local_port[0x8]; 9136 u8 reserved_at_10[0x20]; 9137 9138 u8 beacon_duration[0x10]; 9139 u8 reserved_at_40[0x10]; 9140 9141 u8 beacon_remain[0x10]; 9142 }; 9143 9144 struct mlx5_ifc_ptas_reg_bits { 9145 u8 reserved_at_0[0x20]; 9146 9147 u8 algorithm_options[0x10]; 9148 u8 reserved_at_30[0x4]; 9149 u8 repetitions_mode[0x4]; 9150 u8 num_of_repetitions[0x8]; 9151 9152 u8 grade_version[0x8]; 9153 u8 height_grade_type[0x4]; 9154 u8 phase_grade_type[0x4]; 9155 u8 height_grade_weight[0x8]; 9156 u8 phase_grade_weight[0x8]; 9157 9158 u8 gisim_measure_bits[0x10]; 9159 u8 adaptive_tap_measure_bits[0x10]; 9160 9161 u8 ber_bath_high_error_threshold[0x10]; 9162 u8 ber_bath_mid_error_threshold[0x10]; 9163 9164 u8 ber_bath_low_error_threshold[0x10]; 9165 u8 one_ratio_high_threshold[0x10]; 9166 9167 u8 one_ratio_high_mid_threshold[0x10]; 9168 u8 one_ratio_low_mid_threshold[0x10]; 9169 9170 u8 one_ratio_low_threshold[0x10]; 9171 u8 ndeo_error_threshold[0x10]; 9172 9173 u8 mixer_offset_step_size[0x10]; 9174 u8 reserved_at_110[0x8]; 9175 u8 mix90_phase_for_voltage_bath[0x8]; 9176 9177 u8 mixer_offset_start[0x10]; 9178 u8 mixer_offset_end[0x10]; 9179 9180 u8 reserved_at_140[0x15]; 9181 u8 ber_test_time[0xb]; 9182 }; 9183 9184 struct mlx5_ifc_pspa_reg_bits { 9185 u8 swid[0x8]; 9186 u8 local_port[0x8]; 9187 u8 sub_port[0x8]; 9188 u8 reserved_at_18[0x8]; 9189 9190 u8 reserved_at_20[0x20]; 9191 }; 9192 9193 struct mlx5_ifc_pqdr_reg_bits { 9194 u8 reserved_at_0[0x8]; 9195 u8 local_port[0x8]; 9196 u8 reserved_at_10[0x5]; 9197 u8 prio[0x3]; 9198 u8 reserved_at_18[0x6]; 9199 u8 mode[0x2]; 9200 9201 u8 reserved_at_20[0x20]; 9202 9203 u8 reserved_at_40[0x10]; 9204 u8 min_threshold[0x10]; 9205 9206 u8 reserved_at_60[0x10]; 9207 u8 max_threshold[0x10]; 9208 9209 u8 reserved_at_80[0x10]; 9210 u8 mark_probability_denominator[0x10]; 9211 9212 u8 reserved_at_a0[0x60]; 9213 }; 9214 9215 struct mlx5_ifc_ppsc_reg_bits { 9216 u8 reserved_at_0[0x8]; 9217 u8 local_port[0x8]; 9218 u8 reserved_at_10[0x10]; 9219 9220 u8 reserved_at_20[0x60]; 9221 9222 u8 reserved_at_80[0x1c]; 9223 u8 wrps_admin[0x4]; 9224 9225 u8 reserved_at_a0[0x1c]; 9226 u8 wrps_status[0x4]; 9227 9228 u8 reserved_at_c0[0x8]; 9229 u8 up_threshold[0x8]; 9230 u8 reserved_at_d0[0x8]; 9231 u8 down_threshold[0x8]; 9232 9233 u8 reserved_at_e0[0x20]; 9234 9235 u8 reserved_at_100[0x1c]; 9236 u8 srps_admin[0x4]; 9237 9238 u8 reserved_at_120[0x1c]; 9239 u8 srps_status[0x4]; 9240 9241 u8 reserved_at_140[0x40]; 9242 }; 9243 9244 struct mlx5_ifc_pplr_reg_bits { 9245 u8 reserved_at_0[0x8]; 9246 u8 local_port[0x8]; 9247 u8 reserved_at_10[0x10]; 9248 9249 u8 reserved_at_20[0x8]; 9250 u8 lb_cap[0x8]; 9251 u8 reserved_at_30[0x8]; 9252 u8 lb_en[0x8]; 9253 }; 9254 9255 struct mlx5_ifc_pplm_reg_bits { 9256 u8 reserved_at_0[0x8]; 9257 u8 local_port[0x8]; 9258 u8 reserved_at_10[0x10]; 9259 9260 u8 reserved_at_20[0x20]; 9261 9262 u8 port_profile_mode[0x8]; 9263 u8 static_port_profile[0x8]; 9264 u8 active_port_profile[0x8]; 9265 u8 reserved_at_58[0x8]; 9266 9267 u8 retransmission_active[0x8]; 9268 u8 fec_mode_active[0x18]; 9269 9270 u8 rs_fec_correction_bypass_cap[0x4]; 9271 u8 reserved_at_84[0x8]; 9272 u8 fec_override_cap_56g[0x4]; 9273 u8 fec_override_cap_100g[0x4]; 9274 u8 fec_override_cap_50g[0x4]; 9275 u8 fec_override_cap_25g[0x4]; 9276 u8 fec_override_cap_10g_40g[0x4]; 9277 9278 u8 rs_fec_correction_bypass_admin[0x4]; 9279 u8 reserved_at_a4[0x8]; 9280 u8 fec_override_admin_56g[0x4]; 9281 u8 fec_override_admin_100g[0x4]; 9282 u8 fec_override_admin_50g[0x4]; 9283 u8 fec_override_admin_25g[0x4]; 9284 u8 fec_override_admin_10g_40g[0x4]; 9285 9286 u8 fec_override_cap_400g_8x[0x10]; 9287 u8 fec_override_cap_200g_4x[0x10]; 9288 9289 u8 fec_override_cap_100g_2x[0x10]; 9290 u8 fec_override_cap_50g_1x[0x10]; 9291 9292 u8 fec_override_admin_400g_8x[0x10]; 9293 u8 fec_override_admin_200g_4x[0x10]; 9294 9295 u8 fec_override_admin_100g_2x[0x10]; 9296 u8 fec_override_admin_50g_1x[0x10]; 9297 9298 u8 reserved_at_140[0x140]; 9299 }; 9300 9301 struct mlx5_ifc_ppcnt_reg_bits { 9302 u8 swid[0x8]; 9303 u8 local_port[0x8]; 9304 u8 pnat[0x2]; 9305 u8 reserved_at_12[0x8]; 9306 u8 grp[0x6]; 9307 9308 u8 clr[0x1]; 9309 u8 reserved_at_21[0x1c]; 9310 u8 prio_tc[0x3]; 9311 9312 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9313 }; 9314 9315 struct mlx5_ifc_mpein_reg_bits { 9316 u8 reserved_at_0[0x2]; 9317 u8 depth[0x6]; 9318 u8 pcie_index[0x8]; 9319 u8 node[0x8]; 9320 u8 reserved_at_18[0x8]; 9321 9322 u8 capability_mask[0x20]; 9323 9324 u8 reserved_at_40[0x8]; 9325 u8 link_width_enabled[0x8]; 9326 u8 link_speed_enabled[0x10]; 9327 9328 u8 lane0_physical_position[0x8]; 9329 u8 link_width_active[0x8]; 9330 u8 link_speed_active[0x10]; 9331 9332 u8 num_of_pfs[0x10]; 9333 u8 num_of_vfs[0x10]; 9334 9335 u8 bdf0[0x10]; 9336 u8 reserved_at_b0[0x10]; 9337 9338 u8 max_read_request_size[0x4]; 9339 u8 max_payload_size[0x4]; 9340 u8 reserved_at_c8[0x5]; 9341 u8 pwr_status[0x3]; 9342 u8 port_type[0x4]; 9343 u8 reserved_at_d4[0xb]; 9344 u8 lane_reversal[0x1]; 9345 9346 u8 reserved_at_e0[0x14]; 9347 u8 pci_power[0xc]; 9348 9349 u8 reserved_at_100[0x20]; 9350 9351 u8 device_status[0x10]; 9352 u8 port_state[0x8]; 9353 u8 reserved_at_138[0x8]; 9354 9355 u8 reserved_at_140[0x10]; 9356 u8 receiver_detect_result[0x10]; 9357 9358 u8 reserved_at_160[0x20]; 9359 }; 9360 9361 struct mlx5_ifc_mpcnt_reg_bits { 9362 u8 reserved_at_0[0x8]; 9363 u8 pcie_index[0x8]; 9364 u8 reserved_at_10[0xa]; 9365 u8 grp[0x6]; 9366 9367 u8 clr[0x1]; 9368 u8 reserved_at_21[0x1f]; 9369 9370 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9371 }; 9372 9373 struct mlx5_ifc_ppad_reg_bits { 9374 u8 reserved_at_0[0x3]; 9375 u8 single_mac[0x1]; 9376 u8 reserved_at_4[0x4]; 9377 u8 local_port[0x8]; 9378 u8 mac_47_32[0x10]; 9379 9380 u8 mac_31_0[0x20]; 9381 9382 u8 reserved_at_40[0x40]; 9383 }; 9384 9385 struct mlx5_ifc_pmtu_reg_bits { 9386 u8 reserved_at_0[0x8]; 9387 u8 local_port[0x8]; 9388 u8 reserved_at_10[0x10]; 9389 9390 u8 max_mtu[0x10]; 9391 u8 reserved_at_30[0x10]; 9392 9393 u8 admin_mtu[0x10]; 9394 u8 reserved_at_50[0x10]; 9395 9396 u8 oper_mtu[0x10]; 9397 u8 reserved_at_70[0x10]; 9398 }; 9399 9400 struct mlx5_ifc_pmpr_reg_bits { 9401 u8 reserved_at_0[0x8]; 9402 u8 module[0x8]; 9403 u8 reserved_at_10[0x10]; 9404 9405 u8 reserved_at_20[0x18]; 9406 u8 attenuation_5g[0x8]; 9407 9408 u8 reserved_at_40[0x18]; 9409 u8 attenuation_7g[0x8]; 9410 9411 u8 reserved_at_60[0x18]; 9412 u8 attenuation_12g[0x8]; 9413 }; 9414 9415 struct mlx5_ifc_pmpe_reg_bits { 9416 u8 reserved_at_0[0x8]; 9417 u8 module[0x8]; 9418 u8 reserved_at_10[0xc]; 9419 u8 module_status[0x4]; 9420 9421 u8 reserved_at_20[0x60]; 9422 }; 9423 9424 struct mlx5_ifc_pmpc_reg_bits { 9425 u8 module_state_updated[32][0x8]; 9426 }; 9427 9428 struct mlx5_ifc_pmlpn_reg_bits { 9429 u8 reserved_at_0[0x4]; 9430 u8 mlpn_status[0x4]; 9431 u8 local_port[0x8]; 9432 u8 reserved_at_10[0x10]; 9433 9434 u8 e[0x1]; 9435 u8 reserved_at_21[0x1f]; 9436 }; 9437 9438 struct mlx5_ifc_pmlp_reg_bits { 9439 u8 rxtx[0x1]; 9440 u8 reserved_at_1[0x7]; 9441 u8 local_port[0x8]; 9442 u8 reserved_at_10[0x8]; 9443 u8 width[0x8]; 9444 9445 u8 lane0_module_mapping[0x20]; 9446 9447 u8 lane1_module_mapping[0x20]; 9448 9449 u8 lane2_module_mapping[0x20]; 9450 9451 u8 lane3_module_mapping[0x20]; 9452 9453 u8 reserved_at_a0[0x160]; 9454 }; 9455 9456 struct mlx5_ifc_pmaos_reg_bits { 9457 u8 reserved_at_0[0x8]; 9458 u8 module[0x8]; 9459 u8 reserved_at_10[0x4]; 9460 u8 admin_status[0x4]; 9461 u8 reserved_at_18[0x4]; 9462 u8 oper_status[0x4]; 9463 9464 u8 ase[0x1]; 9465 u8 ee[0x1]; 9466 u8 reserved_at_22[0x1c]; 9467 u8 e[0x2]; 9468 9469 u8 reserved_at_40[0x40]; 9470 }; 9471 9472 struct mlx5_ifc_plpc_reg_bits { 9473 u8 reserved_at_0[0x4]; 9474 u8 profile_id[0xc]; 9475 u8 reserved_at_10[0x4]; 9476 u8 proto_mask[0x4]; 9477 u8 reserved_at_18[0x8]; 9478 9479 u8 reserved_at_20[0x10]; 9480 u8 lane_speed[0x10]; 9481 9482 u8 reserved_at_40[0x17]; 9483 u8 lpbf[0x1]; 9484 u8 fec_mode_policy[0x8]; 9485 9486 u8 retransmission_capability[0x8]; 9487 u8 fec_mode_capability[0x18]; 9488 9489 u8 retransmission_support_admin[0x8]; 9490 u8 fec_mode_support_admin[0x18]; 9491 9492 u8 retransmission_request_admin[0x8]; 9493 u8 fec_mode_request_admin[0x18]; 9494 9495 u8 reserved_at_c0[0x80]; 9496 }; 9497 9498 struct mlx5_ifc_plib_reg_bits { 9499 u8 reserved_at_0[0x8]; 9500 u8 local_port[0x8]; 9501 u8 reserved_at_10[0x8]; 9502 u8 ib_port[0x8]; 9503 9504 u8 reserved_at_20[0x60]; 9505 }; 9506 9507 struct mlx5_ifc_plbf_reg_bits { 9508 u8 reserved_at_0[0x8]; 9509 u8 local_port[0x8]; 9510 u8 reserved_at_10[0xd]; 9511 u8 lbf_mode[0x3]; 9512 9513 u8 reserved_at_20[0x20]; 9514 }; 9515 9516 struct mlx5_ifc_pipg_reg_bits { 9517 u8 reserved_at_0[0x8]; 9518 u8 local_port[0x8]; 9519 u8 reserved_at_10[0x10]; 9520 9521 u8 dic[0x1]; 9522 u8 reserved_at_21[0x19]; 9523 u8 ipg[0x4]; 9524 u8 reserved_at_3e[0x2]; 9525 }; 9526 9527 struct mlx5_ifc_pifr_reg_bits { 9528 u8 reserved_at_0[0x8]; 9529 u8 local_port[0x8]; 9530 u8 reserved_at_10[0x10]; 9531 9532 u8 reserved_at_20[0xe0]; 9533 9534 u8 port_filter[8][0x20]; 9535 9536 u8 port_filter_update_en[8][0x20]; 9537 }; 9538 9539 struct mlx5_ifc_pfcc_reg_bits { 9540 u8 reserved_at_0[0x8]; 9541 u8 local_port[0x8]; 9542 u8 reserved_at_10[0xb]; 9543 u8 ppan_mask_n[0x1]; 9544 u8 minor_stall_mask[0x1]; 9545 u8 critical_stall_mask[0x1]; 9546 u8 reserved_at_1e[0x2]; 9547 9548 u8 ppan[0x4]; 9549 u8 reserved_at_24[0x4]; 9550 u8 prio_mask_tx[0x8]; 9551 u8 reserved_at_30[0x8]; 9552 u8 prio_mask_rx[0x8]; 9553 9554 u8 pptx[0x1]; 9555 u8 aptx[0x1]; 9556 u8 pptx_mask_n[0x1]; 9557 u8 reserved_at_43[0x5]; 9558 u8 pfctx[0x8]; 9559 u8 reserved_at_50[0x10]; 9560 9561 u8 pprx[0x1]; 9562 u8 aprx[0x1]; 9563 u8 pprx_mask_n[0x1]; 9564 u8 reserved_at_63[0x5]; 9565 u8 pfcrx[0x8]; 9566 u8 reserved_at_70[0x10]; 9567 9568 u8 device_stall_minor_watermark[0x10]; 9569 u8 device_stall_critical_watermark[0x10]; 9570 9571 u8 reserved_at_a0[0x60]; 9572 }; 9573 9574 struct mlx5_ifc_pelc_reg_bits { 9575 u8 op[0x4]; 9576 u8 reserved_at_4[0x4]; 9577 u8 local_port[0x8]; 9578 u8 reserved_at_10[0x10]; 9579 9580 u8 op_admin[0x8]; 9581 u8 op_capability[0x8]; 9582 u8 op_request[0x8]; 9583 u8 op_active[0x8]; 9584 9585 u8 admin[0x40]; 9586 9587 u8 capability[0x40]; 9588 9589 u8 request[0x40]; 9590 9591 u8 active[0x40]; 9592 9593 u8 reserved_at_140[0x80]; 9594 }; 9595 9596 struct mlx5_ifc_peir_reg_bits { 9597 u8 reserved_at_0[0x8]; 9598 u8 local_port[0x8]; 9599 u8 reserved_at_10[0x10]; 9600 9601 u8 reserved_at_20[0xc]; 9602 u8 error_count[0x4]; 9603 u8 reserved_at_30[0x10]; 9604 9605 u8 reserved_at_40[0xc]; 9606 u8 lane[0x4]; 9607 u8 reserved_at_50[0x8]; 9608 u8 error_type[0x8]; 9609 }; 9610 9611 struct mlx5_ifc_mpegc_reg_bits { 9612 u8 reserved_at_0[0x30]; 9613 u8 field_select[0x10]; 9614 9615 u8 tx_overflow_sense[0x1]; 9616 u8 mark_cqe[0x1]; 9617 u8 mark_cnp[0x1]; 9618 u8 reserved_at_43[0x1b]; 9619 u8 tx_lossy_overflow_oper[0x2]; 9620 9621 u8 reserved_at_60[0x100]; 9622 }; 9623 9624 enum { 9625 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9626 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9627 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9628 }; 9629 9630 struct mlx5_ifc_mtutc_reg_bits { 9631 u8 reserved_at_0[0x1c]; 9632 u8 operation[0x4]; 9633 9634 u8 freq_adjustment[0x20]; 9635 9636 u8 reserved_at_40[0x40]; 9637 9638 u8 utc_sec[0x20]; 9639 9640 u8 reserved_at_a0[0x2]; 9641 u8 utc_nsec[0x1e]; 9642 9643 u8 time_adjustment[0x20]; 9644 }; 9645 9646 struct mlx5_ifc_pcam_enhanced_features_bits { 9647 u8 reserved_at_0[0x68]; 9648 u8 fec_50G_per_lane_in_pplm[0x1]; 9649 u8 reserved_at_69[0x4]; 9650 u8 rx_icrc_encapsulated_counter[0x1]; 9651 u8 reserved_at_6e[0x4]; 9652 u8 ptys_extended_ethernet[0x1]; 9653 u8 reserved_at_73[0x3]; 9654 u8 pfcc_mask[0x1]; 9655 u8 reserved_at_77[0x3]; 9656 u8 per_lane_error_counters[0x1]; 9657 u8 rx_buffer_fullness_counters[0x1]; 9658 u8 ptys_connector_type[0x1]; 9659 u8 reserved_at_7d[0x1]; 9660 u8 ppcnt_discard_group[0x1]; 9661 u8 ppcnt_statistical_group[0x1]; 9662 }; 9663 9664 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9665 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9666 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9667 9668 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9669 u8 pplm[0x1]; 9670 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9671 9672 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9673 u8 pbmc[0x1]; 9674 u8 pptb[0x1]; 9675 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9676 u8 ppcnt[0x1]; 9677 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9678 }; 9679 9680 struct mlx5_ifc_pcam_reg_bits { 9681 u8 reserved_at_0[0x8]; 9682 u8 feature_group[0x8]; 9683 u8 reserved_at_10[0x8]; 9684 u8 access_reg_group[0x8]; 9685 9686 u8 reserved_at_20[0x20]; 9687 9688 union { 9689 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9690 u8 reserved_at_0[0x80]; 9691 } port_access_reg_cap_mask; 9692 9693 u8 reserved_at_c0[0x80]; 9694 9695 union { 9696 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9697 u8 reserved_at_0[0x80]; 9698 } feature_cap_mask; 9699 9700 u8 reserved_at_1c0[0xc0]; 9701 }; 9702 9703 struct mlx5_ifc_mcam_enhanced_features_bits { 9704 u8 reserved_at_0[0x6b]; 9705 u8 ptpcyc2realtime_modify[0x1]; 9706 u8 reserved_at_6c[0x2]; 9707 u8 pci_status_and_power[0x1]; 9708 u8 reserved_at_6f[0x5]; 9709 u8 mark_tx_action_cnp[0x1]; 9710 u8 mark_tx_action_cqe[0x1]; 9711 u8 dynamic_tx_overflow[0x1]; 9712 u8 reserved_at_77[0x4]; 9713 u8 pcie_outbound_stalled[0x1]; 9714 u8 tx_overflow_buffer_pkt[0x1]; 9715 u8 mtpps_enh_out_per_adj[0x1]; 9716 u8 mtpps_fs[0x1]; 9717 u8 pcie_performance_group[0x1]; 9718 }; 9719 9720 struct mlx5_ifc_mcam_access_reg_bits { 9721 u8 reserved_at_0[0x1c]; 9722 u8 mcda[0x1]; 9723 u8 mcc[0x1]; 9724 u8 mcqi[0x1]; 9725 u8 mcqs[0x1]; 9726 9727 u8 regs_95_to_87[0x9]; 9728 u8 mpegc[0x1]; 9729 u8 mtutc[0x1]; 9730 u8 regs_84_to_68[0x11]; 9731 u8 tracer_registers[0x4]; 9732 9733 u8 regs_63_to_46[0x12]; 9734 u8 mrtc[0x1]; 9735 u8 regs_44_to_32[0xd]; 9736 9737 u8 regs_31_to_0[0x20]; 9738 }; 9739 9740 struct mlx5_ifc_mcam_access_reg_bits1 { 9741 u8 regs_127_to_96[0x20]; 9742 9743 u8 regs_95_to_64[0x20]; 9744 9745 u8 regs_63_to_32[0x20]; 9746 9747 u8 regs_31_to_0[0x20]; 9748 }; 9749 9750 struct mlx5_ifc_mcam_access_reg_bits2 { 9751 u8 regs_127_to_99[0x1d]; 9752 u8 mirc[0x1]; 9753 u8 regs_97_to_96[0x2]; 9754 9755 u8 regs_95_to_64[0x20]; 9756 9757 u8 regs_63_to_32[0x20]; 9758 9759 u8 regs_31_to_0[0x20]; 9760 }; 9761 9762 struct mlx5_ifc_mcam_reg_bits { 9763 u8 reserved_at_0[0x8]; 9764 u8 feature_group[0x8]; 9765 u8 reserved_at_10[0x8]; 9766 u8 access_reg_group[0x8]; 9767 9768 u8 reserved_at_20[0x20]; 9769 9770 union { 9771 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9772 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9773 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9774 u8 reserved_at_0[0x80]; 9775 } mng_access_reg_cap_mask; 9776 9777 u8 reserved_at_c0[0x80]; 9778 9779 union { 9780 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9781 u8 reserved_at_0[0x80]; 9782 } mng_feature_cap_mask; 9783 9784 u8 reserved_at_1c0[0x80]; 9785 }; 9786 9787 struct mlx5_ifc_qcam_access_reg_cap_mask { 9788 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9789 u8 qpdpm[0x1]; 9790 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9791 u8 qdpm[0x1]; 9792 u8 qpts[0x1]; 9793 u8 qcap[0x1]; 9794 u8 qcam_access_reg_cap_mask_0[0x1]; 9795 }; 9796 9797 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9798 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9799 u8 qpts_trust_both[0x1]; 9800 }; 9801 9802 struct mlx5_ifc_qcam_reg_bits { 9803 u8 reserved_at_0[0x8]; 9804 u8 feature_group[0x8]; 9805 u8 reserved_at_10[0x8]; 9806 u8 access_reg_group[0x8]; 9807 u8 reserved_at_20[0x20]; 9808 9809 union { 9810 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9811 u8 reserved_at_0[0x80]; 9812 } qos_access_reg_cap_mask; 9813 9814 u8 reserved_at_c0[0x80]; 9815 9816 union { 9817 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9818 u8 reserved_at_0[0x80]; 9819 } qos_feature_cap_mask; 9820 9821 u8 reserved_at_1c0[0x80]; 9822 }; 9823 9824 struct mlx5_ifc_core_dump_reg_bits { 9825 u8 reserved_at_0[0x18]; 9826 u8 core_dump_type[0x8]; 9827 9828 u8 reserved_at_20[0x30]; 9829 u8 vhca_id[0x10]; 9830 9831 u8 reserved_at_60[0x8]; 9832 u8 qpn[0x18]; 9833 u8 reserved_at_80[0x180]; 9834 }; 9835 9836 struct mlx5_ifc_pcap_reg_bits { 9837 u8 reserved_at_0[0x8]; 9838 u8 local_port[0x8]; 9839 u8 reserved_at_10[0x10]; 9840 9841 u8 port_capability_mask[4][0x20]; 9842 }; 9843 9844 struct mlx5_ifc_paos_reg_bits { 9845 u8 swid[0x8]; 9846 u8 local_port[0x8]; 9847 u8 reserved_at_10[0x4]; 9848 u8 admin_status[0x4]; 9849 u8 reserved_at_18[0x4]; 9850 u8 oper_status[0x4]; 9851 9852 u8 ase[0x1]; 9853 u8 ee[0x1]; 9854 u8 reserved_at_22[0x1c]; 9855 u8 e[0x2]; 9856 9857 u8 reserved_at_40[0x40]; 9858 }; 9859 9860 struct mlx5_ifc_pamp_reg_bits { 9861 u8 reserved_at_0[0x8]; 9862 u8 opamp_group[0x8]; 9863 u8 reserved_at_10[0xc]; 9864 u8 opamp_group_type[0x4]; 9865 9866 u8 start_index[0x10]; 9867 u8 reserved_at_30[0x4]; 9868 u8 num_of_indices[0xc]; 9869 9870 u8 index_data[18][0x10]; 9871 }; 9872 9873 struct mlx5_ifc_pcmr_reg_bits { 9874 u8 reserved_at_0[0x8]; 9875 u8 local_port[0x8]; 9876 u8 reserved_at_10[0x10]; 9877 9878 u8 entropy_force_cap[0x1]; 9879 u8 entropy_calc_cap[0x1]; 9880 u8 entropy_gre_calc_cap[0x1]; 9881 u8 reserved_at_23[0xf]; 9882 u8 rx_ts_over_crc_cap[0x1]; 9883 u8 reserved_at_33[0xb]; 9884 u8 fcs_cap[0x1]; 9885 u8 reserved_at_3f[0x1]; 9886 9887 u8 entropy_force[0x1]; 9888 u8 entropy_calc[0x1]; 9889 u8 entropy_gre_calc[0x1]; 9890 u8 reserved_at_43[0xf]; 9891 u8 rx_ts_over_crc[0x1]; 9892 u8 reserved_at_53[0xb]; 9893 u8 fcs_chk[0x1]; 9894 u8 reserved_at_5f[0x1]; 9895 }; 9896 9897 struct mlx5_ifc_lane_2_module_mapping_bits { 9898 u8 reserved_at_0[0x6]; 9899 u8 rx_lane[0x2]; 9900 u8 reserved_at_8[0x6]; 9901 u8 tx_lane[0x2]; 9902 u8 reserved_at_10[0x8]; 9903 u8 module[0x8]; 9904 }; 9905 9906 struct mlx5_ifc_bufferx_reg_bits { 9907 u8 reserved_at_0[0x6]; 9908 u8 lossy[0x1]; 9909 u8 epsb[0x1]; 9910 u8 reserved_at_8[0xc]; 9911 u8 size[0xc]; 9912 9913 u8 xoff_threshold[0x10]; 9914 u8 xon_threshold[0x10]; 9915 }; 9916 9917 struct mlx5_ifc_set_node_in_bits { 9918 u8 node_description[64][0x8]; 9919 }; 9920 9921 struct mlx5_ifc_register_power_settings_bits { 9922 u8 reserved_at_0[0x18]; 9923 u8 power_settings_level[0x8]; 9924 9925 u8 reserved_at_20[0x60]; 9926 }; 9927 9928 struct mlx5_ifc_register_host_endianness_bits { 9929 u8 he[0x1]; 9930 u8 reserved_at_1[0x1f]; 9931 9932 u8 reserved_at_20[0x60]; 9933 }; 9934 9935 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9936 u8 reserved_at_0[0x20]; 9937 9938 u8 mkey[0x20]; 9939 9940 u8 addressh_63_32[0x20]; 9941 9942 u8 addressl_31_0[0x20]; 9943 }; 9944 9945 struct mlx5_ifc_ud_adrs_vector_bits { 9946 u8 dc_key[0x40]; 9947 9948 u8 ext[0x1]; 9949 u8 reserved_at_41[0x7]; 9950 u8 destination_qp_dct[0x18]; 9951 9952 u8 static_rate[0x4]; 9953 u8 sl_eth_prio[0x4]; 9954 u8 fl[0x1]; 9955 u8 mlid[0x7]; 9956 u8 rlid_udp_sport[0x10]; 9957 9958 u8 reserved_at_80[0x20]; 9959 9960 u8 rmac_47_16[0x20]; 9961 9962 u8 rmac_15_0[0x10]; 9963 u8 tclass[0x8]; 9964 u8 hop_limit[0x8]; 9965 9966 u8 reserved_at_e0[0x1]; 9967 u8 grh[0x1]; 9968 u8 reserved_at_e2[0x2]; 9969 u8 src_addr_index[0x8]; 9970 u8 flow_label[0x14]; 9971 9972 u8 rgid_rip[16][0x8]; 9973 }; 9974 9975 struct mlx5_ifc_pages_req_event_bits { 9976 u8 reserved_at_0[0x10]; 9977 u8 function_id[0x10]; 9978 9979 u8 num_pages[0x20]; 9980 9981 u8 reserved_at_40[0xa0]; 9982 }; 9983 9984 struct mlx5_ifc_eqe_bits { 9985 u8 reserved_at_0[0x8]; 9986 u8 event_type[0x8]; 9987 u8 reserved_at_10[0x8]; 9988 u8 event_sub_type[0x8]; 9989 9990 u8 reserved_at_20[0xe0]; 9991 9992 union mlx5_ifc_event_auto_bits event_data; 9993 9994 u8 reserved_at_1e0[0x10]; 9995 u8 signature[0x8]; 9996 u8 reserved_at_1f8[0x7]; 9997 u8 owner[0x1]; 9998 }; 9999 10000 enum { 10001 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10002 }; 10003 10004 struct mlx5_ifc_cmd_queue_entry_bits { 10005 u8 type[0x8]; 10006 u8 reserved_at_8[0x18]; 10007 10008 u8 input_length[0x20]; 10009 10010 u8 input_mailbox_pointer_63_32[0x20]; 10011 10012 u8 input_mailbox_pointer_31_9[0x17]; 10013 u8 reserved_at_77[0x9]; 10014 10015 u8 command_input_inline_data[16][0x8]; 10016 10017 u8 command_output_inline_data[16][0x8]; 10018 10019 u8 output_mailbox_pointer_63_32[0x20]; 10020 10021 u8 output_mailbox_pointer_31_9[0x17]; 10022 u8 reserved_at_1b7[0x9]; 10023 10024 u8 output_length[0x20]; 10025 10026 u8 token[0x8]; 10027 u8 signature[0x8]; 10028 u8 reserved_at_1f0[0x8]; 10029 u8 status[0x7]; 10030 u8 ownership[0x1]; 10031 }; 10032 10033 struct mlx5_ifc_cmd_out_bits { 10034 u8 status[0x8]; 10035 u8 reserved_at_8[0x18]; 10036 10037 u8 syndrome[0x20]; 10038 10039 u8 command_output[0x20]; 10040 }; 10041 10042 struct mlx5_ifc_cmd_in_bits { 10043 u8 opcode[0x10]; 10044 u8 reserved_at_10[0x10]; 10045 10046 u8 reserved_at_20[0x10]; 10047 u8 op_mod[0x10]; 10048 10049 u8 command[][0x20]; 10050 }; 10051 10052 struct mlx5_ifc_cmd_if_box_bits { 10053 u8 mailbox_data[512][0x8]; 10054 10055 u8 reserved_at_1000[0x180]; 10056 10057 u8 next_pointer_63_32[0x20]; 10058 10059 u8 next_pointer_31_10[0x16]; 10060 u8 reserved_at_11b6[0xa]; 10061 10062 u8 block_number[0x20]; 10063 10064 u8 reserved_at_11e0[0x8]; 10065 u8 token[0x8]; 10066 u8 ctrl_signature[0x8]; 10067 u8 signature[0x8]; 10068 }; 10069 10070 struct mlx5_ifc_mtt_bits { 10071 u8 ptag_63_32[0x20]; 10072 10073 u8 ptag_31_8[0x18]; 10074 u8 reserved_at_38[0x6]; 10075 u8 wr_en[0x1]; 10076 u8 rd_en[0x1]; 10077 }; 10078 10079 struct mlx5_ifc_query_wol_rol_out_bits { 10080 u8 status[0x8]; 10081 u8 reserved_at_8[0x18]; 10082 10083 u8 syndrome[0x20]; 10084 10085 u8 reserved_at_40[0x10]; 10086 u8 rol_mode[0x8]; 10087 u8 wol_mode[0x8]; 10088 10089 u8 reserved_at_60[0x20]; 10090 }; 10091 10092 struct mlx5_ifc_query_wol_rol_in_bits { 10093 u8 opcode[0x10]; 10094 u8 reserved_at_10[0x10]; 10095 10096 u8 reserved_at_20[0x10]; 10097 u8 op_mod[0x10]; 10098 10099 u8 reserved_at_40[0x40]; 10100 }; 10101 10102 struct mlx5_ifc_set_wol_rol_out_bits { 10103 u8 status[0x8]; 10104 u8 reserved_at_8[0x18]; 10105 10106 u8 syndrome[0x20]; 10107 10108 u8 reserved_at_40[0x40]; 10109 }; 10110 10111 struct mlx5_ifc_set_wol_rol_in_bits { 10112 u8 opcode[0x10]; 10113 u8 reserved_at_10[0x10]; 10114 10115 u8 reserved_at_20[0x10]; 10116 u8 op_mod[0x10]; 10117 10118 u8 rol_mode_valid[0x1]; 10119 u8 wol_mode_valid[0x1]; 10120 u8 reserved_at_42[0xe]; 10121 u8 rol_mode[0x8]; 10122 u8 wol_mode[0x8]; 10123 10124 u8 reserved_at_60[0x20]; 10125 }; 10126 10127 enum { 10128 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10129 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10130 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10131 }; 10132 10133 enum { 10134 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10135 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10136 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10137 }; 10138 10139 enum { 10140 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10141 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10142 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10143 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10144 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10145 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10146 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10147 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10148 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10149 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10150 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10151 }; 10152 10153 struct mlx5_ifc_initial_seg_bits { 10154 u8 fw_rev_minor[0x10]; 10155 u8 fw_rev_major[0x10]; 10156 10157 u8 cmd_interface_rev[0x10]; 10158 u8 fw_rev_subminor[0x10]; 10159 10160 u8 reserved_at_40[0x40]; 10161 10162 u8 cmdq_phy_addr_63_32[0x20]; 10163 10164 u8 cmdq_phy_addr_31_12[0x14]; 10165 u8 reserved_at_b4[0x2]; 10166 u8 nic_interface[0x2]; 10167 u8 log_cmdq_size[0x4]; 10168 u8 log_cmdq_stride[0x4]; 10169 10170 u8 command_doorbell_vector[0x20]; 10171 10172 u8 reserved_at_e0[0xf00]; 10173 10174 u8 initializing[0x1]; 10175 u8 reserved_at_fe1[0x4]; 10176 u8 nic_interface_supported[0x3]; 10177 u8 embedded_cpu[0x1]; 10178 u8 reserved_at_fe9[0x17]; 10179 10180 struct mlx5_ifc_health_buffer_bits health_buffer; 10181 10182 u8 no_dram_nic_offset[0x20]; 10183 10184 u8 reserved_at_1220[0x6e40]; 10185 10186 u8 reserved_at_8060[0x1f]; 10187 u8 clear_int[0x1]; 10188 10189 u8 health_syndrome[0x8]; 10190 u8 health_counter[0x18]; 10191 10192 u8 reserved_at_80a0[0x17fc0]; 10193 }; 10194 10195 struct mlx5_ifc_mtpps_reg_bits { 10196 u8 reserved_at_0[0xc]; 10197 u8 cap_number_of_pps_pins[0x4]; 10198 u8 reserved_at_10[0x4]; 10199 u8 cap_max_num_of_pps_in_pins[0x4]; 10200 u8 reserved_at_18[0x4]; 10201 u8 cap_max_num_of_pps_out_pins[0x4]; 10202 10203 u8 reserved_at_20[0x24]; 10204 u8 cap_pin_3_mode[0x4]; 10205 u8 reserved_at_48[0x4]; 10206 u8 cap_pin_2_mode[0x4]; 10207 u8 reserved_at_50[0x4]; 10208 u8 cap_pin_1_mode[0x4]; 10209 u8 reserved_at_58[0x4]; 10210 u8 cap_pin_0_mode[0x4]; 10211 10212 u8 reserved_at_60[0x4]; 10213 u8 cap_pin_7_mode[0x4]; 10214 u8 reserved_at_68[0x4]; 10215 u8 cap_pin_6_mode[0x4]; 10216 u8 reserved_at_70[0x4]; 10217 u8 cap_pin_5_mode[0x4]; 10218 u8 reserved_at_78[0x4]; 10219 u8 cap_pin_4_mode[0x4]; 10220 10221 u8 field_select[0x20]; 10222 u8 reserved_at_a0[0x60]; 10223 10224 u8 enable[0x1]; 10225 u8 reserved_at_101[0xb]; 10226 u8 pattern[0x4]; 10227 u8 reserved_at_110[0x4]; 10228 u8 pin_mode[0x4]; 10229 u8 pin[0x8]; 10230 10231 u8 reserved_at_120[0x20]; 10232 10233 u8 time_stamp[0x40]; 10234 10235 u8 out_pulse_duration[0x10]; 10236 u8 out_periodic_adjustment[0x10]; 10237 u8 enhanced_out_periodic_adjustment[0x20]; 10238 10239 u8 reserved_at_1c0[0x20]; 10240 }; 10241 10242 struct mlx5_ifc_mtppse_reg_bits { 10243 u8 reserved_at_0[0x18]; 10244 u8 pin[0x8]; 10245 u8 event_arm[0x1]; 10246 u8 reserved_at_21[0x1b]; 10247 u8 event_generation_mode[0x4]; 10248 u8 reserved_at_40[0x40]; 10249 }; 10250 10251 struct mlx5_ifc_mcqs_reg_bits { 10252 u8 last_index_flag[0x1]; 10253 u8 reserved_at_1[0x7]; 10254 u8 fw_device[0x8]; 10255 u8 component_index[0x10]; 10256 10257 u8 reserved_at_20[0x10]; 10258 u8 identifier[0x10]; 10259 10260 u8 reserved_at_40[0x17]; 10261 u8 component_status[0x5]; 10262 u8 component_update_state[0x4]; 10263 10264 u8 last_update_state_changer_type[0x4]; 10265 u8 last_update_state_changer_host_id[0x4]; 10266 u8 reserved_at_68[0x18]; 10267 }; 10268 10269 struct mlx5_ifc_mcqi_cap_bits { 10270 u8 supported_info_bitmask[0x20]; 10271 10272 u8 component_size[0x20]; 10273 10274 u8 max_component_size[0x20]; 10275 10276 u8 log_mcda_word_size[0x4]; 10277 u8 reserved_at_64[0xc]; 10278 u8 mcda_max_write_size[0x10]; 10279 10280 u8 rd_en[0x1]; 10281 u8 reserved_at_81[0x1]; 10282 u8 match_chip_id[0x1]; 10283 u8 match_psid[0x1]; 10284 u8 check_user_timestamp[0x1]; 10285 u8 match_base_guid_mac[0x1]; 10286 u8 reserved_at_86[0x1a]; 10287 }; 10288 10289 struct mlx5_ifc_mcqi_version_bits { 10290 u8 reserved_at_0[0x2]; 10291 u8 build_time_valid[0x1]; 10292 u8 user_defined_time_valid[0x1]; 10293 u8 reserved_at_4[0x14]; 10294 u8 version_string_length[0x8]; 10295 10296 u8 version[0x20]; 10297 10298 u8 build_time[0x40]; 10299 10300 u8 user_defined_time[0x40]; 10301 10302 u8 build_tool_version[0x20]; 10303 10304 u8 reserved_at_e0[0x20]; 10305 10306 u8 version_string[92][0x8]; 10307 }; 10308 10309 struct mlx5_ifc_mcqi_activation_method_bits { 10310 u8 pending_server_ac_power_cycle[0x1]; 10311 u8 pending_server_dc_power_cycle[0x1]; 10312 u8 pending_server_reboot[0x1]; 10313 u8 pending_fw_reset[0x1]; 10314 u8 auto_activate[0x1]; 10315 u8 all_hosts_sync[0x1]; 10316 u8 device_hw_reset[0x1]; 10317 u8 reserved_at_7[0x19]; 10318 }; 10319 10320 union mlx5_ifc_mcqi_reg_data_bits { 10321 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10322 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10323 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10324 }; 10325 10326 struct mlx5_ifc_mcqi_reg_bits { 10327 u8 read_pending_component[0x1]; 10328 u8 reserved_at_1[0xf]; 10329 u8 component_index[0x10]; 10330 10331 u8 reserved_at_20[0x20]; 10332 10333 u8 reserved_at_40[0x1b]; 10334 u8 info_type[0x5]; 10335 10336 u8 info_size[0x20]; 10337 10338 u8 offset[0x20]; 10339 10340 u8 reserved_at_a0[0x10]; 10341 u8 data_size[0x10]; 10342 10343 union mlx5_ifc_mcqi_reg_data_bits data[]; 10344 }; 10345 10346 struct mlx5_ifc_mcc_reg_bits { 10347 u8 reserved_at_0[0x4]; 10348 u8 time_elapsed_since_last_cmd[0xc]; 10349 u8 reserved_at_10[0x8]; 10350 u8 instruction[0x8]; 10351 10352 u8 reserved_at_20[0x10]; 10353 u8 component_index[0x10]; 10354 10355 u8 reserved_at_40[0x8]; 10356 u8 update_handle[0x18]; 10357 10358 u8 handle_owner_type[0x4]; 10359 u8 handle_owner_host_id[0x4]; 10360 u8 reserved_at_68[0x1]; 10361 u8 control_progress[0x7]; 10362 u8 error_code[0x8]; 10363 u8 reserved_at_78[0x4]; 10364 u8 control_state[0x4]; 10365 10366 u8 component_size[0x20]; 10367 10368 u8 reserved_at_a0[0x60]; 10369 }; 10370 10371 struct mlx5_ifc_mcda_reg_bits { 10372 u8 reserved_at_0[0x8]; 10373 u8 update_handle[0x18]; 10374 10375 u8 offset[0x20]; 10376 10377 u8 reserved_at_40[0x10]; 10378 u8 size[0x10]; 10379 10380 u8 reserved_at_60[0x20]; 10381 10382 u8 data[][0x20]; 10383 }; 10384 10385 enum { 10386 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10387 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10388 }; 10389 10390 enum { 10391 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10392 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10393 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10394 }; 10395 10396 struct mlx5_ifc_mfrl_reg_bits { 10397 u8 reserved_at_0[0x20]; 10398 10399 u8 reserved_at_20[0x2]; 10400 u8 pci_sync_for_fw_update_start[0x1]; 10401 u8 pci_sync_for_fw_update_resp[0x2]; 10402 u8 rst_type_sel[0x3]; 10403 u8 reserved_at_28[0x8]; 10404 u8 reset_type[0x8]; 10405 u8 reset_level[0x8]; 10406 }; 10407 10408 struct mlx5_ifc_mirc_reg_bits { 10409 u8 reserved_at_0[0x18]; 10410 u8 status_code[0x8]; 10411 10412 u8 reserved_at_20[0x20]; 10413 }; 10414 10415 struct mlx5_ifc_pddr_monitor_opcode_bits { 10416 u8 reserved_at_0[0x10]; 10417 u8 monitor_opcode[0x10]; 10418 }; 10419 10420 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10421 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10422 u8 reserved_at_0[0x20]; 10423 }; 10424 10425 enum { 10426 /* Monitor opcodes */ 10427 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10428 }; 10429 10430 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10431 u8 reserved_at_0[0x10]; 10432 u8 group_opcode[0x10]; 10433 10434 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10435 10436 u8 reserved_at_40[0x20]; 10437 10438 u8 status_message[59][0x20]; 10439 }; 10440 10441 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10442 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10443 u8 reserved_at_0[0x7c0]; 10444 }; 10445 10446 enum { 10447 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10448 }; 10449 10450 struct mlx5_ifc_pddr_reg_bits { 10451 u8 reserved_at_0[0x8]; 10452 u8 local_port[0x8]; 10453 u8 pnat[0x2]; 10454 u8 reserved_at_12[0xe]; 10455 10456 u8 reserved_at_20[0x18]; 10457 u8 page_select[0x8]; 10458 10459 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10460 }; 10461 10462 struct mlx5_ifc_mrtc_reg_bits { 10463 u8 time_synced[0x1]; 10464 u8 reserved_at_1[0x1f]; 10465 10466 u8 reserved_at_20[0x20]; 10467 10468 u8 time_h[0x20]; 10469 10470 u8 time_l[0x20]; 10471 }; 10472 10473 union mlx5_ifc_ports_control_registers_document_bits { 10474 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10475 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10476 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10477 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10478 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10479 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10480 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10481 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10482 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10483 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10484 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10485 struct mlx5_ifc_paos_reg_bits paos_reg; 10486 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10487 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10488 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10489 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10490 struct mlx5_ifc_peir_reg_bits peir_reg; 10491 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10492 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10493 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10494 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10495 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10496 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10497 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10498 struct mlx5_ifc_plib_reg_bits plib_reg; 10499 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10500 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10501 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10502 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10503 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10504 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10505 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10506 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10507 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10508 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10509 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10510 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10511 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10512 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10513 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10514 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10515 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10516 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10517 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10518 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10519 struct mlx5_ifc_pude_reg_bits pude_reg; 10520 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10521 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10522 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10523 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10524 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10525 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10526 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10527 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10528 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10529 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10530 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10531 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10532 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10533 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10534 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10535 u8 reserved_at_0[0x60e0]; 10536 }; 10537 10538 union mlx5_ifc_debug_enhancements_document_bits { 10539 struct mlx5_ifc_health_buffer_bits health_buffer; 10540 u8 reserved_at_0[0x200]; 10541 }; 10542 10543 union mlx5_ifc_uplink_pci_interface_document_bits { 10544 struct mlx5_ifc_initial_seg_bits initial_seg; 10545 u8 reserved_at_0[0x20060]; 10546 }; 10547 10548 struct mlx5_ifc_set_flow_table_root_out_bits { 10549 u8 status[0x8]; 10550 u8 reserved_at_8[0x18]; 10551 10552 u8 syndrome[0x20]; 10553 10554 u8 reserved_at_40[0x40]; 10555 }; 10556 10557 struct mlx5_ifc_set_flow_table_root_in_bits { 10558 u8 opcode[0x10]; 10559 u8 reserved_at_10[0x10]; 10560 10561 u8 reserved_at_20[0x10]; 10562 u8 op_mod[0x10]; 10563 10564 u8 other_vport[0x1]; 10565 u8 reserved_at_41[0xf]; 10566 u8 vport_number[0x10]; 10567 10568 u8 reserved_at_60[0x20]; 10569 10570 u8 table_type[0x8]; 10571 u8 reserved_at_88[0x7]; 10572 u8 table_of_other_vport[0x1]; 10573 u8 table_vport_number[0x10]; 10574 10575 u8 reserved_at_a0[0x8]; 10576 u8 table_id[0x18]; 10577 10578 u8 reserved_at_c0[0x8]; 10579 u8 underlay_qpn[0x18]; 10580 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10581 u8 reserved_at_e1[0xf]; 10582 u8 table_eswitch_owner_vhca_id[0x10]; 10583 u8 reserved_at_100[0x100]; 10584 }; 10585 10586 enum { 10587 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10588 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10589 }; 10590 10591 struct mlx5_ifc_modify_flow_table_out_bits { 10592 u8 status[0x8]; 10593 u8 reserved_at_8[0x18]; 10594 10595 u8 syndrome[0x20]; 10596 10597 u8 reserved_at_40[0x40]; 10598 }; 10599 10600 struct mlx5_ifc_modify_flow_table_in_bits { 10601 u8 opcode[0x10]; 10602 u8 reserved_at_10[0x10]; 10603 10604 u8 reserved_at_20[0x10]; 10605 u8 op_mod[0x10]; 10606 10607 u8 other_vport[0x1]; 10608 u8 reserved_at_41[0xf]; 10609 u8 vport_number[0x10]; 10610 10611 u8 reserved_at_60[0x10]; 10612 u8 modify_field_select[0x10]; 10613 10614 u8 table_type[0x8]; 10615 u8 reserved_at_88[0x18]; 10616 10617 u8 reserved_at_a0[0x8]; 10618 u8 table_id[0x18]; 10619 10620 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10621 }; 10622 10623 struct mlx5_ifc_ets_tcn_config_reg_bits { 10624 u8 g[0x1]; 10625 u8 b[0x1]; 10626 u8 r[0x1]; 10627 u8 reserved_at_3[0x9]; 10628 u8 group[0x4]; 10629 u8 reserved_at_10[0x9]; 10630 u8 bw_allocation[0x7]; 10631 10632 u8 reserved_at_20[0xc]; 10633 u8 max_bw_units[0x4]; 10634 u8 reserved_at_30[0x8]; 10635 u8 max_bw_value[0x8]; 10636 }; 10637 10638 struct mlx5_ifc_ets_global_config_reg_bits { 10639 u8 reserved_at_0[0x2]; 10640 u8 r[0x1]; 10641 u8 reserved_at_3[0x1d]; 10642 10643 u8 reserved_at_20[0xc]; 10644 u8 max_bw_units[0x4]; 10645 u8 reserved_at_30[0x8]; 10646 u8 max_bw_value[0x8]; 10647 }; 10648 10649 struct mlx5_ifc_qetc_reg_bits { 10650 u8 reserved_at_0[0x8]; 10651 u8 port_number[0x8]; 10652 u8 reserved_at_10[0x30]; 10653 10654 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10655 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10656 }; 10657 10658 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10659 u8 e[0x1]; 10660 u8 reserved_at_01[0x0b]; 10661 u8 prio[0x04]; 10662 }; 10663 10664 struct mlx5_ifc_qpdpm_reg_bits { 10665 u8 reserved_at_0[0x8]; 10666 u8 local_port[0x8]; 10667 u8 reserved_at_10[0x10]; 10668 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10669 }; 10670 10671 struct mlx5_ifc_qpts_reg_bits { 10672 u8 reserved_at_0[0x8]; 10673 u8 local_port[0x8]; 10674 u8 reserved_at_10[0x2d]; 10675 u8 trust_state[0x3]; 10676 }; 10677 10678 struct mlx5_ifc_pptb_reg_bits { 10679 u8 reserved_at_0[0x2]; 10680 u8 mm[0x2]; 10681 u8 reserved_at_4[0x4]; 10682 u8 local_port[0x8]; 10683 u8 reserved_at_10[0x6]; 10684 u8 cm[0x1]; 10685 u8 um[0x1]; 10686 u8 pm[0x8]; 10687 10688 u8 prio_x_buff[0x20]; 10689 10690 u8 pm_msb[0x8]; 10691 u8 reserved_at_48[0x10]; 10692 u8 ctrl_buff[0x4]; 10693 u8 untagged_buff[0x4]; 10694 }; 10695 10696 struct mlx5_ifc_sbcam_reg_bits { 10697 u8 reserved_at_0[0x8]; 10698 u8 feature_group[0x8]; 10699 u8 reserved_at_10[0x8]; 10700 u8 access_reg_group[0x8]; 10701 10702 u8 reserved_at_20[0x20]; 10703 10704 u8 sb_access_reg_cap_mask[4][0x20]; 10705 10706 u8 reserved_at_c0[0x80]; 10707 10708 u8 sb_feature_cap_mask[4][0x20]; 10709 10710 u8 reserved_at_1c0[0x40]; 10711 10712 u8 cap_total_buffer_size[0x20]; 10713 10714 u8 cap_cell_size[0x10]; 10715 u8 cap_max_pg_buffers[0x8]; 10716 u8 cap_num_pool_supported[0x8]; 10717 10718 u8 reserved_at_240[0x8]; 10719 u8 cap_sbsr_stat_size[0x8]; 10720 u8 cap_max_tclass_data[0x8]; 10721 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10722 }; 10723 10724 struct mlx5_ifc_pbmc_reg_bits { 10725 u8 reserved_at_0[0x8]; 10726 u8 local_port[0x8]; 10727 u8 reserved_at_10[0x10]; 10728 10729 u8 xoff_timer_value[0x10]; 10730 u8 xoff_refresh[0x10]; 10731 10732 u8 reserved_at_40[0x9]; 10733 u8 fullness_threshold[0x7]; 10734 u8 port_buffer_size[0x10]; 10735 10736 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10737 10738 u8 reserved_at_2e0[0x80]; 10739 }; 10740 10741 struct mlx5_ifc_qtct_reg_bits { 10742 u8 reserved_at_0[0x8]; 10743 u8 port_number[0x8]; 10744 u8 reserved_at_10[0xd]; 10745 u8 prio[0x3]; 10746 10747 u8 reserved_at_20[0x1d]; 10748 u8 tclass[0x3]; 10749 }; 10750 10751 struct mlx5_ifc_mcia_reg_bits { 10752 u8 l[0x1]; 10753 u8 reserved_at_1[0x7]; 10754 u8 module[0x8]; 10755 u8 reserved_at_10[0x8]; 10756 u8 status[0x8]; 10757 10758 u8 i2c_device_address[0x8]; 10759 u8 page_number[0x8]; 10760 u8 device_address[0x10]; 10761 10762 u8 reserved_at_40[0x10]; 10763 u8 size[0x10]; 10764 10765 u8 reserved_at_60[0x20]; 10766 10767 u8 dword_0[0x20]; 10768 u8 dword_1[0x20]; 10769 u8 dword_2[0x20]; 10770 u8 dword_3[0x20]; 10771 u8 dword_4[0x20]; 10772 u8 dword_5[0x20]; 10773 u8 dword_6[0x20]; 10774 u8 dword_7[0x20]; 10775 u8 dword_8[0x20]; 10776 u8 dword_9[0x20]; 10777 u8 dword_10[0x20]; 10778 u8 dword_11[0x20]; 10779 }; 10780 10781 struct mlx5_ifc_dcbx_param_bits { 10782 u8 dcbx_cee_cap[0x1]; 10783 u8 dcbx_ieee_cap[0x1]; 10784 u8 dcbx_standby_cap[0x1]; 10785 u8 reserved_at_3[0x5]; 10786 u8 port_number[0x8]; 10787 u8 reserved_at_10[0xa]; 10788 u8 max_application_table_size[6]; 10789 u8 reserved_at_20[0x15]; 10790 u8 version_oper[0x3]; 10791 u8 reserved_at_38[5]; 10792 u8 version_admin[0x3]; 10793 u8 willing_admin[0x1]; 10794 u8 reserved_at_41[0x3]; 10795 u8 pfc_cap_oper[0x4]; 10796 u8 reserved_at_48[0x4]; 10797 u8 pfc_cap_admin[0x4]; 10798 u8 reserved_at_50[0x4]; 10799 u8 num_of_tc_oper[0x4]; 10800 u8 reserved_at_58[0x4]; 10801 u8 num_of_tc_admin[0x4]; 10802 u8 remote_willing[0x1]; 10803 u8 reserved_at_61[3]; 10804 u8 remote_pfc_cap[4]; 10805 u8 reserved_at_68[0x14]; 10806 u8 remote_num_of_tc[0x4]; 10807 u8 reserved_at_80[0x18]; 10808 u8 error[0x8]; 10809 u8 reserved_at_a0[0x160]; 10810 }; 10811 10812 enum { 10813 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10814 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT, 10815 }; 10816 10817 struct mlx5_ifc_lagc_bits { 10818 u8 fdb_selection_mode[0x1]; 10819 u8 reserved_at_1[0x14]; 10820 u8 port_select_mode[0x3]; 10821 u8 reserved_at_18[0x5]; 10822 u8 lag_state[0x3]; 10823 10824 u8 reserved_at_20[0x14]; 10825 u8 tx_remap_affinity_2[0x4]; 10826 u8 reserved_at_38[0x4]; 10827 u8 tx_remap_affinity_1[0x4]; 10828 }; 10829 10830 struct mlx5_ifc_create_lag_out_bits { 10831 u8 status[0x8]; 10832 u8 reserved_at_8[0x18]; 10833 10834 u8 syndrome[0x20]; 10835 10836 u8 reserved_at_40[0x40]; 10837 }; 10838 10839 struct mlx5_ifc_create_lag_in_bits { 10840 u8 opcode[0x10]; 10841 u8 reserved_at_10[0x10]; 10842 10843 u8 reserved_at_20[0x10]; 10844 u8 op_mod[0x10]; 10845 10846 struct mlx5_ifc_lagc_bits ctx; 10847 }; 10848 10849 struct mlx5_ifc_modify_lag_out_bits { 10850 u8 status[0x8]; 10851 u8 reserved_at_8[0x18]; 10852 10853 u8 syndrome[0x20]; 10854 10855 u8 reserved_at_40[0x40]; 10856 }; 10857 10858 struct mlx5_ifc_modify_lag_in_bits { 10859 u8 opcode[0x10]; 10860 u8 reserved_at_10[0x10]; 10861 10862 u8 reserved_at_20[0x10]; 10863 u8 op_mod[0x10]; 10864 10865 u8 reserved_at_40[0x20]; 10866 u8 field_select[0x20]; 10867 10868 struct mlx5_ifc_lagc_bits ctx; 10869 }; 10870 10871 struct mlx5_ifc_query_lag_out_bits { 10872 u8 status[0x8]; 10873 u8 reserved_at_8[0x18]; 10874 10875 u8 syndrome[0x20]; 10876 10877 struct mlx5_ifc_lagc_bits ctx; 10878 }; 10879 10880 struct mlx5_ifc_query_lag_in_bits { 10881 u8 opcode[0x10]; 10882 u8 reserved_at_10[0x10]; 10883 10884 u8 reserved_at_20[0x10]; 10885 u8 op_mod[0x10]; 10886 10887 u8 reserved_at_40[0x40]; 10888 }; 10889 10890 struct mlx5_ifc_destroy_lag_out_bits { 10891 u8 status[0x8]; 10892 u8 reserved_at_8[0x18]; 10893 10894 u8 syndrome[0x20]; 10895 10896 u8 reserved_at_40[0x40]; 10897 }; 10898 10899 struct mlx5_ifc_destroy_lag_in_bits { 10900 u8 opcode[0x10]; 10901 u8 reserved_at_10[0x10]; 10902 10903 u8 reserved_at_20[0x10]; 10904 u8 op_mod[0x10]; 10905 10906 u8 reserved_at_40[0x40]; 10907 }; 10908 10909 struct mlx5_ifc_create_vport_lag_out_bits { 10910 u8 status[0x8]; 10911 u8 reserved_at_8[0x18]; 10912 10913 u8 syndrome[0x20]; 10914 10915 u8 reserved_at_40[0x40]; 10916 }; 10917 10918 struct mlx5_ifc_create_vport_lag_in_bits { 10919 u8 opcode[0x10]; 10920 u8 reserved_at_10[0x10]; 10921 10922 u8 reserved_at_20[0x10]; 10923 u8 op_mod[0x10]; 10924 10925 u8 reserved_at_40[0x40]; 10926 }; 10927 10928 struct mlx5_ifc_destroy_vport_lag_out_bits { 10929 u8 status[0x8]; 10930 u8 reserved_at_8[0x18]; 10931 10932 u8 syndrome[0x20]; 10933 10934 u8 reserved_at_40[0x40]; 10935 }; 10936 10937 struct mlx5_ifc_destroy_vport_lag_in_bits { 10938 u8 opcode[0x10]; 10939 u8 reserved_at_10[0x10]; 10940 10941 u8 reserved_at_20[0x10]; 10942 u8 op_mod[0x10]; 10943 10944 u8 reserved_at_40[0x40]; 10945 }; 10946 10947 enum { 10948 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 10949 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 10950 }; 10951 10952 struct mlx5_ifc_modify_memic_in_bits { 10953 u8 opcode[0x10]; 10954 u8 uid[0x10]; 10955 10956 u8 reserved_at_20[0x10]; 10957 u8 op_mod[0x10]; 10958 10959 u8 reserved_at_40[0x20]; 10960 10961 u8 reserved_at_60[0x18]; 10962 u8 memic_operation_type[0x8]; 10963 10964 u8 memic_start_addr[0x40]; 10965 10966 u8 reserved_at_c0[0x140]; 10967 }; 10968 10969 struct mlx5_ifc_modify_memic_out_bits { 10970 u8 status[0x8]; 10971 u8 reserved_at_8[0x18]; 10972 10973 u8 syndrome[0x20]; 10974 10975 u8 reserved_at_40[0x40]; 10976 10977 u8 memic_operation_addr[0x40]; 10978 10979 u8 reserved_at_c0[0x140]; 10980 }; 10981 10982 struct mlx5_ifc_alloc_memic_in_bits { 10983 u8 opcode[0x10]; 10984 u8 reserved_at_10[0x10]; 10985 10986 u8 reserved_at_20[0x10]; 10987 u8 op_mod[0x10]; 10988 10989 u8 reserved_at_30[0x20]; 10990 10991 u8 reserved_at_40[0x18]; 10992 u8 log_memic_addr_alignment[0x8]; 10993 10994 u8 range_start_addr[0x40]; 10995 10996 u8 range_size[0x20]; 10997 10998 u8 memic_size[0x20]; 10999 }; 11000 11001 struct mlx5_ifc_alloc_memic_out_bits { 11002 u8 status[0x8]; 11003 u8 reserved_at_8[0x18]; 11004 11005 u8 syndrome[0x20]; 11006 11007 u8 memic_start_addr[0x40]; 11008 }; 11009 11010 struct mlx5_ifc_dealloc_memic_in_bits { 11011 u8 opcode[0x10]; 11012 u8 reserved_at_10[0x10]; 11013 11014 u8 reserved_at_20[0x10]; 11015 u8 op_mod[0x10]; 11016 11017 u8 reserved_at_40[0x40]; 11018 11019 u8 memic_start_addr[0x40]; 11020 11021 u8 memic_size[0x20]; 11022 11023 u8 reserved_at_e0[0x20]; 11024 }; 11025 11026 struct mlx5_ifc_dealloc_memic_out_bits { 11027 u8 status[0x8]; 11028 u8 reserved_at_8[0x18]; 11029 11030 u8 syndrome[0x20]; 11031 11032 u8 reserved_at_40[0x40]; 11033 }; 11034 11035 struct mlx5_ifc_umem_bits { 11036 u8 reserved_at_0[0x80]; 11037 11038 u8 reserved_at_80[0x1b]; 11039 u8 log_page_size[0x5]; 11040 11041 u8 page_offset[0x20]; 11042 11043 u8 num_of_mtt[0x40]; 11044 11045 struct mlx5_ifc_mtt_bits mtt[]; 11046 }; 11047 11048 struct mlx5_ifc_uctx_bits { 11049 u8 cap[0x20]; 11050 11051 u8 reserved_at_20[0x160]; 11052 }; 11053 11054 struct mlx5_ifc_sw_icm_bits { 11055 u8 modify_field_select[0x40]; 11056 11057 u8 reserved_at_40[0x18]; 11058 u8 log_sw_icm_size[0x8]; 11059 11060 u8 reserved_at_60[0x20]; 11061 11062 u8 sw_icm_start_addr[0x40]; 11063 11064 u8 reserved_at_c0[0x140]; 11065 }; 11066 11067 struct mlx5_ifc_geneve_tlv_option_bits { 11068 u8 modify_field_select[0x40]; 11069 11070 u8 reserved_at_40[0x18]; 11071 u8 geneve_option_fte_index[0x8]; 11072 11073 u8 option_class[0x10]; 11074 u8 option_type[0x8]; 11075 u8 reserved_at_78[0x3]; 11076 u8 option_data_length[0x5]; 11077 11078 u8 reserved_at_80[0x180]; 11079 }; 11080 11081 struct mlx5_ifc_create_umem_in_bits { 11082 u8 opcode[0x10]; 11083 u8 uid[0x10]; 11084 11085 u8 reserved_at_20[0x10]; 11086 u8 op_mod[0x10]; 11087 11088 u8 reserved_at_40[0x40]; 11089 11090 struct mlx5_ifc_umem_bits umem; 11091 }; 11092 11093 struct mlx5_ifc_create_umem_out_bits { 11094 u8 status[0x8]; 11095 u8 reserved_at_8[0x18]; 11096 11097 u8 syndrome[0x20]; 11098 11099 u8 reserved_at_40[0x8]; 11100 u8 umem_id[0x18]; 11101 11102 u8 reserved_at_60[0x20]; 11103 }; 11104 11105 struct mlx5_ifc_destroy_umem_in_bits { 11106 u8 opcode[0x10]; 11107 u8 uid[0x10]; 11108 11109 u8 reserved_at_20[0x10]; 11110 u8 op_mod[0x10]; 11111 11112 u8 reserved_at_40[0x8]; 11113 u8 umem_id[0x18]; 11114 11115 u8 reserved_at_60[0x20]; 11116 }; 11117 11118 struct mlx5_ifc_destroy_umem_out_bits { 11119 u8 status[0x8]; 11120 u8 reserved_at_8[0x18]; 11121 11122 u8 syndrome[0x20]; 11123 11124 u8 reserved_at_40[0x40]; 11125 }; 11126 11127 struct mlx5_ifc_create_uctx_in_bits { 11128 u8 opcode[0x10]; 11129 u8 reserved_at_10[0x10]; 11130 11131 u8 reserved_at_20[0x10]; 11132 u8 op_mod[0x10]; 11133 11134 u8 reserved_at_40[0x40]; 11135 11136 struct mlx5_ifc_uctx_bits uctx; 11137 }; 11138 11139 struct mlx5_ifc_create_uctx_out_bits { 11140 u8 status[0x8]; 11141 u8 reserved_at_8[0x18]; 11142 11143 u8 syndrome[0x20]; 11144 11145 u8 reserved_at_40[0x10]; 11146 u8 uid[0x10]; 11147 11148 u8 reserved_at_60[0x20]; 11149 }; 11150 11151 struct mlx5_ifc_destroy_uctx_in_bits { 11152 u8 opcode[0x10]; 11153 u8 reserved_at_10[0x10]; 11154 11155 u8 reserved_at_20[0x10]; 11156 u8 op_mod[0x10]; 11157 11158 u8 reserved_at_40[0x10]; 11159 u8 uid[0x10]; 11160 11161 u8 reserved_at_60[0x20]; 11162 }; 11163 11164 struct mlx5_ifc_destroy_uctx_out_bits { 11165 u8 status[0x8]; 11166 u8 reserved_at_8[0x18]; 11167 11168 u8 syndrome[0x20]; 11169 11170 u8 reserved_at_40[0x40]; 11171 }; 11172 11173 struct mlx5_ifc_create_sw_icm_in_bits { 11174 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11175 struct mlx5_ifc_sw_icm_bits sw_icm; 11176 }; 11177 11178 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11179 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11180 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11181 }; 11182 11183 struct mlx5_ifc_mtrc_string_db_param_bits { 11184 u8 string_db_base_address[0x20]; 11185 11186 u8 reserved_at_20[0x8]; 11187 u8 string_db_size[0x18]; 11188 }; 11189 11190 struct mlx5_ifc_mtrc_cap_bits { 11191 u8 trace_owner[0x1]; 11192 u8 trace_to_memory[0x1]; 11193 u8 reserved_at_2[0x4]; 11194 u8 trc_ver[0x2]; 11195 u8 reserved_at_8[0x14]; 11196 u8 num_string_db[0x4]; 11197 11198 u8 first_string_trace[0x8]; 11199 u8 num_string_trace[0x8]; 11200 u8 reserved_at_30[0x28]; 11201 11202 u8 log_max_trace_buffer_size[0x8]; 11203 11204 u8 reserved_at_60[0x20]; 11205 11206 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11207 11208 u8 reserved_at_280[0x180]; 11209 }; 11210 11211 struct mlx5_ifc_mtrc_conf_bits { 11212 u8 reserved_at_0[0x1c]; 11213 u8 trace_mode[0x4]; 11214 u8 reserved_at_20[0x18]; 11215 u8 log_trace_buffer_size[0x8]; 11216 u8 trace_mkey[0x20]; 11217 u8 reserved_at_60[0x3a0]; 11218 }; 11219 11220 struct mlx5_ifc_mtrc_stdb_bits { 11221 u8 string_db_index[0x4]; 11222 u8 reserved_at_4[0x4]; 11223 u8 read_size[0x18]; 11224 u8 start_offset[0x20]; 11225 u8 string_db_data[]; 11226 }; 11227 11228 struct mlx5_ifc_mtrc_ctrl_bits { 11229 u8 trace_status[0x2]; 11230 u8 reserved_at_2[0x2]; 11231 u8 arm_event[0x1]; 11232 u8 reserved_at_5[0xb]; 11233 u8 modify_field_select[0x10]; 11234 u8 reserved_at_20[0x2b]; 11235 u8 current_timestamp52_32[0x15]; 11236 u8 current_timestamp31_0[0x20]; 11237 u8 reserved_at_80[0x180]; 11238 }; 11239 11240 struct mlx5_ifc_host_params_context_bits { 11241 u8 host_number[0x8]; 11242 u8 reserved_at_8[0x7]; 11243 u8 host_pf_disabled[0x1]; 11244 u8 host_num_of_vfs[0x10]; 11245 11246 u8 host_total_vfs[0x10]; 11247 u8 host_pci_bus[0x10]; 11248 11249 u8 reserved_at_40[0x10]; 11250 u8 host_pci_device[0x10]; 11251 11252 u8 reserved_at_60[0x10]; 11253 u8 host_pci_function[0x10]; 11254 11255 u8 reserved_at_80[0x180]; 11256 }; 11257 11258 struct mlx5_ifc_query_esw_functions_in_bits { 11259 u8 opcode[0x10]; 11260 u8 reserved_at_10[0x10]; 11261 11262 u8 reserved_at_20[0x10]; 11263 u8 op_mod[0x10]; 11264 11265 u8 reserved_at_40[0x40]; 11266 }; 11267 11268 struct mlx5_ifc_query_esw_functions_out_bits { 11269 u8 status[0x8]; 11270 u8 reserved_at_8[0x18]; 11271 11272 u8 syndrome[0x20]; 11273 11274 u8 reserved_at_40[0x40]; 11275 11276 struct mlx5_ifc_host_params_context_bits host_params_context; 11277 11278 u8 reserved_at_280[0x180]; 11279 u8 host_sf_enable[][0x40]; 11280 }; 11281 11282 struct mlx5_ifc_sf_partition_bits { 11283 u8 reserved_at_0[0x10]; 11284 u8 log_num_sf[0x8]; 11285 u8 log_sf_bar_size[0x8]; 11286 }; 11287 11288 struct mlx5_ifc_query_sf_partitions_out_bits { 11289 u8 status[0x8]; 11290 u8 reserved_at_8[0x18]; 11291 11292 u8 syndrome[0x20]; 11293 11294 u8 reserved_at_40[0x18]; 11295 u8 num_sf_partitions[0x8]; 11296 11297 u8 reserved_at_60[0x20]; 11298 11299 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11300 }; 11301 11302 struct mlx5_ifc_query_sf_partitions_in_bits { 11303 u8 opcode[0x10]; 11304 u8 reserved_at_10[0x10]; 11305 11306 u8 reserved_at_20[0x10]; 11307 u8 op_mod[0x10]; 11308 11309 u8 reserved_at_40[0x40]; 11310 }; 11311 11312 struct mlx5_ifc_dealloc_sf_out_bits { 11313 u8 status[0x8]; 11314 u8 reserved_at_8[0x18]; 11315 11316 u8 syndrome[0x20]; 11317 11318 u8 reserved_at_40[0x40]; 11319 }; 11320 11321 struct mlx5_ifc_dealloc_sf_in_bits { 11322 u8 opcode[0x10]; 11323 u8 reserved_at_10[0x10]; 11324 11325 u8 reserved_at_20[0x10]; 11326 u8 op_mod[0x10]; 11327 11328 u8 reserved_at_40[0x10]; 11329 u8 function_id[0x10]; 11330 11331 u8 reserved_at_60[0x20]; 11332 }; 11333 11334 struct mlx5_ifc_alloc_sf_out_bits { 11335 u8 status[0x8]; 11336 u8 reserved_at_8[0x18]; 11337 11338 u8 syndrome[0x20]; 11339 11340 u8 reserved_at_40[0x40]; 11341 }; 11342 11343 struct mlx5_ifc_alloc_sf_in_bits { 11344 u8 opcode[0x10]; 11345 u8 reserved_at_10[0x10]; 11346 11347 u8 reserved_at_20[0x10]; 11348 u8 op_mod[0x10]; 11349 11350 u8 reserved_at_40[0x10]; 11351 u8 function_id[0x10]; 11352 11353 u8 reserved_at_60[0x20]; 11354 }; 11355 11356 struct mlx5_ifc_affiliated_event_header_bits { 11357 u8 reserved_at_0[0x10]; 11358 u8 obj_type[0x10]; 11359 11360 u8 obj_id[0x20]; 11361 }; 11362 11363 enum { 11364 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11365 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11366 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11367 }; 11368 11369 enum { 11370 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11371 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11372 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11373 }; 11374 11375 enum { 11376 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11377 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 11378 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 11379 }; 11380 11381 struct mlx5_ifc_ipsec_obj_bits { 11382 u8 modify_field_select[0x40]; 11383 u8 full_offload[0x1]; 11384 u8 reserved_at_41[0x1]; 11385 u8 esn_en[0x1]; 11386 u8 esn_overlap[0x1]; 11387 u8 reserved_at_44[0x2]; 11388 u8 icv_length[0x2]; 11389 u8 reserved_at_48[0x4]; 11390 u8 aso_return_reg[0x4]; 11391 u8 reserved_at_50[0x10]; 11392 11393 u8 esn_msb[0x20]; 11394 11395 u8 reserved_at_80[0x8]; 11396 u8 dekn[0x18]; 11397 11398 u8 salt[0x20]; 11399 11400 u8 implicit_iv[0x40]; 11401 11402 u8 reserved_at_100[0x700]; 11403 }; 11404 11405 struct mlx5_ifc_create_ipsec_obj_in_bits { 11406 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11407 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11408 }; 11409 11410 enum { 11411 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11412 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11413 }; 11414 11415 struct mlx5_ifc_query_ipsec_obj_out_bits { 11416 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11417 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11418 }; 11419 11420 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11421 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11422 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11423 }; 11424 11425 struct mlx5_ifc_encryption_key_obj_bits { 11426 u8 modify_field_select[0x40]; 11427 11428 u8 reserved_at_40[0x14]; 11429 u8 key_size[0x4]; 11430 u8 reserved_at_58[0x4]; 11431 u8 key_type[0x4]; 11432 11433 u8 reserved_at_60[0x8]; 11434 u8 pd[0x18]; 11435 11436 u8 reserved_at_80[0x180]; 11437 u8 key[8][0x20]; 11438 11439 u8 reserved_at_300[0x500]; 11440 }; 11441 11442 struct mlx5_ifc_create_encryption_key_in_bits { 11443 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11444 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11445 }; 11446 11447 struct mlx5_ifc_sampler_obj_bits { 11448 u8 modify_field_select[0x40]; 11449 11450 u8 table_type[0x8]; 11451 u8 level[0x8]; 11452 u8 reserved_at_50[0xf]; 11453 u8 ignore_flow_level[0x1]; 11454 11455 u8 sample_ratio[0x20]; 11456 11457 u8 reserved_at_80[0x8]; 11458 u8 sample_table_id[0x18]; 11459 11460 u8 reserved_at_a0[0x8]; 11461 u8 default_table_id[0x18]; 11462 11463 u8 sw_steering_icm_address_rx[0x40]; 11464 u8 sw_steering_icm_address_tx[0x40]; 11465 11466 u8 reserved_at_140[0xa0]; 11467 }; 11468 11469 struct mlx5_ifc_create_sampler_obj_in_bits { 11470 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11471 struct mlx5_ifc_sampler_obj_bits sampler_object; 11472 }; 11473 11474 struct mlx5_ifc_query_sampler_obj_out_bits { 11475 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11476 struct mlx5_ifc_sampler_obj_bits sampler_object; 11477 }; 11478 11479 enum { 11480 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11481 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11482 }; 11483 11484 enum { 11485 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11486 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11487 }; 11488 11489 struct mlx5_ifc_tls_static_params_bits { 11490 u8 const_2[0x2]; 11491 u8 tls_version[0x4]; 11492 u8 const_1[0x2]; 11493 u8 reserved_at_8[0x14]; 11494 u8 encryption_standard[0x4]; 11495 11496 u8 reserved_at_20[0x20]; 11497 11498 u8 initial_record_number[0x40]; 11499 11500 u8 resync_tcp_sn[0x20]; 11501 11502 u8 gcm_iv[0x20]; 11503 11504 u8 implicit_iv[0x40]; 11505 11506 u8 reserved_at_100[0x8]; 11507 u8 dek_index[0x18]; 11508 11509 u8 reserved_at_120[0xe0]; 11510 }; 11511 11512 struct mlx5_ifc_tls_progress_params_bits { 11513 u8 next_record_tcp_sn[0x20]; 11514 11515 u8 hw_resync_tcp_sn[0x20]; 11516 11517 u8 record_tracker_state[0x2]; 11518 u8 auth_state[0x2]; 11519 u8 reserved_at_44[0x4]; 11520 u8 hw_offset_record_number[0x18]; 11521 }; 11522 11523 enum { 11524 MLX5_MTT_PERM_READ = 1 << 0, 11525 MLX5_MTT_PERM_WRITE = 1 << 1, 11526 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11527 }; 11528 11529 enum { 11530 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 11531 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 11532 }; 11533 11534 struct mlx5_ifc_suspend_vhca_in_bits { 11535 u8 opcode[0x10]; 11536 u8 uid[0x10]; 11537 11538 u8 reserved_at_20[0x10]; 11539 u8 op_mod[0x10]; 11540 11541 u8 reserved_at_40[0x10]; 11542 u8 vhca_id[0x10]; 11543 11544 u8 reserved_at_60[0x20]; 11545 }; 11546 11547 struct mlx5_ifc_suspend_vhca_out_bits { 11548 u8 status[0x8]; 11549 u8 reserved_at_8[0x18]; 11550 11551 u8 syndrome[0x20]; 11552 11553 u8 reserved_at_40[0x40]; 11554 }; 11555 11556 enum { 11557 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 11558 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 11559 }; 11560 11561 struct mlx5_ifc_resume_vhca_in_bits { 11562 u8 opcode[0x10]; 11563 u8 uid[0x10]; 11564 11565 u8 reserved_at_20[0x10]; 11566 u8 op_mod[0x10]; 11567 11568 u8 reserved_at_40[0x10]; 11569 u8 vhca_id[0x10]; 11570 11571 u8 reserved_at_60[0x20]; 11572 }; 11573 11574 struct mlx5_ifc_resume_vhca_out_bits { 11575 u8 status[0x8]; 11576 u8 reserved_at_8[0x18]; 11577 11578 u8 syndrome[0x20]; 11579 11580 u8 reserved_at_40[0x40]; 11581 }; 11582 11583 struct mlx5_ifc_query_vhca_migration_state_in_bits { 11584 u8 opcode[0x10]; 11585 u8 uid[0x10]; 11586 11587 u8 reserved_at_20[0x10]; 11588 u8 op_mod[0x10]; 11589 11590 u8 reserved_at_40[0x10]; 11591 u8 vhca_id[0x10]; 11592 11593 u8 reserved_at_60[0x20]; 11594 }; 11595 11596 struct mlx5_ifc_query_vhca_migration_state_out_bits { 11597 u8 status[0x8]; 11598 u8 reserved_at_8[0x18]; 11599 11600 u8 syndrome[0x20]; 11601 11602 u8 reserved_at_40[0x40]; 11603 11604 u8 required_umem_size[0x20]; 11605 11606 u8 reserved_at_a0[0x160]; 11607 }; 11608 11609 struct mlx5_ifc_save_vhca_state_in_bits { 11610 u8 opcode[0x10]; 11611 u8 uid[0x10]; 11612 11613 u8 reserved_at_20[0x10]; 11614 u8 op_mod[0x10]; 11615 11616 u8 reserved_at_40[0x10]; 11617 u8 vhca_id[0x10]; 11618 11619 u8 reserved_at_60[0x20]; 11620 11621 u8 va[0x40]; 11622 11623 u8 mkey[0x20]; 11624 11625 u8 size[0x20]; 11626 }; 11627 11628 struct mlx5_ifc_save_vhca_state_out_bits { 11629 u8 status[0x8]; 11630 u8 reserved_at_8[0x18]; 11631 11632 u8 syndrome[0x20]; 11633 11634 u8 actual_image_size[0x20]; 11635 11636 u8 reserved_at_60[0x20]; 11637 }; 11638 11639 struct mlx5_ifc_load_vhca_state_in_bits { 11640 u8 opcode[0x10]; 11641 u8 uid[0x10]; 11642 11643 u8 reserved_at_20[0x10]; 11644 u8 op_mod[0x10]; 11645 11646 u8 reserved_at_40[0x10]; 11647 u8 vhca_id[0x10]; 11648 11649 u8 reserved_at_60[0x20]; 11650 11651 u8 va[0x40]; 11652 11653 u8 mkey[0x20]; 11654 11655 u8 size[0x20]; 11656 }; 11657 11658 struct mlx5_ifc_load_vhca_state_out_bits { 11659 u8 status[0x8]; 11660 u8 reserved_at_8[0x18]; 11661 11662 u8 syndrome[0x20]; 11663 11664 u8 reserved_at_40[0x40]; 11665 }; 11666 11667 #endif /* MLX5_IFC_H */ 11668